54AC161 • 54ACT161 Synchronous Presettable Binary Counter General Description The ’AC/’ACT161 are high-speed synchronous modulo-16 binary counters. They are synchronously presettable for application in programmable dividers and have two types of Count Enable inputs plus a Terminal Count output for versatility in forming synchronous multistage counters. The ’AC/ ’ACT161 has an asynchronous Master Reset input that overrides all other inputs and forces the outputs LOW. n n n n n n Synchronous counting and loading High-speed synchronous expansion Typical count rate of 125 MHz Outputs source/sink 24 mA ’ACT161 has TTL-compatible inputs Standard Microcircuit Drawing (SMD) — ’AC161: 5962-89561 — ’ACT161: 5962-91722 Features n ICC reduced by 50% Logic Symbols Pin Names Description CEP Count Enable Parallel Input CET Count Enable Trickle Input CP Clock Pulse Input MR Asynchronous Master Reset Input P0–P3 Parallel Data Inputs PE Parallel Enable Inputs Q0–Q3 Flip-Flop Outputs TC Terminal Count Output DS100274-1 IEEE/IEC DS100274-2 TRI-STATE ® is a registered trademark of National Semiconductor Corporation. FACT™ is a trademark of Fairchild Semiconductor Corporation. © 1998 National Semiconductor Corporation DS100274 www.national.com 54AC161 • 54ACT161 Synchronous Presettable Binary Counter November 1998 The Terminal Count (TC) output is HIGH when CET is HIGH and counter is in state 15. To implement synchronous multistage counters, the TC outputs can be used with the CEP and CET inputs in two different ways. Connection Diagrams Pin Assignment for DIP and Flatpak Figure 1 shows the connections for simple ripple carry, in which the clock period must be longer than the CP to TC delay of the first stage, plus the cumulative CET to TC delays of the intermediate stages, plus the CET to CP setup time of the last stage. This total delay plus setup time sets the upper limit on clock frequency. For faster clock rates, the carry lookahead connections shown in Figure 2 are recommended. In this scheme the ripple delay through the intermediate stages commences with the same clock that causes the first stage to tick over from max to min in the Up mode, or min to max in the Down mode, to start its final cycle. Since this final cycle requires 16 clocks to complete, there is plenty of time for the ripple to progress through the intermediate stages. The critical timing that limits the clock period is the CP to TC delay of the first stage plus the CEP to CP setup time of the last stage. The TC output is subject to decoding spikes due to internal race conditions and is therefore not recommended for use as a clock or asynchronous reset for flip-flops, registers or counters. Logic Equations: Count Enable = CEP • CET • PE TC = Q0 • Q1 • Q2 • Q3 • CET DS100274-3 Pin Assignment for LCC Mode Select Table PE CET CEP X X X Action on the Rising Clock Edge (N) DS100274-4 Functional Description The ’AC/’ACT161 count in modulo-16 binary sequence. From state 15 (HHHH) they increment to state 0 (LLLL). The clock inputs of all flip-flops are driven in parallel through a clock buffer. Thus all changes of the Q outputs (except due to Master Reset of the ’161) occur as a result of, and synchronous with, the LOW-to-HIGH transition of the CP input signal. The circuits have four fundamental modes of operation, in order of precedence: asynchronous reset, parallel load, count-up and hold. Five control inputs — Master Reset, Parallel Enable (PE), Count Enable Parallel (CEP) and Count Enable Trickle (CET) — determine the mode of operation, as shown in the Mode Select Table. A LOW signal on MR overrides all other inputs and asynchronously forces all outputs LOW. A LOW signal on PE overrides counting and allows information on the Parallel Data (Pn) inputs to be loaded into the flip-flops on the next rising edge of CP. With PE and MR HIGH, CEP and CET permit counting when both are HIGH. Conversely, a LOW signal on either CEP or CET inhibits counting. The ’AC/’ACT161 use D-type edge-triggered flip-flops and changing the PE, CEP and CET inputs when the CP is in either state does not cause errors, provided that the recommended setup and hold times, with respect to the rising edge of CP, are observed. L X X Reset (Clear) Load (Pn→Qn) H H H Count (Increment) H L X No Change (Hold) H X L No Change (Hold) H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial State Diagram DS100274-5 www.national.com 2 State Diagram (Continued) DS100274-8 FIGURE 1. Multistage Counter with Ripple Carry DS100274-9 FIGURE 2. Multistage Counter with Lookahead Carry 3 www.national.com Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. DS100274-6 Block Diagram www.national.com 4 Absolute Maximum Ratings (Note 1) Recommended Operating Conditions If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) DC Input Diode Current (IIK) VI = −0.5V VI = VCC + 0.5V DC Input Voltage (VI) DC Output Diode Current (IOK) VO = −0.5V VO = VCC + 0.5V DC Output Voltage (VO) DC Output Source or Sink Current (IO) DC VCC or Ground Current per Output Pin (ICC or IGND) Storage Temperature (TSTG) Junction Temperature (TJ) CDIP Supply Voltage (VCC) ’AC ’ACT Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) 54AC/ACT Minimum Input Edge Rate (∆V/∆t) ’AC Devices VIN from 30% to 70% of VCC VCC @ 3.3V, 4.5V, 5.5V Minimum Input Edge Rate (∆V/∆t) ’ACT Devices VIN from 0.8V to 2.0V VCC @ 4.5V, 5.5V −0.5V to +7.0V −20 mA +20 mA −0.5V to VCC + 0.5V −20 mA +20 mA −0.5V to VCC + 0.5V ± 50 mA ± 50 mA −65˚C to +150˚C 2.0V to 6.0V 4.5V to 5.5V 0V to VCC 0V to VCC −55˚C to +125˚C 125 mV/ns 125 mV/ns Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. National does not recommend operation of FACT™ circuits outside databook specifications. 175˚C DC Characteristics for ’AC Family Devices Symbol Parameter VCC 54AC TA = (V) −55˚C to +125˚C Units Conditions Guaranteed Limits VIH VIL VOH Minimum High Level 3.0 2.1 Input Voltage 4.5 3.15 5.5 3.85 Maximum Low Level 3.0 0.9 Input Voltage 4.5 1.35 5.5 1.65 Minimum High Level 3.0 2.9 Output Voltage 4.5 4.4 5.5 5.4 VOUT = 0.1V V or VCC − 0.1V V or VCC − 0.1V VOUT = 0.1V IOUT = −50 µA V (Note 2) VIN = VIL or VIH VOL 3.0 2.4 4.5 3.7 5.5 4.7 Maximum Low Level 3.0 0.1 Output Voltage 4.5 0.1 5.5 0.1 IOH = −12 mA V IOH = −24 mA IOH = −24 mA IOUT = 50 µA V (Note 2) VIN = VIL or VIH IIN Maximum Input 3.0 0.5 4.5 0.5 5.5 0.5 5.5 ± 1.0 IOL = 12 mA V IOL = 24 mA µA IOL = 24 mA VI = VCC, GND Leakage Current IOLD Minimum Dynamic Output Current (Note 3) 5.5 50 mA IOHD 5.5 −50 mA ICC Maximum Quiescent 5.5 160 µA 5 VOLD = 1.65V Max VOHD = 3.85V Min VIN = VCC www.national.com DC Characteristics for ’AC Family Devices Symbol Parameter (Continued) VCC 54AC TA = (V) −55˚C to +125˚C Units Conditions Guaranteed Limits Supply Current or GND Note 2: All outputs loaded; thresholds on input associated with output under test. Note 3: Maximum test duration 2.0 ms, one output loaded at a time. Note 4: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC. ICC for 54AC @ 25˚C is identical to 74AC @ 25˚C. DC Characteristics for ’ACT Family Devices Symbol Parameter VCC 54ACT TA = (V) −55˚C to +125˚C Units Conditions Guaranteed Limits VIH VIL VOH Minimum High Level 4.5 3.0 Input Voltage (Note 7) 5.5 3.0 Maximum Low Level 4.5 0.8 Input Voltage 5.5 0.8 Minimum High Level 4.5 4.4 Output Voltage 5.5 5.4 V VOUT = 0.1V V or VCC − 0.1V VOUT = 0.1V V or VCC − 0.1V IOUT = −50 µA (Note 5) VIN = VIL or 3.0V VOL 4.5 3.70 5.5 4.70 Maximum Low Level 4.5 0.1 Output Voltage 5.5 0.1 V IOH = −24 mA V IOH = −24 mA IOUT = 50 µA (Note 5) VIN = VIL or VIH IIN Maximum Input 4.5 0.50 5.5 0.50 V IOL = 24 mA ± 1.0 µA IOL = 24 mA VI = VCC, GND 5.5 5.5 1.6 mA VI = VCC − 2.1V VOLD = 1.65V Max VOHD = 3.85V Min VIN = VCC Leakage Current ICCT Maximum ICC/Input IOLD Minimum Dynamic Output Current (Note 6) 5.5 50 mA IOHD 5.5 −50 mA ICC Maximum Quiescent 5.5 160 µA Supply Current or GND Note 5: All outputs loaded; thresholds on input associated with output under test. Note 6: Maximum test duration 2.0 ms, one output loaded at a time. Note 7: For dynamic operation, a VIH level between 2.0 and 3.0V may be recognized by this device as a high logic level input. For static operation, a VIH ≥ 2.0V will be recognized by this device as a high logic level input. Users are cautioned to verify that this will not affect their system. www.national.com 6 AC Electrical Characteristics 54AC TA = −55˚C VCC Symbol Parameter (V) to +125˚C CL = 50 pF (Note 8) Min fmax tPLH tPHL tPLH tPHL tPLH tPHL tPHL tPHL Maximum Count 3.3 55 Frequency 5.0 80 Fig. Units No. Max MHz Propagation Delay CP to Qn 3.3 1.0 14.0 (PE Input HIGH or LOW) 5.0 1.0 10.0 Propagation Delay CP to Qn 3.3 1.0 14.0 (PE Input HIGH or LOW) 5.0 1.0 10.0 Propagation Delay 3.3 3.0 18.0 CP to TC 5.0 3.0 13.0 Propagation Delay 3.3 1.0 17.5 CP to TC 5.0 1.0 13.0 Propagation Delay 3.3 1.0 13.0 CET to TC 5.0 1.0 8.5 Propagation Delay 3.3 1.0 13.5 CET to TC 5.0 1.0 10.5 Propagation Delay 3.3 1.0 14.5 MR to Qn 5.0 1.0 10.5 Propagation Delay 3.3 1.0 18.5 MR to TC 5.0 1.0 14.0 ns ns ns ns ns ns ns ns Note 8: Voltage Range 3.3 is 3.3V ± 0.3V Range 5.0 is 5.0V ± 0.5V AC Operating Requirements 54AC TA = −55˚C VCC Symbol Parameter (V) to +125˚C CL = 50 pF (Note 9) Fig. Units No. Guaranteed Minimum ts th ts th ts th tw tw tw Setup Time, HIGH or LOW 3.3 16.0 Pn to CP 5.0 10.5 Hold Time, HIGH or LOW 3.3 0.5 Pn to CP 5.0 1.5 Setup Time, HIGH or LOW 3.3 15.0 PE to CP 5.0 10.5 Hold Time, HIGH or LOW 3.3 −1.0 PE to CP 5.0 0.0 Setup Time, HIGH or LOW 3.3 7.5 CEP or CET to CP 5.0 5.5 Hold Time, HIGH or LOW 3.3 2.0 CEP or CET to CP 5.0 2.0 Clock Pulse Width 3.3 5.0 (Load) HIGH or LOW 5.0 5.0 Clock Pulse Width 3.3 5.0 (Count) HIGH or LOW 5.0 5.0 MR Pulse Width, 3.3 5.0 LOW 5.0 5.0 7 ns ns ns ns ns ns ns ns ns www.national.com AC Operating Requirements (Continued) 54AC TA = −55˚C VCC Symbol Parameter (V) Fig. to +125˚C CL = 50 pF (Note 9) Units No. Guaranteed Minimum trec Recovery Time 1.5 MR to CP 2.0 ns Note 9: Voltage Range 3.3 is 3.3V ± 0.3V Voltage Range 5.0 is 5.0V ± 0.5V AC Electrical Characteristics 54ACT TA = −55˚C VCC Symbol Parameter (V) (Note 10) Min fmax Maximum Count Fig. to +125˚C CL = 50 pF Units No. Max 5.0 85 MHz 5.0 1.0 10.5 ns 5.0 1.0 10.5 ns 5.0 1.0 14.0 ns 5.0 1.0 12.5 ns 5.0 1.0 9.5 ns 5.0 1.0 9.5 ns 5.0 1.0 10.0 ns 5.0 1.0 11.5 ns Frequency tPLH Propagation Delay CP to Qn (PE Input HIGH or LOW) tPHL Propagation Delay CP to Qn (PE Input HIGH or LOW) tPLH Propagation Delay CP to TC tPHL Propagation Delay CP to TC tPLH Propagation Delay CET to TC tPHL Propagation Delay CET to TC tPHL Propagation Delay MR to Qn tPHL Propagation Delay MR to TC Note 10: Voltage Range 5.0 is 5.0V ± 0.5V AC Operating Requirements 54ACT TA = −55˚C VCC Symbol Parameter (V) to +125˚C CL = 50 pF (Note 11) Fig. Units Guaranteed Minimum ts Setup Time, HIGH or LOW 5.0 13.0 ns 5.0 0 ns 5.0 11.0 ns Pn to CP th Hold Time, HIGH or LOW Pn to CP ts Setup Time, HIGH or LOW PE to CP www.national.com 8 No. AC Operating Requirements (Continued) 54ACT TA = −55˚C VCC Symbol Parameter (V) to +125˚C CL = 50 pF (Note 11) Fig. Units No. Guaranteed Minimum th Hold Time, HIGH or LOW 5.0 0 ns 5.0 7.0 ns 5.0 0.5 ns 5.0 5.0 ns 5.0 5.0 ns PE to CP ts Setup Time, HIGH or LOW CEP or CET to CP th Hold Time, HIGH or LOW CEP or CET to CP tw Clock Pulse Width, (Load) HIGH or LOW tw Clock Pulse Width, (Count) HIGH or LOW tw MR Pulse Width, LOW 5.0 6.5 ns trec Recovery Time 5.0 0.5 ns MR to CP Note 11: Voltage Range 5.0 is 5.0V ± 0.5V Capacitance Typ Units CIN Symbol Input Capacitance Parameter 4.5 pF CPD Power Dissipation Capacitance 45.0 pF 9 Conditions VCC = OPEN VCC = 5.0V www.national.com 10 Physical Dimensions inches (millimeters) unless otherwise noted 20 Terminal Ceramic Leadless Chip Carrier (L) NS Package Number E20A 16 Lead Ceramic Dual-In-Line Package (D) NS Package Number J16A 11 www.national.com 54AC161 • 54ACT161 Synchronous Presettable Binary Counter Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16 Lead Ceramic Flatpak (F) NS Package Number W16A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. 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