CGS702V Commercial Low Skew PLL 1 to 9 CMOS Clock Driver with Improved EMI Y General Description The CGS702 is an off-the-shelf clock driver specifically designed for today’s high speed processors. It provides low skew outputs which are produced at different frequencies from three fixed input references. The CGS702 is a reduced EMI version of the CGS700. The XTALIN input pin is designed to be driven from three distinct crystal oscillators running at 25 MHz, 33 MHz or 40 MHz. The PLL, using a charge pump and an internal loop filter, multiplies this input frequency to create a maximum output frequency of four times the input. The device includes a TRI-STATEÉ control pin to disable the outputs while the PLL is still in lock. This function allows testing the board without having to wait to acquire the lock once the testing is complete. (Continued) Y Y Y Y Y Y Y Y Y Y Y Features Y Y Guaranteed and tested: 500 ps pin-to-pin skew (TOSHL and TOSLH) on 1x outputs PentiumTM and PowerPCTM compatible Output buffer of nine drivers for large fanout 25 MHz – 160 MHz output frequency range Outputs operating at 4x, 2x, 1x of the reference frequency for multi-frequency bus applications Selectable output frequency Internal loop filter to reduce noise and jitter Separate Analog and digital VCC and Ground pins Low frequency test mode by disabling the PLL Implemented on National’s Core CMOS process Symmetric output current drive: a 30 mA/ b 30 mA IOL/IOH 28-pin PCC for optimum skew performance Guaranteed 2 kV ESD protection Reduced EMI compared to CGS700 (refer to EMI characteristics) Pin Description PLCC Package Connection Diagram Pin Pin Assignment for PLCC TL/F/12386 – 1 TRI-STATEÉ is a registered trademark of National Semiconductor Corporation. PentiumTM is a trademark of Intel Corporation. PowerPCTM is a trademark of International Business Machines Corporation. C1995 National Semiconductor Corporation TL/F/12386 Name Description 1 VCC Digital VCC 2 SKWSEL Skew Test Selector Pin 3 CLK4 4x Clock Output 4 VCC Digital VCC 5 XTALIN Crystal Oscillator Input 6 GND Digital Ground 7 CLK1Ð0 1x Clock Output 8 VCC Digital VCC 9 CLK1Ð1 1x Clock Output 10 GND Digital Ground 11 CLK1Ð2 1x Clock Output 12 TRI-STATE Output TRI-STATE Control 13 SKWTST Skew Testing Pin 14 CLK1Ð3 1x Clock Output 15 GND Digital Ground 16 CLK1Ð4 1x Clock Output 17 VCC Digital VCC 18 EXTCLK External Test Clock 19 GNDA Analog Ground 20 VCCA Analog VCC 21 EXTSEL External Clock MUX Selector 22 GND Digital Ground 23 CLK1Ð5 1x Clock Output 24 VCC Digital VCC 25 CLK1Ð6 1x Clock Output 26 CLK1SEL CLK1 Multiplier Selector 27 GND Digital Ground 28 CLK2 2x Clock Output RRD-B30M105/Printed in U. S. A. CGS702V Commercial Low Skew PLL 1 to 9 CMOS Clock Driver with Improved EMI September 1995 General Description (Continued) Once CLK1SEL pin is set to a low logic level, the CLK1 outputs will be at twice the input frequency, the same as the CLK2 output, with CLK4 output still being at four times the input frequency. In addition two other pins are added for increasing the test capability. SKWSEL and SKWTST pins allow testing of the counter’s output and skew of the output drivers by bypassing the VCO. In this test mode CLK4 frequency is the same as SKWTST input frequency, while CLK2 is (/2 and CLK1 frequencies are (/4 respectively (refer to the truth table). In addition CLK1SEL functionality is also true under this test condition. Also included, are two EXTSEL and EXTCLK pins to allow testing the chip via an external source. The EXTSEL pin, once set to high, causes the External-ClockÐMux to change its input from the output of the VCO and Counter to the external clock signal provided via EXTCLK input pin. CLK1SEL pin changes the output frequency of the CLK1Ð 0,6 outputs. During normal operation, when CLK1SEL pin is high, these outputs are at the same frequency as the input crystal oscillator, while CLK2 and CLK4 outputs are at twice and four times the input frequency respectively. Block Diagram TL/F/12386 – 2 2 Truth Table Input Output CLK1 SEL EXT SEL EXT CLK SKW SEL SKW TST TRISTATE CLK4 CLK2 CLK1 H* L* X H L X L L H L L X X X É X X X L L X H H X X X X É É X H H H H H L 4x fIN 4x fIN É 1x fTST 1x fTST Z 2x fIN 2x fIN É (/2x fTST (/2x fTST Z fIN 2x fIN É (/4x fTST (/2x fTST Z *Steady state phase, frequency lock. Typical Application TL/F/12386 – 3 3 Absolute Maximum Ratings (Note 1) Note 2: Power dissipation is calculated using 49§ /W as the thermal coefficient for the PCC package at 225 LFM airflow. The input frequency is assumed at 33 MHz with CLK4 at 132 MHz and CLK2 and CLK1’s being at 66 MHz. In addition the ambient temperature is assumed 70§ with power supply at 5.0V. If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. b 0.5V to 7.0V Supply Voltage (VCC) DC Input Voltage Diode Current (IIK) b 20 mA V e b0.5V a 20 mA V e VCC a 0.5V b 0.5V to VCC a 0.5V DC Input Voltage (VI) DC Output Diode Current (IO) b 20 mA V e b0.5V a 20 mA V e VCC a 0.5V b 0.5V to VCC a 0.5V DC Output Voltage (VO) DC Output Source g 60 mA or Sink Current (IO) DC VCC or Ground Current g 60 mA per Output Pin (ICO or IGND) b 65§ C to a 150§ C Storage Temperature (TSTG) Junction Temperature 150§ C Power Dissipation (Static and Dynamic) (Note 2) 1400 mW Recommended Operating Conditions Supply Voltage (VCC) Input Voltage (VI) Output Voltage (VO) Input Crystal Frequency Operating Temperature (TA) 4.5V to 5.5V 0V to VCC 0V to VCC 25 MHz – 40 MHz 0§ C to a 70§ C 1 MHz – 10 MHz 25/75 (75/25)% External Clock Frequency (EXTCLK Pin) XTALIN Duty Cycle Range Input Rise and Fall Times (0.8V to 2.0V) Crystal Input All Other Inputs Typical iJA LFM § C/W 0 54 225 45 500 38 900 34 Note 1: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the DC and AC Electrical Characteristics tables are not guaranteed at the Absolute Maximum Ratings. The Recommended Operating Conditions will define the conditions for actual device operation. 5 ns max. 10 ns max. DC Electrical Characteristics over recommended operating free air temperature range. All typical values are measured at VCC e 5V, TA e 25§ C Symbol Parameter Conditions VCC VCC e 4.5V to 5.5V T e 0§ C to 70§ C Min VIH Minimum Input High Level Voltage 4.5 5.5 VIL Maximum Input Low LeveI Voltage 4.5 5.5 VOH Minimum Output High Level Voltage Typ Units Max 2.0 2.0 V 0.8 0.8 IOH e b50 mA 4.5 5.5 4.4 5.4 IOH e b30 mA 4.5 5.5 VCC b 0.6 VCC b 0.6 IOL e 50 mA 4.5 5.5 0.1 0.1 IOL e 30 mA 4.5 5.5 0.6 0.6 High Level Output Current VOH e VCC b 1.0V 4.5 50 110 170 mA IOL Low Level Output Current VOL e 1.0V 4.5 50 110 170 mA IIN Leakage Current VIN e 0.4V or 4.6V 4.5 5.5 b 50 50.0 mA IOZL/H Output Leakage Current VIN e GND VOUT e VCC or GND 5.5 b 5.0 a 5.0 mA CIN Input Capacitance 10.0 pF ICC ICCT Quiescent Analog a Digital Current (No Load) VIN e VCC or GND 5.5 ICC per TTL Input VIN e VCC b 2.1 or GND 5.5 VOL IOH Maximum Output Low Level Voltage 4.4 5.4 V 4.5 5.0 4 3 V 5.0 2.5 V mA CGS702 AC Electrical Characteristics over recommended operating free air temperature range. All typical values are measured at VCC e 5V, TA e 25§ C Symbol VCC e 4.5V to 5.5V fIN e 25 MHz to 40 MHz T e 0§ C to 70§ C CL e Circuit 1 and 2 RL e Circuit 1 and 2 Parameter Min tRISE tFALL tSKEW Output Rise Output Fall Typ Units Notes Max CLK4 CLK2 CLK1 0.8V to 2.6V 1.0V to VCC b 1.0V 1.0V to VCC b 1.0V 2.0 ns (Note 1) CLK4 CLK2 CLK1 2.6V to 0.8V VCC b 1.0V to 1.0V VCC b 1.0V to 1.0V 2.0 ns (Note 1) 500 1000 1500 ps (Note 2) 100 ms 49 49 35 51 51 65 % 300 ps (Notes 4, 5) b 75 a 75 ps (Notes 4, 5, 6) Maximum Edge-to-Edge Output Skew a to a Edges a to a Edges a to a Edges tLOCK Time to Lock the Output to the XTALIN Input tCYCLE Output Duty Cycle CLK1ÐCLK1 CLK1ÐCLK4 CLK2ÐCLK4 CLK1 Outputs CLK2 Output CLK4 Output JLT Output Jitter (Long Term) JCC Output Jitter (Cycle to Cycle) CLK1 (Note 3) CLK2 g 250 ps (Notes 4, 5, 7) CLK4 g 250 ps (Notes 4, 5, 7) FMIN Minimum XTALIN Frequency 15 MHz FMAX Maximum XTALIN Frequency 43 MHz Note 1: tRISE and tFALL parameters are measured at the pin of the device Note 2: Skew is measured at 50% of VCC for CLK1 and CLK2. While it is measured at 1.4V for CLK4. Note 3: Output duty cycle is measured at VDD/2 for CLK1 and CLK2. While it is measured at 1.4V for CLK4. Note 4: Jitter parameter is characterized and is guaranteed by design only. It measures the uncertainty of either the positive or the negative edge over 1000 cycles. It is also measured at output levels of VCC/2 . Refer to Figure 2 for further explanation. Note 5: The GNDA pins of the 702 must be as free of noise as possible for minimum jitter. Separate analog ground plane is recommended for the PCB. Also the VCCA pin requires extra filtering to further reduce noise. Ferrite beads for filtering and bypass capacitors are suggested for VCCA pin. Note 6: Cycle to Cycle Jitter is measured at VCC/2. Note 7: Cycle to Cycle Jitter for CLK2 and CLK4 is only for 25§ C, 5V measured @ VCC/2. TL/F/12386 – 5 TL/F/12386 – 4 Circuit 2. Test Circuit for CLK4 Circuit 1. Test Circuit for CLK1 and CLK2 5 CGS702 AC Electrical Characteristics (Continued) TL/F/12386 – 6 FIGURE 1. Waveforms TL/F/12386 – 7 Jitter e l Period(1) b Period(n a 1) l for either the rising or falling edge, where n is 1 to 1000 cycles. FIGURE 2. Jitter Application References and Bibiliography Information relating to EMI as well as general application hints are in the following application notes: AN-988 (EMI App Note) AN-640 AN-991 6 EMI Characteristics and Measurements for CGS702 The FCC certification test method is an open field measurement procedure. Therefore, the spectral content of the device-under-test (in this case, an IC) cannot be detected below the ambient level of radiation. The test-site is permanent and the average ambient noise level remains relatively constant. The CGS700 and CGS702 were tested for EMI using the above method. A comparison of the EMI results in the form of spectral content is shown in Figures 4 and 5 . For more details on EMI, see Application Note AN-831. MEASURING THE SPECTRAL CONTENT OF A LOGIC IC In order to analyze the frequency, or spectral content of logic ICs, two measurement techniques have been developed. One method, The Radiated Measurement Method, is based on the system-level FCC certification test methodology, FCC Open Site Test (OST) 55. The radiated method utilizes a multilayer PCB with the IC-under-test is mounted on a grounded, adjustable table placed 3 meters from an antenna mast (see Figure 3 ). The IC’s input is stimulated by a known periodic waveform and its output drives a typical PCB microstrip. The 75X microstrip is properly terminated to prevent reflections from affecting the IC’s spectral content results. Screen Room with 120 dB Shielding TL/F/12386 – 9 FIGURE 3. Radiated EMI Measurement Method 7 EMI Characteristics and Measurements (Continued) TL/F/12386 – 8 XTALIN e 40 MHz VCC e 5V T e 25§ C ANTENNA e HORIZONTAL FIGURE 4. CGS700 TL/F/12386 – 12 XTALIN e 40 MHz VCC e 5V T e 25§ C ANTENNA e HORIZONTAL FIGURE 5. CGS702 8 Ordering Information (Contact NSC Marketing for Specific Date of Availability) TL/F/12386 – 11 9 CGS702V Commercial Low Skew PLL 1 to 9 CMOS Clock Driver with Improved EMI Physical Dimensions inches (millimeters) 28-Lead Molded Plated Leaded Chip Carrier Order Number CGS702V NS Package Number V28A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 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