iC-VRV BIDIRECTIONAL µP INTERFACE TO 24V Rev A2, Page 1/12 FEATURES APPLICATIONS Ë Ë Ë Ë Ë Ë Ë Ë Ë Ë Ë Ë Ë 2 × 4 bidirectional input/output stages at 24 V Input/output mode programmable for each 4 bits Guaranteed low-side driving capability of 100 mAdc and 500 mApeak for pulse load Short-circuit-proof driver with high electric strength up to 48 V Low saturation voltage of 0.4 V at 10 mA and 1.5 V at 500 mA Programmable pull-down current sources Built-in free-wheeling diodes with externally accessible common cathode Flashing function for the outputs Programmable digital input filters with externally adjusted filtering times Bus capability via high-speed microprocessor interface Programmable interrupt output Shutdown at overtemperature and low voltage Dual quad low-side driver as bidirectional µP interface with digital filtering in 24 V industrial applications PACKAGES PLCC44 BLOCK DIAGRAM Input/Output Stage 0 D 30 34 VCCA Q R D NQ R CSN 6 WRN 7 RDN Q ENERR 44 CERR 39 CTEST 2 A0 3 A1 40 D0 42 D1 43 D2 1 D3 35 D4 36 D5 37 D6 38 D7 I/O Logic Input/Output Stage 1 I/O Logic Input/Output Stage 2 26 27 28 IO3 29 lower nibble I/O Logic Input/Output Stage 4 I/O Logic Input/Output Stage 5 I/O Logic Input/Output Stage 6 IO4 17 GND45 18 IO5 19 IO6 20 GND67 21 IO7 22 COM 23 Input/Output Stage 7 higher nibble RESN Interrupt IO2 GND23 Input/Output Stage 3 I/O Logic DIV Chn DIV Cln DIV Bhn DIV Bln Low Voltage Thermal Shutdown Bias Frequency Divider Copyright © 2003, 2009 iC-Haus IO1 VCC-1.3V iC-VRV Control Register 25 DISABLE Input Filter I/O Logic 8 GND01 up/dwn 3 Bit Counter R 41 24 Test VCCD 4 IO0 Output Latch INTN CLK 11 10 BLFQ 9 GNDD 12 GNDS 13 GNDA PLCC44 16 www.ichaus.com iC-VRV BIDIRECTIONAL µP INTERFACE TO 24V Rev A2, Page 2/12 DESCRIPTION iC-VRV is an 8-fold low-side driver with integrated control logic which is divided internally into two mutually independent blocks (nibbles). In the input mode, ports IO0 to IO7 can be used to record logical levels. In this process, a programmable pull-down current (200 µA or 2 mA) sets a defined level and functions as the biasing current for switching contacts. The stages programmed as outputs can drive any desired loads (e. g. lamps, long cables, relays) at a continuous current of 100 mA or 500 mA in pulse operation. The free-wheeling currents created upon each stage turn-off are discharged through the integrated free-wheeling diodes to a voltage applied externally to the COM pin; a circuit with a Zener diode is also possible. In the event of a short circuit, a protective circuit breaker ensures that the output stage affected does not just simply switch off but is instead clocked as a function of the load. As a result, the current assumes a low average value. The output stage is ready for operation immediately just as soon as the cause of the short circuit has been eliminated. The shutdown at overtemperature protects the IC against thermal destruction by causing the output stages to turn off and the pull-down currents to be reduced from 2 mA to 200 µA. This shutdown is also triggered in case of undervoltage at VCC. Due to the microprocessor interface the iC-VRV can be operated directly on a bus system. The interface consists of the data bits D0 to D7 and the associated control signals A0, A1, CSN, WRN and RDN. The signal CLK clocks the implemented digital input filter and BLFQ clocks the programmed flashing function. In the event of a signal change of the I/O pins programmed as inputs, an interrupt signal can be generated at output INTN. Activating the input RESN resets the initial condition. Chip programming is conducted via four addresses at A0 and A1. During this programming, presettings for flashing frequencies, filtering times, interrupt control, pull-down currents and input/output mode, etc. are stored in two registers (CONTROL WORD1+2). All inputs and outputs are protected with diodes against destruction due to ESD. iC-VRV BIDIRECTIONAL µP INTERFACE TO 24V Rev A2, Page 3/12 PACKAGES PLCC44 to JEDEC Standard PIN CONFIGURATION PLCC44 (top view) PIN FUNCTIONS PLCC44 No. Name Function Description No. Name 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 D3 A0 A1 CSN n.c. WRN RDN RESN BLFQ CLK INTN GNDD n.c. n.c. n.c. GNDA IO4 GND45 IO5 IO6 GND67 IO7 B I I I Bus Data Bit 3 Address Address Chip Select I I I I I O Write Enable Read Enable Reset Clock, flashing function Clock, filter function Interrupt Report Digital Ground 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39(*) 40 41(*) 42 43 44(x) COM IO0 GND01 IO1 IO2 GND23 IO3 VCCA n.c. n.c. n.c. VCCD D4 D5 D6 D7 CTEST D0 ENERR D1 D2 CERR B B B B Analog Ground I/O Stage 4 Ground Stage 4+5 I/O Stage 5 I/O Stage 6 Ground Stage 6+7 I/O Stage 7 *: pin needs external wiring to Ground x: pin should left open Function: I = Input, O = Output, B = bidirectional Function B B B B Description Diodes, common cathode I/O Stage 0 Ground Stage 0+1 I/O Stage 1 I/O Stage 2 Ground Stage 2+3 I/O Stage 3 +5 V Supply (analog section) B B B B +5 V Supply (digital section) Bus Data Bit 4 Bus Data Bit 5 Bus Data Bit 6 Bus Data Bit 7 B Bus Data Bit 0 B B Bus Data Bit 1 Bus Data Bit 2 iC-VRV BIDIRECTIONAL µP INTERFACE TO 24V Rev A2, Page 4/12 PROGRAMMING Selection of functions Data Word D7..D0 higher nibble lower nibble Selected I/O Stage function: Address Input Output Input Output A1 A0 Write Read Write Read Write Read Write Read 0 0 Test Pattern IR Inputs Outputs Outputs Test Pattern IR Inputs Outputs Outputs 0 1 IR Enable IR Enable Pulse Enable Pulse Enable IR Enable IR Enable Pulse Enable Pulse Enable 1 0 Control Word 2 Inputs Control Word 2 Feedback I/O Stages Control Word 2 Inputs Control Word 2 Feedback I/O Stages 1 1 Control Word 1 Control Word 1 Control Word 1 Control Word 1 Control Word 1 Control Word 1 Control Word 1 Control Word 1 Reading the inputs or the output feedback (IO7..0 to D7..0) I/O stage with input function: A high level at IOx generates a high signal at Dx (selection of functions: read inputs) during the course of the digital hysteresis. I/O stage with output function: A high level at IOx generates a low signal at Dx (selection of functions: read feedback of the outputs). The inversion while reading back the outputs (I/O stage with output function) occurs so that the same signal is applied to Dx as was programmed for switching the output stage on or off, for example: switching on the final stage with Dx = high results in low level at IOx. After the digital hysteresis ends, Q becomes low, the microprocessor interface inverts this message and a high signal can be read back via Dx. The microprocessor can check the output state in this manner. Test The test circuit consists of registers which can be set via the microprocessor interface (test pattern). Its content is applied via constantly active OR gates to the counting direction inputs UP/DOWN (D7..0 to UP/DOWN7..0). In response to a reset (low signal at RESN) the registers are set to low; as a result, there is no effect on the UP/DOWN inputs. In the test mode (control word 2, bit 2 and 6 at high) the comparators of the I/O stages are switched off and only the test registers continue to operate the UP/DOWN inputs. Any desired input signals can be entered to test all digital functions; the microprocessor can also conduct a system test in this manner. Interrupt enable The interrupt generation can be activated separately for every I/O stage with input function. The interrupt enable is programmed via the data word DO..7 (function selection IR enable: 1 = stage relevant, 0 = stage not relevant). If a signal change is recognized for an I/O stage with input function - after the digital hysteresis due to change at Qx - and if this stage is enabled for interrupt generation, this is indicated with INTN = low. The interrupt message as well as the interrupt register which shows the stages with signal changes are reset via control word 2 (writing bit 0 = 1 is sufficient; bit 0 = 0 is set by the chip automatically). iC-VRV BIDIRECTIONAL µP INTERFACE TO 24V Rev A2, Page 5/12 Signal changes which would be relevant for an interrupt generation could occur in the read-out phase following an interrupt message. These signal changes are lost when the interrupt register is deleted. As an alternative, the read-out of the interrupt register is possible (functional selection: read IR inputs). The registers can then be reset separately by blocking the IR enable for each reporting stage singly and then releasing it (functional selection: IR enable). Filter periods The input comparator of each I/O stage switches the counting direction of a 3 bit counter. The counter output Q does not change until the final status is reached (to high for high level at IOx, to low for low level at IOx if constantly applied during the filter period). The counter is clocked externally (pin CLK); the divisor for the clock frequency can be programmed separately for both nibbles. A low signal at reset input RESN resets the counters to the value 3. Due to the digital hysteresis, the change of an input signal is therefore not recognized until the selected filter period has elapsed. Pulse enable and pulse times The flashing or pulsing function can be switched on separately for each I/O stage with output function. The programming of the divisors for the flashing frequency input BLFQ (control word 1, bits 0,1 and 4,5) is conducted for each nibble. The clock signal at BLFQ is transfered with the slope of CLK (synchronized). For this reason the clock frequency for CLK must be higher than the clock frequency for BLFQ, e. g. 2 MHz for CLK and 50 Hz for BLFQ. Control Word 1 higher nibble Bit Name 7 FH0 6 FH1 lower nibble 5 PH0 4 PH1 3 FL0 2 FL1 Control Word 1 (lower nibble) Filtering Time Flashing Pulse Duration Bit 3 FLO Bit 2 FL1 Bit 1 PLO Bit 0 PL1 0 1 0 1 0 0 1 1 0 1 0 1 0 0 1 1 14.5 * CLK 896.5 * CLK 3584.5 * CLK 7168.5 * CLK ± 1 * CLK ± 64 * CLK ± 256 * CLK ± 512 * CLK BLFQ BLFQ * 2 BLFQ * 4 BLFQ * 16 Control Word 1 (higher nibble) Filtering Time Flashing Pulse Duration Bit 7 FHO Bit 6 FH1 Bit 5 PHO Bit 4 PH1 0 1 0 1 0 0 1 1 0 1 0 1 0 0 1 1 14.5 * CLK 896.5 * CLK 3584.5 * CLK 7168.5 * CLK ± 1 * CLK ± 64 * CLK ± 256 * CLK ± 512 * CLK BLFQ BLFQ * 2 BLFQ * 4 BLFQ * 16 1 PL0 0 PL1 iC-VRV BIDIRECTIONAL µP INTERFACE TO 24V Rev A2, Page 6/12 Control Word 2 higher nibble Bit Name 7 NIOH 6 TSTH lower nibble 5 IBH 4 not used 3 NIOL 2 TSTL Control Word 2 (lower nibble) Interrupt Bit 0 (EOI) 0 1 Interrupt is not cancelled Clearing Interrupt Current Sources at I/O Pins Bit 1 (IBL) 0 1 Pull-Down Current 200 µA Pull-Down Current 2 mA 0 1 Feedback of I/O stages active (OR gated with test pattern) Test pattern activated, feedback of I/O stages switched off Test Bit 2 (TSTL) Input/Output Mode Bit 3 (NIOL) 0 1 Input Mode Output Mode Control Word 2 (higher nibble) Bit 4 - not used Current Source at I/O Pins Bit 5 (IBH) 0 1 Pull-Down Current 200 µA Pull-Down Current 2 mA 0 1 Feedback of I/O stages active (OR gated with test pattern) Test pattern activated, feedback of I/O stages switched off Test Bit 6 (TSTH) Input/Output Mode Bit 7 (NIOH) 0 1 Input Mode Output Mode 1 IBL 0 EOI iC-VRV BIDIRECTIONAL µP INTERFACE TO 24V Rev A2, Page 7/12 ABSOLUTE MAXIMUM RATINGS Beyond these values damage may occur; device operation is not guaranteed. Absolute Maximum Ratings are no Operating Conditions. Integrated circuits with system interfaces, e.g. via cable accessible pins (I/O pins, line drivers) are per principle endangered by injected interferences, which may compromise the function or durability. The robustness of the devices has to be verified by the user during system development with regards to applying standards and ensured where necessary by additional protective circuitry. By the manufacturer suggested protective circuitry is for information only and given without responsibility and has to be verified within the actual system with respect to actual interferences. Item Symbol Parameter Conditions Fig. Unit Min. Max. G001 VCCA VCCD Supply Voltage -0.3 6 V G201 V(COM) Voltage at COM -0.3 49 V G202 Vact(IO) Voltage at IOx IOx= lo (* see below) G203 Idc(COM) Current in COM G204 Ipk(COM) Peakcurrent in COM = 2ms, T$ 2s 2 G205 Isc(COM) Free-Wheeling Current in COM -0.3 49 V -500 0 mA -1000 - mA -1.3 A -1 mA G206 Idc(COM) Current in IOx G207 Ipk(IOx) Peakcurrent in IOx IOx= lo, = 2ms, T$ 2s G208 Ipsc (Iox) Peakcurrent in IOx IOx= lo, Overload current protection 2 -1.3 G301 V(IOx) Voltage at IO0..3, IO4..7 IBL= 0, IBH= 0 (current source 200µA) -0.3 49 V G302 V(IOx) Voltage at IO0..3, IO4..7 IBL= 1, IBH= 1 (current source 2mA) -0.3 26 V -0.3 49 V -50 50 mA -20 20 mA 25 mA -100 100 mA 2 kV = 2ms, T$ 2s G401 Imx (VCCD) Current in VCCD, GNDD G402 Ic() Current in Clamping Diodes at CSN, WRN, RDN, A0, A1, D0..7, RESN, CLK, BLFQ G402 I() Current in D0..7,INTN D0..7 set to outputs G404 Ilu() Peakcurrent in CSN, WRN, RDN, A0, A1, D0..7, RESN, CLK, BLFQ, INTN (Latch-Up Strength) pulse duration # 10µs EG1 Vd() ESD Susceptibility, all Inputs and Outputs HBM 100pF discharged through 1.5k D0..7 set to inputs -1 600 mA A TG1 Tj Junction Temperature -40 150 EC TG2 Ts Storage Temperature -40 150 EC (*) IOx= lo : pin set to output, active low, x 0 0..7 THERMAL DATA Operating Conditions: VCC= VCCA= VCCD= 5V ±10% Item Symbol Parameter T1 Ta Operating Ambient Temperature Range T2 Rthja Thermal Resistance Chip to Ambient Conditions Fig. Unit Min. Typ. 0 PLCC44 surface mounted on PCB All voltages are referenced to ground unless otherwise noted. All currents into the device pins are positive; all currents out of the device pins are negative. Max. 70 55 EC K/W iC-VRV BIDIRECTIONAL µP INTERFACE TO 24V Rev A2, Page 8/12 ELECTRICAL CHARACTERISTICS Operating Conditions: VCC= VCCA= VCCD= 5V ±10%, Tj= 0..125°C, unless otherwise noted Item Symbol Parameter Conditions Tj Fig. °C Unit Min. Typ. Max. Total Device 001 VCCA VCCD Permissible Supply Voltage Range 002 I(VCCA) Supply Current in VCCA, power section IO0..7= lo, unloaded 0 27 70 125 4.5 5.5 V 5 5 5 5 65 60 55 55 mA mA mA mA 0 10 mA 003 I(VCCD) Supply Current in VCCD, digital section all logic inputs lo= 0V or hi= VCC 004 I(VCCD) Supply Current in VCCD, digital section all logic inputs lo= 0.8V 80 mA 005 I(VCCD) Supply Current in VCCD, digital section all logic inputs lo= 2.0V 100 mA Bias, Thermal Shutdown and Low Voltage Detection 101 VCCon Turn-on Threshold VCC 3.6 4 4.4 V 102 VCCoff Undervoltage Threshold at VCC decreasing Supply VCC 3.5 3.9 4.3 V 103 VCChys Hysteresis VCChys= VCCon-VCCoff 40 100 250 mV 104 Toff Thermal Shutdown Threshold 120 135 150 EC 105 Thys Thermal Shutdown Hysteresis 4 8 12 EC 100 µA 1.5 V Thys= Toff - Ton I/O Stages: Low-side Driver 201 Ilk(COM) Leakage Current in COM V(COM)= 25V, V(IOx)= 0V 202 Vf(COM) Forward Voltage of the FreeWheeling Diodes Vf()= V(IOx)-V(COM); I(IOx6COM)= 100mA, IOx= hi or set to Inputs 203 Vs(IO) Saturation Voltage lo at IOx I(IOx)= 10mA, IO0..7= lo 1 0.4 V 204 Vs(IO) Saturation Voltage lo at IOx I(IOx)= 100mA, IO0..7= lo 1 0.6 V 205 Vs(IO) Saturation Voltage lo at IOx for pulse load I(IOx)= 500mA, IO0..7= lo, = 2ms, T$ 2s 1 1.5 V 206 Ioff(IO) Threshold Current in IOx for Overcurrent Cut-off IOx= lo, V(IOx)= 0..25V 0.5 1.3 A 207 Ion(IO) Free-Wheeling Current I(IOx6COM) for Cut-off release IOx= lo, V(IOx)= 0..25V 0.1 20 mA 208 f(IO) Cut-off Oscillation Frequency depends on Load 0.1 20 MHz 209 Iav(IO) Mean Current in IOx during Cut-off IOx= lo, V(IOx)= 0..25V 50 700 mA 0.5 iC-VRV BIDIRECTIONAL µP INTERFACE TO 24V Rev A2, Page 9/12 ELECTRICAL CHARACTERISTICS Operating Conditions: VCC= VCCA= VCCD= 5V ±10%, Tj= 0..125°C, unless otherwise noted Item Symbol Parameter Conditions Tj °C Fig. Unit Min. Typ. Max. I/O Stages: Comparator 301 Idwn(IO) Pull-down Current in IOx V(IOx)= 3..48V, IBL= 0, IBH= 0, IO0..7= hi or set to Inputs 120 200 280 µA 302 Idwn(IO) Pull-down Current in IOx V(IOx)= 3..25V, IBL= 1, IBH= 1, IO0..7= hi or set to Inputs 1.4 2 2.6 mA 303 V0(IO) IOx open, IO0..7= hi or set to Inputs 1 V Open-Circuit Voltage at IOx 304 Vt()hi Threshold Voltage hi at IOx 305 Vt()lo Threshold Voltage lo at IOx 4.6 3 V V µP-Interface, I/O-Logic, Frequency Divider, Interrupt 401 Ilk(Dx) Leakage Current in Dx 402 Ilk(Dx) Leakage Current in Schmitt Trigger Inputs CSN, WRN, RDN, A0, A1, RESN, CLK, BLFQ D0..7 set to Inputs -5 5 µA -1 1 µA 403 Vt()hi Threshold Voltage hi at Schmitt D0..7 set to Inputs Trigger Inputs CSN, WRN, RDN, A0, A1, RESN, CLK, BLFQ, D0..7 2.3 V 404 Vt()lo Threshold Voltage lo at Schmitt D0..7 set to Inputs Trigger Inputs CSN, WRN, RDN, A0, A1, RESN, CLK, BLFQ, D0..7 0.7 V 405 Vt()hys Hysteresis at Schmitt Trigger Vt()hys= Vt()hi-Vt()lo; Inputs CSN, WRN, RDN, A0, A1, D0..7 set to Inputs RESN, CLK, BLFQ, D0..7 0.3 V 406 Vs()hi Saturation Voltage hi at INTN Vs()hi= VCCD-V(INTN); INTN=hi, I(INTN)= -100µA 0.2 V 407 Vs()hi Saturation Voltage hi at INTN Vs()hi= VCCD-V(INTN); INTN=hi, I(INTN)= -2mA 0.8 V 408 Vs()lo Saturation Voltage lo at INTN INTN= lo, I(INTN)= 100µA 0.2 V 409 Vs()lo Saturation Voltage lo at INTN INTN= lo, I(INTN)= 2mA 0.49 V 410 Vs(Dx)hi Saturation Voltage hi at Dx Vs(Dx)hi= VCCD-V(Dx); Dx= hi, I(Dx)= -100µA 0.2 V 411 Vs(Dx)hi Saturation Voltage hi at Dx Vs(Dx)hi= VCCD-V(Dx); Dx= hi, I(Dx)= -4mA 0.8 V 412 Vs(Dx)lo Saturation Voltage lo at Dx Dx= lo, I(Dx)= 100µA 0.2 V 413 Vs(Dx)lo Saturation Voltage lo at Dx Dx= lo, I(Dx)= 4mA 0.49 V 414 Vc()hi Clamp Voltage hi at Vc()hi= V()-VCC, CSN, WRN, RDN, A0, A1, RESN, I()= 20mA CLK,BLFQ, D0..7, INTN, CERR 0.4 2.5 V 415 Vc()lo Clamp Voltage lo at I()= -20mA CSN, WRN, RDN, A0, A1, RESN, CLK, BLFQ, D0..7, INTN, CERR -1.8 -0.4 V iC-VRV BIDIRECTIONAL µP INTERFACE TO 24V Rev A2, Page 10/12 ELECTRICAL CHARACTERISTICS Operating Conditions: VCC= VCCA= VCCD= 5V ±10%, Tj= 0..125°C, unless otherwise noted Item Symbol Parameter Conditions Tj °C Fig. Unit Min. Typ. Max. Switching Characteristics 501 tc(CLK) Permissible Cycle Duration CLK 400 ns 502 tw(CLK) Permissible Pulse Width lo at CLK 200 ns 503 tc(BLFQ) Permissible Cycle Duration BLFQ 100 ms 504 tw(BLFQ) Permissible Pulse Width lo at BLFQ 50 ms 505 tphl() Propagation Delay until IOx= lo Write Cycle, WRN: hi6lo 2 µs 506 tplh() Propagation Delay until IOx= off Write Cycle, WRN: hi6lo 3 µs 507 tp()Ion Current Source Enable Time at IOx Write Cycle, WRN: hi6lo 5 µs 508 tp()Ioff Current Source Disable Time at IOx Write Cycle, WRN: hi6lo 5 µs 509 tp(IOx6 up/dwn) Propagation Delay Input IOx to Up/Dwn Filter Input 5 µs ELECTRICAL CHARACTERISTICS: WAVEFORMS I IOxpeak IOxdc T Figure 1: DC load Figure 2: Pulse load, Pulse duration 2 ms t iC-VRV BIDIRECTIONAL µP INTERFACE TO 24V Rev A2, Page 11/12 OPERATING REQUIREMENTS: µP INTERFACE Operating Conditions: VCC= VCCA= VCCD= 5V ±10%, Ta= 0..70EC, CL()= 150pF, input levels lo= 0..0.45V, hi= 2.4V..VCC, see Fig. 3 for reference levels and waveforms Item Symbol Parameter Conditions Fig. Unit Min. Max. Data Word Read Timing I1 tAR Setup Time: CSN, A0, A1 set before RDN hi6lo 4 30 ns I2 tRA Hold Time: CSN, A0, A1 stable after RDN lo6hi 4 10 ns I3 tRD Read Data Access Time: Data valid after RDN hi6lo 4 120 ns I4 tDF Read Data Hold Time: Ports high impedance after RDN lo6hi 4 65 ns I5 tRW Recovery Time between Read/Write Cycles 4 165 ns Data Word Write Timing I6 tAW Setup Time: CSN, A0, A1 set before WRN hi6lo 4 30 ns I7 tDW Write Data Setup Time: Data valid before WRN lo6hi 4 100 ns I8 tWA Hold Time: CSN, A0, A1 stable after WRN lo6hi 4 10 ns I9 tWD Write Data Hold Time: Data valid after WRN lo6hi 4 10 ns Figure 3: Reference levels Figure 4: Data word read/write timing iC-Haus expressly reserves the right to change its products and/or specifications. An info letter gives details as to any amendments and additions made to the relevant current specifications on our internet website www.ichaus.com/infoletter; this letter is generated automatically and shall be sent to registered users by email. Copying B even as an excerpt B is only permitted with iC-Haus approval in writing and precise reference to source. iC-Haus does not warrant the accuracy, completeness or timeliness of the specification on this site and does not assume liability for any errors or omissions in the materials. The data specified is intended solely for the purpose of product description. No representations or warranties, either express or implied, of merchantability, fitness for a particular purpose or of any other nature are made hereunder with respect to information/specification or the products to which information refers and no guarantee with respect to compliance to the intended use is given. In particular, this also applies to the stated possible applications or areas of applications of the product. iC-Haus conveys no patent, copyright, mask work right or other trade mark right to this product. iC-Haus assumes no liability for any patent and/or other trade mark rights of a third party resulting from processing or handling of the product and/or any other use of the product. As a general rule our developments, IPs, principle circuitry and range of Integrated Circuits are suitable and specifically designed for appropriate use in technical applications, such as in devices, systems and any kind of technical equipment, in so far as they do not infringe existing patent rights. In principle the range of use is limitless in a technical sense and refers to the products listed in the inventory of goods compiled for the 2008 and following export trade statistics issued annually by the Bureau of Statistics in Wiesbaden, for example, or to any product in the product catalogue published for the 2007 and following exhibitions in Hanover (Hannover-Messe). We understand suitable application of our published designs to be state-of-the-art technology which can no longer be classed as inventive under the stipulations of patent law. Our explicit application notes are to be treated only as mere examples of the many possible and extremely advantageous uses our products can be put to. iC-VRV BIDIRECTIONAL µP INTERFACE TO 24V Rev A2, Page 12/12 ORDERING INFORMATION Type Package Order designation iC-VRV PLCC44 iC-VRV PLCC44 For technical support, information about prices and terms of delivery please contact: iC-Haus GmbH Am Kuemmerling 18 D-55294 Bodenheim GERMANY Tel +49 (6135) 9292-0 Fax +49 (6135) 9292-192 Web: http://www.ichaus.com E-Mail: [email protected] Appointed local distributors: http://www.ichaus.de/support_distributors.php