IS31LT3932 High PF universal LED Driver General Description Preliminary Features IS31LT3932 is a universal LED driver, which can operate in fly-back, buck-boost and buck convertor. For isolation fly-back, it can achieve high PF, high current accuracy, ± 5 % load and line regulation and wide voltage input voltage range, without loop compensation. For buck convertor, it also can achieve high PF, high current accuracy, high efficiency, good load and line regulation and wide voltage input voltage range, without loop compensation. with very few components. IS31LT3932 has special power line sense and output voltage sense circuits, operates in primary feedback mode without opto-coupler and achieve stable output current control without any loop compensation. IS31LT3932 has multiple protections to improve the system reliability, including LED open circuit, LED short circuit, UVLO, OVP, current sense resistor short, the primary over current limit and over temperature protections. Application LED bulb LED Tube lamp LED PAR Universal isolation and non-isolation Single stage PFC fly-back No loop compensation required No opto-coupler required ± 3 %LED current accuracy ± 5 % line regulation and load regulation Wide input voltage: 85~265Vac Low start-up current(15uA) Valley turn-on MOSFET to achieve high efficiency for buck application Few external components 1A sourcing current and 2A sinking current multiple protections SOP-8 package Typical Operating Circuit Fuse BD TR D1 LED1 C1 Vin D3 R5 C3 C6 R3 R9 D2 LEDn R1 U1 VCC C2 R2 3932 Q1 GATE VSINE CS CT OPT FB GND Rcs R4 D4 D5 C4 R8 R6 C5 R7 Figure 1 Typical isolated Operating Circuit Integrated Silicon Solution, Inc. – www.issi.com Rev. A, 8/14/2013 1 IS31LT3932 Pin Configurations Package Top View SOP-8 Pin Descriptions Pin Name 1 VSINE 2 OPT Function Power line voltage detection Isolation and non-isolation option PIN Floating: fly-back and buck-boost Resistor to ground: buck sinusoidal Time setting through the resistor between PIN and ground Isolation: operation cycle time setting f = 50k × 3 CT 300 VFB × 0.8V Rct (kΩ) Non-isolation: MOS turn-off delay time setting when FB detects zero voltage Tdelay = 15 × 10 −6 × REXT 4 GND Ground 5 FB Fly-back and buck-boost: operation frequency is regulated through this PIN to compensate output current Non-isolation: valley turn-on detect PIN, the external MOS turns on after a short delay when FB detects zero voltage 6 CS Inductor Current sense 7 GATE Driver output to the external Power MOS 8 VCC Power supply input PIN, at a range of 7V~30V Ordering Information Order Part No. Package QTY/Reel IS31LT3932-GRLS2-TR SOP-8, Lead-free 2500 Integrated Silicon Solution, Inc. – www.issi.com Rev. A, 8/14/2013 2 IS31LT3932 Absolute Maximum Ratings Parameter Value VDD,GATE to GND -0.3 - 33.0 VSINE, OPT, CT, ISEN, FB to GND -0.3 - 6.0 Operation Temperature Range(TA=TJ) -40 - 125 Junction Temperature Range -40 - 150 Storage Temperature Range -65 -150 （Hum an Body M ode） ESD 2000 VDD,GATE to GND -0.3 - 33.0 Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other condition beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Electrical Characteristics(Unless otherwise specified, VCC=16V, FB=0V, VSINE=2.5V, RSET=300KΩ, and Tamb=25 oC) Symbol Parameter VDD Power Supply Range VOVP VDD Over Voltage Threshold TOVP OVP Reset Time Ust Startup Voltage Vuvlo Under Voltage Lockout Condition Unit 30 V V 160 15 16.5 ms 18 V 7 TFB,OVP FB OVP Reset Time Tcycle=20us Quiescent Current VDD=16V Startup Current VDD=10V IOP Max 34 FB PIN Over voltage threshold IIN,ST Type 8 VFB,OVP IIN Min ，w Operation Current V 160 ms 700 1000 uA 15 20 uA 600 800 uA 500 505 mV VCSTH Peak Current Voltage Threshold VOCP Over Current Voltage Threshold 700 mV TOCP OCP Reset Time 40 ms 600 ns TBLANK TOFF_MIN Tcycle VGATE,MAX Isource Isink TP 495 1.25 Current Sense Blanking Time VCS=VCSTH+50mV Minimum TOFF Time OPT=0 0.7 VFB=0.8V, RCT=300KΩ Operating Cycle（ note1） VFB=1.04V, RCT=300KΩ VFB=0.56V, RCT=300KΩ GATE output clamp voltage VDD=20V 17.5 V Sourcing Current Vgate=0V 0.22 A Sinking Current Vgate=16V 0.57 A Thermal Shutdown Threshold 1 1.3 us 19.8 20 20.2 us 15.0 15.4 15.8 us 28.2 28.6 29.0 us 150 o C △TP Thermal Shutdown Hysteresis 50 o Tre ISEN Short Protection Reset Time 40 ms Integrated Silicon Solution, Inc. – www.issi.com Rev. A, 8/14/2013 C 3 IS31LT3932 Typical Performance Characteristics (Vin=85~265Vac,Vout=14~30Vdc,Iout=190mA) Figure 4 PF Figure 5 load regulation Figure 6 line regulation Figure 7 THD vs LEDs Figure 8 efficiency vs Vin(Vac) Integrated Silicon Solution, Inc. – www.issi.com Rev. A, 8/14/2013 4 IS31LT3932 Block Diagram Figure 9 Block Diagram Integrated Silicon Solution, Inc. – www.issi.com Rev. A, 8/14/2013 5 IS31LT3932 Application Information (base on Figure 18 Typical Application Circuit) Startup voltage When the VCC pin of the IS31LT3932 reaches 16.5V, the IC is allowed to start. After power is applied to the circuit, R6 and R10 provides a trickle current to allow C9 to begin charging. The IC starts working when the voltage of C9 reaches the start threshold for the IC. The value of R6 and R10 & C9 can be determined by the input voltage. Larger values of R6 and R10 increase the startup time, but reduce the losses after the circuit is running. A low ESR capacitor of 10uF, 50V is recommended for C9. VCC GATE VCC Figure 12 gate clamp GATE VSINE detection network and active PFC The voltage of VSINE pin is used to control the waveform of input current make it follow the input voltage waveform, so can get the high PF and low THD. As Figure 11: Figure 10 startup Soft start control When the device get start the threshold voltage of CS form low level go to 0.5V step by step. Vbulk Ip-pk VCC Ip-pk Figure 13 active PFC Figure 11 soft start GATE output voltage clamp IS31LT3932 has the voltage clamp for GATE output. When the voltage of VCC smaller than the VGATEclp threshold, The voltage of GATE output is about VCC. When the voltage of VCC is greater than VGATEclp threshold, the voltage of GATE is VGATEclp threshold. Integrated Silicon Solution, Inc. – www.issi.com Rev. A, 8/14/2013 The input pin, VSINE is used to detect the input voltage which controls the peak current waveform in the inductor and inside AGC makes the peak current of inductor constant, this allows the IS31LT3932 to actively correct the power factor and constant power during operation. The maximum input voltage of the VSINE pin is 2.5V. This resistor network should be computed such that the peak input voltage condition corresponds to ~2.4VDC. Thus, for 265VAC, the peak voltage is 374.7V. At 374.7V input, the output of the network should be 2.4V, thus values of R5+R9=2M and R18 = 13k are appropriate. High tolerance 6 IS31LT3932 resistors of 1% should be used. A small, 1nF capacitor, C7, is used to filter high frequency noise. Working Frequency The working frequency is set by connecting a resistor between the FSET pin and ground. The relationship between the frequency and resistance is: f = 50k × VFB 250 × 1V RCT (kΩ) Output open circuit protection Open circuit protection is realized by connecting a resistor network to the FB pin. By sensing the voltage of the auxiliary winding, which is proportional to the output voltage, the IS31LT3932 detects when there is an open circuit condition on the secondary and stop the switching action. The threshold voltage for the FB pin is 1.25V. VCC VCC GATE Figure 15 Output short circuit protect UVLO protection The device will not operate if the VCC voltage is below the under-voltage lockout threshold. Until the VCC voltage get startup threshold, the device start again. CS over current and maximum duty cycle protection If the CS pin is shorted to ground, the device can no longer detect the peak current of the inductor, and thus will quickly cause damage to the power MOS, inductor, or other circuit components. The maximum duty cycle of the gate is limited to 62.5% internally to prevent a shorted CS pin from going into current runaway. when the duty cycle greater than 62.5% the gate will turn off 80ms. GATE Figure 14 OVP Output short circuit protection If the output of the circuit is suddenly shorted, the voltage of the secondary winding is quickly reduced. This in-turn reduces the reflected voltage in the auxiliary winding, so VCC of the device drops rapidly. If the VCC voltage drops below the UVLO, the device will stop switching, thus indirectly achieving output short circuit protection. In addition to the duty cycle limit protection, there is also an inductor over current protection. If a fault condition exists wherein the inductor current continues to increase cycle per cycle, this would eventually cause the inductor into an over current condition. However, if the Vcs pin rises to 0.7V, the NMOS will immediately be shut off by the driving the gate low for a period of 40ms, after which the device will attempt a restart. Load regulation Frequency control is controlled by the FB pin voltage, when the FB pin voltage in the range of 0.5~1.25V, the control voltage is proportional to the frequency and FB, when the FB voltage is less than 0.5V, the frequency remained unchanged. Because the auxiliary winding voltage and the output voltage is the transformer turns ratio relationship, the FB pin detection auxiliary winding voltage, so, FB voltage follower output voltage changes, namely control frequency following the change of output voltage, in order to achieve constant output current. Transformer design Integrated Silicon Solution, Inc. – www.issi.com Rev. A, 8/14/2013 7 IS31LT3932 The transformer technique is the other document of ISSI, here please use the “3932 calculator” to design the transformer. PCB design considerations (1) As Figure 30 and 31 shows, Components such as C7,R17,R18,R20,R21,R22,R23,C9etc. Which are connected to the IC should be mounted as close to the IC as possible. (2) Bypass capacitors should always be mounted as close to the IC as possible. (3) Switching signal traces should be kept as short as possible and not be routed parallel to one another so as to prevent coupling. Figure 16 typical PCB top layer out Figure 17 typical PCB bottom layer out Integrated Silicon Solution, Inc. – www.issi.com Rev. A, 8/14/2013 8 IS31LT3932 Typical Application Circuit (It is suited to full input voltage 15~30V-0.2A output applications) R2 5.1kΩ R1 NC BD1 MB6S C1 NC D6 1N4007 L1 3.3mH F1 LED+ L2 3.3mH L3 3.3mH Vin C1 100nF R5 1MΩ R6 300kΩ TR EE16 R3 300kΩ C2 1nF 1kV D1 SB5200 C3 220uF 50V D2 FR107 C4 220uF 50V C5 NC R8 NC D7 39V R10 300kΩ R13 5.1kΩ R9 1MΩ LED- U1 IS31LT3932 VCC R18 13kΩ C7 1nF R17 240kΩ Q1 2N60 GATE VSINE CS CT OPT FB GND D4 1N4148 R21 NC R20 1.0Ω R22 240kΩ D5 ES1J R7 200Ω C10 1uF C9 10uF R23 10kΩ CY 1nF 1kV Figure 18 Typical isolated application schematic R2 5.1kΩ BD1 MB6S D6 1N4007 L1 3.3mH F1 Vin TR EE16 L2 3.3mH L3 3.3mH LEDC1 100nF R5 1MΩ R3 150kΩ C2 1nF 1kV R6 300kΩ R1 NC C3 220uF 50V D2 FR107 C5 NC R8 NC D7 39V C1 NC R10 300kΩ R13 5.1kΩ C4 220uF 50V R9 1MΩ LED+ U1 IS31LT3932 VCC R18 13kΩ C7 1nF R17 240kΩ GATE VSINE CS CT OPT FB GND D4 1N4148 C9 10uF Q1 2N60 R20 1.0Ω R22 240kΩ D5 ES1J D1 SB5200 R21 NC R7 200Ω C10 1uF R23 10kΩ . Figure 19 Typical non-isolated application schematic Integrated Silicon Solution, Inc. – www.issi.com Rev. A, 8/14/2013 9 IS31LT3932 Classification Reflow Profiles Profile Feature Pb-Free Assembly Preheat & Soak Temperature min (Tsmin) Temperature max (Tsmax) Time (Tsmin to Tsmax) (ts) 150°C 200°C 60-120 seconds Average ramp-up rate (Tsmax to Tp) 3°C/second max. Liquidous temperature (TL) Time at liquidous (tL) 217°C 60-150 seconds Peak package body temperature (Tp)* Max 260°C Time (tp)** within 5°C of the specified classification temperature (Tc) Max 30 seconds Average ramp-down rate (Tp to Tsmax) 6°C/second max. Time 25°C to peak temperature 8 minutes max. Classification Profile Integrated Silicon Solution, Inc. – www.issi.com Rev. A, 8/14/2013 10 IS31LT3932 Tape and Reel Information Integrated Silicon Solution, Inc. – www.issi.com Rev. A, 8/14/2013 11 IS31LT3932 Package Information Integrated Silicon Solution, Inc. – www.issi.com Rev. A, 8/14/2013 12