IS31LT3938 Preliminary High Voltage LED Lighting Driver with Three Level Power Sequencing Features General Description IS31LT3938 LED driver IC is a peak current detection buck converter which operates in constant off time mode. It operates over a very wide input voltage supply range of 10VDC to 450VDC or 110VAC/220VAC. IS31LT3938 incorporates the special feature of three power sequencing levels by detecting OFF-ON cycles of the main power switch. When the switch is cycled within a 4 second period (typical) the device automatically switches the power level to the next step. As a result, the input and output power of the luminaire may be adjusted depending on the desired amount of illumination and/or power consumption. There are multiple power levels that the engineer may configure, 2 steps or 3 steps, via the external pins DIM1 and DIM2. IS31LT3938 can also realize LED dimming using an external PWM signal. It can accept a PWM signal from 0% to 100% duty cycle. The LED current may also be adjusted linearly by applying an analog input voltage in the range of 0.5V to 2.5V. IS31LT3938 adopts a peak current mode control architecture, which eliminates the need for any additional loop compensation while maintaining a good degree of constant output current regulation. User configurable power sequencing levels 3% output current accuracy Over current, temperature protection and short circuit protection High efficiency (typical up to 95%) Higher MOS drive voltage Wide input voltage range: 10VDC~450VDC or 85Vac~ 265Vac Linear and PWM dimming Very few external components Applications DC/DC or AC/DC constant current LED driver Signal and decorative lighting Backlight LED driver Typical Application Circuit LED+ Switch K D1 D2 D5 RIN C3 LED- IS3938 VIN AC Input C1 DIM1 CIN Fuse D3 L1 Q1 Gate CS DIM2 ADJ GND TOFF RCS D4 REXT Copyright © 2011 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances Integrated Silicon Solution, Inc. – www.issi.com R0.1, 04/25/2012 1 IS31LT3938 Preliminary Pin Configuration Package Pin Configurations SOP-8 Pin Description Pin Name Pin Number DIM1 1 DIM2 2 ADJ 3 GND GATE CS 4 5 6 TOFF 7 VIN 8 Description These two pins configure the power sequencing levels as follows: DIM1=“floating”DIM2=“floating”, no dimming (100% only)； DIM1=“floating”DIM2=“GND” , 100%-30%-100% DIM1=“GND”DIM2=“floating”, 100%-50%-100% DIM1=“GND”DIM2=“GND”, 100%-50%-20%-100% Linear and PWM dimming input pin. Linear dimming range: 0.5V to 2.5V. If VADJ < 0.5V, GATE output is off. If 0.5V ≤ VADJ ≤ 2.5V, VCSTH = VADJ/10. If VADJ > 2.5V, VCSTH = 0.25V. when the pin is floating, there is an internal pull up to 4.5V (typical) and VCSTH = 0.25V. Recommended PWM dimming frequency range: 200Hz -1kHz. Ground pin. All internal currents return through this pin. This pin connects to the external NMOS’s gate Current detect pin, uses an external resistor to sense the peak inductor current. This pin sets the off time for the switch by connecting a resistor between this pin and GND. 10V – 450V supply voltage is connected to this pin via an external resistor. It is internally clamped and must be bypassed using a capacitor to GND. ORDERING INFORMATION INDUSTRIAL RANGE: -40°C TO +85°C Order Part No. Package QTY/Reel IS31LT3938–GRLS2-TR SOP-8, Lead-free 2500 Integrated Silicon Solution, Inc. – www.issi.com R0.1, 04/25/2012 2 IS31LT3938 Preliminary Absolute Maximum Ratings Parameter Range VIN pin to GND DIM1,DIM2,CS, ADJ, GATE, TOFF pin to GND VIN pin input current (Note1) Operating Junction temperature(TA=TJ) Junction temperature Device storage temperature ESD（Human Body model） Unit -0.3 - 13.0 -0.3 - 6.0 10 -40 - 125 -40 - 150 -65 - 150 2000 V V mA o C o C o C V Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Electrical Characteristics (The specifications are at TA=25°C and VINDC=20V (Note2), RIN =10K, unless otherwise noted) (Note3) Symbol Parameter Conditions Supply voltage connected to VIN via an appropriate resistor Min Typ Unit 450 V 10 V VINDC Input DC supply voltage range Vclamp VIN pin clamp voltage UVLO Undervoltage lockout △UVLO UVLO hysteresis IIN Quiescent Current VIN=Vclamp, Gate floating 450 600 uA IIN,UV Input current in UVLO VIN= UVLO 200 300 uA VCSTH Current sense threshold ADJ=5V 250 255 mV TBLANK Current sense blanking time VCS=VCSTH+50mV 500 ns TOFF Off time REXT=250KΩ 10 us PWM input voltage high threshold 2.5 V PWM input voltage low threshold 0.5 V VADJ (Note 4) 8 VIN falling Linear dimming input voltage range GATE rises from 0.1*Vclamp to 0.9*Vclamp GATE falls from 0.9*Vclamp to 0.1*Vclamp Tr Tf TP 10 Max 245 VOCP TOFF_reset TMAX Over temperature protection hysteresis Over current protection CS voltage threshold Over current protection TOFF delay time Maximum switch off time for power level sequencing 7 V 1.6 V 0.5 2.5 V CGATE=1nF 50 80 ns CGATE=1nF 50 80 ns Over temperature protection threshold △ TP 9 ADJ=5V 150 o C 20 o C 0.4 2.8 4 V 5.2 ms 4 s Note1: Beyond the input current range, VIN pin may not clamp at 9V(typical). Note 2: VINDC is the input voltage. When VINDC>9V, input voltage connected to VIN pin should via a appropriate resistor. Note 3: Production testing of the chip is performed at 25°C. Functional operation of the chip and parameters specified are guaranteed by design, characterization and process control in other temperature Note 4: When VADJ>2.5V, Iout is 100% output current. When VADJ<0.5V, Iout is shutdown. When 0.5V ≤VADJ≤2.5V, Iout is linear dimming. Integrated Silicon Solution, Inc. – www.issi.com R0.1, 04/25/2012 3 IS31LT3938 Preliminary Application Information IS31LT3938 is a peak current control LED driver IC. It Input Voltage Regulation does not require any high side current sensing nor the When supplying a voltage larger than 9V, an external design of any closed loop control, yet provides a very resistor must be used between the input voltage and accurate constant LED drive current. IS31LT3938 the VIN pin. Bypass the VIN pin using a low ESR includes an input allowing either a PWM or an analog capacitor to provide a high frequency path to GND. The dimming signal. current required by the device is 0.45mA plus the The VIN pin is internally clamped to 9V (typical). switching current of the external switch. The switching An external resistor connected to the TOFF pin frequency of the external NMOS affects the amount of determines the internal oscillator’s constant off time. current required, as does the NMOS’s gate charge The off time adds to the on time, controlled by the requirement (found on the NMOS data sheet). internal switching control logic, to set the oscillation IIN 0.45mA QG fS frequency. The inductor current increases when the switch is on. This current also flows through the In the above equation, fS is the switching frequency, QG external current sense resistor RCS, and when the is the external NMOS gate charge (from the NMOS voltage across RCS reaches the current sense threshold, datasheet). VCSTH or 1/10 of the ADJ input voltage, whichever is lower, the switch turns off. The current through the Current Detection inductor will continue to flow through the LEDs, but will The CS pin input voltage is internally provided to 2 decrease linearly during the switch off time. After the comparators. One of the comparators uses an internal programmed off-time, the switch will turn on again. A 250mV reference, while the other uses a scaled value short blanking time of 500ns (typical) is implemented to of the ADJ pin voltage. The outputs of the comparators block the voltage spike encountered across RCS, are ORed, thus causing the lower of the 2 thresholds to caused by the parasitic capacitance of the switch trigger the switch control logic. At the moment the discharging. After the blanking time the control logic switch control logic changes the gate signal to low, the again compares the CS input voltage to the current TOFF timer is started. The external switch will remain sense threshold. off for the length of time programmed, and once the TOFF time is expired, the switch control logic again Choose the acceptable level of ripple current coefficient, toggles the gate signal, this time from low to high, and K，then calculate the value of the current sense resistor: the external switch turns on. As the external switch RCS VCSTH (1 K / 2) I LED VCSTH: If VADJ < 0.5V, GATE output is off. If 0.5V ≤ VADJ ≤ 2.5V, VCSTH = VADJ/10. If VADJ > 2.5V, VCSTH = 0.25V. When ADJ pin is floating, there is an internal pull up to 4.5V (typical) and VCSTH = 0.25V. K: acceptable current ripple coefficient, the recommended value range is 1~1.8。 A constant off-time peak current control scheme can easily operate at duty cycles greater than 0.5 and also gives inherent input voltage rejection making the LED current almost insensitive to input voltage variations. Integrated Silicon Solution, Inc. – www.issi.com R0.1, 04/25/2012 turns on, the parasitic capacitance on the drain of the switch must discharge through the switch channel causing a spike of current which can be quite large, but only lasts for a very short period of time. To prevent this current from causing a false triggering of the current sense comparators, the signal is blocked from the internal comparators for 500ns (typical). In some special cases, the 500ns blanking time may not be sufficient to prevent false triggering of the CS threshold logic. Under these circumstances, an additional RC filter may be added to the CS input pin to help filter the voltage spike. Careful layout of the PCB to minimize parasitic capacitance, trace resistance and inductance greatly aid in the elimination of false triggering. 4 IS31LT3938 Preliminary Oscillator is no switchable power levels, and the output IS31LT3938’s TOFF pin controls the off time of the current is 100% of the programmed value when the internal oscillator. Oscillator off time is determined by power is on. the following equation: 2. When DIM1 is floating and DIM2 is GND, the output current is： Toff ( s ) 40 10 12 REXT a) 100% at power on. REXT：resistor connected between TOFF and GND b) The first power sequencing action causes the Switchable Power Levels c) A second power sequencing action causes the current to change to 30%. current to return to 100%. IS31LT3938 detects the external switch action of the main power switch, and can automatically adjust the d) A third power sequencing action has the same level of the output current based on the action of the effect as the first power sequencing action. e) Subsequent power sequencing actions causes main power switch. the cycle to continue. 3. When DIM1 is GND and DIM2 is floating, the dimming sequence is as described in (2) above, except that the current sequence is 100%-50%-100%. The action of the external power switch can be divided 4. When both DIM1 and DIM2 are connected to GND, into two types. The first is “normal switch operation” the dimming sequence is as described in (2) above, wherein the switch is toggled from ON to OFF, except remaining OFF for longer than 4 seconds (typical). The 100%-50%-20%-100%. that the current sequence is other is “power sequencing action” wherein the switch If the switch is operated normally, that is, switched on is toggled from ON to OFF and back ON within 4 once after being in the OFF position for a long time, or if seconds (typical). both the DIM1 and DIM2 pins are floating, then the When the device experiences normal switch operation, output current always starts up at the initial value of it merely powers on in the first state, 100%, when the 100%. power switch is toggled to ON, and the device turns off Note: Because the main power switch is used to initiate when the external power switch is changed to OFF. the power sequencing function, the device must have a Power sequencing output current levels are configured large enough external capacitor on VIN to maintain by connecting the DIM1 and DIM2 pins as indicated in device operation for 4 seconds. the table below： Linear Dimming DIM1 DIM2 Power sequencing levels An external voltage, 0.5V to 2.5V, connected to the ADJ Floating Floating No Power Sequencing pin can adjust the LED current. Two possible situations Floating GND 2 levels：100%-30%-100% where this might be used are： GND Floating 2 levels：100%-50%-100% If it is not possible to change the value of RCS to obtain GND GND 3 levels：100%-50%-20%-100% the desired value of LED current, an external voltage reference can be connected to the ADJ pin to adjust the When operating the power switch normally the device voltage sense level across RCS, equivalent to changing will always power up at 100% output current. the value of RCS. The operation of the power switch and the configuration Connecting a resistor between the VIN and ADJ pin, of the DIM1 and DIM2 pins control the power then connecting a thermistor from the ADJ pin to GND sequencing process as follows： can adjust the LED current based on temperature, thus 1. When DIM1 and DIM2 pins are both floating, there Integrated Silicon Solution, Inc. – www.issi.com R0.1, 04/25/2012 realizing the temperature compensation feature. 5 IS31LT3938 Preliminary PWM Dimming PWM signal does not shut down other circuit blocks of PWM dimming may be realized by applying a low the device, thus the response to the PWM signal is frequency PWM waveform to the ADJ pin. When the relatively fast, and primarily determined by the rise and PWM signal is low, less than 0.5V, the IS31LT3938 fall time of the inductor current. remains off；When the PWM signal is high, greater than To disable PWM dimming, leave the ADJ pin floating. 2.5V, the driver is enabled and operates normally. Integrated Silicon Solution, Inc. – www.issi.com R0.1, 04/25/2012 The 6 IS31LT3938 Preliminary Application Example Input Voltage： Vin = 220V DC I RIPPLE K 1 I LED 2 2 I PEAK I LED Output：Vo=40V（12 x 1W LEDs in series, Vf=3.3V） Because of ADJ pin floating, VCSTH=0.25V. Assuming a ILED=0.35A typical value for K of 1.8. No Power sequencing levels The current sense resistor is given by： 1. VIN power supply circuit RCS VIN supply current is given by: VCSTH VCSTH 0.25 0.376Ω 1 .8 K I PEAK 1 I LED 1 0.35 2 2 IIN 0.45mA QG f s Choose RCS=0.38Ω and 1% precision. Assuming IIN=1mA, 4. Inductor（L1） The inductance of inductor L1 is dependent on the LED then RIN Vin VIN 220 9 211K I IN 1 Choose two 430KΩ/0.5W in parallel for the resistor lifetime consideration. Choose CIN: 10uF/25V ceramic capacitor. current, in this case 350mA. We have already chosen TOFF=15.6uS, thus: L VO TOFF VO TOFF 40 15.6 10 6 1mH I Ripple K I LED 1.8 0.35 Where Iripple is the design target for ripple current. 2. Constant off time（TOFF） Note: The saturation of inductor must be higher than Off time is given by： the peak current. Toff ( s ) 40 10 12 REXT 5. Freewheeling diode (D5) and NMOS (Q1) To decide the off time, assume the desired switching Choose Q1 to have a voltage rating at least as large as frequency is 50kHz(period time T=20uS), and the duty the peak voltage of the maximum input voltage with cycle: D Vo 40 18.18% Vin 220 approximately 50% margin. VNMOS 150% 2 Vin the duty cycle is decided by the ratio of the output voltage and input voltage, then TOFF: The current through the NMOS is based on the peak TOFF T (1 D) 20uS (1 18.18%) 16.36uS , LED current, choose FET current rating with 50% so REXT =409K , choose the closest resistor, REXT margin. =390KΩ, the actual TOFF=15.6uS(Because the actual TOFF is smaller than theoretical TOFF, the operating I NMOS 150% I PEAK frequency will be little higher than 50KHz). Thus, choose 600V, 2A, NMOS, such as: 2N60 3. Current Sense Resistor（RCS） The diode ratings are equal to that of the NMOS, Q1. The ripple current: I RIPPLE K I LED , K is the ripple Note: The diode must be a superfast recovery diode current coefficient, the recommended value range is than 50nS. Thus, choose 600V, 1A, superfast recovery 1~1.8. diode, such as: ES1J, SF18 and the Reverse Recovery Time (TRR) should be less The peak current : Integrated Silicon Solution, Inc. – www.issi.com R0.1, 04/25/2012 7 IS31LT3938 Preliminary Appendix: Typical application circuit of DC voltage input Integrated Silicon Solution, Inc. – www.issi.com R0.1, 04/25/2012 8 IS31LT3938 Preliminary Classification Reflow Profiles Profile Feature Preheat & Soak Pb-Free Assembly 150°C Temperature min (Tsmin) 200°C Temperature max (Tsmax) 60-120 seconds Time (Tsmin to Tsmax) (ts) Average ramp-up rate (Tsmax to Tp) Liquidous temperature (TL) 3°C/second max. 217°C Time at liquidous (tL) 60-150 seconds Peak package body temperature (Tp)* Time (tp)** within 5°C of the specified classification temperature (Tc) Average ramp-down rate (Tp to Tsmax) Time 25°C to peak temperature Max 260°C Max 30 seconds 6°C/second max. 8 minutes max. Classification Profile Integrated Silicon Solution, Inc. – www.issi.com R0.1, 04/25/2012 9 IS31LT3938 Preliminary Tape and Reel Information Integrated Silicon Solution, Inc. – www.issi.com R0.1, 04/25/2012 10 IS31LT3938 Preliminary Package Information SOP-8 g n i w a r D e n i l t u O e g a k c a P 8 0 D # 51 7 2 . . 00 0 74 2 . . 0 1 0 07 1 . . 4 5 00 0 8 .. 4 3 00 2 8 . . 6 5 80 C S B 7 2 . 1 13 5 3 . . 0 0 50 2 1 . . 0 0 53 5 7 . . 11 55 5. 3 . 1 1 Integrated Silicon Solution, Inc. – www.issi.com R0.1, 04/25/2012 11