IXYS IXDN514D1TR

Preliminary Technical Information
IXDI514 / IXDN514
14 Ampere Low-Side Ultrafast MOSFET Drivers
Features
General Description
• Built using the advantages and compatibility
of CMOS and IXYS HDMOSTM processes
• Latch-Up Protected over entire Operating Range
• High Peak Output Current: 14A Peak
• Wide Operating Range: 4.5V to 30V
• -55°C to +125°C Extended Operating
Temperature
• High Capacitive Load
Drive Capability: 15nF in <30ns
• Matched Rise And Fall Times
• Low Propagation Delay Time
• Low Output Impedance
• Low Supply Current
• Two Drivers in Single Chip
The IXDI514 and IXDN514 are high speed high current gate
drivers specifically designed to drive the largest IXYS
MOSFETs & IGBTs to their minimum switching time and
maximum parctical frequency limits. The IXDI514 and
IXDN514 can source and sink 14 Amps of Peak Current
while producing voltage rise and fall times of less than
30ns. The inputs of the Drivers are compatible with TTL or
CMOS and are virtually immune to latch up over the entire
operating range! Patented* design innovations eliminate
cross conduction and current "shoot-through". Improved
speed and drive capabilities are further enhanced by very
quick & matched rise and fall times.
Applications
•
•
•
•
•
•
•
•
•
•
Driving MOSFETs and IGBTs
Motor Controls
Line Drivers
Pulse Generators
Local Power ON/OFF Switch
Switch Mode Power Supplies (SMPS)
DC to DC Converters
Pulse Transformer Driver
Class D Switching Amplifiers
Power Charge Pumps
The IXDI514 is configured as a Inverting Gate Driver, and the
IXDN514 is configured as a Non-Inverting Gate Driver.
The IXDI514 and IXDN514 are each available in the 8-Pin PDIP (PI) package, the 8-Pin SOIC (SIA) package, and the
6-Lead DFN (D1) package, (which occupies less than 65%
of the board area of the 8-Pin SOIC).
*United States Patent 6,917,227
Ordering Information
Part Number
Description
IXDI514PI
IXDI514SIA
IXDI514SIAT/R
IXDI514D1
IXDI514D1T/R
IXDN514PI
IXDN514SIA
IXDN514SIAT/R
IXDN514D1
IXDN514D1T/R
14A Low Side Gate Driver I.C.
14A Low Side Gate Driver I.C.
14A Low Side Gate Driver I.C.
14A Low Side Gate Driver I.C.
14A Low Side Gate Driver I.C.
14A Low Side Gate Driver I.C.
14A Low Side Gate Driver I.C.
14A Low Side Gate Driver I.C.
14A Low Side Gate Driver I.C.
14A Low Side Gate Driver I.C.
Package
Type
8-Pin PDIP
8-Pin SOIC
8-Pin SOIC
6-Lead DFN
6-Lead DFN
8-Pin PDIP
8-Pin SOIC
8-Pin SOIC
6-Lead DFN
6-Lead DFN
Packing Style
Tube
Tube
13” Tape and Reel
2” x 2” Waffle Pack
13” Tape and Reel
Tube
Tube
13” Tape and Reel
2” x 2” Waffle Pack
13” Tape and Reel
Pack
Qty
50
94
2500
56
2500
50
94
2500
56
2500
Configuration
Inverting
Non-Inverting
NOTE: All parts are lead-free and RoHS Compliant
DS99672(01/07)
Copyright © 2006 IXYS CORPORATION All rights reserved
First Release
IXDI514 / IXDN514
Figure 1 - IXDI514 Inverting 14A Gate Driver Functional Block Diagram
Vcc
Vcc
P
ANTI-CROSS
CONDUCTION
CIRCUIT *
IN
OUT
N
GND
GND
Figure 2 - IXDN514 14A Non-Inverting Gate Driver Functional Block Diagram
Vcc
Vcc
P
ANTI-CROSS
CONDUCTION
CIRCUIT *
*
IN
GND
*
N
GND
United States Patent 6,917,227
Copyright © 2006 IXYS CORPORATION All rights reserved
OUT
2
IXDI514 / IXDN514
Absolute Maximum Ratings (1)
Operating Ratings (2)
Parameter
Supply Voltage
All Other Pins
Junction Temperature
Storage Temperature
Lead Temperature (10 Sec)
Parameter
Value
Operating Supply Voltage
4.5V to 30V
Operating Temperature Range
-55 °C to 125 °C
Package Thermal Resistance *
θJ-A (typ) 125 °C/W
8-PinPDIP
(PI)
8-Pin SOIC
(SIA)
θJ-A(typ) 200 °C/W
6-Lead DFN
(D1)
θJ-A(typ) 125-200 °C/W
θJ-C(max) 1.5 °C/W
6-Lead DFN
(D1)
6-Lead DFN
(D1)
θJ-S(typ) 5.8 °C/W
Value
35 V
-0.3 V to VCC + 0.3V
150 °C
-65 °C to 150 °C
300 °C
Electrical Characteristics @ TA = 25 oC (3)
Unless otherwise noted, 4.5V ≤ VCC ≤ 30V .
All voltage measurements with respect to GND. IXD_514 configured as described in Test Conditions.
Symbol
Parameter
Test Conditions
Min
VIH
High input voltage
4.5V ≤ VCC ≤ 18V
2.5
VIL
Low input voltage
4.5V ≤ VCC ≤ 18V
VIN
Input voltage range
IIN
Input current
VOH
High output voltage
VOL
Low output voltage
ROH
Output resistance
@ Output high
Output resistance
@ Output Low
Peak output current
IOUT = 10mA, VCC = 18V
tR
Continuous output
current
Rise time
Limited by package power
dissipation
CL=15nF Vcc=18V
23
tF
Fall time
CL=15nF Vcc=18V
tONDLY
VCC
On-time propagation
delay
Off-time propagation
delay
Power supply voltage
ICC
Power supply current
ROL
IPEAK
IDC
tOFFDLY
0V ≤ VIN ≤ VCC
Typ(4)
Max
Units
V
1.0
V
-5
VCC + 0.3
V
-10
10
µA
VCC - 0.025
V
0.025
V
600
1000
mΩ
IOUT = 10mA, VCC = 18V
600
1000
mΩ
VCC is 18V
14
A
4
A
25
40
ns
21
22
50
ns
CL=15nF Vcc=18V
29
30
30
ns
CL=15nF Vcc=18V
29
31
50
ns
4.5
18
30
V
1
0
3
10
10
mA
µA
µA
VIN = 3.5V
VIN = 0V
VIN = + VCC
IXYS reserves the right to change limits, test conditions, and dimensions.
3
IXDI514 / IXDN514
Electrical Characteristics @ temperatures over -55 oC to 125 oC (3)
Unless otherwise noted, 4.5V ≤ VCC ≤ 30V , Tj < 150oC
All voltage measurements with respect to GND. IXD_502 configured as described in Test Conditions. All specifications are for one channel.
Symbol
Parameter
Test Conditions
Min
VIH
High input voltage
4.5V ≤ VCC ≤ 18V
2.7
VIL
Low input voltage
4.5V ≤ VCC ≤ 18V
VIN
Input voltage range
IIN
Input current
VOH
High output voltage
VOL
Low output voltage
ROH
tR
Output resistance
@ Output high
Output resistance
@ Output Low
Continuous output
current
Rise time
CL=10,000pF Vcc=18V
tF
Fall time
tONDLY
0V ≤ VIN ≤ VCC
Typ (4)
Max
Units
V
0.8
V
-5
VCC + 0.3
V
-10
10
µA
VCC - 0.025
V
0.025
V
VCC = 18V
1.25
Ω
VCC = 18V
1.25
Ω
1
A
23
100
ns
CL=10,000pF Vcc=18V
30
100
ns
CL=10,000pF Vcc=18V
20
60
ns
CL=10,000pF Vcc=18V
40
60
ns
VCC
On-time propagation
delay
Off-time propagation
delay
Power supply voltage
18
30
V
ICC
Power supply current
VIN = 3.5V
VIN = 0V
VIN = + VCC
1
0
3
10
10
mA
µA
µA
ROL
IDC
tOFFDLY
4.5
Notes:
1. Operating the device beyond the parameters listed as “Absolute Maximum Ratings” may cause permanent
damage to the device. Exposure to absolute maximum rated conditions for extended periods may affect device
reliability.
2. The device is not intended to be operated outside of the Operating Ratings.
3. Electrical Characteristics provided are associated with the stated Test Conditions.
4. Typical values are presented in order to communicate how the device is expected to perform, but not necessarily
to highlight any specific performance limits within which the device is guaranteed to function.
Copyright © 2006 IXYS CORPORATION All rights reserved
4
IXDI514 / IXDN514
* The following notes are meant to define the conditions for the θJ-A, θJ-C and θJ-S values:
1) The θJ-A (typ) is defined as junction to ambient. The θJ-A of the standard single die 8-Lead PDIP and 8-Lead SOIC are dominated by the
resistance of the package, and the IXD_5XX are typical. The values for these packages are natural convection values with vertical boards
and the values would be lower with natural convection. For the 6-Lead DFN package, the θJ-A value supposes the DFN package is soldered
on a PCB. The θJ-A (typ) is 200 °C/W with no special provisions on the PCB, but because the center pad provides a low thermal resistance
to the die, it is easy to reduce the θJ-A by adding connected copper pads or traces on the PCB. These can reduce the θJ-A (typ) to 125 °C/W
easily, and potentially even lower. The θJ-A for DFN on PCB without heatsink or thermal management will vary significantly with size,
construction, layout, materials, etc. This typical range tells the user what he is likely to get if he does no thermal management.
2) θJ-C (max) is defined as juction to case, where case is the large pad on the back of the DFN package. The θJ-C values are generally not
published for the PDIP and SOIC packages. The θJ-C for the DFN packages are important to show the low thermal resistance from junction to
the die attach pad on the back of the DFN, -- and a guardband has been added to be safe.
3) The θJ-S (typ) is defined as junction to heatsink, where the DFN package is soldered to a thermal substrate that is mounted on a heatsink.
The value must be typical because there are a variety of thermal substrates. This value was calculated based on easily available IMS in the
U.S. or Europe, and not a premium Japanese IMS. A 4 mil dialectric with a thermal conductivity of 2.2W/mC was assumed. The result was
given as typical, and indicates what a user would expect on a typical IMS substrate, and shows the potential low thermal resistance for the
DFN package.
Pin Description
SYMBOL
FUNCTION
VCC
Supply Voltage
IN
Input
OUT
Output
GND
Ground
DESCRIPTION
Positive power-supply voltage input. This pin provides power to the
entire chip. The range for this voltage is from 4.5V to 30V.
Input signal-TTL or CMOS compatible.
Driver Output. For application purposes, this pin is connected,
through a resistor, to Gate of a MOSFET/IGBT.
The system ground pin. Internally connected to all circuitry, this pin
provides ground reference for the entire chip. This pin should be
connected to a low noise analog ground plane for optimum
performance.
CAUTION: Follow proper ESD procedures when handling and assembling this component.
Figure 3 - Characteristics Test Diagram
5.0V
10uF
25V
0V
IXDI414
IXDI514
Vcc
IXD_514
0V
Vcc
0V
IXDN414
IXDN514
2500
pf
15nF
Agilent 1147A
Current Probe
5
IXDI514 / IXDN514
Figure 4 - Timing Diagrams
Inverting (IXDI514) Timing Diagram
5V
90%
INPUT 2.5V
10%
0V
PWMIN
tONDLY
tF
tOFFDLY
tR
VCC
90%
OUTPUT
10%
0V
Non-Inverting (IXDN514) Timing Diagram
5V
90%
INPUT 2.5V
10%
0V
PWMIN
tONDLY
tOFFDLY
tR
Vcc
90%
OUTPUT
10%
0V
IXYS reserves the right to change limits, test conditions, and dimensions.
Copyright © 2006 IXYS CORPORATION All rights reserved
6
tF
IXDI514 / IXDN514
Typical Performance Characteristics
Fig. 5
Fig. 6
Rise Time vs. Supply Voltage
30
30
Fall Time vs. Supply Voltage
Fall Time (ns)
40
Rise Time (ns)
40
CL=15,000 pF
CL=15,000 pF
20
20
7,500 pF
10
3,600 pF
10
7,500 pF
3,600 pF
0
0
8
10
12
14
16
8
18
10
12
Fig. 7
40
14
16
18
Supply Voltage (V)
Supply Voltage (V)
Rise And Fall Times vs. Case Temperature
CL = 15 nF, Vcc = 18V
Fig. 8
Rise Time vs. Load Capacitance
50
35
8V
40
tR
12V
Rise Time (ns)
Time (ns)
30
10V
25
tF
20
15
30
18V
14V 16V
20
10
10
5
0
-40
-20
0
20
40
60
80
100
0
0k
120
10k
15k
20k
Load Capacitance (pF)
Temperature (°C)
Fig. 9
5k
Fig. 10
Fall Time vs. Load Capacitance
Max / Min Input vs. Case Temperature
VCC=18V CL=15nF
3.2
40
3.0
Fall Time (ns)
30
8V
10V
Max / Min Input (V)
14V 12V
16V 18V
20
Minimum Input High
2.8
2.6
2.4
2.2
Maximum Input Low
2.0
10
1.8
0
0k
1.6
-60
5k
10k
15k
20k
-40
-20
0
20
40
o
Temperature ( C)
Load Capacitance (pF)
7
60
80
100
IXDI514 / IXDN514
Fig. 11
Supply Current vs. Load Capacitance
Vcc=18V
Supply Current vs. Frequency
Vcc=18V
Fig. 12
1000
CL= 30 nF
Supply Current (mA)
Supply Current (mA)
1000
100 2 MHz
1 MHz
500 kHz
10
100 kHz
15 nF
100
5000 pF
10
2000 pF
1
50 kHz
1
1k
0.1
10k
10
100k
Load Capacitance (pF)
Fig. 13
Supply Current vs. Load Capacitance
Vcc=12V
Fig. 14
1000
1000
10000
Supply Current vs. Frequency
Vcc=12V
1000
Supply Current (mA)
Supply Current (mA)
100
Frequency (kHz)
100
2 MHz
1 MHz
500 kHz
10
CL = 30 nF
100
15 nF
5000 pF
10
2000 pF
1
100 kHz
50 kHz
1
1k
0.1
10k
10
100k
Fig. 15
Supply Current vs. Load Capacitance
Vcc=8V
1000
10000
Supply Current vs. Frequency
Vcc=8V
Fig. 16
1000
Supply Current (mA)
1000
Supply Current (mA)
100
Frequency (kHz)
Load Capacitance (pF)
100
2 MHz
1 MHz
10 500 kHz
CL= 30 nF
100
15 nF
10
5000 pF
2000 pF
1
100 kHz
1 50 kHz
1k
0.1
10k
10
100k
Copyright © 2006 IXYS CORPORATION All rights reserved
100
Frequency (kHz)
Load Capacitance (pF)
8
1000
10000
IXDI514 / IXDN514
Fig. 17
50
tOFFDLY
40
Propagation Delay (ns)
Propagation Delay (ns)
50
Propagation Delay vs. Input Voltage
CL=15nF VCC=15V
Fig. 18
Propagation Delay vs. Supply Voltage
CL=15nF [email protected]
tONDLY
30
20
40
tONDLY
30
tOFFDLY
20
10
10
0
0
8
10
12
14
16
2
18
4
6
Fig. 19
Propagation Delay vs. Case Temperature
CL = 2500pF, VCC = 18V
12
VCC=18V [email protected]
0.60
Quiescent Supply Current (mA)
45
tONDLY
40
Time (ns)
10
Fig. 20 Quiescent Supply Current vs. Case Temperature
50
35
tOFFDLY
30
25
20
15
0.58
0.56
0.54
0.52
0.50
10
-40
-20
0
20
40
60
80
100
-40
120
-20
0
Fig. 21
20
40
60
80
Temperature (oC)
Temperature (°C)
P Channel Output Current vs. Case Temperature
VCC=18V CL=.1uF
Fig. 22 N Channel Output Current vs. Case Temperature
VCC=18V CL=.1uF
16
17
N Channel Output Current (A)
P Channel Output Current (A)
8
Input Voltage (V)
Supply Voltage (V)
15
14
13
16
15
14
12
-40
-20
0
20
40
60
80
-40
100
-20
0
20
40
Temperature (oC)
Temperature (oC)
9
60
80
100
IXDI514 / IXDN514
Fig. 23
Fig. 24
Enable Threshold vs. Supply Voltage
14
High State Output Resistance (Ohm)
1.0
Enable Threshold (V)
12
10
8
6
4
2
0.8
0.6
0.4
0.2
0.0
0
8
10
12
14
16
18
20
22
24
8
26
10
Low-State Output Resistance
vs. Supply Voltage
Fig. 25
15
20
25
Supply Voltage (V)
Supply Voltage (V)
Fig. 26
1.0
VCC vs. P Channel Output Current
CL=.1uF [email protected]
0
-2
P Channel Output Current (A)
Low-State Output Resistance (Ohms)
High State Output Resistance
vs. Supply Voltage
0.8
0.6
0.4
0.2
-4
-6
-8
-10
-12
-14
-16
-18
-20
-22
-24
0.0
8
10
15
20
25
8
Supply Voltage (V)
Fig. 27
Vcc vs. N Channel Output Current
CL=.1uF [email protected]
N Channel Output Current (A)
22
20
18
16
14
12
10
8
6
4
2
0
10
15
15
20
Vcc
24
8
10
20
25
Vcc
Copyright © 2006 IXYS CORPORATION All rights reserved
10
25
IXDI514 / IXDN514
PIN CONFIGURATIONS
8 PIN DIP (PI)
8 PIN SOIC (SIA)
1
VCC
IN
2
NC
3
GND
4
I
X
D
I
5
1
4
8 PIN DIP (PI)
8 PIN SOIC (SIA)
8
VCC
7
OUT
IN
2
6
OUT
NC
3
5
GND
GND
4
VCC
1
I
X
D
N
5
1
4
6 LEAD DFN (D1)
(Bottom View)
VCC 6
OUT 5
GND
4
I
X
D
I
5
1
4
8
VCC
7
OUT
6
OUT
5
GND
6 LEAD DFN (D1)
(Bottom View)
1 IN
VCC 6
2 N/C
OUT 5
3 GND
GND
4
I
X
D
N
5
1
4
1 IN
2 N/C
3 GND
NOTE: Solder tabs on bottoms of DFN packages are grounded
Supply Bypassing, Grounding Practices And Output Lead inductance
GROUNDING
In order for the design to turn the load off properly, the IXD_514
must be able to drain this 5A of current into an adequate
grounding system. There are three paths for returning current
that need to be considered: Path #1 is between the IXD_514
and its load. Path #2 is between the IXD_514 and its power
supply. Path #3 is between the IXD_514 and whatever logic is
driving it. All three of these paths should be as low in resistance
and inductance as possible, and thus as short as practical. In
addition, every effort should be made to keep these three
ground paths distinctly separate. Otherwise, the returning
ground current from the load may develop a voltage that would
have a detrimental effect on the logic line driving the IXD_514.
When designing a circuit to drive a high speed MOSFET
utilizing the IXD_514, it is very important to observe certain
design criteria in order to optimize performance of the driver.
Particular attention needs to be paid to Supply Bypassing,
Grounding, and minimizing the Output Lead Inductance.
Say, for example, we are using the IXD_514 to charge a 5000pF
capacitive load from 0 to 25 volts in 25ns.
Using the formula: I= ∆V C / ∆t, where ∆V=25V C=5000pF &
∆t=25ns, we can determine that to charge 5000pF to 25 volts
in 25ns will take a constant current of 5A. (In reality, the charging
current won’t be constant, and will peak somewhere around
8A).
OUTPUT LEAD INDUCTANCE
Of equal importance to Supply Bypassing and Grounding are
issues related to the Output Lead Inductance. Every effort
should be made to keep the leads between the driver and its
load as short and wide as possible. If the driver must be placed
farther than 2” (5mm) from the load, then the output leads
should be treated as transmission lines. In this case, a twistedpair should be considered, and the return line of each twisted
pair should be placed as close as possible to the ground pin
of the driver, and connected directly to the ground terminal of the
load.
SUPPLY BYPASSING
In order for our design to turn the load on properly, the IXD_514
must be able to draw this 5A of current from the power supply
in the 25ns. This means that there must be very low impedance
between the driver and the power supply. The most common
method of achieving this low impedance is to bypass the power
supply at the driver with a capacitance value that is an order of
magnitude larger than the load capacitance. Usually, this
would be achieved by placing two different types of bypassing
capacitors, with complementary impedance curves, very close
to the driver itself. (These capacitors should be carefully
selected and should have low inductance, low resistance and
high-pulse current-service ratings). Lead lengths may radiate
at high frequency due to inductance, so care should be taken
to keep the lengths of the leads between these bypass
capacitors and the IXD_514 to an absolute minimum.
11
IXDI514 / IXDN514
PRELIMINARYTECHNICALINFORMATION
The product presented herein is under development.
The Technical Specifications offered are derived from
data gathered during objective characterizations of
preliminary engineering lots; but also may yet contain
some information supplied during a pre-production
design evaluation. IXYS reserves the right to change
limits, test conditions, and dimensions without notice.
A2
b
b2
b3
c
D
D1
E
E1
e
eA
eB
L
E
H
B
C
D
E
e
H
h
L
M
N
D
A
A1
e
B
h X 45
N
L
C
]
0.018 [0.47]
0.137 [3.48]
IXYS Corporation
3540 Bassett St; Santa Clara, CA 95054
Tel: 408-982-0700; Fax: 408-496-0670
e-mail: [email protected]
www.ixys.com
0.120 [3.05]
0.020 [0.51]
[
S0.002^0.000; o S0.05^0.00;o
0.039 [1.00]
0.035 [0.90]
0.157±0.005 [3.99±0.13]
0.197±0.005 [5.00±0.13]
0.019 [0.49]
M
0.100 [2.54]
IXYS Semiconductor GmbH
Edisonstrasse15 ; D-68623; Lampertheim
Tel: +49-6206-503-0; Fax: +49-6206-503627
e-mail: [email protected]
Copyright © 2006 IXYS CORPORATION All rights reserved
12