CMF20120D-Silicon Carbide Power MOSFET 1200V 80 mΩ Z-FET™ MOSFET Rev. CMF20120D N-Channel Enhancement Mode Subject to change without notice. www.cree.com/power 1 CMF20120D-Silicon Carbide Power MOSFET Z-FET™ MOSFET N-Channel Enhancement Mode VDS = 1200 V RDS(on) = 80 mΩ ID(MAX)@TC=25°C = 33 A Features • • • • • • Package D D Industry Leading RDS(on) High Speed Switching Low Capacitances Easy to Parallel Simple to Drive Pb-Free Lead Plating, ROHS Compliant, Halogen Free G G SS TO-247-3 Benefits • • • • Higher System Efficiency Reduced Cooling Requirements Avalanche Ruggedness Increased System Switching Frequency Part Number Package CMF20120D TO-247-3 Applications • • • Solar Inverters High Voltage DC/DC Converters Motor Drives Maximum Ratings Symbol ID Continuous Drain Current IDpulse Value 33 17 Unit A Test Conditions VGS@20V, TC = 25˚C VGS@20V, TC = 100˚C Pulse width tP limited by Tjmax Pulsed Drain Current 78 A EAS Single Pulse Avalanche Energy 2.2 J ID = 20A, VDD = 50 V, L = 9.5 mH EAR Repetitive Avalanche Energy 1.5 J tAR limited by Tjmax IAR Repetitive Avalanche Current 20 A VGS Gate Source Voltage -5/+25 V Ptot Power Dissipation 150 W -55 to +125 ˚C ˚C TJ , Tstg 2 Parameter Operating Junction and Storage Temperature TL Solder Temperature 260 Md Mounting Torque 1 8.8 CMF20120D Rev. - TC = 25˚C ID = 20A, VDD = 50 V, L = 3 mH tAR limited by Tjmax TC=25˚C 1.6mm (0.063”) from case for 10s Nm M3 or 6-32 screw lbf-in Note Table of Contents Features.................................................................................................................2 Benefits...........................................................................................................2 Applications.....................................................................................................2 Maximum Ratings...................................................................................................2 Table of Contents....................................................................................................3 Applications Information........................................................................................4 ESD Ratings............................................................................................................7 Electrical Characteristics........................................................................................8 Reverse Diode Characteristics.................................................................................8 Thermal Characteristics..........................................................................................8 Gate Charge Characteristics....................................................................................8 Typical Performance..............................................................................................................9 Clamped Inductive Switch Testing Fixture..............................................................11 Package Dimensions.............................................................................................12 Recommended Solder Pad Layout..........................................................................13 Notice..............................................................................................................14 3 CMF20120D Rev. - Applications Information The Cree SiC MOSFET has removed the upper voltage limit of silicon MOSFETs. However, there are some differences in characteristics when compared to what is usually expected with high voltage silicon MOSFETs. These differences need to be carefully addressed to get maximum benefit from the SiC MOSFET. In general, although the SiC MOSFET is a superior switch compared to its silicon counterparts, it should not be considered as a direct drop-in replacement in existing applications. There are two key characteristics that need to be kept in mind when applying the SiC MOSFETs: modest transconductance requires that VGS needs to be 20 V to optimize performance. This can be see in the Output and Transfer Characteristics shown in Figures 1-3. The modest transconductance also affects the transition where the device behaves as a voltage controlled resistance to where it behaves as a voltage controlled current source as a funtion of VDS. The result is that the transition occurs over higher values of VDS than are usually experienced with Si MOSFETs and IGBTs. This might affect the operation anti-desaturation circuits, especially if the circuit takes advantage of the device entering the constant current region at low values of forward voltage. The modest transconductance needs to be carefully considered in the design of the gate drive circuit. The first obvious requirement is that the gate be capable of a >22 V (+20 V to -2V) swing. The recommended on state VGS is +20 V and the recommended off state VGS is between -2 V to -5 V. Please carefully note that although the gate voltage swing is higher than the typical silicon MOSFETs and IGBTs, the total gate charge of the SiC MOSFET is considerably lower. In fact, the product of gate voltage swing and gate charge for the SiC MOSFET is lower than comparable silicon devices. The gate voltage must have a fast dV/dt to achieve fast switching times which indicates that a very low impedance driver is necessary. Lastly, the fidelity of the gate drive pulse must be carefully controlled.2.5V The nominal threshold voltage is 2.5V and the device is not fully on (dVDS/dt≈0) until the VGS is above 16V. This is a noticeably wider range than what is typically experienced with silicon MOSFETs and IGBTs. The net result of this is that the SiC MOSFET has a somewhat lower ‘noise margin’. Any excessive ringing that is present on the gate drive signal could cause unintentional turn-on or partial turn-off of the device. The gate resistance should be carefully selected to ensure that the gate drive pulse is adequately dampened. To first order, the gate circuit can be approximated as a simple series RLC circuit driven by a voltage pulse as shown below. 4 CMF20120D Rev. - RLOOP ζ = LLOOP RLOOP CGATE ≥1 2 LLOOP VPULSE CGATE ∴ RLOOP ≥ 2 LLOOP CGATE minimizes the value of RLOOP needed As shown, minimizing LLOOP for critical dampening. Minimizing L also minimizes the rise/fall time. Therefore, it is LOOP strongly recommended that the gate drive be located as close to the SiC MOSFET MOSFET as possible to minimize LLOOP. The internal gate resistance of the SiC is 5 Ω. An external resistance of 6.8 Ω was used to characterize this device. Lower values of external gate resistance can be used so long as the gate fidelity is maintained. In the event that no external gate resistance is used, it is suggested that the gate current be checked to indirectly verify that there is no ringing present in the gate circuit. This can be accomplished with a very small current transformer. A recommended setup is a two-stage current transformer as shown below: IG SENSE VCC GATE DRIVER GATE DRIVE INPUT + T1 SiC DMOSFET VEE 5 CMF20120D Rev. - Stray inductance on source lead causes load di/dt to be fed back into gate drive which causes the following: • Switch di/dt is limited • Could cause oscillation Kelvin gate connection with separate source return is highly recommended LOAD CURRENT 20V 20V R GATE R GATE DRIVE SiC DMOS DRIVE SiC DMOS LOAD CURRENT L STRAY L STRAY A schematic of the gate driver circuit used for characterization of the SiC MOSFET is shown below: THESE COMPONENTS ARE LOCATED ON THE -VEE PLANE +VCC +VCC THESE COMPONENTS ARE LOCATED ON THE GND PLANE C1 10u -VEE C2 100n C3 10u -VEE C4 100n GND -VEE C5 +VCC C6 10u R1 C7 1 10u C10 100n IN OUT 2 1 -VEE GND U1 LM2931T-5.0 -VEE -VEE 100n 3 -VEE 100n C11 100u 6.3V R2 C13 J1 BNC C12 100n 390 -VEE 10n ISO1 C8 PIN 1 SOURCE C9 PULSE GEN INPUT -VEE D1 R3 R4 2 R5 120 R6 120 8 330 7 6 2 3 3 5 C14 6N137 PIN 2 GATE U2 1 4 100n VCC IN VCC OUT NC OUT GND GND TBD 1206 8 RB160M-60 7 R7 6 TBD 1206 5 D2 R8 IXDI414 -VEE TBD 1206 -VEE -VEE C15 RB160M-60 J2 BNC 100n -VEE C16 100n -VEE 1 VGS MONITOR 2 1 2 100n +VCC C17 100n -VEE C18 100n -VEE C19 100n -VEE C20 10u -VEE The gate driver is an IXYS IXDI414. This device has a 35 V ouput swing, output resistance of 0.6 Ω typical, and a peak current capability of 14 A. The external gate resistance used for characterization of the SiC MOSFET was 6.8 Ω. Careful consideration needs to be given to the selection of the gate driver. The typical application error is selection of a gate driver that has adequate swing, but output 6 CMF20120D Rev. - resistance and current drive capability are not carefully considered. It is critical that the gate driver possess high peak current capability and low output resistance along with adequate voltage swing. A significant benefit of the SiC MOSFET is the elimination of the tail current observed in silicon IGBTs. However, it is very important to note that the current tail does provide a certain degree of parasitic dampening during turn-off. Additional ringing and overshoot is typically observed when silicon IGBTs are replaced with SiC MOSFETs. The additional voltage overshoot can be high enough to destroy the device. Therefore, it is critical to manage the output interconnection parasitics (and snubbers) to keep the ringing and overshoot from becoming problematic. ESD RATINGS 7 ESD Test Total Devices Sampled Resulting Classification ESD-HBM All Devices Passed 1000V 2 (>2000V) ESD-MM All Devices Passed 400V C (>400V) ESD-CDM All Devices Passed 1000V IV (>1000V) CMF20120D Rev. - Electrical Characteristics Symbol V(BR)DSS VGS(th) Parameter Min. Drain-Source Breakdown Voltage IGSS Gate-Source Leakage Current Ciss Input Capacitance Coss Output Capacitance td(on)i tr td(off)i tfi 1 100 10 250 250 Drain-Source On-State Resistance Transconductance V 4 1.8 Zero Gate Voltage Drain Current Crss 1200 Gate Threshold Voltage gfs Max. Unit 2.5 IDSS RDS(on) Typ. 80 110 95 130 7.3 VDS = VGS, ID = 1mA, TJ = 25ºC V VDS = 1200V, VGS = 0V, TJ = 25ºC μA VDS = 1200V, VGS = 0V, TJ = 125ºC nA VGS = 20V, VDS = 0V VGS = 20V, ID = 20A, TJ = 25ºC mΩ VGS = 20V, ID = 20A, TJ = 125ºC VDS= 20V, IDS= 20A, TJ = 25ºC VDS= 20V, IDS= 20A, TJ = 125ºC VDS = 800V pF Rise Time 13.6 Turn-Off Delay Time VAC = 25mV VDD = 800V ns 62 Fall Time fig. 5 f = 1MHz 13 17.2 fig. 3 VGS = 0V 120 Turn-On Delay Time 1 VDS = VGS, ID = 1mA, TJ = 125ºC 1915 Reverse Transfer Capacitance Note VGS = 0V, ID = 100μA S 6.8 Test Conditions VGS = -2/20V ID = 20A 35.6 fig. 12 RG = 6.8Ω EON Turn-On Switching Loss (25ºC) (125ºC) 530 422 μJ EOff Turn-Off Switching Loss (25ºC) (125ºC) 320 329 μJ RG Internal Gate Resistance 5 Ω L = 856μH Per JEDEC24 Page 27 VGS = 0V, f = 1MHz, VAC = 25mV NOTES: 1. The recommended on-state VGS is +20V and the recommended off-state VGS is between -2V and -5V Reverse Diode Characteristics Symbol Parameter Vsd Diode Forward Voltage Typ. Max. Unit 3.5 V 3.1 trr Reverse Recovery Time 220 ns Qrr Reverse Recovery Charge 142 nC Irrm Peak Reverse Recovery Current 2.3 A Test Conditions VGS Note = -5V, IF=10A, TJ = 25ºC VGS = -2V, IF=10A, TJ = 25ºC VGS = -5V, IF=20A, TJ = 25ºC VR = 800V, diF/dt= 100A/μs fig. 13,14 Thermal Characteristics Symbol Parameter Typ. Max. 0.7 RθJC Thermal Resistance from Junction to Case 0.58 RθCS Case to Sink, w/ Thermal Compound 0.25 RθJA Thermal Resistance From Junction to Ambient Unit Test Conditions °C/W Note fig. 6 40 Gate Charge Characteristics Symbol 8 Parameter Typ. Qgs Gate to Source Charge 23.8 Qgd Gate to Drain Charge 43.1 Qg Gate Charge Total 90.8 CMF20120D Rev. - Max. Unit nC Test Conditions VDD = 800V ID =20A VGS = -2/20V Per JEDEC24-2 Note fig.9 Typical Performance 120 120 20V 100 V GS= V GS= V V 18 V GS= 80 20V 100 18 V GS= 80 6V 60 V GS 40 VGS=14V 60 ID (A) ID (A) VGS=1 =16V V VGS=14 40 VGS=12V VGS=12V 20 VGS=10V 20 VGS=10V 0 0 0 2 4 6 8 10 12 14 16 18 20 0 2 4 6 8 VDS (V) 10 12 14 16 18 20 VDS (V) Fig 1. Typical Output Characteristics TJ = 25ºC Fig 2. Typical Output Characteristics TJ = 125ºC 60 2 1.8 50 1.6 1.4 Normalized RDS(on) 40 ID (A) T = 125°C 30 20 1.2 1 VGS=20V 0.8 0.6 T = 25°C 0.4 10 0.2 0 0 2 4 6 8 10 12 14 16 18 0 20 0 VGS (V) 25 50 Figure 3. Typical Transfer Characteristics 1.0E-08 100 125 150 Fig 4. Normalized On-Resistance vs. Temperature 1.0E-08 VGS = 0 V f = 1 MHz VGS = 0 V f = 1 MHz Ciss Ciss 1.0E-09 1.0E-09 Capacitance (F) Capacitance (F) 75 T (oC) Coss 1.0E-10 Coss 1.0E-10 Crss Crss 1.0E-11 1.0E-11 0 20 40 60 80 100 VDS (V) 120 140 160 180 200 0 100 200 300 400 VDS (V) Fig 5A and 5B. Typical Capacitance vs. Drain – Source Voltage 9 CMF20120D Rev. - 500 600 700 800 Typical Performance 1.E+00 Zth (oC/W) 1.E-01 1.E-02 1.E-03 1.E-04 1.E-06 1.E-05 1.E-04 1.E-03 1.E-02 1.E-01 1.E+00 1.E+01 Time (s) Fig 6. Transient Thermal Impedence, Junction - Case Turn-off Loss 600 500 500 400 VGS= -2/20V RG= 11.8Ω Total VDD= 800V ID= 20A 300 200 Switching Loss (µJ) Switching Loss (µJ) Turn-on Loss 600 400 300 VGS= -2/20V RG= 11.8Ω Total VDD= 800V ID= 20A 200 100 100 0 0 0 25 50 75 Temp ( C) 100 125 150 Fig 7. Inductive Switching Energy(Turn-on) vs. T 0 25 50 75 Temp ( C) 100 125 150 Fig 8. Inductive Switching Energy(Turn-off) vs. T 25 25 2500 VDS 20 20 IDS VDD=800V 10 15 1500 10 1000 IDS (A) ID=20A VDS (V) 15 VGS (V) 2000 5 EAS = 2.20 J 5 500 0 0 -5 0 20 40 60 80 100 Gate Charge (nC) Fig 9. Typical Gate Charge Characteristics @ 25°C 10 CMF20120D Rev. - 0 0 0.001 0.002 0.003 Time (s) 0.004 0.005 0.006 Fig 10. Typical Avalanche Waveform Clamped Inductive Switch Testing Fixture tw pulse duration VGS(on) 90% 90% Input (Vi) 50% 50% 10% 856μH 10% VGS(off) C2D10120D 10A, 1200V SiC Schottky Input Pulse Fall Time Input Pulse Rise Time + 800V 42.3μf - td(on)i iD(on) CMF20120D D.U.T. tfi tri td(off)i 10% 10% Output (iD) 90% 90% iD(off) toff(i) ton(i) Fig 11. Switching Waveform Test Circuit Fig 12. Switching Test Waveform Times trr Qrr= id dt tx ∫ trr Ic tx 10% Irr 10% Vcc 856μH Vcc Vpk CMF20120D D.U.T. + Irr 800V - 42.3μf Diode Recovery Waveforms CMF20120D t2 Erec= id dt t1 ∫ Diode Reverse Recovery Energy t1 t2 Fig 13. Body Diode Recovery Waveform 11 CMF20120D Rev. - Fig 14. Body Diode Recovery Test EA = 1/2L x ID2 Fig 15. Avalanche Test Circuit Fig 16. Theoretical Avalanche Waveform Package Dimensions Package TO-247-3 POS D D D G G G 12 S SS CMF20120D Rev. - Inches Millimeters Min Max Min Max A .190 .205 4.83 5.21 A1 .090 .100 2.29 2.54 A2 .075 .085 1.91 2.16 b .042 .052 1.07 1.33 b1 .075 .095 1.91 2.41 b2 .075 .085 1.91 2.16 b3 .113 .133 2.87 3.38 b4 .113 .123 2.87 3.13 c .022 .027 0.55 0.68 D .819 .831 20.80 21.10 D1 .640 .695 16.25 17.65 D2 .037 .049 0.95 1.25 E .620 .635 15.75 16.13 E1 .516 .557 13.10 14.15 E2 .145 .201 3.68 5.10 E3 .039 .075 1.00 1.90 E4 .487 .529 12.38 13.43 e .214 BSC 5.44 BSC N 3 3 L .780 .800 19.81 20.32 L1 .161 .173 4.10 4.40 ØP .138 .144 3.51 3.65 Q .216 .236 5.49 6.00 S .238 .248 6.04 6.30 Recommended Solder Pad Layout TO-247-3 Part Number Package CMF20120D TO-247-3 “The levels of environmentally sensitive, persistent biologically toxic (PBT), persistent organic pollutants (POP), or otherwise restricted materials in this product are below the maximum concentration values (also referred to as the threshold limits) permitted for such substances, or are used in an exempted application, in accordance with EU Directive 2002/95/EC on the restriction of the use of certain hazardous substances in electrical and electronic equipment (RoHS), as amended through April 21, 2006. This product has not been designed or tested for use in, and is not intended for use in, applications implanted into the human body nor in applications in which failure of the product could lead to death, personal injury or property damage, including but not limited to equipment used in the operation of nuclear facilities, life-support machines, cardiac defibrillators or similar emergency medical equipment, aircraft navigation or communication or control systems, air traffic control systems, or weapons systems. Copyright © 2010-2011 Cree, Inc. All rights reserved. The information in this document is subject to change without notice. Cree, the Cree logo, Z-REC and Z-FET are registered trademarks of Cree, Inc. 13 CMF20120D Rev. - Cree, Inc. 4600 Silicon Drive Durham, NC 27703 USA Tel: +1.919.313.5300 Fax: +1.919.313.5451 www.cree.com/power