PRELIMINARY INFORMATION
L9D3256M32DBG2
L9D3512M32DBG2
16-32 Gb, DDR3, 256-512M x 32 Dual Channel Memory Module
Benefits
FEATURES
DDR3 Integrated Module [iMOD]:
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iMOD Part Information
ORDER NUMBER
SPEED GRADE
/'0'%*[
DDR3-1866
L9D3256M32DBG2x125
DDR3-1600
L9D3256M32DBG2x15
DDR3-1333
/'0'%*[
DDR3-1866
L9D3512M32DBG2x125
DDR3-1600
L9D3512M32DBG2x15
DDR3-1333
PKG FOOTPRINT
I/O
PITCH
PP[PP
PP
PKG NO.
BG2
integrated module products
LOGIC Devices Incorporated
www.logicdevices.com
1
High Performance, Integrated Memory Module Product
March 6, 2013 LDS-L9D3xxxM32DBG2
PRELIMINARY INFORMATION
L9D3256M32DBG2
L9D3512M32DBG2
16-32 Gb, DDR3, 256-512M x 32 Dual Channel Memory Module
FEATURES
FIGURE 1 - 1Gb DDR3 PART NUMBERS
Sample Part Number:
L9D3
256M
32D
L9D3256G32DBG2I107
BG2
107
I
DDR3 iMOD
Word = 256 MB
Code
Speed Grade
15
1.5ns / 667MHz
125
1.25ns / 800MHz
107
1.07ns / 933MHz
Wordwidth
x32
D = Dual Channel
16 x 22mm
PBGA
Temperature
Code
Commercial (0oC to 70oC)
C
Industrial (-40oC to 85oC)
I
o
o
Extended (-40 C to 105 C)
E
Military (-55oC to 125oC)
M
Note: Not all options can be combined. Please see our Part Catalog for available offerings.
TABLE 1: ADDRESSING
Parameter
2 x 256-512 Meg x 32
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8K
52:$GGUHVVLQJ
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256 M
LOGIC Devices Incorporated
www.logicdevices.com
2
512M
High Performance, Integrated Memory Module Product
March 6, 2013 LDS-L9D3xxxM32DBG2
PRELIMINARY INFORMATION
L9D3256M32DBG2
L9D3512M32DBG2
16-32 Gb, DDR3, 256-512M x 32 Dual Channel Memory Module
STATE DIAGRAM
FIGURE 2 - SIMPLIFIED STATE DIAGRAM
CKE L
Power
applied
Power
on
Reset
Procedure
MRS, MPR,
write
leveling
Initialization
Self
refresh
SRE
ZQCL
MRS
SRX
From any
state
RESET
ZQ
Calibration
REF
ZQCL/ZQCS
Idle
Refreshing
PDE
ACT
PDX
Active
PowerDown
Preharge
PowerDown
Activating
PDX
CKE L
CKE L
PDE
Bank
Active
WRITE
WRITE
READ
WRITE AP
READ AP
READ
Writing
READ
Reading
WRITE
READ AP
WRITE AP
WRITE AP
READ AP
PRE, PREA
Writing
PRE, PREA
Preharging
PRE, PREA
Reading
Automatic
Sequence
Command
Sequence
ACT = ACTIVATE
MPR = Multipurpose register
MRS = Mode register set
PDE = Power-down entry
PDX = Power-down exit
PRE = PRECHARGE
LOGIC Devices Incorporated
www.logicdevices.com
PREA=PRECHARGE ALL
READ = RD, RDS4, RDS8
READ AP = RDAP, RDAPS4, RDAPS8
REF = REFRESH
RESET = START RESET PROCEDURE
SRE = Self refresh entry
3
SRX = Self refresh exit
WRITE = WR, WRS4, WRS8
WRITE AP = WRAP, WRAPS4, WRAPS8
ZQCL = ZQ LONG CALIBRATION
ZQCS = ZQ SHORT CALIBRATION
High Performance, Integrated Memory Module Product
March 6, 2013 LDS-L9D3xxxM32DBG2
PRELIMINARY INFORMATION
L9D3256M32DBG2
L9D3512M32DBG2
16-32 Gb, DDR3, 256-512M x 32 Dual Channel Memory Module
INDUSTRIAL TEMPERATURE
FUNCTIONAL DESCRIPTION
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EXTENDED TEMPERATURE
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MILITARY, EXTREME OPERATING TEMPERATURE
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LOGIC Devices Incorporated
www.logicdevices.com
High Performance, Integrated Memory Module Product
March 6, 2013 LDS-L9D3xxxM32DBG2
PRELIMINARY INFORMATION
L9D3256M32DBG2
L9D3512M32DBG2
16-32 Gb, DDR3, 256-512M x 32 Dual Channel Memory Module
FIGURE 3A - L9D3256M32DBG2 FUNCTIONAL BLOCK DIAGRAM
CSA
RESETA
ODTA
WEA
RASA, CASA
CKEA
CKA, CKA#
BA0-2A
ADDR0-15A
ADDR
BA
DM3A
CK, CKE RAS, WE
CK#
CAS
ODT RESET CSA
DIE 1A
DM2A
DQ 15
DQ 8
DQ 7
DQ 0
ZQ
VSSQ
ADDR
BA
CK, CKE RAS, WE
CK#
CAS
ODT RESET CSA
DIE 0A
DM1A
DQ 15
DQ 8
DQ 7
DQ 0
DM0A
ZQ
DQS3A, DQS3A#
DQ 31A
DQ 24A
DQS2A, DQS2A#
DQ 23A
DQ 16A
DQS1A, DQS1A#
DQ 15A
DQ 8A
DQS0A, DQS0A#
DQ 7A
DQ 0A
VSSQ
DIE 1B
DM3B
DM2B
ZQ
ADDR
BA
VSSQ
CK, CKE RAS, WE
CK#
CAS
ODT RESET CSB
DIE 0B
DM1B
DM0B
ZQ
ADDR
VSSQ
BA
CK, CKE RAS, WE
CK#
CAS
ODT RESET CSB
DQ 15
DQ 8
DQ 7
DQ 0
DQ 15
DQ 8
DQ 7
DQ 0
DQS3B, DQS3B#
DQ 31B
DQ 24B
DQS2B, DQS2B#
DQ 23B
DQ 16B
DQS1B, DQS1B#
DQ 15B
DQ 8B
DQS0B, DQS0B#
DQ 7B
DQ 0B
ADDR0-15B
BA0-2B
CKB, CKB#
CKEB
RASB, CASB
WEB
ODTB
RESETB
CSB
LOGIC Devices Incorporated
www.logicdevices.com
5
High Performance, Integrated Memory Module Product
March 6, 2013 LDS-L9D3xxxM32DBG2
PRELIMINARY INFORMATION
L9D3256M32DBG2
L9D3512M32DBG2
16-32 Gb, DDR3, 256-512M x 32 Dual Channel Memory Module
FIGURE 3B - L9D3512M32DBG2 FUNCTIONAL BLOCK DIAGRAM
CS1A
CS0A
RESETA#
ODTA
WEAb
RASA#, CASA#
CKEA
CKA, CKA#
BA0-2A
ADDR0-15A
ADDR
BA
ZQ
CK, CKE RAS, WE
CK#
CAS
ODT RESET CS0 CS1
DQ 7
DQ 0
VSSQ
DM0A
DIE 0A
DM1A
DIE 1A
DQ 7
DQ 0
ZQ
VSSQ
ADDR
BA
ZQ
VSSQ
CK, CKE RAS, WE
CK#
CAS
ODT RESET CS0 CS1
DQ 7
DQ 0
DIE 2A
DIE 3A
DM2A
DM3A
DQ 7
DQ 0
ZQ
DQS0A, DQS0A#
DQ 31A
DQ 24A
DQS1A, DQS1A#
DQ 23A
DQ 16A
DQS2A, DQS2A#
DQ 15A
DQ 8A
DQS3A, DQS3A#
DQ 7A
DQ 0A
VSSQ
ZQ
DQ 7
DQ 0
DIE 3B
DIE 2B
VSSQ
DM3B
DM2B
ZQ
ADDR
BA
CK, CKE RAS, WE
CK#
CAS
ODT RESET CS0 CS1
DQ 7
DQ 0
DQS3B, DQS3B#
DQ 31B
DQ 24B
DQS2B, DQS2B#
DQ 23B
DQ 16B
VSSQ
DQ 7
DQ 0
ZQ
DIE 1B
DIE 0B
VSSQ
DM1B
DM0B
ZQ
ADDR
VSSQ
BA
CK, CKE RAS, WE
CK#
CAS
ODT RESET CS0 CS1
DQ 7
DQ 0
DQS1B, DQS1B#
DQ 15B
DQ 8B
DQS0B, DQS0B#
DQ 7B
DQ 0B
ADDR0-15B
BA0-2B
CKB, CKB#
CKEB
RASB#, CASB#
WEB#
ODTB
RESETB#
CS0B
CS1B
LOGIC Devices Incorporated
www.logicdevices.com
6
High Performance, Integrated Memory Module Product
March 6, 2013 LDS-L9D3xxxM32DBG2
PRELIMINARY INFORMATION
L9D3256M32DBG2
L9D3512M32DBG2
16-32 Gb, DDR3, 256-512M x 32 Dual Channel Memory Module
BALL /SIGNAL LOCATION (PBGA)
FIGURE 4 - PINOUT TOP VIEW
1
2
3
4
5
6
7
8
9
10
11
12
13
A
VssQ
VDDQ
VssQ
VDDQ
VssQ
VDDQ
VssQ
Vss
A14A
A13A
A8A
VDD
VSS
A
B
DQ9A
DQS1A
A6A
A2A
B
C
DQS1A# DQ13A DQ15A DQ14A DQ12A
VDD
DQ11A DQ10A
DQ8A
DQ0A
DQ2A
DQ3A
DQ1A
VSS
RFU
A4A
A5A
A1A
A3A
C
D
VDDQ
VSSQ
VDDQ
VSSQ
VDDQ
VSSQ
VDDQ
VDD
A12A
DM1A
A0A
BA1A
DM0A
D
E
DQ4A
DQ6A
DQ7A
DQ5A
DQS0A#
DQS0A
VssQ
VDD
RESETA#
BA0A
BA2A
Vss
VDD
E
DQ20A DQ22A DQ23A DQ21A DQS2A#
DQS2A
VDDQ
VSS
CSA1# VREFCAA CSA0#
VDD
VSS
F
VDDQ
VssQ
VDD
RFU
A10A
WEA#
ODTA
CKEA
G
F
G
VssQ
VDDQ
VssQ
VDDQ
VssQ
A9A
A11A
A7A
H
DQ26A DQ24A DQ16A DQ18A DQ19A DQ17A
VDD
VSS
VREFDQA
VSS
CASA#
CLKA
VDD
H
J
DQ27A DQ25A
DQS3A# DQ29A DQ31A
Vss
VDD
VDDDLLA
VDD
RASA# CLKA#
VSS
J
K
L
M
VDDQ
VSSQ
DQS3A
VDDQ
VSSQ
DQ28A DQ30A DQ28B DQ30B
VSSQ
VDDQ
VDDQ
VSSQ
VDDQ
VSS
VSSDLLA
VSS
VDD
DM2A
DM3A
K
Vss
VDD
Vss
VDD
Vss
VDD
Vss
VDD
VSS
L
VSSQ
VDDQ
VSSQ
VSS
VSSDLLB
VSS
VDD
DM2B
DM3B
M
VSSQ
VDDQ
DQS3B
DQS3B# DQ29B
N
DQ27B DQ25B
DQ31B
Vss
VDD
VDDDLLB
VDD
RASB# CLKB#
VSS
N
P
DQ26B DQ24B DQ16B DQ18B DQ19B DQ17B
VDD
VSS
VREFDQB
VSS
CASB#
CLKB
VDD
P
R
VDDQ
RFU
A10B
WEB#
ODTB
CKEB
R
T
VSSQ
VDDQ
VSSQ
VDDQ
VSSQ
VDDQ
VDD
DQ20B DQ22B DQ23B DQ21B DQS2B# DQS2B
VSSQ
VSS
CSB1# VREFCAB CSB0#
VDD
VSS
T
U
DQ4B
DQ6B
DQ7B
DQ5B
DQS0B#
DQS0B
VDDQ
VDD
RESETB#
BA0B
BA2B
Vss
VDD
U
V
VSSQ
VDDQ
VSSQ
VDDQ
VSSQ
VDDQ
VSSQ
VDD
A12B
DM1B
A0B
BA1B
DM0B
V
W
DQ11B DQ10B
DQ8B
DQ0B
DQ2B
DQ3B
DQ1B
VSS
RFU
A4B
A5B
A1B
A3B
W
Y
DQ9B
DQS1B
VDD
A9B
A11B
A7B
A6B
A2B
Y
AA
VDDQ
VSSQ
VDDQ
VSSQ
VDDQ
VSSQ
VDDQ
Vss
A14B
A13B
A8B
VDD
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
DQS1B# DQ13B DQ15B DQ14B DQ12B
GND (Core)
V + (Core Power)
Data IO
Address
GND (I/O)
V + (I/O Power)
Level REF
RFU
VSSDLL
VDDDLL
CNTRL
AA
271BGA-1.00MM PITCH - X64, SCB
LOGIC Devices Incorporated
www.logicdevices.com
High Performance, Integrated Memory Module Product
March 6, 2013 LDS-L9D3xxxM32DBG2
PRELIMINARY INFORMATION
L9D3256M32DBG2
L9D3512M32DBG2
16-32 Gb, DDR3, 256-512M x 32 Dual Channel Memory Module
TABLE 2 - BALL/SIGNAL LOCATION AND DESCRIPTION
Ball Assignments
$$$%%
Symbol
Type
A0A, A1A,
Input Address Inputs: 3URYLGHWKH52:DGGUHVVIRU$&7,9$7(FRPPDQGVDQGWKHFROXPQDGGUHVV
Description
%%%&& A2A, A3A,
DQGDXWRSUHFKDUJHELW$10IRU5($'<:5,7(FRPPDQGVWRVHOHFWRQHORFDWLRQRXWRIWKH
&&&'' A4A, A5A,
PHPRU\DUUD\LQWKHUHVSHFWLYHEDQN$10VDPSOHGGXULQJD35(&+$5*(FRPPDQGGHWHUPLQHV
A6A, A7A,
ZKHWKHUWKH35(&+$5*(DSSOLHVWRRQHEDQN$10/2:EDQNVHOHFWHGE\%$>@RUDOOEDQNV
A8A, A9A,
$10+,*+7KHDGGUHVVLQSXWVDOVRSURYLGHWKHRSFRGHGXULQJD/2$'02'(FRPPDQG
A10A /AP,
$GGUHVVLQSXWVDUHUHIHUHQFHGWR9UHI&$$12%&ZKHQHQDEOHGLQWKHPRGHUHJLVWHU05$12
G10
A11A, A12A /
BC, A13A,
LVVDPSOHGGXULQJ5($'DQG:5,7(FRPPDQGVWRGHWHUPLQHZKHWKHUEXUVWFKRS/2: %&
EXUVWFKRS
A14A, A15A
'((
BA0A, BA1A, Input Bank Address Inputs: %$>@GHILQHWKHEDQNWRZKLFKDQ$&7,9$7(5($':5,7(RU
BA2A
35(&+$5*(FRPPDQGLVEHLQJDSSOLHG%$>@GHILQHZKLFKPRGHUHJLVWHU050, MR1, MR2, or
MR3LVORDGHGGXULQJWKH/2$'02'(FRPPDQG%$>@DUHUHIHUHQFHGWR9UHI&$
+-
CLKAX,
CLKAX#
Input Clock: &/.[DQG&/.[DUHGLIIHUHQWLDOFORFNLQSXWVRQHGLIIHUHQWLDOSDLUSHU:25'IRXU:25'V
FRQWDLQHGLQWKH/'[[*SURGXFW$OOFRQWURODQGDGGUHVVLQSXWVLJQDOVDUHVDPSOHGRQWKH
FURVVLQJRIWKHSRVLWLYHHGJHRI&/.[DQGWKHQHJDWLYHHGJHRI&/.[2XWSXWGDWDVWUREHV
'46['46[LVUHIHUHQFHGWRWKHFURVVLQJRI&/.[DQG&/.[
G13
CKEA
Input Clock Enable: &.(HQDEOHVDQGGLVDEOHVLQWHUQDOFLUFXLWU\DQGFORFNVRQWKH6'5$07KH
VSHFLILFFLUFXLWU\WKDWLVHQDEOHGGLVDEOHGLVGHSHQGHQWXSRQWKH''56'5$0FRQILJXUDWLRQDQG
RSHUDWLQJPRGH7DNLQJ&.(/2:SURYLGHV35(&+$5*(SRZHUGRZQDQG6(/)5()5(6+
RSHUDWLRQVDOOEDQNVLGOHRUDFWLYHSRZHUGRZQURZDFWLYHLQDQ\EDQN&.(LVV\QFKURQRXV
IRUSRZHUGRZQHQWU\DQGH[LWDQGIRUVHOIUHIUHVKHQWU\&.(LVDV\QFKURQRXVIRUVHOIUHIUHVK
H[LW,QSXWEXIIHUVH[FOXGLQJ&/.[&/.[&.(5(6(7DQG2'7DUHGLVDEOHGGXULQJ6(/)
5()5(6+&.(LVUHIHUHQFHGWR9UHI&$
F11
CSA#
Input Chip Select: &6HQDEOHVUHJLVWHUHG/2:DQGGLVDEOHVWKHFRPPDQGGHFRGHU$OOFRPPDQGV
DUHPDVNHGZKHQ&6LVUHJLVWHUHG+,*+&6SURYLGHVIRUH[WHUQDOUDQNVHOHFWLRQRQV\VWHPV
ZLWKPXOWLSOH UDQNV&6LVFRQVLGHUHGSDUWRIWKHFRPPDQGFRGH&6LVUHIHUHQFHGWR9UHI&$
D10, D13, K12, K13,
DMxA
Input Input Data Mask: '0[LVWKHE\WHZLGHGDWDPDVNIRUWKHUHVSHFWLYHELWGDWDILHOGV7KHGDWD
PDVNLQSXWPDVNV:5,7(GDWD%\WHGDWDLVPDVNHGZKHQ'0[LVVDPSOHG+,*+'0[SLQVDUH
VWUXFWXUHGDVLQSXWVRQO\WKHSLQVHOHFWULFDOORDGLQJLVGHVLJQHGWRPDWFKWKDWRIWKH'4'46[
'46[SLQV
-
RASA#
Input ROW Address Strobe/Select: 'HILQHVWKHFRPPDQGEHLQJHQWHUHGDORQJ&$6:(DQG&6
7KLVLQSXWSLQLVUHIHUHQFHGWR9UHI&$
+
CASA#
Input COLUMN Address Strobe/Select: 'HILQHVWKHFRPPDQGEHLQJHQWHUHGDORQJZLWK5$6:(
DQG&67KLVLQSXWSLQLVUHIHUHQFHGWR9UHI&$
G11
WEA#
Input WRITE Enable Input: 'HILQHVWKHFRPPDQGEHLQJHQWHUHGDORQJZLWK&$65$6DQG&6
7KLVLQSXWSLQLVUHIHUHQFHGWR9UHI&$
LOGIC Devices Incorporated
www.logicdevices.com
8
High Performance, Integrated Memory Module Product
March 6, 2013 LDS-L9D3xxxM32DBG2
PRELIMINARY INFORMATION
L9D3256M32DBG2
L9D3512M32DBG2
16-32 Gb, DDR3, 256-512M x 32 Dual Channel Memory Module
TABLE 2 - BALL/SIGNAL LOCATION AND DESCRIPTION CONTINUED
Ball Assignments
Symbol
Type
G12
ODTA
Input
Description
On-Die Termination: 2'7HQDEOHVZKHQUHJLVWHUHG+,*+DQGGLVDEOHVWHUPLQDWLRQUHVLVWDQFHLQWHUQDOWRWKH''56'5$0:KHQHQDEOHGLQQRUPDORSHUDWLRQ2'7LVRQO\DSSOLHG
WRHDFKRIWKHIROORZLQJVLJQDOV'4>@'46[DQG'0[7KH2'7LQSXWLVLJQRUHGLI
GLVDEOHGYLDWKH/2$'02'(UHJLVWHUFRPPDQG2'7LVUHIHUHQFHGWR9UHI&$
(
RESETA#
Input
RESET: $QLQSXWFRQWUROSLQDFWLYH/2:UHIHUHQFHGWR9VV7KH5(6(7LQSXWUHFHLYHULV
D&026LQSXWGHILQHGDVDUDLOWRUDLOVLJQDOZLWK'&+,*+t[9DDDQG'&/2:d 0.2 x
9DD45(6(7DVVHUWLRQDQGGHDVVHUWLRQDUHDV\QFKURQRXV
(())
DQSxA,
%%--
DQSxA#
&&&&((
DQ0A, DQ1A,
((
DQ2A, DQ3A,
Input
Data Strobe Byte (per WORD): 2XWSXWHGJHDOLJQHGZLWK5($'GDWD,QSXWFHQWHUDOLJQHG
ZLWK:5,7(GDWD
I/O
Data Input/Output: /2:%\WH/2::25':25'3LQUHIHUHQFHGWR9UHI'4
I/O
Data Input/Output: +,*+%\WH/2::25':25'3LQUHIHUHQFHGWR9UHI'4
I/O
Data Input/Output: /2:%\WH:25'3LQUHIHUHQFHGWR9UHI'4
I/O
Data Input/Output: +,*+%\WH:25'3LQUHIHUHQFHGWR9UHI'4
DQ4A, DQ5A,
DQ6A, DQ7A
%%%%%&
DQ8A, DQ9A,
&&
DQ10A, DQ11A,
DQ12A, DQ13A,
DQ14A, DQ15A
))))++
DQ16A, DQ17A,
++
DQ18A, DQ19A,
DQ20A, DQ21A,
DQ22A, DQ23A
++----
DQ24A, DQ25A,
L1, L2
DQ26A, DQ27A,
DQ28A, DQ29A,
DQ30A, DQ31A
K9
VSSDLLA
*URXQGIRU'//
-
VDDDLLA
6XSSO\IRU'//
F10
VrefCAA
Supply 9ROWDJH5HIHUHQFH&25(9UHI&$PXVWEHPDLQWDLQHGDWDOOWLPHV
+
VrefDAA
Supply 9ROWDJH5HIHUHQFH,29UHI'4PXVWEHPDLQWDLQHGDWDOOWLPHV
LOGIC Devices Incorporated
www.logicdevices.com
9
High Performance, Integrated Memory Module Product
March 6, 2013 LDS-L9D3xxxM32DBG2
PRELIMINARY INFORMATION
L9D3256M32DBG2
L9D3512M32DBG2
16-32 Gb, DDR3, 256-512M x 32 Dual Channel Memory Module
TABLE 2 - BALL/SIGNAL LOCATION AND DESCRIPTION CONTINUED
Ball Assignments
Symbol
599:: A0B, A1B,
Type
Description
L
Input Address Inputs: 3URYLGHWKH52:DGGUHVVIRU$&7,9$7(FRPPDQGVDQGWKHFROXPQDGGUHVV
:::<
A2B, A3B,
DQGDXWRSUHFKDUJHELW$10IRU5($'<:5,7(FRPPDQGVWRVHOHFWRQHORFDWLRQRXWRIWKH
<<<<
A4B, A5B,
PHPRU\DUUD\LQWKHUHVSHFWLYHEDQN$10VDPSOHGGXULQJD35(&+$5*(FRPPDQGGHWHUPLQHV
$$$$$$
A6B, A7B,
ZKHWKHUWKH35(&+$5*(DSSOLHVWRRQHEDQN$10/2:EDQNVHOHFWHGE\%$>@RUDOOEDQNV
A8B, A9B,
$10+,*+7KHDGGUHVVLQSXWVDOVRSURYLGHWKHRSFRGHGXULQJD/2$'02'(FRPPDQG
A10B /AP,
$GGUHVVLQSXWVDUHUHIHUHQFHGWR9UHI&$$12%&ZKHQHQDEOHGLQWKHPRGHUHJLVWHU05$12
LVVDPSOHGGXULQJ5($'DQG:5,7(FRPPDQGVWRGHWHUPLQHZKHWKHUEXUVWFKRS/2: %&
A11B, A12B /
EXUVWFKRS
BC, A13B,
A14B, A15B
889
BA0B, BA1B, Input Bank Address Inputs: %$>@GHILQHWKHEDQNWRZKLFKDQ$&7,9$7(5($':5,7(RU
35(&+$5*(FRPPDQGLVEHLQJDSSOLHG%$>@GHILQHZKLFKPRGHUHJLVWHU050, MR1, MR2, or
BA2B
MR3LVORDGHGGXULQJWKH/2$'02'(FRPPDQG%$>@DUHUHIHUHQFHGWR9UHI&$
13
CLKBX,
Input Clock: &/.[DQG&/.[DUHGLIIHUHQWLDOFORFNLQSXWVRQHGLIIHUHQWLDOSDLUSHU:25'IRXU:25'V
FRQWDLQHGLQWKH/'[[*SURGXFW$OOFRQWURODQGDGGUHVVLQSXWVLJQDOVDUHVDPSOHGRQWKH
CLKBX#
FURVVLQJRIWKHSRVLWLYHHGJHRI&/.[DQGWKHQHJDWLYHHGJHRI&/.[2XWSXWGDWDVWUREHV
'46['46[LVUHIHUHQFHGWRWKHFURVVLQJRI&/.[DQG&/.[
R13
CKEB
Input Clock Enable: &.(HQDEOHVDQGGLVDEOHVLQWHUQDOFLUFXLWU\DQGFORFNVRQWKH6'5$07KH
VSHFLILFFLUFXLWU\WKDWLVHQDEOHGGLVDEOHGLVGHSHQGHQWXSRQWKH''56'5$0FRQILJXUDWLRQDQG
RSHUDWLQJPRGH7DNLQJ&.(/2:SURYLGHV35(&+$5*(SRZHUGRZQDQG6(/)5()5(6+
RSHUDWLRQVDOOEDQNVLGOHRUDFWLYHSRZHUGRZQURZDFWLYHLQDQ\EDQN&.(LVV\QFKURQRXV
IRUSRZHUGRZQHQWU\DQGH[LWDQGIRUVHOIUHIUHVKHQWU\&.(LVDV\QFKURQRXVIRUVHOIUHIUHVK
H[LW,QSXWEXIIHUVH[FOXGLQJ&/.[&/.[&.(5(6(7DQG2'7DUHGLVDEOHGGXULQJ6(/)
5()5(6+&.(LVUHIHUHQFHGWR9UHI&$
T11
CSB#
Input Chip Select: &6HQDEOHVUHJLVWHUHG/2:DQGGLVDEOHVWKHFRPPDQGGHFRGHU$OOFRPPDQGV
DUHPDVNHGZKHQ&6LVUHJLVWHUHG+,*+&6SURYLGHVIRUH[WHUQDOUDQNVHOHFWLRQRQV\VWHPV
ZLWKPXOWLSOH UDQNV&6LVFRQVLGHUHGSDUWRIWKHFRPPDQGFRGH&6LVUHIHUHQFHGWR9UHI&$
0099
DMxB,
Input Input Data Mask: '0[LVWKHE\WHZLGHGDWDPDVNIRUWKHUHVSHFWLYHELWGDWDILHOGV7KHGDWD
PDVNLQSXWPDVNV:5,7(GDWD%\WHGDWDLVPDVNHGZKHQ'0[LVVDPSOHG+,*+'0[SLQVDUH
VWUXFWXUHGDVLQSXWVRQO\WKHSLQVHOHFWULFDOORDGLQJLVGHVLJQHGWRPDWFKWKDWRIWKH'4'46[
'46[SLQV
N11
RASB#
Input ROW Address Strobe/Select: 'HILQHVWKHFRPPDQGEHLQJHQWHUHGDORQJ&$6:(DQG&6
7KLVLQSXWSLQLVUHIHUHQFHGWR9UHI&$
3
CASB#
Input COLUMN Address Strobe/Select: 'HILQHVWKHFRPPDQGEHLQJHQWHUHGDORQJZLWK5$6:(
DQG&67KLVLQSXWSLQLVUHIHUHQFHGWR9UHI&$
R11
WEB#
Input WRITE Enable Input: 'HILQHVWKHFRPPDQGEHLQJHQWHUHGDORQJZLWK&$65$6DQG&6
7KLVLQSXWSLQLVUHIHUHQFHGWR9UHI&$
LOGIC Devices Incorporated
www.logicdevices.com
10
High Performance, Integrated Memory Module Product
March 6, 2013 LDS-L9D3xxxM32DBG2
PRELIMINARY INFORMATION
L9D3256M32DBG2
L9D3512M32DBG2
16-32 Gb, DDR3, 256-512M x 32 Dual Channel Memory Module
TABLE 2 - BALL/SIGNAL LOCATION AND DESCRIPTION CONTINUED
Ball Assignments
R12
Symbol
ODTB
Type
Input
Description
On-Die Termination: 2'7HQDEOHVZKHQUHJLVWHUHG+,*+DQGGLVDEOHVWHUPLQDWLRQUHVLVWDQFHLQWHUQDOWRWKH''56'5$0:KHQHQDEOHGLQQRUPDORSHUDWLRQ2'7LVRQO\DSSOLHG
WRHDFKRIWKHIROORZLQJVLJQDOV'4>@'46[DQG'0[7KH2'7LQSXWLVLJQRUHGLI
GLVDEOHGYLDWKH/2$'02'(UHJLVWHUFRPPDQG2'7LVUHIHUHQFHGWR9UHI&$
8
RESETB#
Input
RESET: $QLQSXWFRQWUROSLQDFWLYH/2:UHIHUHQFHGWR9VV7KH5(6(7LQSXWUHFHLYHULV
D&026LQSXWGHILQHGDVDUDLOWRUDLOVLJQDOZLWK'&+,*+t[9DDDQG'&/2:d 0.2 x
9DD45(6(7DVVHUWLRQDQGGHDVVHUWLRQDUHDV\QFKURQRXV
7788
DQSxB,
11<<
DQSxB#
8888::
DQ0B, DQ1B,
::
DQ2B, DQ3B,
Input
Data Strobe, Byte (per WORD): 2XWSXWHGJHDOLJQHGZLWK5($'GDWD,QSXWFHQWHUDOLJQHG
ZLWK:5,7(GDWD
I/O
Data Input/Output: /2:%\WH/2::25':25'3LQUHIHUHQFHGWR9UHI'4
I/O
Data Input/Output: +,*+%\WH/2::25':25'3LQUHIHUHQFHGWR9UHI'4
I/O
Data Input/Output: /2:%\WH:25'3LQUHIHUHQFHGWR9UHI'4
I/O
Data Input/Output: +,*+%\WH:25'3LQUHIHUHQFHGWR9UHI'4
DQ4B, DQ5B,
DQ6B, DQ7B
:::<<<
DQ8B, DQ9B,
<<
DQ10B, DQ11B,
DQ12B, DQ13B,
DQ14B, DQ15B
333377 DQ16B, DQ17B,
77
DQ18B, DQ19B,
DQ20B, DQ21B,
DQ22B, DQ23B
//1111 DQ24B, DQ25B,
33
DQ26B, DQ27B,
DQ28B, DQ29B,
DQ30B, DQ31B
M9
VSSDLLB
*URXQGIRU'//
N9
VDDDLLB
6XSSO\IRU'//
T10
VrefCAB
Supply 9ROWDJH5HIHUHQFH&25(9UHI&$PXVWEHPDLQWDLQHGDWDOOWLPHV
3
VrefDAB
Supply 9ROWDJH5HIHUHQFH,29UHI'4PXVWEHPDLQWDLQHGDWDOOWLPHV
LOGIC Devices Incorporated
www.logicdevices.com
11
High Performance, Integrated Memory Module Product
March 6, 2013 LDS-L9D3xxxM32DBG2
PRELIMINARY INFORMATION
L9D3256M32DBG2
L9D3512M32DBG2
16-32 Gb, DDR3, 256-512M x 32 Dual Channel Memory Module
TABLE 2 - BALL/SIGNAL LOCATION AND DESCRIPTION CONTINUED
Ball Assignments
$%'((
Symbol
VDD
Type
Description
Supply 3RZHU6XSSO\99
)*++-
-.///
/0113
35788
9<$$
$$$'''
VDDQ
Supply 'DWD,26XSSO\99
')***.
...000
555589
99$$$$$$
$$
$$&()
Vss
Supply Ground
)++--
..////
/0011
33778
:$$$$
$$$$''
'(****
VssQ
Supply 'DWD,2*URXQG,VRODWHGIURP&RUHIRULPSURYHGQRLVHLPPXQLW\
...000
055579
999$$$$
$$
F9, G9, R9, T9
LOGIC Devices Incorporated
RFU
www.logicdevices.com
5HVHUYHGIRU)XWXUH8VH
12
High Performance, Integrated Memory Module Product
March 6, 2013 LDS-L9D3xxxM32DBG2
PRELIMINARY INFORMATION
L9D3256M32DBG2
L9D3512M32DBG2
16-32 Gb, DDR3, 256-512M x 32 Dual Channel Memory Module
FIGURE 5 - MECHANICAL DRAWING
[120
Ø
$
B
&
D
(
F
G
+
K
L
M
N
3
R
T
8
9
:
<
$$
20.00 NOM
1.00 NOM
0$;
1.00 NOM
12.00 NOM
1RWH$OOGLPHQVLRQVLQPP
LOGIC Devices Incorporated
www.logicdevices.com
13
High Performance, Integrated Memory Module Product
March 6, 2013 LDS-L9D3xxxM32DBG2
L9D3256M32DBG2
L9D3512M32DBG2
PRELIMINARY INFORMATION
16-32 Gb, DDR3, 256-512M x 32 Dual Channel Memory Module
TABLE 3: ABSOLUTE MAXIMUM RATINGS
Symbol
MIN
MAX
UNITS
NOTES
9DD
9DD6XSSO\9ROWDJHUHODWLYHWR9VV
Parameter
9
1
9DDQ
9DD6XSSO\9ROWDJHUHODWLYHWR9VVQ
9
1
9IN9287
9ROWDJHRQDQ\SLQUHODWLYHWR9VV
9
1
T$,QGXVWULDO
2SHUDWLQJ$PELHQW7HPSHUDWXUH
85
°&
2,3
T$([WHQGHG
2SHUDWLQJ$PELHQW7HPSHUDWXUH
105
°&
2,3
T$0LOWHPS
2SHUDWLQJ$PELHQW&DVH7HPSHUDWXUH
-55
125
°&
2,3
TSTG
6WRUDJH7HPSHUDWXUH
-55
150
°&
2,3
127(6
9DDDQG9DD4PXVWEHZLWKLQP9RIHDFKRWKHUDWDOOWLPHVDQG95()PXVWQRWEHJUHDWHUWKDQ[9DD4:KHQ9DD and
9DD4DUHOHVVWKDQ0995()PD\EHdP9
0D[RSHUDWLQJDPELHQWWHPSHUDWXUHT$LVPHDVXUHGLQWKHFHQWHURIWKHSDFNDJH
'HYLFH)XQFWLRQDOLW\LVQRWJXDUDQWHHGLIWKH'5$0GHYLFHH[FHHGVWKH0D[LPXP7$GXULQJRSHUDWLRQ
TABLE 4: INPUT/OUTPUT CAPACITANCE
Capacitance Parameter
&.DQG&.?
PACKAGE OUTLINE DIMENSIONS
Symbol
MIN
MAX (256M) MAX (512M)
&&.
1.6
3.2
S)
UNITS
NOTES
6LQJOHHQG,2'4'0
&10
2.2
S)
2
'LIIHUHQWLDO,2'46'46?
&10
2.2
S)
3
1.5
2.8
5.6
S)
5
,QSXWV5$6?&$6?:(?&6?&.(5(6(7?$''5%$
&I_Shared
127(6
9DD 9P999DDQ 9DD95() 9VVI 0+]T$ = 25°&9287'& [9DDQ9287SHDNWRSHDN 9
'0LQSXWLVJURXSHGZLWK,2SLQVUHIOHFWLQJWKHVLJQDOLVJURXSHGZLWK'4DQGWKHUHIRUHPDWFKHGLQORDGLQJ
&&&46LVIRU'46YV'46?
&DIO &,2'4[&,2>'46@&,2>'46?@
([FOXGHV&.&.?
&',B&17/ &,&17/[&&.>&.@&&.>&.?@&17/ 2'7&6?DQG&.(
&',B&0'B$''5 &,&0'B$''5[&&.>&.@&&.>&.?@&0' 5$6?&$6?DQG:(?$''5 >Q@
LOGIC Devices Incorporated
www.logicdevices.com
High Performance, Integrated Memory Module Product
March 6, 2013 LDS-L9D3xxxM32DBG2
PRELIMINARY INFORMATION
L9D3256M32DBG2
L9D3512M32DBG2
16-32 Gb, DDR3, 256-512M x 32 Dual Channel Memory Module
TABLE 5: TIMING PARAMETERS FOR IDD MEASUREMENTS - CLOCK UNITS
IDD Parameter
DDR3-1333
DDR3-1600
DDR3-1866
-15
-12
-11
10-10-10
11-11-11
13-13-13
t&.0,1,DD
1.5
1.25
QV
&/,DD
10
11
13
&.
t5&'0,1,DD
10
11
13
&.
W5&0,1,DD
39
&.
t5$60,1,DD
28
32
&.
10
11
13
&.
30
32
33
&.
t530,1,DD
t)$:
[
tRRD IDD
[
t5)&
LOGIC Devices Incorporated
5
6
6
&.
208
&.
www.logicdevices.com
15
High Performance, Integrated Memory Module Product
March 6, 2013 LDS-L9D3xxxM32DBG2
LOGIC Devices Incorporated
ODT
WE\
CAS\
RAS\
Sub-Loop
CKE
www.logicdevices.com
1
2
3
4
5
6
7
BA [2:0]
Cycle
Number
0
A [15:11]
PRE
A [10]
0
1
1
1
1
A [9:7]
ACT
D
D
D\
D\
0
PRE
A [6:3]
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
1
1
0
0
0
0
0
0
Repeat cycles 1 through 4 until n RAS - 1, truncate if needed
0
1
0
0
0
0
0
0
0
Repeat cycles 1 through 4 until n RC - 1, truncate if needed
0
1
1
0
0
0
0
0
F
0
0
0
0
0
0
0
0
F
0
0
0
0
0
0
0
0
F
1
1
1
0
0
0
0
0
F
1
1
1
0
0
0
0
0
F
Repeat cycles n RC +1 through n RC +4 until n RC - 1 + n RAS - 1, truncate if needed
0
1
0
0
0
0
0
0
F
Repeat cycles n RC +1 through n RC +4 until 2 x RC - 1, truncate if needed
Repeat sub-loop 0, use BA [2:0] = 1
Repeat sub-loop 0, use BA [2:0] = 2
Repeat sub-loop 0, use BA [2:0] = 3
Repeat sub-loop 0, use BA [2:0] = 4
Repeat sub-loop 0, use BA [2:0] = 5
Repeat sub-loop 0, use BA [2:0] = 6
Repeat sub-loop 0, use BA [2:0] = 7
CK, CK\
16
0
0
0
0
0
0
0
0
0
0
0
0
A [2:0]
0
0
0
1
1
-
-
-
-
Data
0
0
1
1
1
1
Command
ACT
D
D
D\
D\
CS\
0
1
2
3
4
n RAS
n RC
n RC + 1
n RC + 2
n RC + 3
n RC + 4
n RC + n RAS
2 x nRC
4 x n RC
6 x n RC
8 x n RC
10 x n RC
12 x n RC
14 x n RC
PRELIMINARY INFORMATION
L9D3256M32DBG2
L9D3512M32DBG2
16-32 Gb, DDR3, 256-512M x 32 Dual Channel Memory Module
TABLE 6: IDD0 MEASUREMENT LOOP
Static HIGH
Toggling
High Performance, Integrated Memory Module Product
March 6, 2013 LDS-L9D3xxxM32DBG2
Cycle
Number
Sub-Loop
CKE
CK, CK\
LOGIC Devices Incorporated
www.logicdevices.com
2 x n RC
2 x n RC
2 x n RC
2 x n RC
2 x n RC
2 x n RC
2 x n RC
Command
1
2
3
4
5
6
7
CS\
0
1
1
1
1
0
0
ACT
D
D
D\
D\
RD
PRE
0
RAS\
PRE
0
1
0
0
0
1
1
0
CAS\
0
WE\
1
ODT
0
BA [2:0]
RD
A [15:11]
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
Repeat cycles 1 through 4 until nRCD - 1, truncate if needed
0
1
0
0
0
0
0
0
Repeat cycles 1 through 4 until nRAS - 1, truncate if needed
1
0
0
0
0
0
0
0
Repeat cycles 1 through 4 until nRC - 1, truncate if needed
1
1
0
0
0
0
0
F
0
0
0
0
0
0
0
F
0
0
0
0
0
0
0
F
1
1
0
0
0
0
0
F
1
1
0
0
0
0
0
F
Repeat cycles nRC + 1 through nRC + 4 until nRC + nRCD - 1, truncate if needed
0
1
0
0
0
0
0
F
Repeat cycles nRC + 1 through nRC + 4 until nRC + nRAS - 1, truncate if needed
1
0
0
0
0
0
0
F
Repeat cycle nRC + 1 through nRC + 4 until 2 x nRC - 1, truncate if needed
Repeat sub-loop 0, use BA [2:0] = 1
Repeat sub-loop 0, use BA [2:0] = 2
Repeat sub-loop 0, use BA [2:0] = 3
Repeat sub-loop 0, use BA [2:0] = 4
Repeat sub-loop 0, use BA [2:0] = 5
Repeat sub-loop 0, use BA [2:0] = 6
Repeat sub-loop 0, use BA [2:0] = 7
A [10]
1
0
0
1
1
A [9:7]
0
0
0
1
1
A [6:3]
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
A [2:0]
ACT
D
D
D\
D\
-
00110011
-
-
00000000
-
Data
0
1
2
3
4
n RCD
n RAS
n RC
n RC +1
nRC +2
n RC +3
n RC +4
n RC + nRCD
n RC + nRAS
PRELIMINARY INFORMATION
L9D3256M32DBG2
L9D3512M32DBG2
16-32 Gb, DDR3, 256-512M x 32 Dual Channel Memory Module
TABLE 7: IDD1 MEASUREMENT LOOP
Static HIGH
Toggling
High Performance, Integrated Memory Module Product
March 6, 2013 LDS-L9D3xxxM32DBG2
PRELIMINARY INFORMATION
L9D3256M32DBG2
L9D3512M32DBG2
16-32 Gb, DDR3, 256-512M x 32 Dual Channel Memory Module
TABLE 8: IDD MEASUREMENT CONDITIONS FOR POWER-DOWN CURRENTS
IDD2P0
IDD2P1
IDD2Q
Precharge Power- Precharge PowerPrecharge Quiet
Down Current
Down Current
Standby Current
(Slow Exit)
(Fast Exit)
Name
7LPLQJ3DWWHUQ
&.(
([WHUQDO&ORFN
IDD3P
Active PowerDown Current
QD
QD
QD
QD
/2:
/2:
+,*+
/2:
Toggling
Toggling
Toggling
Toggling
t&.
t&.0,1,DD
t&.0,1,DD
t&.0,1,DD
t&.0,1,DD
t5&
Q?D
Q?D
Q?D
Q?D
t5$6
Q?D
Q?D
Q?D
Q?D
t5&'
Q?D
Q?D
Q?D
Q?D
tRRD
Q?D
Q?D
Q?D
Q?D
t5&
Q?D
Q?D
Q?D
Q?D
&/
Q?D
Q?D
Q?D
Q?D
$/
Q?D
Q?D
Q?D
Q?D
&6?
+,*+
+,*+
+,*+
+,*+
&RPPDQG,QSXWV
/2:
/2:
/2:
/2:
52:&2/801$GGU
/2:
/2:
/2:
/2:
%DQN$GGUHVV
/2:
/2:
/2:
/2:
DM
/2:
/2:
/2:
/2:
'DWD,2
0LGOHYHO
0LGOHYHO
0LGOHYHO
0LGOHYHO
2XWSXW%XIIHU'4'46
(QDEOHG
(QDEOHG
(QDEOHG
(QDEOHG
(QDEOHG2))
(QDEOHG2))
(QDEOHG2))
(QDEOHG2))
8
8
8
8
ODT
%XUVW/HQJWK
None
None
None
None
,'/(%DQNV
$OO
$OO
$OO
$OO
6SHFLDO1RWHV
Q?D
Q?D
Q?D
Q?D
$&7,9(%DQNV
LOGIC Devices Incorporated
www.logicdevices.com
18
High Performance, Integrated Memory Module Product
March 6, 2013 LDS-L9D3xxxM32DBG2
PRELIMINARY INFORMATION
L9D3256M32DBG2
L9D3512M32DBG2
16-32 Gb, DDR3, 256-512M x 32 Dual Channel Memory Module
A [15:11]
BA [2:0]
ODT
WE\
CAS\
RAS\
CKE
CK, CK\
www.logicdevices.com
0
0
0
0
0
0
F
F
0
1
2
3
4
5
6
7
D
D
D\
D\
Cycle
Number
Sub-Loop
LOGIC Devices Incorporated
0
0
0
0
Command
0
1
2
3
4-7
8-11
12-15
16-19
20-23
24-27
28-31
CS\
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Repeat sub-loop 0, use BA [2:0] = 1
Repeat sub-loop 0, use BA [2:0] = 2
Repeat sub-loop 0, use BA [2:0] = 3
Repeat sub-loop 0, use BA [2:0] = 4
Repeat sub-loop 0, use BA [2:0] = 5
Repeat sub-loop 0, use BA [2:0] = 6
Repeat sub-loop 0, use BA [2:0] = 7
A [10]
0
0
1
1
A [9:7]
0
0
1
1
A [6:3]
0
0
1
1
A [2:0]
1
1
1
1
Data
-
TABLE 9: IDD2N / IDD3N MEASUREMENT LOOP
Static HIGH
Toggling
19
High Performance, Integrated Memory Module Product
March 6, 2013 LDS-L9D3xxxM32DBG2
LOGIC Devices Incorporated
www.logicdevices.com
D
D
D\
D\
A [15:11]
BA [2:0]
ODT
WE\
CAS\
RAS\
CS\
Sub-Loop
CKE
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
Repeat sub-loop 0, use BA [2:0] = 1; ODT = 0
Repeat sub-loop 0, use BA [2:0] = 2; ODT = 1
Repeat sub-loop 0, use BA [2:0] = 3; ODT = 1
Repeat sub-loop 0, use BA [2:0] = 4; ODT = 0
Repeat sub-loop 0, use BA [2:0] = 5; ODT = 0
Repeat sub-loop 0, use BA [2:0] = 6; ODT = 1
Repeat sub-loop 0, use BA [2:0] = 7; ODT = 1
A [10]
0
0
1
1
0
0
0
0
A [9:7]
0
0
1
1
0
0
F
F
A [6:3]
1
1
1
1
0
0
0
0
A [2:0]
1
2
3
4
5
6
7
Command
Cycle
Number
0
1
2
3
4-7
8-11
12-15
16-19
20-23
24-27
28-31
-
Data
0
PRELIMINARY INFORMATION
CK, CK\
20
L9D3256M32DBG2
L9D3512M32DBG2
16-32 Gb, DDR3, 256-512M x 32 Dual Channel Memory Module
TABLE 10: IDD2NT MEASUREMENT LOOP
Static HIGH
Toggling
High Performance, Integrated Memory Module Product
March 6, 2013 LDS-L9D3xxxM32DBG2
LOGIC Devices Incorporated
www.logicdevices.com
BA [2:0]
ODT
WE\
CAS\
RAS\
CS\
Sub-Loop
CKE
CK, CK\
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Repeat sub-loop 0, use BA [2:0] = 1
Repeat sub-loop 0, use BA [2:0] = 2
Repeat sub-loop 0, use BA [2:0] = 3
Repeat sub-loop 0, use BA [2:0] = 4
Repeat sub-loop 0, use BA [2:0] = 5
Repeat sub-loop 0, use BA [2:0] = 6
Repeat sub-loop 0, use BA [2:0] = 7
A [15:11]
1
0
1
1
1
0
1
1
A [10]
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
A [9:7]
1
0
1
1
1
0
1
1
0
0
0
0
F
F
F
F
A [6:3]
0
1
1
1
0
1
1
1
0
0
0
0
0
0
0
0
A [2:0]
1
2
3
4
5
6
7
RD
D
D\
D\
RD
D
D\
D\
00000000
00110011
-
Data
0
Command
Cycle
Number
0
1
2
3
4
5
6
7
8-15
16-23
24-31
32-39
40-47
48-55
56-63
PRELIMINARY INFORMATION
21
L9D3256M32DBG2
L9D3512M32DBG2
16-32 Gb, DDR3, 256-512M x 32 Dual Channel Memory Module
TABLE 11: IDD4R MEASUREMENT LOOP
Static HIGH
Toggling
High Performance, Integrated Memory Module Product
March 6, 2013 LDS-L9D3xxxM32DBG2
LOGIC Devices Incorporated
www.logicdevices.com
BA [2:0]
ODT
WE\
CAS\
RAS\
CS\
Sub-Loop
CKE
CK, CK\
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
Repeat sub-loop 0, use BA [2:0] = 1
Repeat sub-loop 0, use BA [2:0] = 2
Repeat sub-loop 0, use BA [2:0] = 3
Repeat sub-loop 0, use BA [2:0] = 4
Repeat sub-loop 0, use BA [2:0] = 5
Repeat sub-loop 0, use BA [2:0] = 6
Repeat sub-loop 0, use BA [2:0] = 7
A [15:11]
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
A [10]
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
A [9:7]
1
0
1
1
1
0
1
1
0
0
0
0
F
F
F
F
A [6:3]
0
1
1
1
0
1
1
1
0
0
0
0
0
0
0
0
A [2:0]
1
2
3
4
5
6
7
WR
D
D\
D\
WR
D
D\
D\
00000000
00110011
-
Data
0
Command
Cycle
Number
0
1
2
3
4
5
6
7
8-15
16-23
24-31
32-39
40-47
48-55
56-63
PRELIMINARY INFORMATION
22
L9D3256M32DBG2
L9D3512M32DBG2
16-32 Gb, DDR3, 256-512M x 32 Dual Channel Memory Module
TABLE 12: IDD4W MEASUREMENT LOOP
Stac HIGH
Toggling
High Performance, Integrated Memory Module Product
March 6, 2013 LDS-L9D3xxxM32DBG2
LOGIC Devices Incorporated
www.logicdevices.com
REF
D
D
D\
D\
Cycle
Number
0
1
2
3
4
5-8
9-12
13-16
17-20
21-24
25-28
29-32
33-n RFC-1
Sub-Loop
CKE
CK, CK\
1b
1c
1d
1e
1f
1g
1h
2
1a
Command
0
A [9:7]
A [10]
A [15:11]
BA [2:0]
ODT
WE\
CAS\
Repeat sub-loop 1a, use BA [2:0] = 1
Repeat sub-loop 1a, use BA [2:0] = 2
Repeat sub-loop 1a, use BA [2:0] = 3
Repeat sub-loop 1a, use BA [2:0] = 4
Repeat sub-loop 1a, use BA [2:0] = 5
Repeat sub-loop 1a, use BA [2:0] = 6
Repeat sub-loop 1a, use BA [2:0] = 7
Repeat sub-loop 1a through 1h until
n RFC - 1, truncate if needed
PRELIMINARY INFORMATION
23
L9D3256M32DBG2
L9D3512M32DBG2
16-32 Gb, DDR3, 256-512M x 32 Dual Channel Memory Module
TABLE 13: IDD5B MEASUREMENT LOOP
Data
A [2:0]
A [6:3]
RAS\
CS\
Static HIGH
Toggling
High Performance, Integrated Memory Module Product
March 6, 2013 LDS-L9D3xxxM32DBG2
PRELIMINARY INFORMATION
L9D3256M32DBG2
L9D3512M32DBG2
16-32 Gb, DDR3, 256-512M x 32 Dual Channel Memory Module
PACKAGE OUTLINE DIMENSIONS
TABLE 14: IDD MEASUREMENT LOOP
,QGXVWULDO5DQJH ([WHQGHGRU0LO7HPSHUDWXUH5DQJH
T$ &WR&
T$ &WR&RU&WR&
IDD6: Self Refresh
Current
IDD6E/M: Self Refresh
Current
IDD8: Reset
&.(
/2:
/2:
0LGOHYHO
([WHUQDO&ORFN
2II&.DQG&.? /2:
2II&.DQG&.? /2:
0LGOHYHO
t&.
Q?D
Q?D
Q?D
IDD Test
t5&
Q?D
Q?D
Q?D
t5$6
Q?D
Q?D
Q?D
t5&'
Q?D
Q?D
Q?D
tRRD
Q?D
Q?D
Q?D
t5&
Q?D
Q?D
Q?D
&/
Q?D
Q?D
Q?D
$/
Q?D
Q?D
Q?D
&6?
0LGOHYHO
0LGOHYHO
0LGOHYHO
&RPPDQG,QSXWV
0LGOHYHO
0LGOHYHO
0LGOHYHO
52:&2/081DGGUHVVHV
0LGOHYHO
0LGOHYHO
0LGOHYHO
%$1.DGGUHVVHV
0LGOHYHO
0LGOHYHO
0LGOHYHO
'DWD,2
0LGOHYHO
0LGOHYHO
0LGOHYHO
2XWSXWEXIIHU'4'46
(QDEOHG
(QDEOHG
0LGOHYHO
ODT
(QDEOHG0LGOHYHO
(QDEOHG0LGOHYHO
0LGOHYHO
%XUVW/HQJWK
Q?D
Q?D
Q?D
$FWLYH%$1.6
Q?D
Q?D
None
,'/(%$1.6
Q?D
Q?D
$OO
SRT
'LVDEOHGQRUPDO
(QDEOHGH[WHQGHG
Q?D
$65
'LVDEOHG
'LVDEOHG
Q?D
LOGIC Devices Incorporated
www.logicdevices.com
High Performance, Integrated Memory Module Product
March 6, 2013 LDS-L9D3xxxM32DBG2
LOGIC Devices Incorporated
Sub-Loop
CKE
www.logicdevices.com
CK, CK\
25
19
15
16
17
18
14
12
13
11
10
9
5
6
7
8
Cycle
Number
0
0
1
ACT
RDA
D
D
1
1
0
0
1
ACT
RDA
D
D
1
D
RAS\
1
0
0
0
1
0
0
1
0
0
0
CAS\
D
WE\
0
1
0
ODT
4
0
0
1
ACT
RDA
D
BA [2:0]
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
Repeat cycle 2 until n RRD - 1
1
1
0
1
0
0
0
0
1
0
1
0
1
0
0
0
0
1
0
0
0
Repeat cycle n RRD + 2 until 2 x n RRD - 1
Repeat sub-loop 0, use BA[2:0] = 2
Repeat sub-loop 0, use BA[2:0] = 3
0
0
0
3
0
0
0
Repeat cycle 4 x n RRD until n FAW - 1, if needed
Repeat sub-loop 0, use BA[2:0] = 4
Repeat sub-loop 1, use BA[2:0] = 5
Repeat sub-loop 0, use BA[2:0] = 6
Repeat sub-loop 1, use BA[2:0] = 7
0
0
0
7
0
0
0
Repeat cycle n FAW + 4 x n RRD until 2 x n FAW - 1, if needed
1
1
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
Repeat cycle 2 x n FAW + 2 until 2 x n FAW + n RRD - 1
1
1
0
1
0
0
0
0
1
0
1
0
1
0
0
0
0
1
0
0
0
Repeat cycle 2 x n FAW + n RRD + 2 until 2 x n FAW + 2 x n RRD - 1
Repeat sub-loop 10, use BA[2:0] = 2
Repeat sub-loop 11, use BA[2:0] = 3
0
0
0
3
0
0
0
Repeat cycle 2 x n FAW + 4 x n RRD until 3 x n FAW - 1, if needed
Repeat sub-loop 10, use BA[2:0] = 4
Repeat sub-loop 11, use BA[2:0] = 5
Repeat sub-loop 10, use BA[2:0] = 6
Repeat sub-loop 11, use BA[2:0] = 7
0
0
0
7
0
0
0
Repeat cycle 3 x n FAW + 4 x n RRD until 4 x n FAW - 1, if needed
A [15:11]
1
1
0
A [10]
1
0
0
A [9:7]
0
1
0
0
0
0
0
0
F
F
F
F
F
F
F
F
0
0
0
A [6:3]
2
3
0
0
1
Command
ACT
RDA
D
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
A [2:0]
1
CS\
0
1
2
3
n RRD
n RRD + 1
n RRD + 2
n RRD + 3
2 x n RRD
3x n RRD
4 x n RRD
4 x n RRD + 1
n FAW
n FAW + n RRD
n FAW + 2xn RRD
n FAW + 3xn RRD
n FAW + 4xn RRD
n FAW + 4xn RRD+1
2 x n FAW
2 x n FAW + 1
2 x n FAW + 2
2 x n FAW + 3
2 x n FAW + n RRD
2 x n FAW + n RRD+1
2 x n FAW + n RRD+2
2 x n FAW + n RRD+3
2 x nFAW + 2x n RRD
2 x n FAW + 3x n RRD
2 x n FAW + 4x n RRD
2 x n FAW+4x n RRD+1
3 x nFAW
3 x nFAW + nRRD
3 x nFAW + 2x nRRD
3 x nFAW + 3x nRRD
3 x nFAW + 4x nRRD
3 x nFAW + 4x nRRD +1
-
00000000
-
00110011
-
-
-
00110011
-
00000000
-
Data
0
PRELIMINARY INFORMATION
L9D3256M32DBG2
L9D3512M32DBG2
16-32 Gb, DDR3, 256-512M x 32 Dual Channel Memory Module
TABLE 15: IDD7 MEASUREMENT LOOP
Static HIGH
Toggling
High Performance, Integrated Memory Module Product
March 6, 2013 LDS-L9D3xxxM32DBG2
PRELIMINARY INFORMATION
L9D3256M32DBG2
L9D3512M32DBG2
16-32 Gb, DDR3, 256-512M x 32 Dual Channel Memory Module
TABLE 16A: IDD MAXIMUM LIMITS (256M)
Speed Bin
IDD
DDR3-1333
DDR3-1600
DDR3-1866
UNITS
IDD0
IDD1
IDD3
IDD3
IDD2Q
IDD2N
IDD3
IDD3N
IDD5
IDD:
IDD5B
IDD6
IDD
IDD8
320
80
128
200
232
292
960
800
88
IDD3P$
IDD3P$
IDD3P$
360
80
188
220
252
308
1120
900
880
88
IDD3P$
IDD3P$
IDD3P$
80
168
208
328
1200
1000
920
88
1280
IDD3P$
IDD3P$
IDD3P$
P$
P$
P$
P$
P$
P$
P$
P$
P$
P$
P$
P$
P$
P$
P$
P$
IND
(;7
0,/7(03
127(6T$ = 0°&WRd 85°&657DQG$65DUHGLVDEOHGHQDEOLQJ$65FRXOGLQFUHDVH,DD[E\XSWRDQDGGLWLRQDOP$
TABLE 16B: IDD MAXIMUM LIMITS (512M)
Speed Bin
IDD
DDR3-1333
DDR3-1600
DDR3-1866
UNITS
IDD0
IDD1
IDD3
IDD3
IDD2Q
IDD2N
IDD3
IDD3N
IDD5
IDD:
IDD5B
IDD6
IDD
IDD8
880
160
256
352
1920
1600
1680
2080
IDD3P$
IDD3P$
IDD3P$
920
160
296
616
1800
2280
IDD3P$
IDD3P$
IDD3P$
800
960
160
336
656
2000
2560
IDD3P$
IDD3P$
IDD3P$
P$
P$
P$
P$
P$
P$
P$
P$
P$
P$
P$
P$
P$
P$
P$
P$
IND
(;7
0,/7(03
127(6T$ = 0°&WRd 85°&657DQG$65DUHGLVDEOHGHQDEOLQJ$65FRXOGLQFUHDVH,DD[E\XSWRDQDGGLWLRQDOP$
LOGIC Devices Incorporated
www.logicdevices.com
26
High Performance, Integrated Memory Module Product
March 6, 2013 LDS-L9D3xxxM32DBG2
PRELIMINARY INFORMATION
L9D3256M32DBG2
L9D3512M32DBG2
16-32 Gb, DDR3, 256-512M x 32 Dual Channel Memory Module
TABLE 17: DC ELECTRICAL CHARACTERISTICS AND OPERATINGPC
ONDITIONS
ACKAGE
OUTLINE DIMENSIONS
$OO9ROWDJHVDUHUHIHUHQFHGWR9VV
Parameter/Condition
Supply Voltage
I/O Supply Voltage
Input Leakage Current:
Symbol
MIN
TYP
MAX
UNITS
NOTES
9DD
1.2825
1.35
9
1,2
9DDQ
1.2825
1.35
9
1,2
II
-
$
I95()
-
$
$Q\LQSXW9d9INd9DD95()SLQ9d9INd9
$OORWKHUSLQVQRWXQGHUWHVW 9
VREF Supply Leakage Current:
95()'4 9DDRU95()&$ 9DD
$OORWKHUSLQVQRWXQGHUWHVW 9
127(6
1.
9DDDQG9DD4PXVWWUDFNRQHDQRWKHU9DD4PXVWEHOHVVWKDQRUHTXDO
3.
95()VHH7DEOH
7KH PLQLPXP OLPLW UHTXLUHPHQW LV IRU WHVWLQJ SXUSRVHV 7KH OHDNDJH
WR9DD9VV 9VV4
2.
9DDDQG9DD4PD\LQFOXGH$&QRLVHRIP9N+]WR0+]LQ
FXUUHQWRQWKH95()SLQVKRXOGEHPLQLPDO
DGGLWLRQWRWKH'&+]WRN+]VSHFLILFDWLRQV9DDDQG9DD4PXVW
EHDWWKHVDPHOHYHOIRUYDOLG$&WLPLQJSDUDPHWHUV
TABLE 18: DC ELECTRICAL CHARACTERISTICS AND INPUT CONDITIONS
PACKAGE OUTLINE DIMENSIONS
$OO9ROWDJHVDUHUHIHUHQFHGWR9VV
Parameter/Condition
VIN low; DC/commands/address busses
VIN high; DC/commands/address busses
Symbol
MIN
TYP
9IL
9VV
QD
9,+
6HH7DEOH
MAX
UNITS
6HH7DEOH
9
QD
9DD
9
NOTES
Input reference voltage command/address bus
95()&$'&
[9DD
[9DD
[9DD
9
1,2
I/O reference voltage DQ bus
95()'4'&
[9DD
[9DD
[9DD
9
2,3
I/O reference voltage DQ bus in SELF REFRESH
95()'465
9VV
[9DD
9DD
9
9TT
-
[9DDQ
-
9
5
Command/address termination voltage V\VWHPOHYHOQRW
GLUHFW'5$0LQSXW
127(6
1.
95()&$'&LVH[SHFWHGWREHDSSUR[LPDWHO\[9DDDQGWRWUDFNYDUL-
PRQ PRGH RQ 95()'4 PD\ QRW H[FHHG [ 9DD around the
DWLRQVLQWKH'&OHYHO([WHUQDOO\JHQHUDWHGSHDNQRLVHQRQFRPPRQ
95()'4'&YDOXH3HDNWRSHDN$&QRLVHRQ95()'4VKRXOGQRW
PRGHRQ95()&$PD\QRWH[FHHG[9DDDURXQGWKH95()&$'&
H[FHHGRI95()'4'&
YDOXH3HDNWRSHDN$&QRLVHRQ95()&$VKRXOGQRWH[FHHGRI
95()&$'&
95()'4'& PD\ WUDQVLWLRQ WR 95()'465 DQG EDFN WR 95()'4'&
ZKHQ LQ 6(/) ]5()5(6+ ZLWKLQ UHVWULFWLRQV RXWOLQHG LQ WKH 6(/)
2.
'&YDOXHVDUHGHWHUPLQHGWREHOHVVWKDQ0+]LQIUHTXHQF\'5$0
5()5(6+VHFWLRQ
PXVW PHHW VSHFLILFDWLRQV LI WKH '5$0 LQGXFHV DGGLWLRQDO $& QRLVH
JUHDWHUWKDQ0+]LQIUHTXHQF\
5.
9TT LV QRW DSSOLHG GLUHFWO\ WR WKH GHYLFH 9TT LV D V\VWHP VXSSO\ IRU
VLJQDOWHUPLQDWLRQUHVLVWRUV0,1DQG0$;YDOXHVDUHV\VWHPGHSHQ-
3.
95()'4'& LV H[SHFWHG WR EH DSSUR[LPDWHO\ [ 9DD DQG WR WUDFN
dent.
YDULDWLRQVLQWKH'&OHYHO([WHUQDOO\JHQHUDWHGSHDNQRLVHQRQFRP-
LOGIC Devices Incorporated
www.logicdevices.com
High Performance, Integrated Memory Module Product
March 6, 2013 LDS-L9D3xxxM32DBG2
PRELIMINARY INFORMATION
L9D3256M32DBG2
L9D3512M32DBG2
16-32 Gb, DDR3, 256-512M x 32 Dual Channel Memory Module
TABLE 19: INPUT SWITCHING CONDITIONS
PACKAGE OUTLINE DIMENSIONS
Symbol
DDR3-1333
DDR3-1600
9,+$&0,1
Input high AC voltage: Logic 1
9,+$&0,1
Input high DC voltage: Logic 1
9,+'&0,1
Input high DC voltage: Logic 0
Input high AC voltage: Logic 0
Input high AC voltage: Logic 0
Parameter/Condition
DDR3-1866
UNITS
&RPPDQGDQG$GGUHVV
Input high AC voltage: Logic 1
-
P9
-
P9
P9
9,/'&0$;
-100
-100
P9
9,/$&0$;
-150
-
P9
9,/$&0$;
-
P9
DQ and DM
Input high AC voltage: Logic 1
9,+$&0,1
-
-
P9
Input high AC voltage: Logic 1
9,+$&0,1
-
P9
Input high DC voltage: Logic 1
9,+'&0,1
P9
Input high DC voltage: Logic 0
9,/'&0$;
-100
-100
P9
Input high AC voltage: Logic 0
9,/$&0$;
-150
-
P9
Input high AC voltage: Logic 0
9,/$&0$;
-
-
P9
127(6
1.
$OOYROWDJHVDUHUHIHUHQFHGWR95()95()LV95()&$IRUFRQWUROFRP-
3.
PDQGDQGDGGUHVV$OOVOHZUDWHVDQGVHWXSKROGWLPHVDUHVSHFLILHGDW
,QSXWKROGWLPLQJSDUDPHWHUVt,+DQG t'+DUHUHIHUHQFHGDW9IL'&
9,+'&QRW95()$&
WKH'5$0EDOO95()LV95()'4IRU'4DQG'0LQSXWV
2.
,QSXWVHWXSWLPLQJSDUDPHWHUVtIS and t'6DUHUHIHUHQFHGDW9IL$&
6LQJOHHQGHG LQSXW VOHZ UDWH 9QV PD[LPXP LQSXW YROWDJH VZLQJ
XQGHUWHVWLVP9SHDNWRSHDN
9,+$&QRW95()'&
LOGIC Devices Incorporated
www.logicdevices.com
28
High Performance, Integrated Memory Module Product
March 6, 2013 LDS-L9D3xxxM32DBG2
PRELIMINARY INFORMATION
L9D3256M32DBG2
L9D3512M32DBG2
16-32 Gb, DDR3, 256-512M x 32 Dual Channel Memory Module
OPERATING CONDITIONS
FIGURE 6 - INPUT SIGNAL
VIL and VIH levels with ringback
1.90V
VDDQ + 0.4V narrow pulse width
1.50V
VDDQ
Minimum VIL and VIH levels
VIH (AC)
0.925V
0.925V
VIH (AC)
VIH (DC)
VIH (DC)
0.850V
0.850V
0.780V
0.765V
0.750V
0.735V
0.720V
0.780V
0.765V
0.750V
0.735V
0.720V
VREF + AC noise
VREF + DC error
VREF + DC error
VREF + AC noise
0.650V
VIL (DQ)
0.575V
VIL (AC)
0.650V
VIL (DC)
0.575V
VIL (AC)
VSS
0.0V
VSS 0.4V narrow pulse width
-0.40V
Notes:
LOGIC Devices Incorporated
www.logicdevices.com
1. Numbers in diagrams reflect nominal values.
29
High Performance, Integrated Memory Module Product
March 6, 2013 LDS-L9D3xxxM32DBG2
PRELIMINARY INFORMATION
L9D3256M32DBG2
L9D3512M32DBG2
16-32 Gb, DDR3, 256-512M x 32 Dual Channel Memory Module
AC OVERSHOOT/UNDERSHOOT SPECIFICATION
TABLE 20: CONTROL AND ADDRESS PINS
PACKAGE OUTLINE DIMENSIONS
Parameter
DDR3-1333
DDR3-1600
DDR3-1866
9
9
9
9
9
9
Maximum overshoot area above Vcc VHH)LJXUH
9QV
9QV
9QV
Maximum undershoot area below Vss VHH)LJXUH
9QV
9QV
9QV
Maximum peak amplitude allowed for overshoot area
VHH)LJXUH
Maximum peak amplitude allowed for undershoot area
VHH)LJXUH
TABLE 21: CLOCK, DATA, STROBE, AND MASK PINS
PACKAGE OUTLINE DIMENSIONS
Parameter
DDR3-1333
Maximum peak amplitude allowed for overshoot area
DDR3-1600
DDR3-1866
9
9
9
9
9
9
9QV
9QV
9QV
9QV
9QV
9QV
VHH)LJXUH
Maximum peak amplitude allowed for undershoot area
VHH)LJXUH
Maximum overshoot area above Vcc/ VccQ
VHH)LJXUH
Maximum undershoot area below Vss/ VssQ
VHH)LJXUH
FIGURE 7 & 8: OVERSHOOT/UNDERSHOOT SPECIFICATIONS
Maximum amplitude
Volts (V)
Figure 7: Overshoot
Overshoot area
VDD/VDDQ
Time (ns)
Time (ns)
Figure 8: Undershoot
VSS/VSSQ
Volts (V)
Maximum amplitude
LOGIC Devices Incorporated
www.logicdevices.com
30
Undershoot area
High Performance, Integrated Memory Module Product
March 6, 2013 LDS-L9D3xxxM32DBG2
PRELIMINARY INFORMATION
L9D3256M32DBG2
L9D3512M32DBG2
16-32 Gb, DDR3, 256-512M x 32 Dual Channel Memory Module
TABLE 22: DIFFERENTIAL INPUT OPERATING CONDITIONS (CKXP, ACKAGE
CKX\, DQS
X, AND
DQSX\)
OUTLINE
DIMENSIONS
Parameter/Condition
Symbol
MIN
MAX
UNITS
NOTES
Differential input voltage, logic high - slew
9,+',))$&VOHZ
QD
P9
Differential input voltage, logic low - slew
9IL ',))$&VOHZ
QD
-200
P9
Differential input voltage, logic high
9,+',))$&
[9,+$&95()
9DD9DDQ
P9
5
Differential input voltage, logic low
9IL ',))$&
9VV9VVQ
[95()9IL$&
P9
6
9,;
95()'&
95()'&
P9
9,;
95()'&
95()'&
P9
96+(
9DD49,+$&
9DDQ
P9
5
9DD9,+$&
9DD
9VVQ
9DD49IL$&
P9
6
9VV
9DD-9IL$&
Differential input crossing voltage relative to VDD/2
for DQS, DQS\, CK, CK\
Differential input crossing voltage relative to VDD/2
for CK, CK\
Single-ended high level for strobes
Single-ended high level for CK, CK\
Single-ended low level for strobes
96(/
Single-ended low level for CK, CK\
127(6
1.
&ORFN LV UHIHUHQFHG WR 9DD' DQG 9VV 'DWD VWUREH LV UHIHUHQFHG WR
6.
9DD4DQG9VV4
2.
0,1OLPLWLVUHODWLYHWRVLQJOHHQGHGVLJQDOVWKHXQGHUVKRRWVSHFLILFDWLRQVDUHDSSOLFDEOH
5HIHUHQFHLV95()&$'&IRUFORFNDQGIRU95()'4'&IRUVWUREH
7KHW\SLFDOYDOXHRI9,;$&LVH[SHFWHGWREHDERXW[9DDRIWKH
WUDQVPLWWLQJGHYLFHDQG9,;$&LVH[SHFWHGWRWUDFNYDULDWLRQVLQ9DD.
3.
'LIIHUHQWLDOLQSXWVOHZUDWH 9PV
9,;$& LQGLFDWHV WKH YROWDJH DW ZKLFK GLIIHUHQWLDO LQSXW VLJQDOV PXVW
FURVV
'HILQHVVOHZUDWHUHIHUHQFHSRLQWVUHODWLYHWRLQSXWFURVVLQJYROWDJHV
5.
0$; OLPLW LV UHODWLYH WR VLQJOHHQGHG VLJQDOV WKH RYHUVKRRW VSHFLILFD-
9,;H[WHQGHGUDQJHLVRQO\DOORZHGZKHQWKHIROORZLQJFRQGLWLRQVDUH
WLRQVDUHDSSOLFDEOH
PHW7KHVLQJOHHQGHGLQSXWVLJQDOVDUHPRQRWRQLFKDYHWKHVLQJOH
8.
7KH9,;H[WHQGHGUDQJHP9LVDOORZHGRQO\IRUWKHFORFNDQGWKLV
HQGHGVZLQJ96(/96(+RIDWOHDVW9DDP9DQGWKHGLIIHUHQWLDO
VOHZUDWHRI&.&.?LVJUHDWHUWKDQ9QV
LOGIC Devices Incorporated
www.logicdevices.com
31
High Performance, Integrated Memory Module Product
March 6, 2013 LDS-L9D3xxxM32DBG2
PRELIMINARY INFORMATION
L9D3256M32DBG2
L9D3512M32DBG2
16-32 Gb, DDR3, 256-512M x 32 Dual Channel Memory Module
OVERSHOOT/UNDERSHOOT SPECIFICATIONS
FIGURE 9 - VIX FOR DIFFERENTIAL SIGNALS
VDD, VDDQ
VDD, VDDQ
CK#, DQS#
CK#, DQS#
VIX
X
VIX
VDD/2, VDDQ/2
X
VDD/2, VDDQ/2
X
VIX
VIX
X
CK, DQS
CK, DQS
VSS, VSSQ
VSS, VSSQ
FIGURE 10 - SINGLE-ENDED REQUIREMENTS FOR DIFFERENTIAL SIGNALS
V DD or VDD Q
VSEH (MIN)
V DD /2 or VDD Q/2
VSEH
CK or DQS
VSEL (MAX)
VSEL
VSS or VSS Q
LOGIC Devices Incorporated
www.logicdevices.com
32
High Performance, Integrated Memory Module Product
March 6, 2013 LDS-L9D3xxxM32DBG2
PRELIMINARY INFORMATION
L9D3256M32DBG2
L9D3512M32DBG2
16-32 Gb, DDR3, 256-512M x 32 Dual Channel Memory Module
OVERSHOOT/UNDERSHOOT SPECIFICATIONS
FIGURE 11 - DEFINITION OF DIFFERENTIAL AC-SWING AND tDVAC
t DVAC
V IHDIFF ( A C) MIN
V IHDIFF (MIN)
V IHDIFF ( DC) MIN
CK - CK#
DQ S - DQS #
0.0
V ILDIFF ( DC) MAX
V ILDIFF (MAX)
V ILDIFF ( A C) MAX
t DVAC
half cycle
TABLE 23: DIFFERENTIAL INPUT OPERATING CONDITIONS (tDVAC)
FOR CK
X, CKD
X\,
DQSX, AND DQSX\
PACKAGE
OUTLINE
IMENSIONS
%HORZ9IL$&
tDVAC (ps) at [VIHDIFF(AC) to VILDiff(AC)]
LOGIC Devices Incorporated
Slew Rate (V/ns)
350mV
300mV
-4.0
4.0
3.0
50
2.0
38
163
1.9
162
1.6
29
161
1.4
22
159
1.2
13
155
1.0
0
150
<1.0
0
150
www.logicdevices.com
33
High Performance, Integrated Memory Module Product
March 6, 2013 LDS-L9D3xxxM32DBG2
PRELIMINARY INFORMATION
L9D3256M32DBG2
L9D3512M32DBG2
16-32 Gb, DDR3, 256-512M x 32 Dual Channel Memory Module
SLEW RATE DEFINITIONS FOR SINGLE-ENDED INPUT SIGNALS
+ROGt,+DQGt'+QRPLQDOVOHZUDWHIRUDULVLQJVLJQDOLVGHILQHGDVWKHVOHZ
UDWHEHWZHHQWKHODVWFURVVLQJRI9IL'&0$;DQGWKHILUVWFURVVLQJRI95().
+ROGt,+DQGt'+QRPLQDOVOHZUDWHIRUDIDOOLQJVLJQDOLVGHILQHGDVWKHVOHZ
UDWHEHWZHHQWKHODVWFURVVLQJRI9,+'&0,1DQGWKHILUVWFURVVLQJRI95().
6HWXS tIS and t'6 QRPLQDO VOHZ UDWH IRU D ULVLQJ VLJQDO LV GHILQHG DV WKH
VOHZUDWHEHWZHHQWKHODVWFURVVLQJRI95()DQGWKHILUVWFURVVLQJ9,+$&
0,1 6HWXS tIS and t'6 QRPLQDO VOHZ UDWH IRU D IDOOLQJ VLJQDO LV GHILQHG
DVWKHVOHZUDWHEHWZHHQWKHODVWFURVVLQJRI95()DQWKHILUVWFURVVLQJRI
9IL$&0$;
TABLE 24: SINGLE-ENDED INPUT SLEW RATE
Measured
Input Slew Rate (Linear Signals)
Input
PACKAGE OUTLINE DIMENSIONS
Edge
From
To
5LVLQJ
95()
9,+$&0,1
Falling
95()
9IL$&0$;
5LVLQJ
9IL'&0D[
95()
Setup
Calculation
9,+$&0,195()
95()9IL$&0$;
'TFS
95()9IL'&0$;
'7)+
Hold
Falling
9,+'&0,1
95()
9,+'&0,195()
'756+
LOGIC Devices Incorporated
www.logicdevices.com
High Performance, Integrated Memory Module Product
March 6, 2013 LDS-L9D3xxxM32DBG2
PRELIMINARY INFORMATION
L9D3256M32DBG2
L9D3512M32DBG2
16-32 Gb, DDR3, 256-512M x 32 Dual Channel Memory Module
SLEW RATE DEFINITIONS FOR SINGLE-ENDED INPUT SIGNALS
FIGURE 12 - NOMINAL SLEW RATE DEFINITION FOR SINGLE-ENDED INPUT SIGNALS
ΔTRS
Setup
Single-ended input voltage (DQ, CMD, ADDR)
VIH(AC) MIN
VIH(DC) MIN
VREFDQ or
VREFCA
VIL(DC) MAX
VIL(AC) MAX
ΔTFS
ΔTRH
Hold
Single-ended input voltage (DQ, CMD, ADDR)
VIH(AC) MIN
VIH(DC) MIN
VREFDQ or
VREFCA
VIL(DC) MAX
VIL(AC) MAX
ΔTFH
LOGIC Devices Incorporated
www.logicdevices.com
35
High Performance, Integrated Memory Module Product
March 6, 2013 LDS-L9D3xxxM32DBG2
PRELIMINARY INFORMATION
L9D3256M32DBG2
L9D3512M32DBG2
16-32 Gb, DDR3, 256-512M x 32 Dual Channel Memory Module
SLEW RATE DEFINITIONS FOR DIFFERENTIAL INPUT SIGNALS
,QSXWVOHZUDWHIRUGLIIHUHQWLDOVLJQDOV&.[&.[?8'46[8'46[?/'46[DQG/'46[?DUHGHILQHGDQGPHDVXUHGDVVKRZQLQ7DEOH7KHQRPLQDOVOHZ
UDWHIRUDULVLQJVLJQDOLVGHILQHGDVWKHVOHZUDWHEHWZHHQ9IL',))0$;DQG9,+',))0,17KHQRPLQDOVOHZUDWHIRUDIDOOLQJVLJQDOLVGHILQHGDVWKHVOHZ
UDWHEHWZHHQ9,+',))0,1DQG9IL',))0$;
TABLE 25: DIFFERENTIAL INPUT SLEW RATE DEFINITION
Measured
Input Slew Rate (Linear Signals)
Input
Edge
PACKAGE OUTLINE DIMENSIONS
From
5LVLQJ
95()
To
Calculation
9,+',))0,1- 9IL',))0$;
9,+$&0,1
'75',))
CK and DQS
Reference
9,+',))0,1 9IL',))0$;
Falling
95()
9,/$&0$;
'7)',))
FIGURE 13 - NOMINAL DIFFERENTIAL INPUT SLEW RATE DEFINITION FOR DQS, DQS# AND CK, CK#
Differential input voltage (DQS, DQS#; CK, CK#)
ΔTR DIFF
VIH(DIFF) MIN
0
VIL(DIFF) MAX
ΔTFDIFF
LOGIC Devices Incorporated
www.logicdevices.com
36
High Performance, Integrated Memory Module Product
March 6, 2013 LDS-L9D3xxxM32DBG2
PRELIMINARY INFORMATION
L9D3256M32DBG2
L9D3512M32DBG2
16-32 Gb, DDR3, 256-512M x 32 Dual Channel Memory Module
ODT CHARACTERISTICS
FIGURE 14 - ODT LEVELS AND I-V CHARACTERISTICS
Chip in termination mode
2'7uV HIIHFWLYH UHVLVWDQFH 5TT LV GHILQHG E\ 05> DQG @ 2'7 LV
DSSOLHGWRWKH'4[8'0[/'0[8'46[8'46[?/'46[DQG/'46[?
EDOOV7KH2'7WDUJHWYDOXHVDUHOLVWHGLQ7DEOH
ODT
VDD Q
IPU
IOUT = IPD - IPU
To
other
circuitry
such as
RCV, . . .
RTTPU
DQ
IOUT
R TTPD
VOUT
IPD
VSSQ
TABLE 26: ON-DIE TERMINATION DC ELECTRICAL CHARACTERISTICS
Parameter/Condition
Symbol
RTTHIIHFWLYHLPSHGDQFH
RTTB())
'HYLDWLRQRI90ZLWKUHVSHFWWR9DD4
'90
MIN
TYP
MAX
UNITS
NOTES
6HH7DEOH
-5
5
127(6
1.
7ROHUDQFH OLPLWV DUH DSSOLFDEOH DIWHU D SURSHU =4 FDOLEUDWLRQ KDV EHHQ
3.
0HDVXUHYROWDJH90DWWKHWHVWHGSLQZLWKQRORDG
SHUIRUPHGDWDVWDEOHWHPSHUDWXUHDQGYROWDJH9DD4 9DD9VV49VV
5HIHUWRv2'76HQVLWLYLW\wRQSDJHLIHLWKHUWKHWHPSHUDWXUHRUYROWDJH
'90
FKDQJHVDIWHUFDOLEUDWLRQ
2.
[90
-1 x 100
9DDQ
0HDVXUHPHQWGHILQLWLRQIRU5TT$SSO\9,+$&WRDSLQXQGHUWHVWDQG
PHDVXUHWKHFXUUHQW,>9,+$&@WKHQDSSO\9IL$&WRSLQXQGHUWHVWDQG
)RU H[WHQGHG 0,/WHPS GHYLFHV WKH PLQLPXP YDOXHV DUH GHUDWHG E\
ZKHQWKHGHYLFHLVEHWZHHQ&DQG&T$
PHDVXUHFXUUHQW,>9IL$&@
9IL$&9IL$&
RTT =
LOGIC Devices Incorporated
,>9,+$&,9IL$&@
www.logicdevices.com
High Performance, Integrated Memory Module Product
March 6, 2013 LDS-L9D3xxxM32DBG2
PRELIMINARY INFORMATION
L9D3256M32DBG2
L9D3512M32DBG2
16-32 Gb, DDR3, 256-512M x 32 Dual Channel Memory Module
TABLE 27: RTT EFFECTIVE IMPEDANCES
MR1
[9,6,2]
RTT
PACKAGE OUTLINE DIMENSIONS
Resistor
RTT1203'
0, 1, 0
120:
RTT12038
120:
RTT603'120
0, 0, 1
60:
RTT6038
60:
RTT3'80
0, 1, 1
:
RTT3880
:
RTT303'60
1, 0, 1
30:
RTT303860
30:
RTT203'
1, 0, 0
20:
RTT2038
20:
LOGIC Devices Incorporated
www.logicdevices.com
VOUT
MIN
TYP
MAX
UNITS
[9DDQ
0.6
1.0
1.1
5=4
[9DDQ
0.9
1.0
1.1
5=4
[9DDQ
0.9
1.0
5=4
[9DDQ
0.9
1.0
5=4
[9DDQ
0.9
1.0
1.1
5=4
[9DDQ
0.9
1.0
1.1
5=4
9IL$&WR9,+$&
0.9
1.0
1.6
5=4
[9DDQ
0.6
1.0
1.1
5=4
[9DDQ
0.9
1.0
1.1
5=4
[9DDQ
0.9
1.0
5=4
[9DDQ
0.9
1.0
5=4
[9DDQ
0.9
1.0
1.1
5=4
[9DDQ
0.9
1.0
1.1
5=4
9IL$&WR9,+$&
0.9
1.0
1.6
5=4
[9DDQ
0.6
1.0
1.1
5=4
[9DDQ
0.9
1.0
1.1
5=4
[9DDQ
0.9
1.0
5=4
[9DDQ
0.9
1.0
5=4
[9DDQ
0.9
1.0
1.1
5=4
[9DDQ
0.9
1.0
1.1
5=4
9IL$&WR9,+$&
0.9
1.0
1.6
5=4
[9DDQ
0.6
1.0
1.1
5=4
[9DDQ
0.9
1.0
1.1
5=4
[9DDQ
0.9
1.0
5=4
[9DDQ
0.9
1.0
5=4
[9DDQ
0.9
1.0
1.1
5=4
[9DDQ
0.9
1.0
1.1
5=4
9IL$&WR9,+$&
0.9
1.0
1.6
5=4
[9DDQ
0.6
1.0
1.1
5=4
[9DDQ
0.9
1.0
1.1
5=4
[9DDQ
0.9
1.0
5=4
[9DDQ
0.9
1.0
5=4
[9DDQ
0.9
1.0
1.1
5=4
[9DDQ
0.9
1.0
1.1
5=4
9IL$&WR9,+$&
0.9
1.0
1.6
5=4
38
High Performance, Integrated Memory Module Product
March 6, 2013 LDS-L9D3xxxM32DBG2
PRELIMINARY INFORMATION
L9D3256M32DBG2
L9D3512M32DBG2
16-32 Gb, DDR3, 256-512M x 32 Dual Channel Memory Module
ODT SENSITIVITY
,IHLWKHUWKHWHPSHUDWXUHRUYROWDJHFKDQJHVDIWHU,2FDOLEUDWLRQWKHWROHUDQFHOLPLWVOLVWHGLQ7DEOHFDQEHH[SHFWHGWRZLGHQDFFRUGLQJWR7DEOHVDQG
TABLE 28: ODT SENSITIVITY DEFINITION
Symbol
RTT
MIN
0.9 - dRTTdT x dRTTG9[>'9@
MAX
UNITS
5=4
G5TTG7[>'7@G5TTG9[>'9@
TABLE 29 - ODT TEMPERATURE & VOLTAGE SENSITIVITY
Change
MIN
MAX
UNITS
dRTTdT
0
1.5
0
dRTTdV
0
0.15
0
FIGURE 15 - ODT TIMING REFERENCE LOAD
ODT TIMING DEFINITIONS
2'7ORDGLQJGLIIHUVIURPWKDWXVHGLQ$&WLPLQJPHDVXUHPHQWV7ZRSDUDPHWHUVGHILQHZKHQ2'7WXUQVRQRURIIV\QFKURQRXVO\WZRGHILQHZKHQ2'7
WXUQVRQRURII$V\QFKURQRXVO\DQGDQRWKHUGHILQHVZKHQ2'7WXUQVRQRU
RIIG\QDPLFDOO\7DEOHRXWOLQHVDQGSURYLGHVGHILQLWLRQDQGPHDVXUHPHQW
UHIHUHQFHVHWWLQJVIRUHDFKSDUDPHWHU
DUT
CK, CK#
2'7 WXUQRQ WLPH EHJLQV ZKHQ WKH RXWSXW OHDYHV +,*+= DQG 2'7 UHVLVWDQFHEHJLQVWRWXUQRQ2'7WXUQRIIWLPHEHJLQVZKHQWKHRXWSXWOHDYHV
/2:=DQG2'7UHVLVWDQFHEHJLQVWRWXUQRII
VREF
DQ, DM
DQS, DQS#
ZQ
VDDQ/2
RTT = 25Ω
VTT = VSSQ
Timing reference point
RZQ = 240Ω
VSSQ
LOGIC Devices Incorporated
www.logicdevices.com
39
High Performance, Integrated Memory Module Product
March 6, 2013 LDS-L9D3xxxM32DBG2
PRELIMINARY INFORMATION
L9D3256M32DBG2
L9D3512M32DBG2
16-32 Gb, DDR3, 256-512M x 32 Dual Channel Memory Module
ODT TIMING DEFINITIONS
TABLE 30: ODT TIMING DEFINITIONS
Symbol
PACKAGE OUTLINE DIMENSIONS
End Point Definition
Figure
5LVLQJHGJHRI&.&.?GHILQHGE\WKHHQGSRLQWRI2'7/RQ
Begin Point Definition
([WUDSRODWHGSRLQWDW9VV4
)LJXUHRQSDJH
tAOF
5LVLQJHGJHRI&.&.?GHILQHGE\WKHHQGSRLQWRI2'7/RII
([WUDSRODWHGSRLQWDW95TT_NORM
)LJXUHRQSDJH
tAONPD
5LVLQJHGJHRI&.&.?ZLWK2'7ILUVWEHLQJUHJLVWHUHG+,*+
([WUDSRODWHGSRLQWDW9VV4
)LJXUHRQSDJH
5LVLQJHGJHRI&.&.?ZLWK2'7ILUVWEHLQJUHJLVWHUHG/2:
([WUDSRODWHGSRLQWDW95TT_NOM
)LJXUHRQSDJH
5LVLQJHGJHRI&.&.?GHILQHGE\WKHHQGSRLQWRI2'7/&1:
([WUDSRODWHGSRLQWVDW95TTB:5DQG95TT_NOM
)LJXUHRQSDJH
tAON
tAOFPD
tADC
2'7/&:1RU2'7/&:1
TABLE 31: REFERENCE SETTINGS FOR ODT TIMING MEASUREMENTS
PACKAGE OUTLINE DIMENSIONS
Measured
Parameter
RTT_NORM Setting
tAON
tAOF
tAONPD
tAOFPD
tADC
VSW1
VSW2
5=4:
RTT_WR_Setting
QD
P9
P9
5=4:
QD
P9
P9
5=4:
QD
P9
P9
5=4:
QD
P9
P9
5=4:
QD
P9
P9
5=4:
QD
P9
P9
5=4:
QD
P9
P9
5=4:
QD
P9
P9
5=4:
5=4:
P9
P9
FIGURE 16 - tAON AND tAOF DEFINITIONS
t AON
t AOF
Begin point: Rising edge of CK - CK#
defined by the end point of ODTL off
Begin point: Rising edge of CK - CK#
defined by the end point of ODTL on
CK
CK
VDDQ/2
CK#
CK#
t AON
t AOF
End point: Extrapolated point at VRTT_NOM
TSW 2
VRTT_NOM
TSW 1
TSW 1
TSW 1
VSW 2
DQ, DM
DQS, DQS#
VSS Q
VSW 2
VSW 1
VSW 1
VSS Q
End point: Extrapolated point at VSS Q
LOGIC Devices Incorporated
www.logicdevices.com
High Performance, Integrated Memory Module Product
March 6, 2013 LDS-L9D3xxxM32DBG2
PRELIMINARY INFORMATION
L9D3256M32DBG2
L9D3512M32DBG2
16-32 Gb, DDR3, 256-512M x 32 Dual Channel Memory Module
ODT CHARACTERISTICS
FIGURE 17 - tAONPD AND tAOFPD DEFINITION
t AONPD
t AOFPD
Begin point: Rising edge of CK - CK#
with ODT first registered HIGH
Begin point: Rising edge of CK - CK#
with ODT first registered LOW
CK
CK
VDD Q/2
CK#
CK#
t AONPD
t AOFPD
End point: Extrapolated point at VRTT_NOM
VRTT_NOM
TSW 2
TSW 2
TSW 1
TSW 1
VSW 2
VSW 2
DQ, DM
DQS, DQS#
VSW 1
VSW1
VSS Q
VSS Q
End point: Extrapolated point at VSS Q
FIGURE 18 - tADC DEFINITION
Begin point: Rising edge of CK - CK#
defined by the end point of ODTLCNW
Begin point: Rising edge of CK - CK#
defined by the end point of ODTLCNW4 or ODTLCNW8
CK
VDDQ/2
CK#
t ADC
VRTT_NOM
DQ, DM
DQS, DQS#
End point:
Extrapolated
point at VRTT_NOM
t ADC
VRTT_NOM
TSW 21
TSW 11
VSW 2
TSW 22
TSW 12
VSW 1
VRTT_WR
End point: Extrapolated point at VRTT_WR
VSS Q
LOGIC Devices Incorporated
www.logicdevices.com
High Performance, Integrated Memory Module Product
March 6, 2013 LDS-L9D3xxxM32DBG2
PRELIMINARY INFORMATION
L9D3256M32DBG2
L9D3512M32DBG2
16-32 Gb, DDR3, 256-512M x 32 Dual Channel Memory Module
OUTPUT DRIVER IMPEDANCE
FIGURE 19 - OUTPUT DRIVER
34 OHM OUTPUT DRIVER IMPEDANCE
7KH:GULYHU05>@ LVWKHGHIDXOWGULYHU8QOHVVRWKHUZLVHVWDWHG
DOOWLPLQJVDQGVSHFLILFDWLRQVOLVWHGKHUHLQDSSO\WRWKH:GULYHURQO\,WV
LPSHGDQFH 5ON LV GHILQHG E\ WKH YDOXH RI WKH H[WHUQDO UHIHUHQFH UHVLVWRU
5=4DVIROORZV5ON 5=4ZLWKQRPLQDO5=4 :DQGLVDFWXDOO\:7KH:RXWSXWGULYHULPSHGDQFHFKDUDFWHULVWLFVDUHOLVWHG
LQ7DEOH
Chip in drive mode
Output driver
VDDQ
IPU
To
other
circuitry
such as
RCV, . . .
RONPU
DQ
IOUT
RONPD
IPD
VOUT
VSSQ
TABLE 32: 34: DRIVER IMPEDANCE CHARACTERISTICS
MR1[5,1]
0, 1
RON
PACKAGE OUTLINE DIMENSIONS
RESISTOR
VOUT
MIN
TYP
MAX
UNITS
9DDQ
0.6
1.0
1.1
5=4
1
RON34PD
9DDQ
0.9
1.0
1.1
5=4
1
9DDQ
0.9
1.0
5=4
1
9DDQ
0.9
1.0
5=4
1
9DDQ
0.9
1.0
1.1
5=4
1
9DDQ
0.6
1.0
1.1
5=4
1
9DDQ
-10
QD
10
1, 2
34.3:
RON34PU
Pull-Up/Pull-Down mismatch (MMPUPD)
NOTES
127(6
1.
7ROHUDQFHOLPLWVDVVXPH5=4RI:DQGDUHDSSOLFDEOHDIWHUSURSHU=4FDOLEUDWLRQKDVEHHQSHUIRUPHGDWDVWDEOHWHPSHUDWXUHDQGYROWDJH
9DD4 9DD9VV4 9VV5HIHUWRv2KPGULYHVHQVLWLYLW\wLIHLWKHUWKHWHPSHUDWXUHRUWKHYROWDJHFKDQJHVDIWHUFDOLEUDWLRQ
2.
0HDVXUHPHQWGHILQLWLRQIRUPLVPDWFKEHWZHHQSXOOXSDQGSXOOGRZQ00383'0HDUXUHERWK52138 and R213'DW[9DDQ:
MM38' =
R2138 - R213'
RONNOM
LOGIC Devices Incorporated
www.logicdevices.com
High Performance, Integrated Memory Module Product
March 6, 2013 LDS-L9D3xxxM32DBG2
PRELIMINARY INFORMATION
L9D3256M32DBG2
L9D3512M32DBG2
16-32 Gb, DDR3, 256-512M x 32 Dual Channel Memory Module
34 OHM OUTPUT DRIVER IMPEDANCE
34 OHM DRIVER
7KH:GULYHUuVFXUUHQWUDQJHKDVEHHQFDOFXODWHGDQGVXPPDUL]HGLQ7DEOHIRU9DD 97DEOHIRU9DD 9DQG7DEOHIRU9DD 9
7KHLQGLYLGXDOSXOOXSDQGSXOOGRZQUHVLVWRUV5213'DQG52138DUHGHILQHGDVIROORZVZLWKWKH,PSHGDQFH&DOFXODWLRQVOLVWHGLQ7DEOH
xRON3' 9287>,287@52138LVWXUQHGRII
xRON38 9DD49287>,287@5213'LVWXUQHGRII
TABLE 33: 34: DRIVER PULL-UP AND PULL-DOWN IMPEDANCE
CALCULATIONS
PACKAGE
OUTLINE DIMENSIONS
MR1[5,1]
RON
RON
MIN
RZQ = 240:±1%
RZQ = (240:±1%)/7
RESISTOR
RON34PD
0, 1
34.3:
RON34PU
TYP
MAX
UNITS
:
33.9
:
VOUT
MIN
TYP
MAX
9DDQ
38.1
UNITS
:
9DDQ
30.5
38.1
:
9DDQ
30.5
:
9DDQ
30.5
:
9DDQ
30.5
38.1
:
9DDQ
38.1
:
TABLE 34: 34: DRIVER IOH/IOL CHARACTERISTICS: VDD = VPDD
Q = 1.35V
ACKAGE
OUTLINE DIMENSIONS
MR1[5,1]
RON
RESISTOR
RON34PD
0, 1
34.3:
RON34PU
VOUT
MIN
TYP
MAX
UNITS
IOL#[9DDQ
8.8
P$
IOL#[9DDQ
21.9
P$
IOL#[9DDQ
39.3
35
P$
IOL#[9DDQ
39.3
35
P$
IOL#[9DDQ
21.9
P$
IOL#[9DDQ
8.8
P$
TABLE 35: 34: DRIVER IOH/IOL CHARACTERISTICS: VDD=VDD
Q=1.4175V
PACKAGE
OUTLINE DIMENSIONS
MR1[5,1]
RON
RESISTOR
RON34PD
0, 1
34.3:
RON34PU
LOGIC Devices Incorporated
www.logicdevices.com
VOUT
MIN
TYP
IOL#[9DDQ
15.5
9.2
8.3
P$
IOL#[9DDQ
25.8
23
P$
IOL#[9DDQ
36.8
26
P$
IOL#[9DDQ
36.8
26
P$
IOL#[9DDQ
25.8
23
P$
IOL#[9DDQ
15.5
9.2
8.3
P$
MAX
UNITS
High Performance, Integrated Memory Module Product
March 6, 2013 LDS-L9D3xxxM32DBG2
PRELIMINARY INFORMATION
L9D3256M32DBG2
L9D3512M32DBG2
16-32 Gb, DDR3, 256-512M x 32 Dual Channel Memory Module
34 OHM OUTPUT DRIVER IMPEDANCE
TABLE 36: 34: DRIVER IOH/IOL CHARACTERISTICS: VDD=VDD
Q=1.2825V
PACKAGE
OUTLINE DIMENSIONS
MR1[5,1]
RON
RESISTOR
RON34PD
0, 1
34.3:
RON34PU
VOUT
MIN
TYP
MAX
UNITS
IOL#[9DDQ
8.3
P$
IOL#[9DDQ
23.3
20.8
P$
IOL#[9DDQ
33.3
23.5
P$
IOL#[9DDQ
33.3
23.5
P$
IOL#[9DDQ
23.3
20.8
P$
IOL#[9DDQ
8.3
P$
34: OUTPUT DRIVER SENSITIVITY
,IHLWKHUWKHWHPSHUDWXUHRUYROWDJHFKDQJHVDIWHU=4FDOLEUDWLRQWKHWROHUDQFHOLPLWVOLVWHGLQ7DEOHFDQEHH[SHFWHGWRZLGHQDFFRUGLQJWR7DEOHDQG
TABLE 37: 34: OUTPUT DRIVER SENSITIVITY DEFINITION
Symbol
MIN
MAX
UNITS
RON @ 0.8 x VDDQ
0.9 - dRONG7+[>'7@G5ONG9+[>'9@
1.1 - dRONG7+[>'7@G5ONG9+[>'9@
5=4
RON @ 0.5 x VDDQ
0.9 - dRONdTM x ['7@G5ONG90[>'9@
1.1 - dRONdTM x ['7@G5ONG90[>'9@
5=4
RON @ 0.2 x VDDQ
0.9 - dRONdTL x ['7@G5ONG9/[>'9@
1.1 - dRONdTL x ['7@G5ONG9/[>'9@
5=4
TABLE 38: 34: OUTPUT DRIVER VOLTAGE AND TEMPERATURE SENSITIVITY
Change
MIN
MAX
UNITS
dRONdTM
0
1.5
&
dRONdVM
0
0.13
P9
dRONdTL
0
1.5
&
dRONdVL
0
0.13
P9
dRONdTH
0
1.5
&
dRONdVH
0
0.13
P9
LOGIC Devices Incorporated
www.logicdevices.com
High Performance, Integrated Memory Module Product
March 6, 2013 LDS-L9D3xxxM32DBG2
PRELIMINARY INFORMATION
L9D3256M32DBG2
L9D3512M32DBG2
16-32 Gb, DDR3, 256-512M x 32 Dual Channel Memory Module
ALTERNATIVE 40 OHM DRIVER
TABLE 39 - 40: DRIVER IMPEDANCE CHARACTERISTICS
MR1[5,1]
0, 1
RON
PACKAGE OUTLINE DIMENSIONS
RESISTOR
VOUT
MIN
TYP
MAX
UNITS
NOTES
9DDQ
0.6
1.0
1.1
5=4
1
RON40PD
9DDQ
0.9
1.0
1.1
5=4
1
9DDQ
0.9
1.0
5=4
1
9DDQ
0.9
1.0
5=4
1
9DDQ
0.9
1.0
1.1
5=4
1
9DDQ
0.6
1.0
1.1
5=4
1
9DDQ
-10
QD
10
1, 2
40.0:
RON40PU
Pull-Up/Pull-Down mismatch (MMPUPD)
127(6
1.
7ROHUDQFHOLPLWVDVVXPH5=4RI:DQGDUHDSSOLFDEOHDIWHUSURSHU=4FDOLEUDWLRQKDVEHHQSHUIRUPHGDWDVWDEOHWHPSHUDWXUHDQGYROWDJH
9DD4 9DD9VV4 9VV5HIHUWRv2KPGULYHVHQVLWLYLW\wLIHLWKHUWKHWHPSHUDWXUHRUWKHYROWDJHFKDQJHVDIWHUFDOLEUDWLRQ
2.
0HDVXUHPHQWGHILQLWLRQIRUPLVPDWFKEHWZHHQSXOOXSDQGSXOOGRZQ00383'0HDUXUHERWK5ON38DQG5ON3'DW[9DDQ:
MM383' = R2138 - R213'
x 100
RONNOM
40: OUTPUT DRIVER SENSITIVITY
,IHLWKHUWKHWHPSHUDWXUHRUYROWDJHFKDQJHVDIWHU,2FDOLEUDWLRQWKHWROHUDQFHOLPLWVOLVWHGLQ7DEOHFDQEHH[SHFWHGWRZLGHQDFFRUGLQJWR7DEOHDQG
TABLE 40: 40: OUTPUT DRIVER SENSITIVITY DEFINITION
Symbol
MIN
MAX
UNITS
RON @ 0.8 x VDDQ
0.9 - dRONG7+[>'7@G5ONG9+[>'9@
1.1 - dRONG7+[>'7@G5ONG9+[>'9@
5=4
RON @ 0.5 x VDDQ
0.9 - dRONdTM x ['7@G5ONG90[>'9@
1.1 - dRONdTM x ['7@G5ONG90[>'9@
5=4
RON @ 0.2 x VDDQ
0.9 - dRONdTL x ['7@G5ONG9/[>'9@
1.1 - dRONdTL x ['7@G5ONG9/[>'9@
5=4
LOGIC Devices Incorporated
www.logicdevices.com
High Performance, Integrated Memory Module Product
March 6, 2013 LDS-L9D3xxxM32DBG2
PRELIMINARY INFORMATION
L9D3256M32DBG2
L9D3512M32DBG2
16-32 Gb, DDR3, 256-512M x 32 Dual Channel Memory Module
ALTERNATIVE 40 OHM DRIVER
TABLE 41: 40: OUTPUT DRIVER VOLTAGE AND TEMPERATURE SENSITIVITY
Change
MIN
MAX
dRONdTM
0
1.5
UNITS
&
dRONdVM
0
0.15
P9
dRONdTL
0
1.5
&
dRONdVL
0
0.15
P9
dRONdTH
0
1.5
&
dRONdVH
0
0.15
P9
OUTPUT CHARACTERISTICS AND OPERATING CONDITIONS
7KH6'5$0XVHVERWKVLQJOHHQGHGDQGGLIIHUHQWLDORXWSXWGULYHUV7KHVLQJOHHQGHGRXWSXWGULYHULVVXPPDUL]HGLQ7DEOHZKLOHWKHGLIIHUHQWLDORXWSXW
GULYHULVVXPPDUL]HGLQ7DEOH
TABLE 42: SINGLE-ENDED OUTPUT DRIVER CHARACTERISTICS PACKAGE OUTLINE DIMENSIONS
Parameter/Condition
Output leakage current:'4DUHGLVDEOHG
Symbol
MIN
UNITS
NOTES
I2=
-5
MAX
5
X$
1
6546(
2.5
6
9QV
9d9287d9DD42'7LVGLVDEOHG2'7LV+,*+
Output slew rate:6LQJOHHQGHGIRUULVLQJDQGIDOOLQJ
HGJHVPHDVXUHEHWZHHQ9OL$& 95()[9DDQ
DQG92+$& 95()[9DDQ
Single-ended DC high-level output voltage
92+'&
[9DDQ
9
1, 2, 5
Single-ended DC mid-point level output voltage
9OM'&
[9DDQ
9
1, 2, 5
Single-ended DC low-point level output voltage
9OL'&
[9DDQ
9
1, 2, 5
Single-ended DC high-point level output voltage
92+$&
977[9DDQ
9
1, 2, 3, 6
Single-ended DC low-point level output voltage
9OL$&
977[9DDQ
9
1, 2, 3, 6
Delta RON between pull-up and pull-down for DQ/DQS
MM383'
Test load for AC timing and output slew rates
-10
10
3
2XWSXWWR9TT9DD4YLD:UHVLVWRU
127(6
1.
5=4RI:ZLWK5=4HQDEOHGGHIDXOW:GULYHUDQGLVDSSOL-
5.
6HH7DEOHRQSDJH,9FXUYHOLQHDULW\'RQRWXVH$&7HVWORDG
FDEOH DIWHU SURSHU =4 FDOLEUDWLRQ KDV EHHQ SHUIRUPHG DW D VWDEOH WHP-
6.
6HH7DEOHRQSDJHIRURXWSXWVOHZUDWH
SHUDWXUHDQGYROWDJH9DD4 9DD9VV4 9VV
6HH7DEOHRQSDJHIRUDGGLWLRQDOLQIRUPDWLRQ
2.
9TT 9DD4
8.
6HH )LJXUH RQ SDJH IRU DQ H[DPSOH RI D VLQJOHHQGHG RXWSXW
3.
6HH)LJXUHRQSDJHIRUWKHWHVWORDGFRQILJXUDWLRQ
7KH9QVPD[LPXPLVDSSOLFDEOHIRUDVLQJOH'4VLJQDOZKHQLWLVVZLWFK-
VLJQDO
LQJIURPHLWKHU+,*+WR/2:RU/2:WR+,*+ZKLOHWKHUHPDLQLQJ'4
VLJQDOVLQWKHVDPHE\WHODQHDUHFRPELQDWLRQVWKHPD[LPXPOLPLWRI9
QVPD[LPXPLVUHGXFHGWR9QV
LOGIC Devices Incorporated
www.logicdevices.com
High Performance, Integrated Memory Module Product
March 6, 2013 LDS-L9D3xxxM32DBG2
PRELIMINARY INFORMATION
L9D3256M32DBG2
L9D3512M32DBG2
16-32 Gb, DDR3, 256-512M x 32 Dual Channel Memory Module
TABLE 43: DIFFERENTIAL OUTPUT DRIVER CHARACTERISTICS PACKAGE OUTLINE DIMENSIONS
Parameter/Condition
Output leakage current:'4DUHGLVDEOHG
Symbol
MIN
MAX
UNITS
NOTES
I2=
-5
5
X$
1
SRQDIFF
5
12
9QV
1
92;$&
95()-150
95()
P9
1, 2, 3
9d9287d9DD42'7LV+,*+
Output slew rate:'LIIHUHQWLDOIRUULVLQJDQGIDOOLQJHGJHV
PHDVXUHEHWZHHQ9OL',))$& [9DD4DQG92+
$& [9DDQ
Output differential cross-point voltage
Differential high-level output voltage
92+',))$&
[9DDQ
9
Differential low-level output voltage
9OL',))$&
[9DDQ
9
1, 5
Delta RON between pull-up and pull-down for DQ/DQS
MM383'
-10
10
2XWSXWWR9TT9DD4YLD:UHVLVWRU
Test load for AC timing and output slew rates
3
127(6
1.
5=4RI:ZLWK5=4HQDEOHGGHIDXOW:GULYHUDQGLVDSSOL-
6HH7DEOHRQSDJHIRUWKHRXWSXWVOHZUDWH
FDEOH DIWHU SURSHU =4 FDOLEUDWLRQ KDV EHHQ SHUIRUPHG DW D VWDEOH WHP-
5.
6HH7DEOHRQSDJHIRUDGGLWLRQDOLQIRUPDWLRQ
SHUDWXUHDQGYROWDJH9DD4 9DD9VV4 9VV
6.
6HH)LJXUHRQSDJHIRUDQH[DPSOHRIDGLIIHUHQWLDORXWSXWVLJQDO
2.
95() 9DD4
3.
6HH)LJXUHRQSDJHIRUWKHWHVWORDGFRQILJXUDWLRQ
FIGURE 20 - DQ OUTPUT SIGNAL
MAX output
VOH(AC)
VOL(AC)
MIN output
LOGIC Devices Incorporated
www.logicdevices.com
High Performance, Integrated Memory Module Product
March 6, 2013 LDS-L9D3xxxM32DBG2
PRELIMINARY INFORMATION
L9D3256M32DBG2
L9D3512M32DBG2
16-32 Gb, DDR3, 256-512M x 32 Dual Channel Memory Module
OUTPUT CHARACTERISTICS AND OPERATING CONDITIONS
FIGURE 21 - DIFFERENTIAL OUTPUT SIGNAL
MAX output
VOH(DIFF)
X
VOX(AC) MAX
X
X
VOX(AC) MIN
X
VOL(DIFF)
MIN output
REFERENCE OUTPUT LOAD
)LJXUHUHSUHVHQWVWKHHIIHFWLYHUHIHUHQFHORDGRI:XVHGLQGHILQLQJWKHUHOHYDQWGHYLFH$&WLPLQJSDUDPHWHUVH[FHSW2'7UHIHUHQFHWLPLQJDVZHOODVWKH
RXWSXWVOHZUDWHPHDVXUHPHQWV,WLVQRWLQWHQGHGWREHDSUHFLVHUHSUHVHQWDWLRQRIDSDUWLFXODUV\VWHPHQYLURQPHQWRUDGHSLFWLRQRIWKHDFWXDOORDGSUHVHQWHG
E\DQ\VSHFLILF,QGXVWU\WHVWV\VWHPDSSDUDWXV6\VWHPGHVLJQHUVVKRXOGXVH,%,6RURWKHUVLPXODWLRQWRROVWRFRUUHODWHWKHWLPLQJUHIHUHQFHORDGSUHVHQWHGRU
H[KLELWHGRQWKHV\VWHPRUV\VWHPHQYLURQPHQW
FIGURE 22 - REFERENCE OUTPUT LOAD FOR AC TIMING AND OUTPUT SLEW RATE
DUT
VREF
DQ
DQS
DQS#
VDDQ/2
RTT = 25Ω
VTT = VDDQ/2
Timing Reference Point
ZQ
RZQ = 240Ω
VSS
LOGIC Devices Incorporated
www.logicdevices.com
High Performance, Integrated Memory Module Product
March 6, 2013 LDS-L9D3xxxM32DBG2
PRELIMINARY INFORMATION
L9D3256M32DBG2
L9D3512M32DBG2
16-32 Gb, DDR3, 256-512M x 32 Dual Channel Memory Module
SLEW RATE DEFINITIONS FOR SINGLE-ENDED OUTPUT SIGNALS
7KHVLQJOHHQGHGRXWSXWGULYHULVVXPPDUL]HGLQ7DEOH:LWKWKHUHIHUHQFHORDGIRUWLPLQJPHDVXUHPHQWVWKHRXWSXWVOHZUDWHIRUIDOOLQJDQGULVLQJHGJHV
LVGHILQHGDQGPHDVXUHGEHWZHHQ9OL$&DQG92+$&IRUVLQJOHHQGHGVLJQDOVDVLQGLFDWHGLQ7DEOHDQG)LJXUH
TABLE 44: SINGLE-ENDED OUTPUT SLEW RATE
Measured
Output Slew Rate (Linear Signals)
Output
PACKAGE OUTLINE DIMENSIONS
Edge
From
To
5LVLQJ
9OL$&
92+$&
Falling
92+$&
9OL$&
Calculation
92+$&9OL $&
'756(
DQ
92+$&9OL$&
'7)6(
FIGURE 23 - NOMINAL SLEW RATE DEFINITION FOR SINGLE-ENDED OUTPUT SIGNALS
ΔTRSE
VOH(AC)
VTT
VOL(AC)
ΔTFSE
LOGIC Devices Incorporated
www.logicdevices.com
High Performance, Integrated Memory Module Product
March 6, 2013 LDS-L9D3xxxM32DBG2
PRELIMINARY INFORMATION
L9D3256M32DBG2
L9D3512M32DBG2
16-32 Gb, DDR3, 256-512M x 32 Dual Channel Memory Module
SLEW RATE DEFINITIONS FOR DIFFERENTIAL OUTPUT SIGNALS
7KHGLIIHUHQWLDORXWSXWGULYHULVVXPPDUL]HGLQ7DEOH:LWKWKHUHIHUHQFHORDGIRUWLPLQJPHDVXUHPHQWVWKHRXWSXWVOHZUDWHIRUIDOOLQJDQGULVLQJHGJHVLV
GHILQHGDQGPHDVXUHGEHWZHHQ9OL$&DQG92+$&IRUGLIIHUHQWLDOVLJQDOVDVVKRZQLQ7DEOHDQG)LJXUH
TABLE 45: DIFFERENTIAL OUTPUT SLEW RATE DEFINITION
Measured
Output Slew Rate (Linear Signals)
Output
PACKAGE OUTLINE DIMENSIONS
Edge
From
To
5LVLQJ
9OL',))$&
92+',))$&
Falling
92+',))$&
9OL',))$&
Calculation
92+',))$&9OL ',))$&
'TRDIFF
DQS, DQS\
92+',))$&9OL',))$&
'TFDIFF
FIGURE 24 - NOMINAL DIFFERENTIAL OUTPUT SLEW RATE DEFINITION FOR DQS, DQS#
VOH(DIFF) AC
0
VOL(DIFF) AC
ΔTFDIFF
LOGIC Devices Incorporated
www.logicdevices.com
50
High Performance, Integrated Memory Module Product
March 6, 2013 LDS-L9D3xxxM32DBG2
PRELIMINARY INFORMATION
L9D3256M32DBG2
L9D3512M32DBG2
16-32 Gb, DDR3, 256-512M x 32 Dual Channel Memory Module
TABLE 46: SPEED BINS
PACKAGE OUTLINE DIMENSIONS
''5''5''5
>&:/ @>&:/ @>&:/ @
Parameter
Symbol
MIN
MAX
MIN
MAX
MIN
t5&'
15
-
-
13.91
-
QV
35(&+$5*(FRPPDQGSHULRG
t53
15
-
-
13.91
-
QV
$&7,9$7(WR$&7,9$7(RU5()5(6+FRPPDQGSHULRG
t5&
51
-
-
-
QV
t5$6
36
9 x t5(),
35
9 x t5(),
9 x t5(),
QV
1
&:/ t&.$9*
3
3.3
3
3.3
3
3
QV
2
&:/ t&.$9*
QV
3
QV
3
QV
2
$&7,9$7(WRLQWHUQDO5($'RU:5,7(GHOD\WLPH
$&7,9$7(WR35(&+$5*(FRPPDQGSHULRG
&/ &/ &/ &/ MAX UNITS NOTES
&:/ t&.$9*
&:/ t&.$9*
&:/ t&.$9*
QV
3
&:/ t&.$9*
QV
3
&:/ t&.$9*
&:/ t&.$9*
&:/ 2.5
3.3
2.5
3.3
2.5
3.3
QV
3
QV
2,3
t&.$9*
QV
3
&:/ t&.$9*
QV
3
&:/ t&.$9*
&:/ t&.$9*
1.5
5, 6, 8, 10
6XSSRUWHG&/6HWWLQJV
1.5
5, 6, 8,10
QV
3
QV
2,3
5, 6, 8, 10, 11,13
&.
1.5
6XSSRUWHG&:/6HWWLQJV
&.
127(6
1.
t5(),GHSHQGVRQt23(5
2.
7KH &/ DQG &:/ VHWWLQJ UHVXOW LQ t&. UHTXLUHPHQWV :KHQ PDNLQJ D
VHOHFWLRQRI t&.ERWK&/DQG&:/UHTXLUHPHQWVHWWLQJVQHHGWREHIXO-
3.
5HVHUYHGILOOHGEORFNVVHWWLQJVDUHQRWDOORZHG
ILOOHG
LOGIC Devices Incorporated
www.logicdevices.com
51
High Performance, Integrated Memory Module Product
March 6, 2013 LDS-L9D3xxxM32DBG2
LOGIC Devices Incorporated
www.logicdevices.com
t
t
CK (AVG)
CKDLL_DIS
52
Cumulave error across
3 Cycles
4 Cycles
5 Cycles
6 Cycles
7 Cycles
8 Cycles
9 Cycles
10 Cycles
11 Cycles
12 Cycles
2 Cycles
n = 13, 14 … 49, 50 Cycles
DLL LOCKED
DLL LOCKING
ERR3PERR
t
ERRnPER
ERR4PERR
t
ERR5PERR
t
ERR6PERR
t
ERR7PERR
t
ERR8PERR
t
ERR9PERR
t
ERR10PERR
t
ERR11PERR
t
ERR12PERR
t
t
t
JITCC
JITCC, LCK
t
ERR2PERR
t
-140
-155
-168
-177
-186
-193
-200
-205
-210
-215
-118
0.43
t
Clock absolute LOW pulse width
Cycle-to-Cycle JITTER
0.43
CH (ABS)
CL (ABS)
0.53
0.53
80
70
0.47
0.47
-70
-60
0.53
0.53
70
60
0.47
0.47
-60
-50
See SPEED BIN TABLE (#49) for tCK range allowed
0.53
0.53
60
50
118
-103
0.43
0.43
140
120
103
-
-
-88
0.43
0.43
120
100
140
-122
122
-105
155
-136
136
-117
168
-147
147
-126
177
-155
155
-133
186
-163
163
-139
193
-169
169
-145
200
-175
175
-150
205
-180
180
-154
210
-184
184
-158
215
-188
188
-161
tERRnPER MIN = (1+0.68ln[n]) x tJITPER MIN
tERRnPER MAX = (1+0.68ln[n]) x tJITPER MAX
160
140
-
-
105
117
126
133
139
145
150
154
158
161
88
-
-
MIN=tCK (AVG) MIN+tJITPER MIN; MAX=tCK (AVG)MAX+tJITPER MAX
0.47
0.47
-80
-70
Clock absolute HIGH pusle width
CH (AVG)
t
CL (AVG)
t
JITPER
t
JITPER, LCK
t
CLK (ABS)
t
Symbol
t
Parameter
TC = 0˚C to <85˚C
Clock period average: DLL
TC = 85˚C to 105˚C
disable mode
TC = >105˚C to ≤125˚C
Clock period average: DLL enable mode
HIGH pulse width average
LOW pulse width average
DLL LOCKED
Clock period JITTER
DLL LOCKING
Clock absolute period
-15 (DDR3-1333)
-12 (DDR3-1600)
-11 (DDR3-1866)
[CWL=1.5; 10-10-10] [CWL=1.25; 11-11-11] [CWL=1.07; 13-13-13]
MIN
MAX
MIN
MAX
MIN
MAX
8
7800
8
7800
8
7800
8
3900
8
3900
8
3900
8
2900
8
2900
-
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
17
17
17
17
17
17
17
17
17
17
17
16
16
17
15
tCK (AVG)
ps
ps
ps
14
10,11
12
12
13
13
Notes
9,42
9,42
9,42
tCK (AVG)
ns
CK
CK
ps
ps
ps
ns
Units
PRELIMINARY INFORMATION
L9D3256M32DBG2
L9D3512M32DBG2
16-32 Gb, DDR3, 256-512M x 32 Dual Channel Memory Module
TABLE 47 (SHEET 1 OF 6) - ELECTRICAL CHARACTERISTICS AND AC OPERATING CONDITIONS
High Performance, Integrated Memory Module Product
March 6, 2013 LDS-L9D3xxxM32DBG2
LOGIC Devices Incorporated
www.logicdevices.com
53
DQS, DQS\ DIFFERENTIAL READ postamble
DQS, DQS\ DIFFERENTIAL Output HIGH me
DQS, DQS\ DIFFERENTIAL Output LOW me
DQS, DQS\ LOW-Z me (RL-1)
DQS, DQS\ HIGH-Z me (RL+BL/2)
DQS, DQS\ DIFFERENTIAL READ preamble
DQS, DQS\ RISING to/from RISING CK, CK\ when DLL is disabled
DQS, DQS\ RISING to/from RISING CK, CK\
DQS,DQS\ RISING to CK, CK\ RISING
DQS, DQS\ DIFFERENTIAL Input Low pulse width
DQS, DQS\ DIFFERENTIAL Input HIGH pulse width
DQS, DQS\ FALLING Setup to CK, CK\ RISING
DQS, DQS\ FALLING Hold from CK, CK\ RISING
DQS, DQS\ DIFFERENTIAL WRITE preamble
DQS, DQS\ DIFFERENTIAL WRITE postamble
t
QH
0.38
t
RPST
DQSK
DLL_DIS
t
QSH
t
QSL
t
LZ (DQS)
t
HZ (DQS)
t
RPRE
t
0.3
0.4
0.4
-500
0.9
1
-500
LZ (DQ)
HZ (DQ)
DQ Strobe Input Timing
t
-0.25
DQSS
t
0.45
DQSL
t
0.45
DQSH
t
0.2
DSS
t
0.2
DSH
t
0.9
WPRE
t
0.3
WPST
DQ Strobe Output Timing
t
-255
DQSCK
t
DQ LOW-Z me from CK, CK\
DQ HIGH-A me from CK, CK\
Base (specificaon)
VREF @ 1V/ns
Base (specificaon)
VREF @ 1V/ns
Base (specificaon)
VREF @ 1V/ns
t
DQ Output HOLD me from DQS, DQS\
DQS, DQS\ to DQ SKEW, per access
Data HOLD me from DQS,
DQS\
Minimum Data Pulse Width
Data SETUP me to DQS, DQS\
Data SETUP me to DQS, DQS\
Parameter
Note 27
250
250
Note 24
10
255
0.25
0.55
0.55
-
250
250
-
0.3
0.4
0.4
-450
0.9
1
-225
-0.27
0.45
0.45
0.18
0.18
0.9
0.3
-
-450
0.38
Note 27
225
225
Note 24
10
225
0.27
0.55
0.55
-
225
225
-
0.3
0.4
0.4
-390
0.9
1
-195
-0.27
0.45
0.45
0.18
0.18
0.9
0.3
-
-390
0.38
Note 27
195
195
Note 24
10
195
0.27
0.55
0.55
-
195
195
-
-15 (DDR3-1333)
-12 (DDR3-1600)
-11 (DDR3-1866)
[CWL=1.5; 10-10-10] [CWL=1.25; 11-11-11] [CWL=1.07; 13-13-13]
Symbol
MIN
MAX
MIN
MAX
MIN
MAX
DQ Input Timing
t
DS AC175
10
30
t
DS AC150
180
135
160
65
45
20
t
DH AC100
165
145
120
t
400
360
320
DIPW
DQ Ouput Timing
t
125
100
85
DQSQ
CK
CK
CK
ps
ps
CK
ns
ps
CK
CK
CK
CK
CK
CK
CK
ps
ps
tCK (AVG)
ps
ps
ps
ps
ps
ps
ps
ps
Units
23,27
21
21
22,23
22,23
23,24
26
23
25
25
25
22,23
22,23
21
18,19
19,20
18,19
19,20
18,19
19,20
41
Notes
PRELIMINARY INFORMATION
L9D3256M32DBG2
L9D3512M32DBG2
16-32 Gb, DDR3, 256-512M x 32 Dual Channel Memory Module
TABLE 47 (SHEET 2 OF 6) - ELECTRICAL CHARACTERISTICS AND AC OPERATING CONDITIONS
High Performance, Integrated Memory Module Product
March 6, 2013 LDS-L9D3xxxM32DBG2
LOGIC Devices Incorporated
www.logicdevices.com
2KB page size
1KB page size
MULTIPURPOSE REGISTER READ burst end to mode register set for
mulpurpose register exit
MODE REGISTER SET command cycle me
MODE REGISTER SET command update delay
t
DAL
MPRR
MOD
MRD
t
t
t
RTP
CCD
MIN = 1CK; MAX = n/a
MIN = 4CK; MAX = n/a
MIN = greater of 12CK or 15ns; MAX = n/a
MIN = WR + tRP/tCK (AVG); MAX = n/a
MIN = greater of 4CK or 7.5ns; MAX = n/a
MIN = 4CK; MAX = n/a
t
MIN = greater of 4CK or 7.5ns; MAX = n/a
MIN = 15ns; MAX = n/a
WTR
WR
t
t
t
Auto precharge WRITE recovery + PRECHARGE me
Delay from start of internal WRITE transacon to internal READ
command
READ-to-PRECHARE me
CAS\-to-CAS\ command delay
WRITE recovery me
Four ACTIVATE windows for 1KB page size
Four ACTIVATE windows for 2KB page size
ACTIVATE-to-ACTIVATE
minimum command period
DLL Locking me
Base (specificaon)
CTRL, CMD, ADDR setup to CK,
VREF @ 1V/ns
CK\
Base (specificaon)
CTRL, CMD, ADDR setup to CK,
VREF @ 1V/ns
CK\
Base (specificaon)
CTRL, CMD, ADDR hold to CK,
VREF @ 1V/ns
CK\
Minimum CTRL, CMD, ADDR pulse width
ACTIVATE to Internal READ or WRITE delay
PRECHARGE command period
ACTIVATE-to-PRECHARGE command period
ACTIVATE-to-ACTIVATE command period
Parameter
-15 (DDR3-1333)
-12 (DDR3-1600)
-11 (DDR3-1866)
[CWL=1.5; 10-10-10] [CWL=1.25; 11-11-11] [CWL=1.07; 13-13-13]
Symbol
MIN
MAX
MIN
MAX
MIN
MAX
Command and Address Timing
t
512
512
512
DLLK
65
65
45
t
IS AC175
240
220
200
150
190
170
t
IS AC150
275
340
320
100
140
120
t
IH DC100
200
240
220
t
535
620
560
IPW
t
See "Speed Bin Table (#49) for tRCD
RCD
t
See "Speed Bin Table (#49) for tRP
RP
t
See "Speed Bin Table (#49) for tRAS
RAS
t
See "Speed Bin Table (#49) for tRC
RCD
MIN=greater of 4CK MIN=greater of 4CK MIN=greater of 4CK
or 5ns
or 6ns
or 6ns
t
RRD
MIN=greater of 4CK
MIN=greater of 4CK or 7.5ns
or 6ns
25
30
30
t
FAW
35
45
40
-
CK
CK
CK
CK
CK
CK
CK
CK
31,34
31,32,33
31
31
31
CK
ns
ns
31
28
29,30
20,30
29,30
20,30
29,30
20,30
41
31
31
31,32
31
Notes
CK
CK
ps
ps
ps
ps
ps
ps
ps
ns
ns
ns
ns
Units
PRELIMINARY INFORMATION
L9D3256M32DBG2
L9D3512M32DBG2
16-32 Gb, DDR3, 256-512M x 32 Dual Channel Memory Module
TABLE 47 (SHEET 3 OF 6) - ELECTRICAL CHARACTERISTICS AND AC OPERATING CONDITIONS
High Performance, Integrated Memory Module Product
March 6, 2013 LDS-L9D3xxxM32DBG2
LOGIC Devices Incorporated
www.logicdevices.com
55
TC ≤ 85˚C
TC >85˚C ≤ 105˚C
TC >105˚C ≤ 125˚C
TC ≤ 85˚C
TC >85˚C ≤ 105˚C
TC >105˚C ≤ 125˚C
Valid clocks before SELF REFRESH exit, POWER-DOWN exit, or RESET
exit
Valid clocks aer SELF REFRESH entry or POWER-DOWN entry
MINIMUM CKE LOW pulse width for SELF REFRESH entry to SELF
REFRESH exit ming
EXIT SELF REFRESH TO commands requiring a locked DLL
Exit SELF REFRESH TO commands not requiring a locked DLL
Maximum REFRESH
period/interval
Maximum REFRESH period
REFRESH-to-ACTIVATE or REFRESH command period
RESET\ LOW to power supplies stable
RESET\ LOW to I/O and RTT HIGH-Z
Begin power supply ramp to power supplies stable
Exit RESET from CKE HIGH to a valid command
Normal operaon
POWER-UP and RESET operaon
ZQCS command: Short Calibraon Time
ZQCL command: Long
Calibraon me
Parameter
ZQINIT
512
512
512
t
VDDPR
REFI
-
CKSRE
CKESR
XSDLL
XS
CKSRX
t
t
t
t
t
SELF REFRESH Timing
t
t
RPS
IOZ
REFRESH Timing
t
RFC - 1Gb
t
RFC - 2Gb
t
RFC - 4Gb
t
MIN = greater of 5CK or 10ns; MAX = n/a
MIN = greater of 5CK or 10ns; MAX = n/a
MIN = tCKE (MIN) + CK; MAX = n/a
MIN = tDLLK (MIN); MAX = n/a
CK
CK
CK
CK
CK
28
36
36
36
36
36
36
ns
ns
ns
ms
ms
ms
μs
μs
μs
MIN = 110; MAX = 70,200
MIN = 160; MAX = 70,200
MIN = 260; MAX = 70,200
64 (1X)
32 (2X)
24
7.8
3.9
2.9
MIN = greater of 5CK or tRFC + 10ns; MAX = n/a
35
ms
CK
CK
CK
CK
Notes
ms
ns
-
-
Units
MIN = 0; MAX = 200
MIN = n/a; MAX = 20
MIN = n/a; MAX = 200
256
256
256
ZQOPER
t
64
64
64
ZQCS
Inializaon and RESET Timing
t
MIN = greater of 5CK or tRFC + 10ns; MAX = n/a
XPR
t
t
-15 (DDR3-1333)
-12 (DDR3-1600)
-11 (DDR3-1866)
[CWL=1.5; 10-10-10] [CWL=1.25; 11-11-11] [CWL=1.07; 13-13-13]
Symbol
MIN
MAX
MIN
MAX
MIN
MAX
Calibraon Timing
PRELIMINARY INFORMATION
L9D3256M32DBG2
L9D3512M32DBG2
16-32 Gb, DDR3, 256-512M x 32 Dual Channel Memory Module
TABLE 47 (SHEET 4 OF 6) - ELECTRICAL CHARACTERISTICS AND AC OPERATING CONDITIONS
High Performance, Integrated Memory Module Product
March 6, 2013 LDS-L9D3xxxM32DBG2
LOGIC Devices Incorporated
www.logicdevices.com
56
t
BL8 (OTF, MRS) BC4OTF
BC4MRS
WRPDEN
WRPDEN
RDPDEN
WRAPDEN
t
t
t
XP
XPDLL
t
t
WRAPDEN
POWER-DOWN Exit Timing
t
BC4MRS
BL8 (OTF, MRS) BC4OTF
DLL on, any valid command, or DLL off to commands not requiring DLL
locked
PRECHARGE POWER-DOWN with DLL off to command requiring DLL
locked
WRITE with AUTO PRECHARGE
command to POWER-DOWN
entry
WRITE Command to POWERDOWN entry
READ/READ with AUTO PRECHARGE commant to POWER-DOWN entry
PRPDEN
REFPDEN
MRSPDEN
REFRESH command to POWER-DOWN entry
MRS command to POWER-DOWN entry
t
t
ACTPDEN
PRECHARGE/PRECHARGE ALL command to POWER-DOWN entry
t
WL - 1CK
ANPD + tXPDLL
MIN = 2
MIN = 2
MIN = 2
MIN = Greater of 10CK or 24ns; MAX = n/a
MIN = Greater of 3CK or 6.0ns; MAX = n/a
MIN = WL + 2 + WR + 1
MIN = WL + 4 + WR + 1
t
MIN = WL + 2 + WR/ CK (AVG)
t
MIN = WL + 4 + tWR/tCK (AVG)
MIN = RL + 4 + 1
MIN = tMOD (MIN)
MIN = 1
MIN = 1
MIN = 1
t
Greater of tANPD or tRFC - REFRESH command to CKE LOW me
POWER-DOWN Entry MINIMUM Timing
t
ACTIVATE command to POWER-DOWN entry
PDX
POWER-DOWN exit period: ODT either synchronous or asynchronous
ANPD
PDE
t
POWER-DOWN entry period: ODT eher synchronous or asynchronous
Begin POWER-DOWN period prior to CKE registered HIGH
Command pass disable delay
POWER-DOWN entry to POWER-DOWN exit ming
CKE MIN pulse width
Parameter
-15 (DDR3-1333)
-12 (DDR3-1600)
-11 (DDR3-1866)
[CWL=1.5; 10-10-10] [CWL=1.25; 11-11-11] [CWL=1.07; 13-13-13]
Symbol
MIN
MAX
MIN
MAX
MIN
MAX
POWER-DOWN Timing
Greater of 3CK or
Greater of 3CK or
Greater of 3CK or
t
CKE (MIN)
5.625ns
5ns
5ns
t
MIN = 1; MAX = n/a
CPDED
t
MIN = tCKE (MIN); MAX = 60ms
PD
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
Units
28
37
Notes
PRELIMINARY INFORMATION
L9D3256M32DBG2
L9D3512M32DBG2
16-32 Gb, DDR3, 256-512M x 32 Dual Channel Memory Module
TABLE 47 (SHEET 5 OF 6) - ELECTRICAL CHARACTERISTICS AND AC OPERATING CONDITIONS
High Performance, Integrated Memory Module Product
March 6, 2013 LDS-L9D3xxxM32DBG2
LOGIC Devices Incorporated
www.logicdevices.com
First DQS, DQS\ RISING edge
DQS; DQS\ delay
WRITE Leveling SETUP from rising CK, CK\ crossing to rising DQS, DQS\
crossing
WRITE Leveling HOLD from rising DQS, DQS\ crossing to rising CK, CK\
crossing
WRITE Leveling output delay
WRITE Leveling output error
RTT_NOM-to=RTT_WR change skew
RTT_WR-to-RTT_NOM change skew - BC4
RTT_WR-to-RTT_NOM change skew - BC8
RTT dynamic change skew
t
WLH
WLS
WLO
WLOE
t
t
t
0
0
195
195
9
2
-
-
-
0
0
163
163
40
25
7.5
2
-
-
-
WL - 2CK
4CK + ODTL OFF
6CK + ODTL OFF
0.3
0.7
MIN = 4; MAX = n/a
ODTH4
Dynamic ODT Timing
ODTLCNW
ODTLCNW4
ODTLCNW8
t
0.3
ADC
WRITE Leveling Timing
t
40
WLMRD
t
25
WLDQSEN
MIN = 6; MAX = n/a
ODTH8
0.7
t
Asynchronous RTT TURN-OFF delay (POWER-DOWN with DLL OFF)
ODT HIGH me without WRITE command or with WRITE command and
BC8
ODT HIGH me without WRITE command or with WRITE command and
BC4
MIN = 2; MAX = 8.5
AONPD
AOFPD
MIN = 2; MAX = 8.5
t
Asynchronous RTT TURN-ON delay (POWER-DOWN with DLL OFF)
RTT synchronous TURN-ON delay
RTT synchronous TURN-OFF delay
RTT TURN-ON from ODTL ON reference
RTT TURN-OFF from ODTL OFF reference
Parameter
0
0
140
140
40
25
0.3
7.5
2
-
-
-
0.7
-12 (DDR3-1600)
-15 (DDR3-1333)
-11 (DDR3-1866)
[CWL=1.5; 10-10-10] [CWL=1.25; 11-11-11] [CWL=1.07; 13-13-13]
Symbol
MIN
MAX
MIN
MAX
MIN
MAX
ODT Timing
ODTL on
ODTL off
t
-250
250
-225
225
-195
195
AON
t
0.3
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Units
39
40
38
38
40
23,38
39,40
Notes
PRELIMINARY INFORMATION
L9D3256M32DBG2
L9D3512M32DBG2
16-32 Gb, DDR3, 256-512M x 32 Dual Channel Memory Module
TABLE 47 (SHEET 6 OF 6) - ELECTRICAL CHARACTERISTICS AND AC OPERATING CONDITIONS
High Performance, Integrated Memory Module Product
March 6, 2013 LDS-L9D3xxxM32DBG2
PRELIMINARY INFORMATION
L9D3256M32DBG2
L9D3512M32DBG2
16-32 Gb, DDR3, 256-512M x 32 Dual Channel Memory Module
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High Performance, Integrated Memory Module Product
March 6, 2013 LDS-L9D3xxxM32DBG2
PRELIMINARY INFORMATION
L9D3256M32DBG2
L9D3512M32DBG2
16-32 Gb, DDR3, 256-512M x 32 Dual Channel Memory Module
NOTES CONTINUED
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59
High Performance, Integrated Memory Module Product
March 6, 2013 LDS-L9D3xxxM32DBG2
PRELIMINARY INFORMATION
L9D3256M32DBG2
L9D3512M32DBG2
16-32 Gb, DDR3, 256-512M x 32 Dual Channel Memory Module
COMMAND AND ADDRESS SETUP, HOLD, AND DERATING
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TABLE 48: COMMAND AND ADDRESS SETUP AND HOLD VALUES REFERENCED AT 1V/NS – AC/DC BASED
Symbol
DDR3-1333
DDR3-1600
DDR3-1866
UNITS
tIS(base)AC
600
600
-
SV
9,+$&9IL$&
tIS(base)AC
600
600
-
SV
9,+$&9IL$&
600
600
600
SV
9,+$&9IL$&
tIH(base)DC100
REFERENCE
TABLE 49: DERATING VALUES FOR tIS/tIH – AC175/DC100-BASED
Shaded cells indicate slew-rate combinations not supported
'tIS, 'tIH Derating (ps) - AC/DC-Based, AC175 Threshold; VIH(AC) = VREF(DC) + 175mV, VIL(AC) = VREF(DC) - 175mV
CMD/ADDR
Slew Rate V/ns
CK, CK\ Differential Slew Rate
4.0V/ns
3.0V/ns
2.0V/ns
1.8V/ns
1.6V/ns
1.4V/ns
1.2V/ns
1.0V/ns
'tIS
'tIH
'tIS
'tIH
'tIS
'tIH
'tIS
'tIH
'tIS
'tIH
'tIS
'tIH
'tIS
'tIH
'tIS
'tIH
2.0
88
50
88
50
88
50
96
58
96
66
112
120
128
100
1.5
59
50
59
50
83
58
91
68
99
1.0
0
0
0
0
0
0
8
8
8
16
32
50
0.9
-2
-2
-2
6
6
12
22
20
30
30
38
0.8
-6
-10
-6
-10
-6
-10
2
-2
2
6
18
26
-11
-16
-11
-16
-11
-16
-3
-8
-3
0
13
8
21
18
29
0.6
-26
-26
-26
-9
-18
-9
-10
-2
15
8
23
0.5
-35
-35
-35
-32
-11
-16
-2
-6
5
10
-62
-60
-62
-60
-62
-60
-52
-38
-36
-30
-26
-22
-10
LOGIC Devices Incorporated
www.logicdevices.com
60
High Performance, Integrated Memory Module Product
March 6, 2013 LDS-L9D3xxxM32DBG2
PRELIMINARY INFORMATION
L9D3256M32DBG2
L9D3512M32DBG2
16-32 Gb, DDR3, 256-512M x 32 Dual Channel Memory Module
TABLE 50: DERATING VALUES FOR tIS/tIH – AC150/DC100-BASED
Shaded cells indicate slew-rate combinations not supported
'tIS, 'tIH Derating (ps) - AC/DC-Based, AC150 Threshold; VIH(AC) = VREF(DC) + 150mV, VIL(AC) = VREF(DC) - 150mV
CMD/ADDR
Slew Rate V/ns
CK, CK\ Differential Slew Rate
4.0V/ns
3.0V/ns
2.0V/ns
1.8V/ns
1.6V/ns
1.4V/ns
1.2V/ns
1.0V/ns
'tIS
'tIH
'tIS
'tIH
'tIS
'tIH
'tIS
'tIH
'tIS
'tIH
'tIS
'tIH
'tIS
'tIH
'tIS
'tIH
2.0
50
50
50
83
58
91
66
99
115
100
1.5
50
50
50
58
66
50
58
82
68
90
1.0
0
0
0
0
0
0
8
8
16
16
32
50
0.9
0
0
0
8
16
12
20
32
30
0.8
0
-10
0
-10
0
-10
8
-2
16
6
32
0
-16
0
-16
0
-16
8
-8
16
0
8
32
18
0.6
-1
-26
-1
-26
-1
-26
-18
15
-10
23
-2
31
8
39
0.5
-10
-10
-10
-2
-32
6
-16
22
-6
30
10
-25
-60
-25
-60
-25
-60
-52
-9
-1
-36
-26
15
-10
TABLE 51: MINIMUM REQUIRED TIME tVAC ABOVE VIH(AC) FOR A VALID TRANSITION
Below VIL(AC)
Slew Rate (V/ns)
tVAC
at 175mV(ps)
tVAC
at 150mV(ps)
tVAC
at 135mV(ps)
tVAC
at 125mV(ps)
>2.0
200
2.0
160
190
1.5
50
150
180
1.0
38
163
0.9
162
130
160
0.8
29
161
120
150
22
159
110
QD
0.6
13
155
105
QD
0.5
0
150
QD
QD
0
150
QD
QD
LOGIC Devices Incorporated
www.logicdevices.com
61
High Performance, Integrated Memory Module Product
March 6, 2013 LDS-L9D3xxxM32DBG2
PRELIMINARY INFORMATION
L9D3256M32DBG2
L9D3512M32DBG2
16-32 Gb, DDR3, 256-512M x 32 Dual Channel Memory Module
FIGURE 25 - NOMINAL SLEW RATE AND tVAC FOR tIS (COMMAND AND ADDRESS – CLOCK)
t IS
t IH
t IS
t IH
CK
CK#
DQS#
DQS
VDDQ
t VAC
VIH(AC) MIN
VREF to AC
region
VIH(DC) MIN
Nominal
slew rate
VREF(DC)
Nominal
slew rate
VIL(DC) MAX
VREF to AC
region
VIL(DC) MAX
t VAC
VSS
∆TF
Setup slew rate
falling signal
∆TR
VREF(DC) - VIL(AC) MAX
Setup slew rate
risin g signal
=
∆TF
Notes:
LOGIC Devices Incorporated
VIH(AC) MIN - V REF(DC)
=
∆TR
1. Both the clock and the strobe are drawn on different time scales.
www.logicdevices.com
62
High Performance, Integrated Memory Module Product
March 6, 2013 LDS-L9D3xxxM32DBG2
PRELIMINARY INFORMATION
L9D3256M32DBG2
L9D3512M32DBG2
16-32 Gb, DDR3, 256-512M x 32 Dual Channel Memory Module
FIGURE 26 - NOMINAL SLEW RATE FOR tIH (COMMAND AND ADDRESS – CLOCK)
t IS
t IH
t IS
t IH
CK
CK#
DQS#
DQS
VDDQ
VIH(AC) MIN
VIH(DC) MIN
Nominal
slew rate
DC to V REF
region
VREF(DC)
Nominal
slew rate
DC to V REF
region
VIL(DC) MAX
VIL(AC) MAX
VSS
∆TF
∆TR
Hol d slew rate
=
rising signal
VREF(DC) - VIL(DC) MAX
Hol d slew rate
falling signal =
∆TR
Notes:
LOGIC Devices Incorporated
www.logicdevices.com
VIH(DC) MIN - V REF(DC)
∆TF
1. Both the clock and the strobe are drawn on different time scales.
63
High Performance, Integrated Memory Module Product
March 6, 2013 LDS-L9D3xxxM32DBG2
PRELIMINARY INFORMATION
L9D3256M32DBG2
L9D3512M32DBG2
16-32 Gb, DDR3, 256-512M x 32 Dual Channel Memory Module
FIGURE 27 - TANGENT LINE FOR tIS (COMMAND AND ADDRESS – CLOCK)
t IS
t IH
t IS
t IH
CK
CK#
DQS#
DQS
VDDQ
t VAC
Nominal
line
VIH(AC) MIN
VREF to AC
region
VIH(DC) MIN
Tangent
line
VREF(DC)
Tangent
line
VIL(DC) MAX
VREF to AC
region
VIL(AC) MAX
Nominal
line
t VAC
∆TR
VSS
Setup slew rate
rising signal =
∆TF
Notes:
LOGIC Devices Incorporated
Tangent line (V IH [ DC] MIN - VREF[ DC ])
∆TR
Tangent line (VREF [ DC] - V IL[ AC] MAX)
Setup slew rate
falling signal =
∆TF
1. Both the clock and the strobe are drawn on different time scales.
www.logicdevices.com
High Performance, Integrated Memory Module Product
March 6, 2013 LDS-L9D3xxxM32DBG2
PRELIMINARY INFORMATION
L9D3256M32DBG2
L9D3512M32DBG2
16-32 Gb, DDR3, 256-512M x 32 Dual Channel Memory Module
FIGURE 28 - TANGENT LINE FOR tIH (COMMAND AND ADDRESS – CLOCK)
t IS
t IH
t IS
t IH
CK
CK#
DQS #
DQS
VDDQ
VIH(AC) MIN
Nominal
line
VIH(DC) MIN
DC to V REF
region
Tangent
line
VREF(DC)
DC to V REF
region
Tangent
line
Nominal
line
VIL( DC) MAX
VIL( AC) MAX
VSS
∆TR
∆TR
Hol d slew rate
rising signal =
Tangent line (V REF [ DC] - V IL[ DC] MAX)
Hol d slew rate
falling signal =
Tangent line (V IH [ DC] MIN - VREF[ DC])
∆TR
∆TF
Notes:
LOGIC Devices Incorporated
1. Both the clock and the strobe are drawn on different time scales.
www.logicdevices.com
65
High Performance, Integrated Memory Module Product
March 6, 2013 LDS-L9D3xxxM32DBG2
PRELIMINARY INFORMATION
L9D3256M32DBG2
L9D3512M32DBG2
16-32 Gb, DDR3, 256-512M x 32 Dual Channel Memory Module
DATA SETUP, HOLD AND DERATING
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TABLE 52: DATA SETUP AND HOLD VALUES AT 1V/NS (DQSX, DQSX\ AT 2V/NS) - AC/DC BASED
DDR3-1333
DDR3-1600
tDS(base)AC175
Symbol
-
-
DDR3-1866
-
UNITS
SV
REFERENCE
9,+$&9IL$&
tDS(base)AC175
-
-
-
SV
9,+$&9IL$&
tDS(base)DC150
30
10
10
SV
9,+$&9IL$&
tDS(base)DC150
65
SV
9,+$&9IL$&
TABLE 53: DERATING VALUE FOR tDS/tDH – AC175/DC100 - BASED
Shaded cells indicate slew-rate combinations not supported
ǻtDS, ǻtDH Derating (ps) – AC175/D100-Based
DQ
Slew Rate V/ns
DQS, DQS# Differential Slew Rate
4.0V/ns
3.0V/ns
2.0V/ns
1.8V/ns
1.6V/ns
1.4V/ns
1.2V/ns
1.0V/ns
'tDS 'tDH 'tDS 'tDH 'tDS 'tDH 'tDS 'tDH 'tDS 'tDH 'tDS 'tDH 'tDS 'tDH 'tDS 'tDH
2.0
88
50
88
50
88
50
1.5
59
59
59
1.0
0
0
0
0
0
0
8
8
16
16
-2
-2
6
12
22
20
-6
-10
2
-2
10
6
18
26
-3
-8
5
0
13
8
21
18
29
-1
-10
-2
15
8
23
-11
-16
0.9
0.8
0.6
0.5
LOGIC Devices Incorporated
www.logicdevices.com
66
-2
-6
5
10
-30
-26
-22
-10
High Performance, Integrated Memory Module Product
March 6, 2013 LDS-L9D3xxxM32DBG2
PRELIMINARY INFORMATION
L9D3256M32DBG2
L9D3512M32DBG2
16-32 Gb, DDR3, 256-512M x 32 Dual Channel Memory Module
TABLE 54: DERATING VALUE FOR tDS/tDH – AC150/DC100 - BASED
Shaded cells indicate slew-rate combinations not supported
ǻtDS, ǻtDH Derating (ps) – AC150/DC100-Based
DQ Slew
Rate V/ns
DQS, DQS# Differential Slew Rate
4.0V/ns
3.0V/ns
2.0V/ns
1.8V/ns
1.6V/ns
1.4V/ns
1.2V/ns
1.0V/ns
'tDS 'tDH 'tDS 'tDH 'tDS 'tDH 'tDS 'tDH 'tDS 'tDH 'tDS 'tDH 'tDS 'tDH 'tDS 'tDH
2.0
50
50
50
1.5
50
50
50
58
1.0
0
0
0
0
0
0
8
8
16
16
0
0
8
16
12
20
0
-10
8
-2
16
6
32
8
-8
16
0
8
32
18
15
-10
23
-2
31
8
39
-16
22
-6
30
10
-26
15
-10
0.9
0.8
0.6
0.5
TABLE 55: REQUIRED TIME tVAC ABOVE VIH(AC) (BELOW VIL[AC]) FOR A VALID TRANSITION
tVAC
Slew Rate (V/ns)
at 175mV(ps) [MIN]
tVAC
at 150mV(ps) [MIN]
>2.0
2.0
1.5
50
1.0
38
163
0.9
162
0.8
29
161
22
159
0.6
13
155
0.5
0
150
0
150
LOGIC Devices Incorporated
www.logicdevices.com
High Performance, Integrated Memory Module Product
March 6, 2013 LDS-L9D3xxxM32DBG2
PRELIMINARY INFORMATION
L9D3256M32DBG2
L9D3512M32DBG2
16-32 Gb, DDR3, 256-512M x 32 Dual Channel Memory Module
FIGURE 29 - NOMINAL SLEW RATE AND tVAC FOR tDS (DQ – STROBE)
CK
CK#
DQS#
DQS
t DS
t DH
t DS
t DH
VDDQ
t VAC
VIH(AC) MIN
VREF to AC
region
VIH(DC) MIN
Nominal
slew rate
VREF(DC)
Nominal
slew rate
VIL(DC) MAX
VREF to AC
region
VIL(AC) MAX
t VAC
VSS
∆TF
Setup slew rate
=
rising signal
Notes:
LOGIC Devices Incorporated
∆TR
VREF(DC) - VIL(AC) MAX
∆TF
Setup slew rate
=
rising signal
VIH(AC) MIN - VREF (DC)
∆TR
1. Both the clock and the strobe are drawn on different time scales.
www.logicdevices.com
68
High Performance, Integrated Memory Module Product
March 6, 2013 LDS-L9D3xxxM32DBG2
PRELIMINARY INFORMATION
L9D3256M32DBG2
L9D3512M32DBG2
16-32 Gb, DDR3, 256-512M x 32 Dual Channel Memory Module
FIGURE 30 - NOMINAL SLEW RATE FOR tDH (DQ – STROBE)
CK
CK#
DQS#
DQS
t DS
t DH
t DS
t DH
VDDQ
VIH(AC) MIN
VIH(DC) MIN
Nominal
slew rate
DC to V REF
region
VREF(DC)
Nominal
slew rate
DC to V REF
region
VIL(DC) MAX
VIL(AC) MAX
VSS
∆TF
∆TR
Hold slew rate
=
rising signal
Notes:
LOGIC Devices Incorporated
VREF(DC) - VIL(DC) MAX
∆TR
Hold slew rate
=
falling signal
VIH(DC) MIN - V REF(DC)
∆TF
1. Both the clock and the strobe are drawn on different time scales.
www.logicdevices.com
69
High Performance, Integrated Memory Module Product
March 6, 2013 LDS-L9D3xxxM32DBG2
PRELIMINARY INFORMATION
L9D3256M32DBG2
L9D3512M32DBG2
16-32 Gb, DDR3, 256-512M x 32 Dual Channel Memory Module
FIGURE 31 - NOMINAL SLEW RATE AND tVAC FOR tDS (DQ – STROBE)
CK
CK#
DQS#
DQS
t DS
t DH
t DS
t DH
VDDQ
Nominal
line
t VAC
VIH(AC) MIN
VREF to AC
region
VIH(DC) MIN
Tangent
line
VREF(DC)
Tangent
line
VIL(DC) MAX
VREF to AC
region
VIL(AC) MAX
Nominal
line
t VAC
∆TR
VSS
Setup slew rate
rising signal
=
Tangent line (V IH[ AC ] MIN - V REF [ DC])
∆TR
∆TF
Setup slew rate
falling signal
=
Tangent line (V REF[ DC] - V IL[ AC] MAX)
∆TF
Notes:
LOGIC Devices Incorporated
1. Both the clock and the strobe are drawn on different time scales.
www.logicdevices.com
High Performance, Integrated Memory Module Product
March 6, 2013 LDS-L9D3xxxM32DBG2
PRELIMINARY INFORMATION
L9D3256M32DBG2
L9D3512M32DBG2
16-32 Gb, DDR3, 256-512M x 32 Dual Channel Memory Module
FIGURE 32 - NOMINAL SLEW RATE FOR tDH (DQ – STROBE)
CK
CK#
DQS#
DQS
t DS
t DH
t DS
t DH
VDDQ
VIH(AC) MIN
Nominal
line
VIH(DC) MIN
DC to VREF
region
Tangent
line
VREF(DC)
DC to VREF
region
Tangent
line
Nominal
line
VIL(DC) MAX
VIL(AC) MAX
VSS
∆TR
Notes:
LOGIC Devices Incorporated
∆TF
Tangent line (V REF[ DC] - V IL[ DC] MAX)
Hol d slew rate
falling signal
=
Hol d slew rate
falling signal
=
∆TR
Tangent line (V IH [ DC] MIN - VREF[ DC])
∆TF
1. Both the clock and the strobe are drawn on different time scales.
www.logicdevices.com
High Performance, Integrated Memory Module Product
March 6, 2013 LDS-L9D3xxxM32DBG2
PRELIMINARY INFORMATION
L9D3256M32DBG2
L9D3512M32DBG2
16-32 Gb, DDR3, 256-512M x 32 Dual Channel Memory Module
COMMANDS TRUTH TABLE
TABLE 56: TRUTH TABLE - COMMAND
PACKAGE OUTLINE DIMENSIONS
CKE
Function
Symbol
Prev
Cycle
Next
Cycle
CS\
RAS\
CAS\
WE\
BA[2:0]
An
A12
A10
A[11,0:0] Notes
Mode Register Set
MRS
+
+
L
L
L
L
%$
REFRESH
5()
+
+
L
L
L
+
9
9
9
9
9
SELF REFRESH entry
65(
+
L
L
L
L
+
9
9
9
9
9
6
SELF REFRESH exit
65;
L
+
+
L
9
+
9
+
9
+
9
9
9
9
9
35(
+
+
L
L
L
L
9%$
9
9
L
9
35($
+
+
L
L
L
L
9
9
9
+
9
$&7
+
+
L
L
L
+
%$
:5
+
+
L
+
+
L
%$
5)8
9
L
&$
8
%&27)
:56
+
+
L
+
+
L
%$
5)8
L
L
&$
8
BL8OTF
:56
+
+
L
+
+
L
%$
5)8
+
L
&$
8
BL8MRS
%&056
:5$3
+
+
L
+
+
L
%$
5)8
9
+
&$
8
%&27)
:5$36
+
+
L
+
+
L
%$
5)8
L
+
&$
8
BL8OTF
:5$36
+
+
L
+
+
L
%$
5)8
+
+
&$
8
BL8MRS
%&056
RD
+
+
L
+
+
+
%$
5)8
9
L
&$
8
%&27)
5'6
+
+
L
+
+
+
%$
5)8
L
L
&$
8
BL8OTF
RDS8
+
+
L
+
+
+
%$
5)8
+
L
&$
8
Single-Bank PRECHARGE
PRECHARGE all banks
Bank ACTIVATE
BL8MRS
%&056
WRITE
WRITE with AUTO
PRECHARGE
READ
READ with AUTO
PRECHARGE
5$
5'$3
+
+
L
+
+
+
%$
5)8
9
+
&$
8
%&27)
5'$36
+
+
L
+
+
+
%$
5)8
L
+
&$
8
BL8OTF
BL8MRS
%&056
5'$36
+
+
L
+
+
+
%$
5)8
+
+
&$
8
NO OPERATION
123
+
+
L
+
+
+
9
9
9
9
9
9
Device DESELECTED
'(6
+
+
+
;
;
;
;
;
;
;
;
3'(
+
+
9
+
9
+
9
+
9
10
POWER-DOWN entry
+
9
+
9
9
9
9
9
9
6
9
9
9
9
9
6,11
12
3';
L
+
L
+
L
+
ZQ CALIBRATION LONG
=4&/
+
+
L
+
+
L
;
;
;
+
;
ZQ CALIBRATION SHORT
=4&6
+
+
L
+
+
L
;
;
;
L
;
POWER-DOWN exit
L
127(6
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LOGIC Devices Incorporated
www.logicdevices.com
High Performance, Integrated Memory Module Product
March 6, 2013 LDS-L9D3xxxM32DBG2
PRELIMINARY INFORMATION
L9D3256M32DBG2
L9D3512M32DBG2
16-32 Gb, DDR3, 256-512M x 32 Dual Channel Memory Module
TABLE 57: TRUTH TABLE - CKE
CKE
Current State 3
(n-1)
(n)
Previous Cycle 4
Present Cycle 4
(RAS\, CAS\, WE\, CS\)
Command 5
Action 5
Notes
L
L
v'RQuW&DUHw
0DLQWDLQ32:(5'2:1
1,2
L
+
'(6RU123
32:(5'2:1H[LW
1,2
POWER-DOWN
SELF REFRESH
L
L
v'RQuW&DUHw
0DLQWDLQ6(/)5()5(6+
1,2
Bank(s) ACTIVE
+
+
'(6RU123
6(/)5()5(6+H[LW
1,2
READING
+
L
'(6RU123
$FWLYH32:(5'2:1HQWU\
1,2
WRITING
+
L
'(6RU123
32:(5'2:1HQWU\
1,2
PRECHARGING
+
L
'(6RU123
32:(5'2:1HQWU\
1,2
REFRESHING
+
L
'(6RU123
35(&+$5*(32:(5'2:1HQWU\
1,2
All Banks IDLE
+
L
'(6RU123
35(&+$5*(32:(5'2:1HQWU\
1,2,6
+
L
5()5(6+
6(/)5()5(6+
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n.
5()5(6+H[LWDQG32:(5'2:1H[LWSDUDPHWHUVDUHDOVRVDWLVILHG
NO OPERATION (NOP)
DESELECT (DES)
7KH'(6FRPPDQG&6?+,*+SUHYHQWVQHZFRPPDQGVIURPEHLQJH[HFXWHGE\WKH6'5$02SHUDWLRQVDOUHDG\LQSURJUHVVDUHQRWDIIHFWHG
7KH123FRPPDQG&6?/2:SUHYHQWVXQZDQWHGFRPPDQGVIURPEHLQJ
UHJLVWHUHG GXULQJ LGOH RU ZDLW VWDWHV 2SHUDWLRQV DOUHDG\ LQ SURJUHVV DUH
QRWDIIHFWHG
ZQ CALIBRATION
ZQ Calibration LONG (ZQCL)
7KH=4&/FRPPDQGLVXVHGWRSHUIRUPWKHLQLWLDOFDOLEUDWLRQGXULQJDSRZHUXSLQLWLDOL]DWLRQDQGUHVHWVHTXHQFH7KLVFRPPDQGPD\EHLVVXHGDWDQ\WLPHE\
WKHFRQWUROOHUGHSHQGLQJRQWKHV\VWHPHQYLURQPHQW7KH=4&/FRPPDQGWULJJHUVWKHFDOLEUDWLRQHQJLQHLQVLGHWKH6'5$0$IWHUFDOLEUDWLRQLVDFKLHYHGWKH
FDOLEUDWHGYDOXHVDUHWUDQVIHUUHGIURPWKHFDOLEUDWLRQHQJLQHWRWKH6'5$0,2ZKLFKDUHUHIOHFWHGDVXSGDWHG5ONDQG2'7YDOXHV
7KH6'5$0LVDOORZHGDWLPLQJZLQGRZGHILQHGE\HLWKHU t=4,1,7RU t=423(5WRSHUIRUPWKHIXOOFDOLEUDWLRQDQGWUDQVIHURIYDOXHV:KHQ=4&/LVLVVXHG
GXULQJWKHLQLWLDOL]DWLRQVHTXHQFHWKHWLPLQJSDUDPHWHUW=4,1,7PXVWEHVDWLVILHG:KHQLQLWLDOL]DWLRQLVFRPSOHWHVXEVHTXHQW=4&/FRPPDQGVUHTXLUHWKH
WLPLQJSDUDPHWHUt=423(5WREHVDWLVILHG
ZQ Calibration SHORT (ZQCS)
7KH=4&6FRPPDQGLVXVHGWRSHUIRUPSHULRGLFFDOLEUDWLRQVWRDFFRXQWIRUVPDOOYROWDJHDQGWHPSHUDWXUHYDULDWLRQV7KHVKRUWHUWLPLQJZLQGRZLVSURYLGHG
WRSHUIRUPWKHUHGXFHGFDOLEUDWLRQDQGWUDQVIHURIYDOXHVDVGHILQHGE\WLPLQJSDUDPHWHUt=4&6$=4&6FRPPDQGFDQHIIHFWLYHO\FRUUHFWDPLQLPXPRI
RON and RTTLPSHGDQFHHUURUVZLWKLQFORFNF\FOHVDVVXPLQJWKHPD[LPXPVHQVLWLYLWLHVVSHFLILHGLQ7DEOHDQG7DEOH
LOGIC Devices Incorporated
www.logicdevices.com
High Performance, Integrated Memory Module Product
March 6, 2013 LDS-L9D3xxxM32DBG2
PRELIMINARY INFORMATION
L9D3256M32DBG2
L9D3512M32DBG2
16-32 Gb, DDR3, 256-512M x 32 Dual Channel Memory Module
ACTIVATE
READ
7KH $&7,9$7( FRPPDQG LV XVHG WR RSHQ RU $&7,9$7( D URZ LQ D
SDUWLFXODU EDQN IRU D VXEVHTXHQW DFFHVV 7KH YDOXH RQ WKH %$ >@
LQSXWVVHOHFWVWKHEDQNDQGWKHDGGUHVVSURYLGHGRQLQSXWV$>Q@VHOHFWV
WKHURZ7KLVURZUHPDLQVRSHQRU$&7,9(IRUDFFHVVHVXQWLOD35(&+$5*(FRPPDQGLVLVVXHGWRWKDWEDQN
7KH5($'FRPPDQGLVXVHGWRLQLWLDWHDEXUVW5($'DFFHVVWRDQ$&7,9(
URZ 7KH DGGUHVV SURYLGHG RQ LQSXWV $>@ VHOHFWV WKH VWDUWLQJ FROXPQ
DGGUHVVGHSHQGLQJRQWKHEXUVWOHQJWKDQGEXUVWW\SHVHOHFWHGVHHWDEOH
7KHYDOXHRQLQSXW$GHWHUPLQHVZKHWKHURUQRWDXWRSUHFKDUJHLV
XVHG,IDXWRSUHFKDUJHLVVHOHFWHGWKHURZEHLQJDFFHVVHGZLOOEH35(&+$5*('DWWKHHQGRIWKH5($'EXUVW,I$87235(&+$5*(LVQRW
VHOHFWHGWKHURZZLOOUHPDLQRSHQIRUVXEVHTXHQWDFFHVVHV7KHYDOXHRQ
LQSXW$LIHQDEOHGLQWKH02'(5(*,67(5ZKHQWKH5($'FRPPDQG
LVLVVXHGGHWHUPLQHVZKHWKHU%&FKRSRU%/LVXVHG$IWHUD5($'
FRPPDQGLVLVVXHGWKH5($'EXUVWPD\QRWEHLQWHUUXSWHG$VXPPDU\
RI5($'FRPPDQGVLVVKRZQLQ7DEOH
$35(&+$5*(FRPPDQGPXVWEHLVVXHGEHIRUHRSHQLQJDGLIIHUHQWURZ
LQWKHVDPHEDQN
TABLE 58: READ COMMAND SUMMARY
CKE
Function
READ
READ with AUTO
PRECHARGE
Symbol
Prev
Cycle
Next
Cycle
CS\
RAS\
CAS\
WE\
+
L
+
L
+
%$
5)8
+
L
+
L
+
%$
RDS8
+
L
+
L
+
%$
BL8MRS
%&056
5'$3
+
L
+
L
+
%&27)
5'$36
+
L
+
L
+
BL8OTF
5'$36
+
L
+
L
+
BL8MRS
%&056
RD
%&27)
5'6
BL8OTF
BA[2:0]
An
A12
A10
A[11,0:0] Notes
9
L
&$
5)8
L
L
&$
5)8
+
L
&$
%$
5)8
9
+
&$
%$
5)8
L
+
&$
%$
5)8
+
+
&$
WRITE
7KH:5,7(FRPPDQGLVXVHGWRLQLWLDWHDEXUVW:5,7(DFFHVVWRDQ$&7,9(URZ7KHYDOXHRQWKH%$>@LQSXWVVHOHFWVWKHEDQN7KHYDOXHRQLQSXW$
GHWHUPLQHVZKHWKHURUQRW$87235(&+$5*(LVXVHG7KHYDOXHRQLQSXW$LIHQDEOHGLQWKH02'(5(*,67(5>05@ZKHQWKH:5,7(FRPPDQGLV
LVVXHGGHWHUPLQHVZKHWKHU%&FKRSRU%/LVXVHG7KH:5,7(FRPPDQGVXPPDU\LVVKRZQLQ7DEOH
TABLE 59: WRITE COMMAND SUMMARY
CKE
Function
Symbol
BL8MRS
%&056
WRITE
WRITE with AUTO
PRECHARGE
:5
Prev
Cycle
Next
Cycle
CS\
RAS\
CAS\
WE\
BA[2:0]
An
A12
A10
A[11,0:0] Notes
+
L
+
L
L
%$
5)8
9
L
&$
+
%&27)
:56
+
L
L
L
%$
5)8
L
L
&$
BL8OTF
:56
+
L
+
L
L
%$
5)8
+
L
&$
+
BL8MRS
%&056
:5$3
+
L
L
L
%$
5)8
9
+
&$
%&27)
:5$36
+
L
+
L
L
%$
5)8
L
+
&$
+
L
+
L
L
%$
5)8
+
+
&$
BL8OTF
LOGIC Devices Incorporated
:5$36
www.logicdevices.com
High Performance, Integrated Memory Module Product
March 6, 2013 LDS-L9D3xxxM32DBG2
PRELIMINARY INFORMATION
L9D3256M32DBG2
L9D3512M32DBG2
16-32 Gb, DDR3, 256-512M x 32 Dual Channel Memory Module
PRECHARGE
REFRESH
7KH35(&+$5*(FRPPDQGLVXVHGWR'($&7,9$7(WKHRSHQURZLQD
SDUWLFXODUEDQNRULQDOOEDQNV7KHEDQNVDUHDYDLODEOHIRUDVXEVHTXHQW
URZDFFHVVDWDVSHFLILHGWLPHt53DIWHUWKH35(&+$5*(FRPPDQGLV
LVVXHGH[FHSWLQWKHFDVHRIFRQFXUUHQW$87235(&+$5*($5($'RU
:5,7(FRPPDQGWRDGLIIHUHQWEDQNLVDOORZHGGXULQJFRQFXUUHQW$872
35(&+$5*(DVORQJDVLWGRHVQRWLQWHUUXSWWKHGDWDWUDQVIHULQWKHFXUUHQWEDQNDQGGRHVQRWYLRODWHDQ\RWKHUWLPLQJSDUDPHWHUV,QSXW$
GHWHUPLQHVZKHWKHURQHRUDOOEDQNVDUHSUHFKDUJHG,QWKHFDVHZKHUH
RQO\RQHEDQNLVUHFKDUJHG,QSXWV%$>@VHOHFWWKHEDQNRWKHUZLVH
%$>@DUHWUHDWHGDVv'RQuW&DUHw$IWHUDEDQNLV35(&+$5*('LWLV
LQWKHLGOHVWDWHDQGPXVWEHDFWLYDWHGSULRUWRDQ\5($'RU:5,7(FRPPDQGVEHLQJLVVXHGWRWKDWEDQN$35(&+$5*(FRPPDQGLVWUHDWHG
DVD123LIWKHUHLVQRRSHQURZLQWKDWEDQNLGOHVWDWHRULIWKHSUHYLRXVO\RSHQURZLVDOUHDG\LQWKHSURFHVVRISUHFKDUJLQJ+RZHYHUWKH
35(&+$5*(SHULRGLVGHWHUPLQHGE\WKHODVW35(&+$5*(FRPPDQG
LVVXHGWRWKHEDQN
5()5(6+LVXVHGGXULQJQRUPDORSHUDWLRQRIWKH6'5$0DQGLVDQDORJRXV
WR&$6?EHIRUH5$6?&%5UHIUHVKRU$8725()5(6+7KLVFRPPDQG
LVQRQSHUVLVWHQWVRLWPXVWEHLVVXHGHDFKWLPHD5()5(6+LVUHTXLUHG
7KH DGGUHVVLQJ LV JHQHUDWHG E\ WKH LQWHUQDO 5()5(6+ FRPPDQG 7KH
6'5$0UHTXLUHV5()5(6+F\FOHVDWDQDYHUDJHLQWHUYDORIVPD[LPXPZKHQ7$d&RUV0$;ZKHQ7$d&7KH5()5(6+SHULRG
EHJLQVZKHQWKH5()5(6+FRPPDQGLVUHJLVWHUHGDQGHQGV t5)&0,1
later.
7RDOORZIRULPSURYHGHIILFLHQF\LQVFKHGXOLQJDQGVZLWFKLQJEHWZHHQWDVNV
VRPHIOH[LELOLW\LQWKHDEVROXWH5()5(6+LQWHUYDOLVSURYLGHG$PD[LPXP
RIHLJKW5()5(6+FRPPDQGVFDQEHSRVWHGWRDQ\JLYHQ6'5$0PHDQLQJWKDWWKHPD[LPXPDEVROXWHLQWHUYDOEHWZHHQDQ\5()5(6+FRPPDQG
DQG WKH QH[W 5()5(6+ FRPPDQG LV QLQH WLPHV WKH PD[LPXP DYHUDJH
LQWHUYDO UHIUHVK UDWH 6(/) 5()5(6+ PD\ EH HQWHUHG ZLWK XS WR HLJKW
5()5(6+FRPPDQGVEHLQJSRVWHG$IWHUH[LWLQJ6(/)5()5(6+ZKHQ
HQWHUHGZLWKSRVWHG5()5(6+FRPPDQGVDGGLWLRQDOSRVWLQJRI5()5(6+
FRPPDQGV LV DOORZHG WR WKH H[WHQW WKH PD[LPXP QXPEHU RI FXPXODWLYH
SRVWHG5()5(6+FRPPDQGVERWKSUHDQGSRVW6(/)5()5(6+GRHV
QRWH[FHHGHLJKW5()5(6+FRPPDQGV
FIGURE 33 - REFRESH MODE
T0
T2
T1
T3
T4
Ta0
Ta1
Tb0
Tb1
Valid 1
Valid 1
NOP1
NOP1
Tb2
CK#
CK
t CK
t CH
t CL
Valid 1
CKE
Command
NOP 1
PRE
NOP 1
NOP 1
REF
NOP 1
REF 2
ACT
Address
RA
All banks
A10
RA
One bank
Bank(s) 3
BA[2:0]
BA
DQS, DQS# 4
DQ4
DM 4
t RP
t RFC (MIN)
t RFC 2
Indicates A Break in
Time Scale
Notes:
LOGIC Devices Incorporated
Don’t Care
1. NOP commands are shown for ease of illustration; other valid commands may be
possible at these times. CKE must be active during the PRECHARGE, ACTIVATE,
and REFRESH commands, but may be inactive at other times (see “Power-Down
Mode” on page 153).
www.logicdevices.com
High Performance, Integrated Memory Module Product
March 6, 2013 LDS-L9D3xxxM32DBG2
PRELIMINARY INFORMATION
L9D3256M32DBG2
L9D3512M32DBG2
16-32 Gb, DDR3, 256-512M x 32 Dual Channel Memory Module
SELF REFRESH
7KH6(/)5()5(6+FRPPDQGLVXVHGWRUHWDLQGDWDLQWKH6'5$0HYHQLIWKHUHVWRIWKHV\VWHPLVSRZHUHGGRZQ:KHQLQWKH6(/)5()5(6+PRGHWKH
6'5$0UHWDLQVGDWDZLWKRXWH[WHUQDOFORFNLQJ7KH6(/)5()5(6+PRGHLVDOVRDFRQYHQLHQWPHWKRGXVHGWRHQDEOHGLVDEOHWKH'//DVZHOODVWRFKDQJH
WKHFORFNIUHTXHQF\ZLWKLQWKHDOORZHGV\QFKURQRXVRSHUDWLQJUDQJH$OOSRZHUVXSSO\LQSXWVLQFOXGLQJ95()&$DQG95()'4PXVWEHPDLQWDLQHGDWYDOLGOHYHOV
XSRQHQWU\H[LWDQGGXULQJ6(/)5()5(6+PRGHRSHUDWLRQ$OOSRZHUVXSSO\LQSXWVLQFOXGLQJ95()&$DQG95()'4PXVWEHPDLQWDLQHGDWYDOLGOHYHOVXSRQ
HQWU\H[LWDQGGXULQJ6(/)5()5(6+PRGHXQGHUFHUWDLQFRQGLWLRQV
x9VV95()'49DDLVPDLQWDLQHG
x95()'4LVYDOLGDQGVWDEOHSULRUWR&.(JRLQJEDFN+,*+
x7KHILUVW:5,7(RSHUDWLRQPD\QRWRFFXUHDUOLHUWKDQFORFNVDIWHU95()'4LVYDOLG
x$OORWKHU6(/)5()5(6+PRGHH[LWWLPHUHTXLUHPHQWVDUHPHW
DLL DISABLE MODE
,IWKH'//LVGLVDEOHGE\WKH02'(5(*,67(505>@FDQEHVZLWFKHGGXULQJLQLWLDOL]DWLRQRUODWHUWKH6'5$0LVWDUJHWHGEXWQRWJXDUDQWHHGWRRSHUDWH
VLPLODUO\WRWKH1250$/PRGHZLWKDIHZQRWDEOHH[FHSWLRQV
x
x
x
7KH6'5$0VXSSRUWVRQO\RQHYDOXHRI&$6ODWHQF\&/ DQGRQHYDOXHRI&$6:5,7(ODWHQF\&:/ '//',6$%/(PRGHDIIHFWVWKH5($'GDWDFORFNWRGDWDVWUREHUHODWLRQVKLSt'46&.EXWQRWWKH5($'GDWDWRGDWDVWUREHUHODWLRQVKLS
tDQSQ, t4+6SHFLDODWWHQWLRQLVQHHGHGWROLQHWKH5($'GDWDXSZLWKWKHFRQWUROOHUWLPHGRPDLQZKHQWKH'//LVGLVDEOHG
,Q1250$/RSHUDWLRQ'//RQ t'46&.VWDUWVIURPWKHULVLQJFORFNHGJH$/&/F\FOHVDIWHUWKH5($'FRPPDQG,Q'//',6$%/(
PRGH t'46&.VWDUWV$/ &/yF\FOHVDIWHUWKH5($'FRPPDQG$GGLWLRQDOO\ZLWKWKH'//GLVDEOHGWKHYDOXHRI t'46&.FRXOGEH
larger than t&.
7KH2'7IHDWXUHLVQRWVXSSRUWHGGXULQJ'//',6$%/(PRGHLQFOXGLQJG\QDPLF2'77KH2'7UHVLVWRUVPXVWEHGLVDEOHGE\FRQWLQXRXVO\UHJLVWHULQJWKH
2'7EDOO/2:E\SURJUDPPLQJ5TT_NORM MR1[9,6,2] and RTTB:505>@WRvwZKLOHLQ'//',6$%/(PRGH
6SHFLILFVWHSVPXVWEHIROORZHGWRVZLWFKEHWZHHQWKH'//HQDEOHDQG'//',6$%/(PRGHVGXHWRDJDSLQWKHDOORZHGFORFNUDWHVEHWZHHQWKHWZRPRGHV
t&.>$9*@0$;DQG t&.>'//',6$%/(@0,1UHVSHFWLYHO\7KHRQO\WLPHWKHFORFNLVDOORZHGWRFURVVWKLVFORFNUDWHJDSLVGXULQJ6(/)5()5(6+PRGH
7KXVWKHUHTXLUHGSURFHGXUHIRUVZLWFKLQJIURPWKH'//(1$%/(WR'//',6$%/(PRGHLVWRFKDQJHIUHTXHQF\FXULQJVHOIUHIUHVKVHH)LJXUH
1.
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+,*+=VHW05>@WRvwWR',6$%/(WKH'//
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6(/)5()5(6+PD\EHH[LWHGZKHQWKHFORFNLVVWDEOHGZLWKWKHQHZIUHTXHQF\IRUt&.65;
7KH6'5$0ZLOOEHUHDG\IRULWVQH[WFRPPDQGLQWKH'//',6$%/(PRGHDIWHUWKHJUHDWHURItMRD or t02'KDVEHHQVDWLVILHG$=4&/
FRPPDQGVKRXOGEHLVVXHGZLWKDSSURSULDWHWLPLQJPHWDVZHOO
LOGIC Devices Incorporated
www.logicdevices.com
High Performance, Integrated Memory Module Product
March 6, 2013 LDS-L9D3xxxM32DBG2
L9D3256M32DBG2
L9D3512M32DBG2
PRELIMINARY INFORMATION
16-32 Gb, DDR3, 256-512M x 32 Dual Channel Memory Module
FIGURE 34 - DLL ENABLE MODE TO DLL DISABLE MODE
T0
T1
Ta0
Ta1
Tb0
Tc0
Td0
Td1
Te0
Te1
Tf0
CK#
CK
Vali d 1
CKE
Command
MRS2
6
NOP
SRE 3
t MOD
SRX 4
NOP
t CKSRE
t CKSRX 8
7
NOP
MRS5
NOP
Vali d 1
t MOD
t XS
t CKESR
ODT 9
Vali d 1
Indicates a Break in
Time Scale
127(6
1.
$Q\YDOLGFRPPDQG
2.
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3.
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:DLWt05'WKHQVHW05>@WRvwWREHJLQ'//5(6(7
5.
:DLWt05'XSGDWHUHJLVWHUV&/&:/DQGZULWHUHFRYHU\PD\EHQHFHVVDU\
6.
:DLWt02'DQ\YDOLGFRPPDQG
6WDUWLQJZLWKWKHLGOHVWDWH
8.
&KDQJHIUHTXHQF\
9.
&ORFNPXVWEHVWDEOHDWOHDVWt&.65;
10.
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Don ’t Care
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UHIUHVKPRGHVHH)LJXUHRQSDJH
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EHIRUHDSSO\LQJDQ\FRPPDQGRUIXQFWLRQUHTXLULQJDORFNHG'//DGHOD\RIt'//.DIWHU'//5(6(7PXVWEHVDWLVILHG$=4&/FRPPDQG
VKRXOGEHLVVXHGZLWKWKHDSSURSULDWHWLPLQJVPHWDVZHOO
LOGIC Devices Incorporated
www.logicdevices.com
High Performance, Integrated Memory Module Product
March 6, 2013 LDS-L9D3xxxM32DBG2
PRELIMINARY INFORMATION
L9D3256M32DBG2
L9D3512M32DBG2
16-32 Gb, DDR3, 256-512M x 32 Dual Channel Memory Module
FIGURE 35- DLL DISABLE MODE TO DLL ENABLE MODE
T0
Ta0
Ta1
Tb0
Tc0
Tc1
Td0
Te0
Tf0
Tg0
Th0
CK#
CK
CKE
Vali d
t DLLK
Command
SRE1
NOP
SRX2
NOP
t CKSRE
7
t CKSRX 9
8
MRS3
t XS
MRS4
t MRD
MRS5
Vali d 6
t MRD
ODTL off + 1 × t CK
t CKESR
ODT10
Indicates a Break in
Time Scale
Don ’t Care
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LOGIC Devices Incorporated
www.logicdevices.com
High Performance, Integrated Memory Module Product
March 6, 2013 LDS-L9D3xxxM32DBG2
PRELIMINARY INFORMATION
L9D3256M32DBG2
L9D3512M32DBG2
16-32 Gb, DDR3, 256-512M x 32 Dual Channel Memory Module
FIGURE 36 - DLL DISABLE tDQSCK TIMING
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
READ
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
CK#
CK
Command
Add ress
Vali d
RL = AL + C L = 6 (C L = 6, AL = 0)
CL = 6
DQS, DQS# DLL on
DI
b
DQ BL8 DLL on
DI
b+1
DI
b+2
DI
b+3
DI
b+4
DI
b+5
DI
b+6
DI
b+7
RL (DLLdisable) = AL + (C L - 1) = 5
t DQSCK (DLL_DIS) MIN
DQS, DQS# DLL off
DI
b
DQ BL8 DLL disable
DI
b+1
DI
b+2
DI
b+3
DI
b+4
DI
b+5
DI
b+6
DI
b+7
DI
b+3
DI
b+4
DI
b+5
DI
b+6
t DQSCK (DLL_ DIS) MAX
DQS, DQS# DLL off
DI
b
DQ BL8 DLL disable
DI
b+1
DI
b+2
DI
b+7
Transitioning Data
Don ’t Care
INPUT CLOCK FREQUENCY CHANGE
:KHQWKH''56'5$0LVLQLWLDOL]HGLWUHTXLUHVWKHFORFNWREHVWDEOHGXULQJPRVW1250$/VWDWHVRIRSHUDWLRQ7KLVPHDQVWKDWDIWHUWKHFORFNIUHTXHQF\
KDVEHHQVHWWRWKHVWDEOHVWDWHWKHFORFNSHULRGLVQRWDOORZHGWRGHYLDWHH[FHSWZKDWLVDOORZHGIRUE\WKHFORFNMLWWHUDQGVSUHDGVSHFWUXPFORFNLQJ66&
VSHFLILFDWLRQV
7KHLQSXWFORFNIUHTXHQF\FDQEHFKDQJHGIURPRQHVWDEOHFORFNUDWHWRDQRWKHUXQGHUWZRFRQGLWLRQV6(/)5()5(6+PRGHDQG35(&+$5*(SRZHUGRZQ
PRGH2XWVLGHRIWKHVHWZRPRGHVLWLVLOOHJDOWRFKDQJHWKHFORFNIUHTXHQF\)RUWKH6(/)5()5(6+PRGHFRQGLWLRQZKHQWKH''56'5$0KDVEHHQ
VXFFHVVIXOO\SODFHGLQWR6(/)5()5(6+PRGHDQG t&.65(KDVEHHQVDWLVILHGWKHVWDWHRIWKHFORFNEHFRPHVDv'RQuW&DUHw:KHQWKHFORFNEHFRPHVD
v'RQuW&DUHwFKDQJLQJWKHFORFNIUHTXHQF\LVSHUPLVVLEOHSURYLGHGWKHQHZFORFNIUHTXHQF\LVVWDEOHSULRUWRt&.65;:KHQHQWHULQJDQGH[LWLQJVHOIUHIUHVK
PRGHIRUWKHVROHSXUSRVHRIFKDQJLQJWKHFORFNIUHTXHQF\WKH6(/)5()5(6+HQWU\DQGH[LWVSHFLILFDWLRQVPXVWVWLOOEHPHW
7KH35(&+$5*(SRZHUGRZQPRGHFRQGLWLRQLVZKHQWKH''56'5$0LVLQ35(&+$5*(SRZHUGRZQPRGHHLWKHUIDVWH[LWPRGHRUVORZH[LWPRGH
(LWKHU2'7PXVWEHDWDORJLF/2:RU5TT_NOM and RTTB:5PXVWEHGLVDEOHGYLD05DQG057KLVHQVXUHV5TT_NOM and RTTB:5DUHLQDQRIIVWDWH
SULRUWRHQWHULQJ35(&+$5*(SRZHUGRZQPRGHZKLOHPDLQWDLQLQJ&.(DWDORJLF/2:$PLQLPXPRIt&.65(PXVWRFFXUDIWHU&.(JRHV/2:EHIRUHWKH
FORFNIUHTXHQF\FDQFKDQJH7KH''56'5$0LQSXWFORFNIUHTXHQF\LVDOORZHGWRFKDQJHRQO\ZLWKLQWKHPLQLPXPDQGPD[LPXPRSHUDWLQJIUHTXHQF\VSHFLILHGIRUWKHSDUWLFXODUVSHHGWHPSHUDWXUHJUDGHt&.>$9*@0,1WRt&.>$9*@0$;GHYLFH'XULQJWKHLQSXWFORFNIUHTXHQF\FKDQJH&.(PXVWEHKHOGDWD
VWDEOH/2:OHYHO:KHQWKHLQSXWFORFNIUHTXHQF\LVFKDQJHGDVWDEOHFORFNPXVWEHSURYLGHGWRWKH6'5$0t&.65;EHIRUH35(&+$5*(SRZHUGRZQPD\
EHH[LWHG$IWHU35(&+$5*(SRZHUGRZQLVH[LWHGDQGt;3KDVEHHQVDWLVILHGWKH'//PXVWEHUHVHWYLDWKH056'HSHQGLQJRQWKHQHZFORFNIUHTXHQF\
DGGLWLRQDO056FRPPDQGVPD\QHHGWREHLVVXHG'XULQJWKH'//ORFNWLPH5TT_NOM and RTTB:5PXVWUHPDLQLQDQRIIVWDWH$IWHUWKH'//ORFNWLPH
WKH6'5$0LVUHDG\WRRSHUDWHZLWKDQHZFORFNIUHTXHQF\SHULRG7KLVSURFHVVLVGHSLFWHGLQ)LJXUH
LOGIC Devices Incorporated
www.logicdevices.com
High Performance, Integrated Memory Module Product
March 6, 2013 LDS-L9D3xxxM32DBG2
PRELIMINARY INFORMATION
L9D3256M32DBG2
L9D3512M32DBG2
16-32 Gb, DDR3, 256-512M x 32 Dual Channel Memory Module
FIGURE 37- CHANGE FREQUENCY DURING PRECHARGE POWER-DOWN
Previous clock frequency
T0
T1
T2
New clock fre quency
Ta0
Tb0
Tc1
Tc0
Td0
Td1
Te0
Te1
CK#
CK
t CH
t CL
t CH
t CK
t CK
t CKSRE
t IS
t IH
t CH
b
t CK
b
t CL
b
t CH
b
b
b
t CL
t CK
b
b
t CKSRX
t CKE
t IH
CKE
t IS
t CPDED
Command
t CL
b
NOP
NOP
NOP
NOP
NOP
Address
MRS
Valid
NOP
Valid
DLL RESET
t AOFPD/ t AOF
t XP
t IH
t IS
ODT
DQS, DQS#
High-Z
High-Z
DQ
DM
t DLLK
Enter precharge
power-down mode
Frequency
change
Exit precharge
power-down mode
Indicates a Break in
Time Scale
Don’t Care
127(6
1.
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the RTTB120IHDWXUHZDVGLVDEOHGLQWKHPRGHUHJLVWHUSULRUWRHQWHULQJSUHFKDUJHSRZHUGRZQ
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WKLVFDVH
LOGIC Devices Incorporated
www.logicdevices.com
80
High Performance, Integrated Memory Module Product
March 6, 2013 LDS-L9D3xxxM32DBG2
PRELIMINARY INFORMATION
L9D3256M32DBG2
L9D3512M32DBG2
16-32 Gb, DDR3, 256-512M x 32 Dual Channel Memory Module
WRITE LEVELING
)RUEHWWHUVLJQDOLQWHJULW\''56'5$0PHPRU\VXEV\VWHPGHVLJQVKDYHDGRSWHGXVHRIIO\E\WRSRORJ\IRUWKHFRPPDQGVDGGUHVVHVFRQWUROVLJQDOVDQG
FORFNV:5,7(OHYHOLQJLVDVFKHPHIRUWKHPHPRU\FRQWUROOHUWRGHVNHZWKH'46[VWUREH'46['46[?WR&.UHODWLRQVKLSDWWKH6'5$0ZLWKDVLPSOH
IHHGEDFNIHDWXUHSURYLGHGLWE\WKH''56'5$0LWVHOI:5,7(OHYHOLQJLVJHQHUDOO\XVHGDVSDUWRIWKHLQLWLDOL]DWLRQSURFHVVLIUHTXLUHG)RU1250$/
6'5$0RSHUDWLRQWKLVIHDWXUHPXVWEHGLVDEOHG7KLVLVWKHRQO\6'5$0RSHUDWLRQZKHUHWKH'46IXQFWLRQVDVDQLQSXWWRFDSWXUHWKHLQFRPLQJFORFNDQG
WKH'4VIXQFWLRQDVRXWSXWVWRUHSRUWWKHVWDWRIWKHFORFN1RWHWKDWQRQVWDQGDUG2'7VFKHPHVDUHUHTXLUHG
7KHPHPRU\FRQWUROOHUXVLQJWKH:5,7(OHYHOLQJSURFHGXUHPXVWKDYHDGMXVWDEOHGHOD\VHWWLQJRQLWV'46VWUREHWRDOLJQWKHULVLQJHGJHRI'46WRWKHFORFN
DWWKH6'5$0SLQV7KLVLVDFFRPSOLVKHGZKHQWKH6'5$0DV\QFKURQRXVO\IHHGVEDFNWKH&.VWDWXVYLDWKH'4EXVDQGVDPSOHVZLWKWKHULVLQJHGJHRI
'467KHFRQWUROOHUUHSHDWHGO\GHOD\VWKH'46VWUREHXQWLOD&.WUDQVLWLRQIURPvwWRvwLVGHWHFWHG7KH'46GHOD\HVWDEOLVKHGWKURXJKWKLVSURFHGXUH
KHOSVHQVXUHtDQSS, tDSS, and t'6+VSHFLILFDWLRQVLQV\VWHPVWKDWXVHIO\E\WRSRORJ\E\GHVNHZLQJWKHWUDFHOHQJWKPLVPDWFK$FRQFHSWXDOWLPLQJRIWKLV
SURFHGXUHLVVKRZQLQ)LJXUH
FIGURE 38- WRITE LEVELING CONCEPT
T0
T1
T2
T3
T4
T5
T6
T7
CK#
CK
Source
Differential DQS
Tn
T0
T1
T2
T3
T4
T5
T4
T5
T6
CK#
CK
Destination
Differential DQS
0
DQ
Destination
Tn
T0
T1
0
T2
T3
T6
CK#
CK
Push DQS to capture
0–1 transition
Differential DQS
1
DQ
1
Don’t Care
LOGIC Devices Incorporated
www.logicdevices.com
81
High Performance, Integrated Memory Module Product
March 6, 2013 LDS-L9D3xxxM32DBG2
PRELIMINARY INFORMATION
L9D3256M32DBG2
L9D3512M32DBG2
16-32 Gb, DDR3, 256-512M x 32 Dual Channel Memory Module
WRITE LEVELING
:KHQ:5,7(OHYHOLQJLVHQDEOHGWKHULVLQJHGJHRI'46VDPSOHV&.DQGWKHULPH'4RXWSXWVWKHVDPSOHG&.uVVWDWXV7KHSULPH'4IRUHDFKRIWKH
ZRUGVFRQWDLQHGLQWKHL02'LV'4IRUWKHORZE\WH'4IRUWKHKLJKE\WH,WRXWSXWVWKHVWDWXVRI&.VDPSOHGE\/'46[DQG8'46[$OORWKHU'4V
'4>@'4>@IRUWKHORZZRUG'4>@'4>@IRUWKHQH[WZRUG'4>@'4>@IRUWKHQH[WDQG'4>@'4>@IRUWKH+,*+ZRUG
FRQWLQXHWRGULYH/2:7ZRSULPH'4RQHDFKRIWKHZRUGVFRQWDLQHGLQWKH/',L02'DOORZHDFKE\WHODQHWREHOHYHOHGLQGHSHQGHQWO\
WRITE LEVELING PROCEDURE
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DQG05DUHILUVWVHWDQGWKH'//LVIXOO\UHVHWDQGORFNHG7KH'4EDOOVHQWHUWKH:5,7(/HYHOLQJPRGHJRLQJIURPDv+,*+=wVWDWHWRDQXQGHILQHGGULYLQJVWDWHVRWKH'4EXVVKRXOGQRWEHGULYHQ'XULQJ:5,7(/HYHOLQJPRGHRQO\WKH123DQG'(6FRPPDQGVDUHDOORZHG7KHPHPRU\FRQWUROOHUVKRXOG
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UHTXLUHPHQW
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LOGIC Devices Incorporated
www.logicdevices.com
82
High Performance, Integrated Memory Module Product
March 6, 2013 LDS-L9D3xxxM32DBG2
PRELIMINARY INFORMATION
L9D3256M32DBG2
L9D3512M32DBG2
16-32 Gb, DDR3, 256-512M x 32 Dual Channel Memory Module
FIGURE 39- WRITE LEVELING SEQUENCE
T1
T2
t WLS
t WLH
CK#
CK
Command
MRS1
NOP2
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
t MOD
ODT
t WLDQSEN
t DQSL3
t DQSH3
t DQSL3
t DQSH3
Differential DQS4
t WLMRD
t WLO
t WLO
Prime DQ 5
t WLO
t WLOE
Early remaining DQ
t WLO
Late remaining DQ
Indicates a Break in
Time Scale
Undefined Driving Mode
Don’t Care
127(6
1.
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2.
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3.
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WRITE LEVELING EXIT MODE
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LOGIC Devices Incorporated
www.logicdevices.com
83
High Performance, Integrated Memory Module Product
March 6, 2013 LDS-L9D3xxxM32DBG2
PRELIMINARY INFORMATION
L9D3256M32DBG2
L9D3512M32DBG2
16-32 Gb, DDR3, 256-512M x 32 Dual Channel Memory Module
FIGURE 40- EXIT WRITE LEVELING
T0
T1
T2
Ta0
Tb0
Tc0
Tc1
Tc2
Td0
Td1
Te0
Te1
NOP
NOP
NOP
NOP
NOP
NOP
NOP
M RS
NOP
t MRD
Valid
NOP
Valid
CK#
CK
Command
Add ress
Valid
MR1
t IS
Valid
t MOD
ODT
ODTL off
R TT DQS, R TT DQS#
t AOF (MIN)
RTT_NOM
t AOF (MAX)
DQS, DQS#
RTT_DQ
t WLO + t WLOE
DQ
CK = 1
Indicates a Break in
Time Scale
Undefined Driving Mode
Transitioning
Don ’t Care
Notes: 1. The DQ result, “= 1,” between Ta0 and Tc0, is a result of the DQS, DQS# signals capturing
CK HIGH just after the T0 state.
LOGIC Devices Incorporated
www.logicdevices.com
High Performance, Integrated Memory Module Product
March 6, 2013 LDS-L9D3xxxM32DBG2
PRELIMINARY INFORMATION
L9D3256M32DBG2
L9D3512M32DBG2
16-32 Gb, DDR3, 256-512M x 32 Dual Channel Memory Module
OPERATIONS
Initialization
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5.
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6.
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8.
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9.
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10.
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LOGIC Devices Incorporated
www.logicdevices.com
85
High Performance, Integrated Memory Module Product
March 6, 2013 LDS-L9D3xxxM32DBG2
PRELIMINARY INFORMATION
L9D3256M32DBG2
L9D3512M32DBG2
16-32 Gb, DDR3, 256-512M x 32 Dual Channel Memory Module
FIGURE 41- INITIALIZATION SEQUENCE
T (MAX) = 200ms
VDD
VDDQ
VTT
See power-up
c onditions
in the
initialization
sequence text,
set up 1
VREF
Power-up
ramp
t VTD
Sta ble and
vali d clo ck
T0
T1
t CK
Tc0
Tb0
Ta0
Td0
CK#
CK
t CKSRX
t CL
t CL
t IOz = 20ns
RESET#
t IS
T (MIN) = 10ns
Valid
CKE
Valid
ODT
t IS
Command
NOP
MRS
MRS
MRS
MRS
ZQCL
Add ress
Code
Code
Code
Code
A10
Code
Code
Code
Code
BA0 = L
BA1 = H
BA2 = L
BA0 = H
BA1 = H
BA2 = L
BA0 = H
BA1 = L
BA2 = L
BA0 = L
BA1 = L
BA2 = L
Valid
DM
BA[2:0]
Valid
Valid
A10 = H
Valid
DQS
DQ
RTT
T = 200μs (MIN)
T = 500μs (MIN)
MR2
All voltage
supplies valid
and stable
t MRD
t MRD
t MRD
t XPR
MR3
MR1 with
DLL ena ble
t MOD
MR0 with
DLL reset
t ZQ INIT
ZQ cali bration
t DLLK
DRAM ready for
external commands
Normal
operation
Indicates a Break in
Time Scale
LOGIC Devices Incorporated
www.logicdevices.com
86
Don ’t Care
High Performance, Integrated Memory Module Product
March 6, 2013 LDS-L9D3xxxM32DBG2
PRELIMINARY INFORMATION
L9D3256M32DBG2
L9D3512M32DBG2
16-32 Gb, DDR3, 256-512M x 32 Dual Channel Memory Module
MODE REGISTERS
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WKH02'(5(*,67(56(7056FRPPDQGGXULQJLQLWLDOL]DWLRQDQGLWUHWDLQVWKHVWRUHGLQIRUPDWLRQH[FHSWIRU05>@ZKLFKLVVHOIFOHDULQJXQWLOLWLVHLWKHU
UHSURJUDPPHG5(6(7?JRHV/2:RUXQWLOWKHGHYLFHORVHVSRZHU
&RQWHQWVRIDPRGHUHJLVWHUFDQEHDOWHUHGE\UHH[HFXWLQJWKH056FRPPDQG,IWKHXVHUFKRRVHVWRPRGLI\RQO\DVXEVHWRIWKHPRGHUHJLVWHUuVYDULDEOHV
DOOYDULDEOHVPXVWEHSURJUDPPHGZKHQWKH056FRPPDQGLVLVVXHG5HSURJUDPPLQJWKHPRGHUHJLVWHUZLOOQRWDOWHUWKHFRQWHQWVRIWKHPHPRU\DUUD\
SURYLGHGLWLVSHUIRUPHGFRUUHFWO\
7KH056FRPPDQGFDQRQO\EHLVVXHGRUUHLVVXHGZKHQDOOEDQNVDUHLGOHDQGLQWKH35(&+$5*('VWDWHt53LVVDWLVILHGDQGQRGDWDEXUVWVDUHLQSURJUHVV$IWHUDQ056FRPPDQGKDVEHHQLVVXHGWZRSDUDPHWHUVPXVWEHVDWLVILHGtMRD and tMOD.
7KHFRQWUROOHUPXVWZDLWt05'EHIRUHLQLWLDWLQJDQ\VXEVHTXHQW056FRPPDQGVVHH)LJXUH
FIGURE 42- MRS-TO-MRS COMMAND TIMING (tMRD)
T0
T1
T2
Ta0
Ta1
Ta2
MRS1
NOP
NOP
NOP
NOP
MRS2
CK#
CK
Command
t MRD
Add ress
Valid
Valid
CKE 3
Indicates a Break in
Time Scale
Don ’t Care
127(6
1.
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DQGQRGDWDEXUVWVFDQEHLQSURJUHVVWKHOHYHOLQJSURFHGXUH
2.
t05'VSHFLILHVWKH056WR056FRPPDQGPLQLPXPF\FOHWLPH
3.
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0RGHwRQSDJH
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7KHFRQWUROOHUPXVWDOVRZDLW t02'EHIRUHLQLWLDWLQJDQ\QRQ056FRPPDQGVH[FOXGLQJ123DQG'(6DVVKRZQLQ)LJXUHRQSDJH7KH'5$0
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LOGIC Devices Incorporated
www.logicdevices.com
High Performance, Integrated Memory Module Product
March 6, 2013 LDS-L9D3xxxM32DBG2
PRELIMINARY INFORMATION
L9D3256M32DBG2
L9D3512M32DBG2
16-32 Gb, DDR3, 256-512M x 32 Dual Channel Memory Module
FIGURE 43- MRS-TO-NONMRS COMMAND TIMING (tMOD)
T1
T2
t WLS
t WLH
CK#
CK
Command
MRS1
NOP2
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
t MOD
ODT
t WLDQSEN
t DQSL3
t DQSH3
t DQSL3
t DQSH3
Differential DQS4
t WLMRD
t WLO
t WLO
Prime DQ 5
t WLO
t WLOE
Early remaining DQ
t WLO
Late remaining DQ
Indicates a Break in
Time Scale
Undefined Driving Mode
Don’t Care
127(6
1.
3ULRUWRLVVXLQJWKH056FRPPDQGDOOEDQNVPXVWEHLGOHWKH\PXVWEHSUHFKDUJHGt53PXVWEH
VDWLVILHGDQGQRGDWDEXUVWVFDQEHLQSURJUHVV
2.
3.
3ULRUWR7DZKHQt02'0,1LVEHLQJVDWLVILHGQRFRPPDQGVH[FHSW123'(6PD\EHLVVXHG
,I577ZDVSUHYLRXVO\HQDEOHG2'7PXVWEHUHJLVWHUHG/2:DW7VRWKDW2'7/LVVDWLVILHGSULRU
WR7D2'7PXVWDOVREHUHJLVWHUHG/2:DWHDFKULVLQJ&.HGJHIURP7XQWLO t02'0,1LV
VDWLVILHGDW7D
&.( PXVW EH UHJLVWHUHG +,*+ IURP WKH 056 FRPPDQG XQWLO t0563'(1 0,1 DW ZKLFK WLPH
SRZHUGRZQPD\RFFXUVHHv3RZHU'RZQ0RGHwRQSDJH
MODE REGISTER 0 (MR0)
7KHEDVHUHJLVWHU05LVXVHGWRGHILQHYDULRXV''5L02'PRGHVRIRSHUDWLRQ7KHVHGHILQLWLRQVLQFOXGHWKHVHOHFWLRQRIDEXUVWOHQJWKEXUVWW\SH&$6
ODWHQF\RSHUDWLQJPRGH'//5(6(7:5,7(UHFRYHU\DQG35(&+$5*(SRZHUGRZQPRGHDVVKRZQLQ)LJXUH
LOGIC Devices Incorporated
www.logicdevices.com
88
High Performance, Integrated Memory Module Product
March 6, 2013 LDS-L9D3xxxM32DBG2
PRELIMINARY INFORMATION
L9D3256M32DBG2
L9D3512M32DBG2
16-32 Gb, DDR3, 256-512M x 32 Dual Channel Memory Module
MODE REGISTER 0 (MR0)
BURST TYPE
BURST LENGTH
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