L9D364M64SBG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) Benefits FEATURES DDR3 Integrated Module [iMOD]: x9DD 9DD4 99 x9FHQWHUWHUPLQDWHGSXVKSXOO ,2 x3DFNDJHPP[PP[PP [PDWUL[ZEDOOV x0DWUL[EDOOSLWFKPP 6SDFHVDYLQJIRRWSULQW 7KHUPDOO\HQKDQFHG,PSHGDQFH PDWFKHGLQWHJUDWHGSDFNDJLQJ 'LIIHUHQWLDOELGLUHFWLRQDOGDWDVWUREH QELWSUHIHWFKDUFKLWHFWXUH LQWHUQDOEDQNVSHUZRUGZRUGV LQWHJUDWHGLQSDFNDJH 1RPLQDODQGG\QDPLFRQGLHWHUPLQDWLRQ2'7IRUGDWDVWUREHDQGPDVN VLJQDOV 3URJUDPPDEOH&$65($'ODWHQF\ &/DQG &$6:5,7(ODWHQF\&:/ 9, and 11 )L[HGEXUVWOHQJWK%/RIDQGEXUVW FKRS%&RI 6HOHFWDEOH%&RU%/RQWKHIO\ 27) 6HOI$XWR5HIUHVKPRGHV 2SHUDWLQJ7HPSHUDWXUH5DQJH DPELHQWWHPS 7$ x&RPPHUFLDO&WR& x,QGXVWULDO&WR&VXSSRUWLQJ 6(/)$8725()5(6+ x([WHQGHG&WR&PDQXDO 5()5(6+RQO\ x0LO7HPS&WR&PDQXDO 5()5(6+RQO\ &25(FORFNLQJIUHTXHQFLHV 0+] 'DWD7UDQVIHU5DWHV 0ESV :ULWHOHYHOLQJ 0XOWLSXUSRVHUHJLVWHU 2XWSXW'ULYHU&DOLEUDWLRQ VSDFHVDYLQJVZKLOHSURYLGLQJDVXUIDFHPRXQWIULHQGO\SLWFK PP 5HGXFHG,2URXWLQJ LPSURYHPHQWLQURXWLQJVIRU\RXU PHPRU\DUUD\ 5HGXFHGWUDFHOHQJWKVGXHWR WKHKLJKO\LQWHJUDWHGLPSHGDQFH PDWFKHGSDFNDJLQJ 7KHUPDOO\HQKDQFHGSDFNDJLQJ WHFKQRORJ\DOORZVLOLFRQLQWHJUDWLRQ ZLWKRXWSHUIRUPDQFHGHJUDGDWLRQGXH WRSRZHUGLVVLSDWLRQKHDW +LJK7&(RUJDQLFODPLQDWHLQWHUSRVHUIRULPSURYHGJODVVVWDELOLW\ RYHUDZLGHRSHUDWLQJWHPSHUDWXUH 6XLWDELOLW\RIXVHLQ+LJK5HOLDELOLW\ DSSOLFDWLRQVUHTXLULQJ0LOWHPSQRQ KHUPHWLFGHYLFHRSHUDWLRQ 1RWH7KLVLQWHJUDWHGSURGXFWDQGRULWVVSHFLILFDWLRQV DUHVXEMHFWWRFKDQJHZLWKRXWQRWLFH/DWHVWGRFXPHQW VKRXOGEHUHWULHYHGIURP/',SULRUWR\RXUGHVLJQ FRQVLGHUDWLRQ iMOD Part Information ORDER NUMBER SPEED GRADE /'06%*[ DDR3-1866 /'06%*[ DDR3-1600 /'06%*[ DDR3-1333 /'06%*[ DDR3-1066 /'06%*[ DDR3-800 PKG FOOTPRINT I/O PITCH PP[PP PP PKG NO. BG2 integrated module products LOGIC Devices Incorporated www.logicdevices.com 1 High Performance, Integrated Memory Module Product May 3, 2012 LDS-L9D364M64SBG2-G L9D364M64SBG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) FEATURES FIGURE 1 - DDR3 PART NUMBERS Sample Part Number: L9D3 64M 64S L9D364M64SBG2 BG2 X DDR3 iMOD XXX Code Word = 64MB Wordwidth x64 S = Single Channel Speed Grade 15 1.5ns / 667MHz 125 1.25ns / 800MHz 107 1.07ns / 933MHz 093 0.938ns / 1066MHz 16 x 22mm PBGA Temperature Code Commercial (0oC to 70oC) C Industrial (-40oC to 85oC) I o o Extended (-40 C to 105 C) E Military (-55oC to 125oC) M Note: Not all options can be combined. Please see our Part Catalog for available offerings. TABLE 1: ADDRESSING Parameter LOGIC Devices Incorporated 64 Meg x 64 &RQILJXUDWLRQ >0HJ[EDQNV[@[ 5HIUHVK&RXQW 8K 52:$GGUHVVLQJ .$>@ %DFN$GGUHVVLQJ %$>@ &ROXPQ$GGUHVVLQJ .$>@ www.logicdevices.com 2 High Performance, Integrated Memory Module Product May 3, 2012 LDS-L9D364M64SBG2-G L9D364M64SBG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) STATE DIAGRAM FIGURE 2 - SIMPLIFIED STATE DIAGRAM CKE L Power applied Power on Reset Procedure MRS, MPR, write leveling Initialization Self refresh SRE ZQCL MRS SRX From any state RESET ZQ Calibration REF ZQCL/ZQCS Idle Refreshing PDE ACT PDX Active PowerDown Preharge PowerDown Activating PDX CKE L CKE L PDE Bank Active WRITE WRITE READ WRITE AP READ AP READ Writing READ Reading WRITE WRITE AP READ AP WRITE AP READ AP PRE, PREA Writing PRE, PREA Preharging PRE, PREA Reading Automatic Sequence Command Sequence ACT = ACTIVATE MPR = Multipurpose register MRS = Mode register set PDE = Power-down entry PDX = Power-down exit PRE = PRECHARGE LOGIC Devices Incorporated www.logicdevices.com PREA=PRECHARGE ALL READ = RD, RDS4, RDS8 READ AP = RDAP, RDAPS4, RDAPS8 REF = REFRESH RESET = START RESET PROCEDURE SRE = Self refresh entry 3 SRX = Self refresh exit WRITE = WR, WRS4, WRS8 WRITE AP = WRAP, WRAPS4, WRAPS8 ZQCL = ZQ LONG CALIBRATION ZQCS = ZQ SHORT CALIBRATION High Performance, Integrated Memory Module Product May 3, 2012 LDS-L9D364M64SBG2-G L9D364M64SBG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) INDUSTRIAL TEMPERATURE FUNCTIONAL DESCRIPTION 7KH ''5 6'5$0 XVHV GRXEOH GDWD UDWH DUFKLWHFWXUH WR DFKLHYH KLJK VSHHGRSHUDWLRQ7KHGRXEOHGDWDUDWH''5DUFKLWHFWXUHLVDQQSUHIHWFK ZLWKDQLQWHUIDFHGHVLJQHGWRWUDQVIHUWZRGDWDZRUGVSHUFORFNF\FOHDWWKH ,2SLQV$VLQJOH5($'RU:5,7(DFFHVVIRUWKH''56'5$0FRQVLVWV RIDVLQJOHQELWZLGHRQHFORFNF\FOHGDWDWUDQVIHUDWWKHLQWHUQDOPHPRU\ FRUHDQGHLJKWFRUUHVSRQGLQJQELWZLGHRQHKDOIFORFNF\FOHGDWDWUDQVIHU DWWKH,2SLQ 7KH LQGXVWULDO WHPSHUDWXUH , GHYLFH UHTXLUHV WKH DPELHQW WHPSHUDWXUH QRWH[FHHG&RU&-('(&VSHFLILFDWLRQVUHTXLUHWKH5()5(6+ UDWHWRGRXEOHZKHQ7$H[FHHGV&WKLVDOVRUHTXLUHVXVHRIWKHKLJK WHPSHUDWXUH6(/)5()5(6+RSWLRQ$GGLWLRQDOO\2'7UHVLVWDQFHDQG WKH ,1387287387 LPSHGDQFH PXVW EH GHUDWHG ZKHQ WKH 7$ LV & RU!& 7KHGLIIHUHQWLDOVWUREHV/'46[/'46[?8'46[8'46[?DUHWUDQVPLWWHGH[WHUQDOO\DORQJZLWKGDWDIRUXVHLQGDWDFDSWXUHDWWKH''56'5$0 LQSXW UHFHLYHU '46 LV FHQWHUDOLJQHG ZLWK GDWD IRU :5,7(V 7KH 5($' GDWD LV WUDQVPLWWHG E\ WKH ''5 6'5$0 DQG HGJHDOLJQHG WR WKH GDWD VWUREHV EXTENDED TEMPERATURE 7KH([WHQGHGWHPSHUDWXUH(GHYLFHUHTXLUHVWKHDPELHQWWHPSHUDWXUH QRWH[FHHG&RU&-('(&VSHFLILFDWLRQVUHTXLUHWKHUHIUHVK UDWHWRGRXEOHZKHQ7$H[FHHGV&WKLVDOVRUHTXLUHVXVHRIWKHKLJK WHPSHUDWXUH6(/)5()5(6+RSWLRQ$GGLWLRQDOO\2'7UHVLVWDQFHDQG WKH ,1387287387 LPSHGDQFH PXVW EH GHUDWHG ZKHQ WKH 7$ LV & or >85& 7KH ''5 6'5$0 RSHUDWHV IURP D GLIIHUHQWLDO FORFN &.[ &.[? 7KH FURVVLQJRI&.JRLQJ+,*+DQG&.?JRLQJ/2:LVUHIHUUHGWRDVWKHSRVLWLYHHGJHRI&ORFN&.&RQWURO&RPPDQGDQG$GGUHVVVLJQDOVDUHUHJLVWHUHGDWHYHU\SRVLWLYHHGJHRI&.,QSXWGDWDLVUHJLVWHUHGRQWKHILUVW ULVLQJ HGJH RI '46 DIWHU WKH :5,7( SUHDPEOH DQG RXWSXW GDWD LV UHIHUHQFHGRQWKHILUVWULVLQJHGJHRI'46DIWHUWKH5($'SUHDPEOH MILITARY, EXTREME OPERATING TEMPERATURE 5($' DQG :5,7( DFFHVVHV WR WKH ''5 6'5$0 DUH EXUVWRULHQWHG $FFHVVHV VWDUW DW D VHOHFWHG ORFDWLRQ DQG FRQWLQXH IRU D SURJUDPPHG QXPEHURIORFDWLRQVLQDSURJUDPPHGVHTXHQFH$FFHVVHVEHJLQZLWKWKH UHJLVWUDWLRQRIDQ$&7,9$7(FRPPDQGZKLFKLVWKHQIROORZHGE\D5($' RU:5,7(FRPPDQG7KHDGGUHVVELWVUHJLVWHUHGFRLQFLGHQWZLWKWKH$&7,9$7(FRPPDQGDUHXVHGWRVHOHFWWKHEDQNDQGWKHVWDUWLQJFROXPQORFDWLRQIRUWKHEXUVWDFFHVV 7KH0LO7HPS0GHYLFHUHTXLUHVWKHDPELHQWWHPSHUDWXUHQRWH[FHHG -55&RU&-('(&UHTXLUHVWKH5()5(6+UDWHGRXEOHZKHQ7$ H[FHHGV&DQG/',UHFRPPHQGVDQDGGLWLRQDOGHUDWLQJDVVSHFLILHG LQ WKLV GRFXPHQW DV WR SURSHUO\ PDLQWDLQ WKH '5$0 FRUH FHOO FKDUJH DW WHPSHUDWXUHVDERYH7$>105& ''56'5$0GHYLFHVXVH5($'DQG:5,7(%/DQG%&$Q$872 35(&+$5*(IXQFWLRQPD\EHHQDEOHGWRSURYLGHDVHOIWLPHG52:35(&+$5*(WKDWLVLQLWLDWHGDWWKHHQGRIWKHEXUVWDFFHVV $VZLWKVWDQGDUG''56'5$0GHYLFHVWKHSLSHOLQHGPXOWLEDQNDUFKLWHFWXUHRIWKH''56'5$0DOORZVIRUFRQFXUUHQWRSHUDWLRQWKHUHE\SURYLGLQJKLJKEDQGZLGWKE\KLGLQJ52:35(&+$5*(DQG$&7,9$7,21WLPH $ 6(/) 5()5(6+ PRGH LV SURYLGHG IRU DOO WHPSHUDWXUH JUDGH RIIHULQJV DORQJZLWK$8726(/)5()5(6+IRU,QGXVWULDOSURGXFWDVZHOODVSRZHU VDYLQJ32:(5'2:1PRGH LOGIC Devices Incorporated www.logicdevices.com 4 High Performance, Integrated Memory Module Product May 3, 2012 LDS-L9D364M64SBG2-G L9D364M64SBG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) FIGURE 3 - FUNCTIONAL BLOCK DIAGRAM CS\ RAS\ CAS\ CKE WE\ VDDQ VDD VSSQ VSS RESET\ A0-A12, BA0-2 A, BA CK0 CK0\ LDQS0 LDQS0\ UDQS0 UDQS0\ RST\ VSS VSSQ VDD VDDQ WE\ CKE CAS\ RAS\ CS\ D0 LDM0 UDM0 A, BA CK1 CK1\ LDQS1 LDQS1\ UDQS1 UDQS1\ LDM1 UDM1 CK2 CK2\ LDQS2 LDQS2\ UDQS2 UDQS2\ LDM2 UDM2 CK3 CK3\ LDQS3 LDQS3\ UDQS3 UDQS3\ D3 LDM3 www.logicdevices.com DQ 8 DQ 15 DQ 0 DQ 7 DQ 16 DQ 23 DQ 8 DQ 15 DQ 24 DQ 31 DQ 0 DQ 7 DQ 32 DQ 39 DQ 8 DQ 15 DQ 40 DQ 47 DQ 0 DQ 7 DQ 48 DQ 55 DQ 8 DQ 15 DQ 56 DQ 63 RST\ VSS VSSQ VDD VDDQ WE\ CKE CAS\ RAS\ CS\ UDM3 LOGIC Devices Incorporated DQ 8 DQ 15 RST\ VSS VSSQ VDD VDDQ WE\ CKE CAS\ RAS\ CS\ D2 A, BA DQ 0 DQ 7 RST\ VSS VSSQ VDD VDDQ WE\ CKE CAS\ RAS\ CS\ D1 A, BA DQ 0 DQ 7 5 High Performance, Integrated Memory Module Product May 3, 2012 LDS-L9D364M64SBG2-G L9D364M64SBG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) BALL /SIGNAL LOCATION (PBGA) FIGURE 4 - SDRAM - DDR3 PINOUT TOP VIEW 1 A 2 3 VssQ VDDQ VDD 4 5 6 7 8 9 10 11 12 13 VDDQ Vss Vss VssQ Vss Vss VDDQ VDDQ VssQ VssQ A Vss VDD VDD Vss VDD VDD Vss VDD Vss VssQ B B VssQ C VDDQ VDD Vss Vss ZQ3 ZQ2 Vss Vss Vss Vss Vss VDD VDDQ C D VDDQ Vss Vss Vss ZQ0 ZQ1 Vss Vss DQ34 CK3 CK3\ Vss VDDQ D E Vss DQ35 DQ51 Vss Vss Vss VrefCA DQ50 DQ53 DQ37 CK2\ CK2 Vss E F Vss DQ52 DQ36 DQ33 RESET\ BA2 RFU DQ39 LDQS2 LDQS3 DQ48 DQ32 Vss F G Vss LDM3 LDM2 DQ49 DQ43 DQ59 RFU DQ55 DQ58 DQ42 Vss G H Vss DQ38 DQ54 DQ60 DQ57 UDM2 Vss DQ63 DQ56 DQ40 Vss H J Vss UDM3 DQ44 DQ41 DQ46 DQ62 VDD UDQS2\ DQ47 Vss J K VDDQ VDD A6 A10 A9 VDD Vss VDD A3 A12 RFU VDD VDDQ K L VssQ Vss A0 A11 VDD Vss VrefDA Vss VDD A1 BA1 VssDL VssQ L M VDDQ VDD A2 A4 A8 VDD Vss VDD BA0 A5 A7 VDDDL VDDQ M N Vss DQ15 UDQS0\ VDD DQ30 DQ14 DQ9 DQ12 UDM1 Vss N P Vss DQ8 DQ24 DQ31 Vss UDM0 DQ25 DQ28 DQ22 DQ6 Vss P R Vss DQ10 DQ26 DQ23 ODT DQ27 DQ11 DQ17 LDM0 LDM1 Vss R T Vss DQ0 DQ16 DQ7 Vss Vss Vss DQ1 DQ4 DQ20 Vss T U Vss CK0 CK0\ DQ5 DQ21 DQ18 Vss Vss CKE WE\ DQ19 DQ3 Vss U V VDDQ Vss CK1\ CK1 DQ2 RAS\ CAS\ Vss Vss Vss Vss Vss VDDQ V W VDDQ VDD Vss Vss Vss CS\ Vss Vss Vss Vss Vss VDD VDDQ W Y VssQ Vss VDD Vss VDD VDD Vss VDD VDD Vss VDD Vss VssQ Y AA VssQ VssQ VDDQ VDDQ Vss Vss VssQ Vss Vss VDDQ VDDQ VssQ VssQ AA 1 2 3 4 5 6 7 8 9 10 11 12 13 UDQS1\ UDQS1 UDQS0 DQ13 DQ29 LDQS1\ LDQS0\ LDQS1 LDQS0 LDQS2\ LDQS3\ DQ61 DQ45 UDQS2 UDQS3 UDQS3\ GND (Core) V + (Core Power) UNPOPULATED Address GND (I/O) V + (I/O Power) Data IO CNTRL VSSDL VDDDL Level REF 271BGA-1.00MM PITCH - X64, SCB LOGIC Devices Incorporated www.logicdevices.com 6 High Performance, Integrated Memory Module Product May 3, 2012 LDS-L9D364M64SBG2-G L9D364M64SBG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) TABLE 2 - BALL/SIGNAL LOCATION AND DESCRIPTION Ball Assignments Symbol Type Input Address Inputs: 3URYLGHWKH52:DGGUHVVIRU$&7,9$7(FRPPDQGVDQGWKHFROXPQDGGUHVV Description L3, L10, M3, K9, M4, A0, A1, A2, M10, K3, M11, M5, K5, A3, A4, A5, DQGDXWRSUHFKDUJHELW$10IRU5($'<:5,7(FRPPDQGVWRVHOHFWRQHORFDWLRQRXWRIWKH K4, L4, K10 A6, A7, A8, PHPRU\DUUD\LQWKHUHVSHFWLYHEDQN$10VDPSOHGGXULQJD35(&+$5*(FRPPDQGGHWHUPLQHV A9, A10 /AP, ZKHWKHUWKH35(&+$5*(DSSOLHVWRRQHEDQN$10/2:EDQNVHOHFWHGE\%$>@RUDOOEDQNV A11, A12 /BC $10+,*+7KHDGGUHVVLQSXWVDOVRSURYLGHWKHRSFRGHGXULQJD/2$'02'(FRPPDQG $GGUHVVLQSXWVDUHUHIHUHQFHGWR9UHI&$$12%&ZKHQHQDEOHGLQWKHPRGHUHJLVWHU05$12 LVVDPSOHGGXULQJ5($'DQG:5,7(FRPPDQGVWRGHWHUPLQHZKHWKHUEXUVWFKRS/2: %&4 EXUVWFKRS M9, L11, F6 BA0, BA1, BA2 Input Bank Address Inputs: %$>@GHILQHWKHEDQNWRZKLFKDQ$&7,9$7(5($':5,7(RU 35(&+$5*(FRPPDQGLVEHLQJDSSOLHG%$>@GHILQHZKLFKPRGHUHJLVWHU050, MR1, MR2, or MR3LVORDGHGGXULQJWKH/2$'02'(FRPPDQG%$>@DUHUHIHUHQFHGWR9UHI&$ .*) RFU 8899( CKX, CKX\ Input )XWXUH$GGUHVV$13, $14, $15 Input Clock: &.[DQG&.[?DUHGLIIHUHQWLDOFORFNLQSXWVRQHGLIIHUHQWLDOSDLUSHU:25'IRXU:25'V FRQWDLQHGLQWKH/'[[*SURGXFW$OOFRQWURODQGDGGUHVVLQSXWVLJQDOVDUHVDPSOHGRQWKH ('' FURVVLQJRIWKHSRVLWLYHHGJHRI&.[DQGWKHQHJDWLYHHGJHRI&.[?2XWSXWGDWDVWUREHV8'46[ 8'46[?DQG/'46[/'46[?LVUHIHUHQFHGWRWKHFURVVLQJRI&.[DQG&.[? 8 CKE Input Clock Enable: &.(HQDEOHVDQGGLVDEOHVLQWHUQDOFLUFXLWU\DQGFORFNVRQWKH6'5$07KH VSHFLILFFLUFXLWU\WKDWLVHQDEOHGGLVDEOHGLVGHSHQGHQWXSRQWKH''56'5$0FRQILJXUDWLRQDQG RSHUDWLQJPRGH7DNLQJ&.(/2:SURYLGHV35(&+$5*(SRZHUGRZQDQG6(/)5()5(6+ RSHUDWLRQVDOOEDQNVLGOHRUDFWLYHSRZHUGRZQURZDFWLYHLQDQ\EDQN&.(LVV\QFKURQRXV IRUSRZHUGRZQHQWU\DQGH[LWDQGIRUVHOIUHIUHVKHQWU\&.(LVDV\QFKURQRXVIRUVHOIUHIUHVK H[LW,QSXWEXIIHUVH[FOXGLQJ&.[&.[?&.(5(6(7DQG2'7DUHGLVDEOHGGXULQJ6(/) 5()5(6+&.(LVUHIHUHQFHGWR9UHI&$ : CS\ Input Chip Select: &6?HQDEOHVUHJLVWHUHG/2:DQGGLVDEOHVWKHFRPPDQGGHFRGHU$OOFRPPDQGV DUHPDVNHGZKHQ&6?LVUHJLVWHUHG+,*+&6?SURYLGHVIRUH[WHUQDOUDQNVHOHFWLRQRQV\VWHPVZLWK PXOWLSOH UDQNV&6?LVFRQVLGHUHGSDUWRIWKHFRPPDQGFRGH&6?LVUHIHUHQFHGWR9UHI&$ 5351 LDMx, Input Input Data Mask: /'0[LVWKH/RZHUE\WHRID:25'8'0[LVWKH8SSHUE\WHRID:25'WKH *+* UDMx /'[[*FRQWDLQVIRXU:25'67KHGDWDPDVNLQSXWPDVNV:5,7(GDWD/RZHUE\WHGDWD PDVNHGZKHQ/'0[LVVDPSOHG+,*+XSSHUE\WHGDWDPDVNHGZKHQ8'0[LVVDPSOHG+,*+ - 7KH8'0[DQG/'0[SLQVDUHVWUXFWXUHGDVLQSXWVRQO\WKHSLQVHOHFWULFDOORDGLQJLVGHVLJQHGWR PDWFKWKDWRIWKH'4DQG/'46[?8'46[DQG8'46[?SLQV 9 RAS\ Input ROW Address Strobe/Select: 'HILQHVWKHFRPPDQGEHLQJHQWHUHGDORQJ&$6?:(?DQG&6? 7KLVLQSXWSLQLVUHIHUHQFHGWR9UHI&$ 9 CAS\ Input COLUMN Address Strobe/Select: 'HILQHVWKHFRPPDQGEHLQJHQWHUHGDORQJZLWK5$6?:(? DQG&6?7KLVLQSXWSLQLVUHIHUHQFHGWR9UHI&$ 8 WE\ Input WRITE Enable Input: 'HILQHVWKHFRPPDQGEHLQJHQWHUHGDORQJZLWK&$6?5$6?DQG&6?7KLV LQSXWSLQLVUHIHUHQFHGWR9UHI&$ LOGIC Devices Incorporated www.logicdevices.com High Performance, Integrated Memory Module Product May 3, 2012 LDS-L9D364M64SBG2-G L9D364M64SBG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) TABLE 2 - BALL/SIGNAL LOCATION AND DESCRIPTION CONTINUED Ball Assignments Symbol 5 ODT Type Description Input On-Die Termination: 2'7HQDEOHVZKHQUHJLVWHUHG+,*+DQGGLVDEOHVWHUPLQDWLRQUHVLVWDQFH LQWHUQDOWRWKH''56'5$0:KHQHQDEOHGLQQRUPDORSHUDWLRQ2'7LVRQO\DSSOLHGWRHDFKRI WKHIROORZLQJVLJQDOV'4>@/'4;[?8'46[?8'0[DQG/'0[7KH2'7LQSXWLVLJQRUHGLI GLVDEOHGYLDWKH/2$'02'(UHJLVWHUFRPPDQG2'7LVUHIHUHQFHGWR9UHI&$ F5 RESET\ Input RESET: $QLQSXWFRQWUROSLQDFWLYH/2:UHIHUHQFHGWR9VV7KH5(6(7?LQSXWUHFHLYHULVD &026LQSXWGHILQHGDVDUDLOWRUDLOVLJQDOZLWK'&+,*+t[9DDDQG'&/2:d[9DDQ. 5(6(7?DVVHUWLRQDQGGHDVVHUWLRQDUHDV\QFKURQRXV T5, R3, T4, R2, F9, G11, LDQSx, F10, G12 LDQSx\ 1111-- UDQSx, -- UDQSx\ 77987 DQ0, DQ1, 837 DQ2, DQ3, Input Data Strobe, LOW Byte (per WORD): 2XWSXWHGJHDOLJQHGZLWK5($'GDWD,QSXWFHQWHU DOLJQHGZLWK:5,7(GDWD Input Data Strobe, HIGH Byte (per WORD): 2XWSXWHGJHDOLJQHGZLWK5($'GDWD,QSXWFHQWHU DOLJQHGZLWK:5,7(GDWD I/O Data Input/Output: /2:%\WH/2::25':25'3LQUHIHUHQFHGWR9UHI'4 I/O Data Input/Output: +,*+%\WH/2::25':25'3LQUHIHUHQFHGWR9UHI'4 I/O Data Input/Output: /2:%\WH:25'3LQUHIHUHQFHGWR9UHI'4 I/O Data Input/Output: +,*+%\WH:25'3LQUHIHUHQFHGWR9UHI'4 I/O Data Input/Output: /2:%\WH:25'3LQUHIHUHQFHGWR9UHI'4 I/O Data Input/Output: +,*+%\WH:25'3LQUHIHUHQFHGWR9UHI'4 DQ4, DQ5, DQ6, DQ7 31551 DQ8, DQ9, 311 DQ10, DQ11, DQ12, DQ13, DQ14, DQ15 75887 DQ16, DQ17, 835 DQ18, DQ19, DQ20, DQ21, DQ22, DQ23 335533 DQ24, DQ25, 13 DQ26, DQ27, DQ28, DQ29, DQ30, DQ31 ))'() DQ32, DQ33, (+) DQ34, DQ35, DQ36, DQ37, DQ38, DQ39 +-**- DQ40, DQ41, +-- DQ42, DQ43, DQ44, DQ45, DQ46, DQ47 LOGIC Devices Incorporated www.logicdevices.com 8 High Performance, Integrated Memory Module Product May 3, 2012 LDS-L9D364M64SBG2-G L9D364M64SBG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) TABLE 2 - BALL/SIGNAL LOCATION AND DESCRIPTION CONTINUED Ball Assignments Symbol Type Description )*(()( DQ48, DQ49, Supply Data Input/Output: /2:%\WH+,*+:25':25'3LQUHIHUHQFHGWR9UHI'4 DQ50, DQ51, +* DQ52, DQ53, DQ54, DQ55 ++**+ +-+ DQ56, DQ57, Supply Data Input/Output: +,*+%\WH+,*+:25':25'3LQUHIHUHQFHGWR9UHI'4 DQ58, DQ59, DQ60, DQ61, DQ62, DQ63 B3, B5, B6, B8, B9, B11, VDD Supply 3RZHU6XSSO\99 &&-... K12, L5, L9, M2, M6, M8, 1::<< <<<<% $$$$& VDDQ Supply 'DWD,26XSSO\99 &''.. 009:: $$$$$$$$ %%%&& Vss Supply Ground ''+.// /0399 ::<<< <<%$$ $$&&&& &''''( ((()) **++- -1133 557777 78888 9999: ::::: $$$$$$$$( $$$$% VssQ Supply 'DWD,2*URXQG,VRODWHGIURP&RUHIRULPSURYHGQRLVHLPPXQLW\ %//<< $$$$$$$$ $$ L12 VSSDL *URXQGIRU'// M12 VDDDL ( VrefCA Supply 9ROWDJH5HIHUHQFH&25(9UHI&$PXVWEHPDLQWDLQHGDWDOOWLPHV / VrefDQ Supply 9ROWDJH5HIHUHQFH,29UHI'4PXVWEHPDLQWDLQHGDWDOOWLPHV &&'' ZQx $% UNPOPULATED LOGIC Devices Incorporated 6XSSO\IRU'// Ref. ([WHUQDO5HIHUHQFHIRURXWSXWGULYHFDOLEUDWLRQ 8QSRSXODWHGXQSODWHGPDWUL[ORFDWLRQV www.logicdevices.com 9 High Performance, Integrated Memory Module Product May 3, 2012 LDS-L9D364M64SBG2-G L9D364M64SBG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) FIGURE 5 - MECHANICAL DRAWING [120 Ø $ B & D ( F G + K L M N 3 R T 8 9 : < $$ 20.00 NOM 0$; 1.00 NOM 1.00 NOM 12.00 NOM 1RWH$OOGLPHQVLRQVLQPP LOGIC Devices Incorporated www.logicdevices.com 10 High Performance, Integrated Memory Module Product May 3, 2012 LDS-L9D364M64SBG2-G L9D364M64SBG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) TABLE 3: ABSOLUTE MAXIMUM RATINGS Symbol MIN MAX UNITS NOTES 9DD 9DD6XSSO\9ROWDJHUHODWLYHWR9VV Parameter -0.4 9 1 9DDQ 9DD6XSSO\9ROWDJHUHODWLYHWR9VVQ -0.4 9 1 9IN9287 9ROWDJHRQDQ\SLQUHODWLYHWR9VV -0.4 9 1 T$,QGXVWULDO 2SHUDWLQJ$PELHQW7HPSHUDWXUH -40 85 °& 2,3 T$([WHQGHG 2SHUDWLQJ$PELHQW7HPSHUDWXUH -40 105 °& 2,3 T$0LOWHPS 2SHUDWLQJ$PELHQW&DVH7HPSHUDWXUH -55 125 °& 2,3 TSTG 6WRUDJH7HPSHUDWXUH -55 120 °& 2,3 127(6 9DDDQG9DD4PXVWEHZLWKLQP9RIHDFKRWKHUDWDOOWLPHVDQG95()PXVWQRWEHJUHDWHUWKDQ[9DD4:KHQ9DD and 9DD4DUHOHVVWKDQ0995()PD\EHdP9 0D[RSHUDWLQJDPELHQWWHPSHUDWXUHT$LVPHDVXUHGLQWKHFHQWHURIWKHSDFNDJH 'HYLFH)XQFWLRQDOLW\LVQRWJXDUDQWHHGLIWKH'5$0GHYLFHH[FHHGVWKH0D[LPXP7$GXULQJRSHUDWLRQ TABLE 4: INPUT/OUTPUT CAPACITANCE PACKAGE OUTLINE DIMENSIONS DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 DDR3-1866 Capacitance Parameter Symbol MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX UNITS NOTES &.DQG&.? &&. 3.1 6.2 3.1 6.2 3.0 6.1 3.0 6.1 3.0 6.1 S) 6LQJOHHQG,2'4'0 &10 1.5 3.0 1.5 3.0 1.5 2.5 1.5 2.5 1.5 2.5 S) 2 1.5 2.5 1.5 2.5 1.5 2.5 S) 3 12 22 12 22 12 22 S) 5 &10 'LIIHUHQWLDO,2'46'46? ,QSXWV5$6?&$6?:(?&6?&.(5(6(7?$''5%$ &,B6KDUHG 1.5 3.0 1.5 3.0 12 22 12 22 127(6 9DD 9P99DDQ 9DD95() 9VVI 0+]T$ = 25°&9287'& [9DDQ9287SHDNWRSHDN 9 '0LQSXWLVJURXSHGZLWK,2SLQVUHIOHFWLQJWKHVLJQDOLVJURXSHGZLWK'4DQGWKHUHIRUHPDWFKHGLQORDGLQJ &&&46LVIRU'46YV'46? &DIO &,2'4[&,2>'46@&,2>'46?@ ([FOXGHV&.&.? &',B&17/ &,&17/[&&.>&.@&&.>&.?@&17/ 2'7&6?DQG&.( &',B&0'B$''5 &,&0'B$''5[&&.>&.@&&.>&.?@&0' 5$6?&$6?DQG:(?$''5 >Q@ LOGIC Devices Incorporated www.logicdevices.com 11 High Performance, Integrated Memory Module Product May 3, 2012 LDS-L9D364M64SBG2-G L9D364M64SBG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) TABLE 5: TIMING PARAMETERS FOR IDD MEASUREMENTS - CLOCK UNITS DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 DDR3-1866 -25 -19 -15 -12 -11 6-6-6 8-8-8 10-10-10 11-11-11 13-13-13 2.5 1.5 1.25 QV &/,DD 6 8 10 11 13 &. t5&'0,1,DD 6 8 10 11 13 &. W5&0,1,DD 21 28 34 36 40 &. t5$60,1,DD 15 20 24 28 32 &. 6 8 10 12 14 &. 20 30 33 36 &. IDD Parameter t&.0,1,DD t530,1,DD t)$: [ tRRD IDD [ t5)& 0[; LOGIC Devices Incorporated 4 6 5 6 6 &. 44 59 90 110 &. www.logicdevices.com 12 High Performance, Integrated Memory Module Product May 3, 2012 LDS-L9D364M64SBG2-G LOGIC Devices Incorporated ODT WE\ CAS\ RAS\ Sub-Loop CKE www.logicdevices.com 1 2 3 4 5 6 7 BA [2:0] Cycle Number 0 A [15:11] PRE A [10] 0 1 1 1 1 A [9:7] ACT D D D\ D\ 0 PRE A [6:3] 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 Repeat cycles 1 through 4 until n RAS - 1, truncate if needed 0 1 0 0 0 0 0 0 0 Repeat cycles 1 through 4 until n RC - 1, truncate if needed 0 1 1 0 0 0 0 0 F 0 0 0 0 0 0 0 0 F 0 0 0 0 0 0 0 0 F 1 1 1 0 0 0 0 0 F 1 1 1 0 0 0 0 0 F Repeat cycles n RC +1 through n RC +4 until n RC - 1 + n RAS - 1, truncate if needed 0 1 0 0 0 0 0 0 F Repeat cycles n RC +1 through n RC +4 until 2 x RC - 1, truncate if needed Repeat sub-loop 0, use BA [2:0] = 1 Repeat sub-loop 0, use BA [2:0] = 2 Repeat sub-loop 0, use BA [2:0] = 3 Repeat sub-loop 0, use BA [2:0] = 4 Repeat sub-loop 0, use BA [2:0] = 5 Repeat sub-loop 0, use BA [2:0] = 6 Repeat sub-loop 0, use BA [2:0] = 7 CK, CK\ 13 0 0 0 0 0 0 0 0 0 0 0 0 A [2:0] 0 0 0 1 1 - - - - Data 0 0 1 1 1 1 Command ACT D D D\ D\ CS\ 0 1 2 3 4 n RAS n RC n RC + 1 n RC + 2 n RC + 3 n RC + 4 n RC + n RAS 2 x nRC 4 x n RC 6 x n RC 8 x n RC 10 x n RC 12 x n RC 14 x n RC L9D364M64SBG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) TABLE 6: IDD0 MEASUREMENT LOOP Static HIGH Toggling High Performance, Integrated Memory Module Product May 3, 2012 LDS-L9D364M64SBG2-G Cycle Number Sub-Loop CKE CK, CK\ LOGIC Devices Incorporated www.logicdevices.com 14 2 x n RC 2 x n RC 2 x n RC 2 x n RC 2 x n RC 2 x n RC 2 x n RC Command 1 2 3 4 5 6 7 CS\ 0 1 1 1 1 0 0 ACT D D D\ D\ RD PRE 0 RAS\ PRE 0 1 0 0 0 1 1 0 CAS\ 0 WE\ 1 ODT 0 BA [2:0] RD A [15:11] 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 Repeat cycles 1 through 4 until nRCD - 1, truncate if needed 0 1 0 0 0 0 0 0 Repeat cycles 1 through 4 until nRAS - 1, truncate if needed 1 0 0 0 0 0 0 0 Repeat cycles 1 through 4 until nRC - 1, truncate if needed 1 1 0 0 0 0 0 F 0 0 0 0 0 0 0 F 0 0 0 0 0 0 0 F 1 1 0 0 0 0 0 F 1 1 0 0 0 0 0 F Repeat cycles nRC + 1 through nRC + 4 until nRC + nRCD - 1, truncate if needed 0 1 0 0 0 0 0 F Repeat cycles nRC + 1 through nRC + 4 until nRC + nRAS - 1, truncate if needed 1 0 0 0 0 0 0 F Repeat cycle nRC + 1 through nRC + 4 until 2 x nRC - 1, truncate if needed Repeat sub-loop 0, use BA [2:0] = 1 Repeat sub-loop 0, use BA [2:0] = 2 Repeat sub-loop 0, use BA [2:0] = 3 Repeat sub-loop 0, use BA [2:0] = 4 Repeat sub-loop 0, use BA [2:0] = 5 Repeat sub-loop 0, use BA [2:0] = 6 Repeat sub-loop 0, use BA [2:0] = 7 A [10] 1 0 0 1 1 A [9:7] 0 0 0 1 1 A [6:3] 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A [2:0] ACT D D D\ D\ - 00110011 - - 00000000 - Data 0 1 2 3 4 n RCD n RAS n RC n RC +1 nRC +2 n RC +3 n RC +4 n RC + nRCD n RC + nRAS L9D364M64SBG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) TABLE 7: IDD1 MEASUREMENT LOOP Static HIGH Toggling High Performance, Integrated Memory Module Product May 3, 2012 LDS-L9D364M64SBG2-G L9D364M64SBG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) TABLE 8: IDD MEASUREMENT CONDITIONS FOR POWER-DOWN CURRENTS IDD2P0 IDD2P1 IDD2Q Precharge Power- Precharge PowerPrecharge Quiet Down Current Down Current Standby Current (Slow Exit) (Fast Exit) Name 7LPLQJ3DWWHUQ &.( ([WHUQDO&ORFN IDD3P Active PowerDown Current QD QD QD QD /2: /2: +,*+ /2: Toggling Toggling Toggling Toggling t&. t&.0,1,DD t&.0,1,DD t&.0,1,DD t&.0,1,DD t5& Q?D Q?D Q?D Q?D t5$6 Q?D Q?D Q?D Q?D t5&' Q?D Q?D Q?D Q?D tRRD Q?D Q?D Q?D Q?D t5& Q?D Q?D Q?D Q?D &/ Q?D Q?D Q?D Q?D $/ Q?D Q?D Q?D Q?D &6? +,*+ +,*+ +,*+ +,*+ &RPPDQG,QSXWV /2: /2: /2: /2: 52:&2/801$GGU /2: /2: /2: /2: %DQN$GGUHVV /2: /2: /2: /2: DM /2: /2: /2: /2: 'DWD,2 0LGOHYHO 0LGOHYHO 0LGOHYHO 0LGOHYHO 2XWSXW%XIIHU'4'46 (QDEOHG (QDEOHG (QDEOHG (QDEOHG (QDEOHG2)) (QDEOHG2)) (QDEOHG2)) (QDEOHG2)) 8 8 8 8 ODT %XUVW/HQJWK None None None None ,'/(%DQNV $OO $OO $OO $OO 6SHFLDO1RWHV Q?D Q?D Q?D Q?D $&7,9(%DQNV LOGIC Devices Incorporated www.logicdevices.com 15 High Performance, Integrated Memory Module Product May 3, 2012 LDS-L9D364M64SBG2-G L9D364M64SBG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) A [15:11] BA [2:0] ODT WE\ CAS\ RAS\ CKE CK, CK\ www.logicdevices.com 0 0 0 0 0 0 F F 0 1 2 3 4 5 6 7 D D D\ D\ Cycle Number Sub-Loop LOGIC Devices Incorporated 0 0 0 0 Command 0 1 2 3 4-7 8-11 12-15 16-19 20-23 24-27 28-31 CS\ 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Repeat sub-loop 0, use BA [2:0] = 1 Repeat sub-loop 0, use BA [2:0] = 2 Repeat sub-loop 0, use BA [2:0] = 3 Repeat sub-loop 0, use BA [2:0] = 4 Repeat sub-loop 0, use BA [2:0] = 5 Repeat sub-loop 0, use BA [2:0] = 6 Repeat sub-loop 0, use BA [2:0] = 7 A [10] 0 0 1 1 A [9:7] 0 0 1 1 A [6:3] 0 0 1 1 A [2:0] 1 1 1 1 Data - TABLE 9: IDD2N / IDD3N MEASUREMENT LOOP Static HIGH Toggling 16 High Performance, Integrated Memory Module Product May 3, 2012 LDS-L9D364M64SBG2-G LOGIC Devices Incorporated www.logicdevices.com D D D\ D\ A [15:11] BA [2:0] ODT WE\ CAS\ RAS\ CS\ Sub-Loop CKE 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 Repeat sub-loop 0, use BA [2:0] = 1; ODT = 0 Repeat sub-loop 0, use BA [2:0] = 2; ODT = 1 Repeat sub-loop 0, use BA [2:0] = 3; ODT = 1 Repeat sub-loop 0, use BA [2:0] = 4; ODT = 0 Repeat sub-loop 0, use BA [2:0] = 5; ODT = 0 Repeat sub-loop 0, use BA [2:0] = 6; ODT = 1 Repeat sub-loop 0, use BA [2:0] = 7; ODT = 1 A [10] 0 0 1 1 0 0 0 0 A [9:7] 0 0 1 1 0 0 F F A [6:3] 1 1 1 1 0 0 0 0 A [2:0] 1 2 3 4 5 6 7 Command Cycle Number 0 1 2 3 4-7 8-11 12-15 16-19 20-23 24-27 28-31 - Data 0 L9D364M64SBG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) TABLE 10: IDD2NT MEASUREMENT LOOP Static HIGH CK, CK\ Toggling High Performance, Integrated Memory Module Product May 3, 2012 LDS-L9D364M64SBG2-G LOGIC Devices Incorporated www.logicdevices.com BA [2:0] ODT WE\ CAS\ RAS\ CS\ Sub-Loop CKE CK, CK\ 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Repeat sub-loop 0, use BA [2:0] = 1 Repeat sub-loop 0, use BA [2:0] = 2 Repeat sub-loop 0, use BA [2:0] = 3 Repeat sub-loop 0, use BA [2:0] = 4 Repeat sub-loop 0, use BA [2:0] = 5 Repeat sub-loop 0, use BA [2:0] = 6 Repeat sub-loop 0, use BA [2:0] = 7 A [15:11] 1 0 1 1 1 0 1 1 A [10] 0 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 A [9:7] 1 0 1 1 1 0 1 1 0 0 0 0 F F F F A [6:3] 0 1 1 1 0 1 1 1 0 0 0 0 0 0 0 0 A [2:0] 1 2 3 4 5 6 7 RD D D\ D\ RD D D\ D\ 00000000 00110011 - Data 0 Command Cycle Number 0 1 2 3 4 5 6 7 8-15 16-23 24-31 32-39 40-47 48-55 56-63 L9D364M64SBG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) TABLE 11: IDD4R MEASUREMENT LOOP Static HIGH Toggling 18 High Performance, Integrated Memory Module Product May 3, 2012 LDS-L9D364M64SBG2-G LOGIC Devices Incorporated www.logicdevices.com BA [2:0] ODT WE\ CAS\ RAS\ CS\ Sub-Loop CKE CK, CK\ 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 Repeat sub-loop 0, use BA [2:0] = 1 Repeat sub-loop 0, use BA [2:0] = 2 Repeat sub-loop 0, use BA [2:0] = 3 Repeat sub-loop 0, use BA [2:0] = 4 Repeat sub-loop 0, use BA [2:0] = 5 Repeat sub-loop 0, use BA [2:0] = 6 Repeat sub-loop 0, use BA [2:0] = 7 A [15:11] 0 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 A [10] 0 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 A [9:7] 1 0 1 1 1 0 1 1 0 0 0 0 F F F F A [6:3] 0 1 1 1 0 1 1 1 0 0 0 0 0 0 0 0 A [2:0] 1 2 3 4 5 6 7 WR D D\ D\ WR D D\ D\ 00000000 00110011 - Data 0 Command Cycle Number 0 1 2 3 4 5 6 7 8-15 16-23 24-31 32-39 40-47 48-55 56-63 L9D364M64SBG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) TABLE 12: IDD4W MEASUREMENT LOOP Stac HIGH Toggling 19 High Performance, Integrated Memory Module Product May 3, 2012 LDS-L9D364M64SBG2-G LOGIC Devices Incorporated www.logicdevices.com REF D D D\ D\ Cycle Number 0 1 2 3 4 5-8 9-12 13-16 17-20 21-24 25-28 29-32 33-n RFC-1 Sub-Loop CKE CK, CK\ 1b 1c 1d 1e 1f 1g 1h 2 1a Command 0 A [9:7] A [10] A [15:11] BA [2:0] ODT WE\ CAS\ Repeat sub-loop 1a, use BA [2:0] = 1 Repeat sub-loop 1a, use BA [2:0] = 2 Repeat sub-loop 1a, use BA [2:0] = 3 Repeat sub-loop 1a, use BA [2:0] = 4 Repeat sub-loop 1a, use BA [2:0] = 5 Repeat sub-loop 1a, use BA [2:0] = 6 Repeat sub-loop 1a, use BA [2:0] = 7 Repeat sub-loop 1a through 1h until n RFC - 1, truncate if needed L9D364M64SBG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) TABLE 13: IDD5B MEASUREMENT LOOP Data A [2:0] A [6:3] RAS\ CS\ Static HIGH Toggling 20 High Performance, Integrated Memory Module Product May 3, 2012 LDS-L9D364M64SBG2-G L9D364M64SBG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) PACKAGE OUTLINE DIMENSIONS TABLE 14: IDD MEASUREMENT LOOP ,QGXVWULDO5DQJH ([WHQGHGRU0LO7HPSHUDWXUH5DQJH T$ &WR& T$ &WR&RU&WR& IDD6: Self Refresh Current IDD6E/M: Self Refresh Current IDD8: Reset &.( /2: /2: 0LGOHYHO ([WHUQDO&ORFN 2II&.DQG&.? /2: 2II&.DQG&.? /2: 0LGOHYHO t&. Q?D Q?D Q?D IDD Test t5& Q?D Q?D Q?D t5$6 Q?D Q?D Q?D t5&' Q?D Q?D Q?D tRRD Q?D Q?D Q?D t5& Q?D Q?D Q?D &/ Q?D Q?D Q?D $/ Q?D Q?D Q?D &6? 0LGOHYHO 0LGOHYHO 0LGOHYHO &RPPDQG,QSXWV 0LGOHYHO 0LGOHYHO 0LGOHYHO 52:&2/081DGGUHVVHV 0LGOHYHO 0LGOHYHO 0LGOHYHO %$1.DGGUHVVHV 0LGOHYHO 0LGOHYHO 0LGOHYHO 'DWD,2 0LGOHYHO 0LGOHYHO 0LGOHYHO 2XWSXWEXIIHU'4'46 (QDEOHG (QDEOHG 0LGOHYHO ODT (QDEOHG0LGOHYHO (QDEOHG0LGOHYHO 0LGOHYHO %XUVW/HQJWK Q?D Q?D Q?D $FWLYH%$1.6 Q?D Q?D None ,'/(%$1.6 Q?D Q?D $OO SRT 'LVDEOHGQRUPDO (QDEOHGH[WHQGHG Q?D $65 'LVDEOHG 'LVDEOHG Q?D LOGIC Devices Incorporated www.logicdevices.com 21 High Performance, Integrated Memory Module Product May 3, 2012 LDS-L9D364M64SBG2-G LOGIC Devices Incorporated Sub-Loop CKE www.logicdevices.com CK, CK\ 22 19 15 16 17 18 14 12 13 11 10 9 5 6 7 8 Cycle Number 0 0 1 ACT RDA D D 1 1 0 0 1 ACT RDA D D 1 D RAS\ 1 0 0 0 1 0 0 1 0 0 0 CAS\ D WE\ 0 1 0 ODT 4 0 0 1 ACT RDA D BA [2:0] 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 Repeat cycle 2 until n RRD - 1 1 1 0 1 0 0 0 0 1 0 1 0 1 0 0 0 0 1 0 0 0 Repeat cycle n RRD + 2 until 2 x n RRD - 1 Repeat sub-loop 0, use BA[2:0] = 2 Repeat sub-loop 0, use BA[2:0] = 3 0 0 0 3 0 0 0 Repeat cycle 4 x n RRD until n FAW - 1, if needed Repeat sub-loop 0, use BA[2:0] = 4 Repeat sub-loop 1, use BA[2:0] = 5 Repeat sub-loop 0, use BA[2:0] = 6 Repeat sub-loop 1, use BA[2:0] = 7 0 0 0 7 0 0 0 Repeat cycle n FAW + 4 x n RRD until 2 x n FAW - 1, if needed 1 1 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 Repeat cycle 2 x n FAW + 2 until 2 x n FAW + n RRD - 1 1 1 0 1 0 0 0 0 1 0 1 0 1 0 0 0 0 1 0 0 0 Repeat cycle 2 x n FAW + n RRD + 2 until 2 x n FAW + 2 x n RRD - 1 Repeat sub-loop 10, use BA[2:0] = 2 Repeat sub-loop 11, use BA[2:0] = 3 0 0 0 3 0 0 0 Repeat cycle 2 x n FAW + 4 x n RRD until 3 x n FAW - 1, if needed Repeat sub-loop 10, use BA[2:0] = 4 Repeat sub-loop 11, use BA[2:0] = 5 Repeat sub-loop 10, use BA[2:0] = 6 Repeat sub-loop 11, use BA[2:0] = 7 0 0 0 7 0 0 0 Repeat cycle 3 x n FAW + 4 x n RRD until 4 x n FAW - 1, if needed A [15:11] 1 1 0 A [10] 1 0 0 A [9:7] 0 1 0 0 0 0 0 0 F F F F F F F F 0 0 0 A [6:3] 2 3 0 0 1 Command ACT RDA D 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A [2:0] 1 CS\ 0 1 2 3 n RRD n RRD + 1 n RRD + 2 n RRD + 3 2 x n RRD 3x n RRD 4 x n RRD 4 x n RRD + 1 n FAW n FAW + n RRD n FAW + 2xn RRD n FAW + 3xn RRD n FAW + 4xn RRD n FAW + 4xn RRD+1 2 x n FAW 2 x n FAW + 1 2 x n FAW + 2 2 x n FAW + 3 2 x n FAW + n RRD 2 x n FAW + n RRD+1 2 x n FAW + n RRD+2 2 x n FAW + n RRD+3 2 x nFAW + 2x n RRD 2 x n FAW + 3x n RRD 2 x n FAW + 4x n RRD 2 x n FAW+4x n RRD+1 3 x nFAW 3 x nFAW + nRRD 3 x nFAW + 2x nRRD 3 x nFAW + 3x nRRD 3 x nFAW + 4x nRRD 3 x nFAW + 4x nRRD +1 - 00000000 - 00110011 - - - 00110011 - 00000000 - Data 0 L9D364M64SBG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) TABLE 15: IDD7 MEASUREMENT LOOP Static HIGH Toggling High Performance, Integrated Memory Module Product May 3, 2012 LDS-L9D364M64SBG2-G L9D364M64SBG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) TABLE 16: IDD MAXIMUM LIMITS Speed Bin IDD DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 DDR3-1866 UNITS IDD0 IDD1 IDD3 IDD3 IDD2Q IDD2N IDD3 IDD3N IDD4R IDD: IDD5B IDD6 IDD IDD8 360 440 40 100 180 200 100 200 520 840 800 28 1400 IDD3P$ IDD3P$ IDD3P$ 400 520 40 100 200 220 120 220 640 1060 880 28 1520 IDD3P$ IDD3P$ IDD3P$ 440 600 40 120 220 240 140 240 800 1300 960 28 1680 IDD3P$ IDD3P$ IDD3P$ 480 680 40 140 240 260 160 260 1000 1600 1040 28 2400 IDD3P$ IDD3P$ IDD3P$ 520 40 150 260 280 180 280 1200 1800 1080 28 TBD IDD3P$ IDD3P$ IDD3P$ P$ P$ P$ P$ P$ P$ P$ P$ P$ P$ P$ P$ P$ P$ P$ P$ IND (;7 0,/7(03 127(6T$ = 0°&WRd 85°&657DQG$65DUHGLVDEOHGHQDEOLQJ$65FRXOGLQFUHDVH,DD[E\XSWRDQDGGLWLRQDOP$ LOGIC Devices Incorporated www.logicdevices.com 23 High Performance, Integrated Memory Module Product May 3, 2012 LDS-L9D364M64SBG2-G L9D364M64SBG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) TABLE 17: DC ELECTRICAL CHARACTERISTICS AND OPERATINGPC ONDITIONS ACKAGE OUTLINE DIMENSIONS $OO9ROWDJHVDUHUHIHUHQFHGWR9VV Parameter/Condition Supply Voltage I/O Supply Voltage Input Leakage Current: Symbol MIN TYP MAX UNITS NOTES 9DD 1.425 1.5 9 1,2 9DDQ 1.425 1.5 9 1,2 II -2 - 2 $ I95() -1 - 1 $ $Q\LQSXW9d9INd9DD95()SLQ9d9INd9 $OORWKHUSLQVQRWXQGHUWHVW 9 VREF Supply Leakage Current: 3,4 95()'4 9DDRU95()&$ 9DD $OORWKHUSLQVQRWXQGHUWHVW 9 127(6 1. 9DDDQG9DD4PXVWWUDFNRQHDQRWKHU9DD4PXVWEHOHVVWKDQRUHTXDO 3. 95()VHH7DEOH 4. 7KH PLQLPXP OLPLW UHTXLUHPHQW LV IRU WHVWLQJ SXUSRVHV 7KH OHDNDJH WR9DD9VV 9VV4 2. 9DDDQG9DD4PD\LQFOXGH$&QRLVHRIP9N+]WR0+]LQ FXUUHQWRQWKH95()SLQVKRXOGEHPLQLPDO DGGLWLRQWRWKH'&+]WRN+]VSHFLILFDWLRQV9DDDQG9DD4PXVW EHDWWKHVDPHOHYHOIRUYDOLG$&WLPLQJSDUDPHWHUV TABLE 18: DC ELECTRICAL CHARACTERISTICS AND INPUT CONDITIONS PACKAGE OUTLINE DIMENSIONS $OO9ROWDJHVDUHUHIHUHQFHGWR9VV Parameter/Condition VIN low; DC/commands/address busses VIN high; DC/commands/address busses Symbol MIN TYP 9IL 9VV QD 9,+ 6HH7DEOH MAX UNITS 6HH7DEOH 9 QD 9DD 9 NOTES Input reference voltage command/address bus 95()&$'& [9DD [9DD [9DD 9 1,2 I/O reference voltage DQ bus 95()'4'& [9DD [9DD [9DD 9 2,3 I/O reference voltage DQ bus in SELF REFRESH 95()'465 9VV [9DD 9DD 9 4 9TT - [9DDQ - 9 5 Command/address termination voltage V\VWHPOHYHOQRW GLUHFW'5$0LQSXW 127(6 1. 95()&$'&LVH[SHFWHGWREHDSSUR[LPDWHO\[9DDDQGWRWUDFNYDUL- PRQ PRGH RQ 95()'4 PD\ QRW H[FHHG [ 9DD DURXQG WKH DWLRQVLQWKH'&OHYHO([WHUQDOO\JHQHUDWHGSHDNQRLVHQRQFRPPRQ 95()'4'&YDOXH3HDNWRSHDN$&QRLVHRQ95()'4VKRXOGQRW PRGHRQ95()&$PD\QRWH[FHHG[9DDDURXQGWKH95()&$'& H[FHHGRI95()'4'& YDOXH3HDNWRSHDN$&QRLVHRQ95()&$VKRXOGQRWH[FHHGRI 95()&$'& 4. 95()'4'& PD\ WUDQVLWLRQ WR 95()'465 DQG EDFN WR 95()'4'& ZKHQ LQ 6(/) ]5()5(6+ ZLWKLQ UHVWULFWLRQV RXWOLQHG LQ WKH 6(/) 2. '&YDOXHVDUHGHWHUPLQHGWREHOHVVWKDQ0+]LQIUHTXHQF\'5$0 5()5(6+VHFWLRQ PXVW PHHW VSHFLILFDWLRQV LI WKH '5$0 LQGXFHV DGGLWLRQDO $& QRLVH JUHDWHUWKDQ0+]LQIUHTXHQF\ 5. 9TT LV QRW DSSOLHG GLUHFWO\ WR WKH GHYLFH 9TT LV D V\VWHP VXSSO\ IRU VLJQDOWHUPLQDWLRQUHVLVWRUV0,1DQG0$;YDOXHVDUHV\VWHPGHSHQ- 3. 95()'4'& LV H[SHFWHG WR EH DSSUR[LPDWHO\ [ 9DD DQG WR WUDFN dent. YDULDWLRQVLQWKH'&OHYHO([WHUQDOO\JHQHUDWHGSHDNQRLVHQRQFRP- LOGIC Devices Incorporated www.logicdevices.com 24 High Performance, Integrated Memory Module Product May 3, 2012 LDS-L9D364M64SBG2-G L9D364M64SBG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) TABLE 19: INPUT SWITCHING CONDITIONS PACKAGE OUTLINE DIMENSIONS DDR3-1333 Symbol DDR3-1066 DDR3-800 DDR3-1600 DDR3-1866 UNITS 9,+$&0,1 P9 Input high AC voltage: Logic 1 9,+$&0,1 P9 Input high DC voltage: Logic 1 9,+'&0,1 P9 Input high DC voltage: Logic 0 9,/'&0$; -100 -100 P9 Input high AC voltage: Logic 0 9,/$&0$; -150 -150 P9 Input high AC voltage: Logic 0 9,/$&0$; P9 Input high AC voltage: Logic 1 9,+$&0,1 - P9 Input high AC voltage: Logic 1 9,+$&0,1 P9 Input high DC voltage: Logic 1 9,+'&0,1 P9 Input high DC voltage: Logic 0 9,/'&0$; -100 -100 P9 Input high AC voltage: Logic 0 9,/$&0$; -150 -150 P9 Input high AC voltage: Logic 0 9,/$&0$; - P9 Parameter/Condition &RPPDQGDQG$GGUHVV Input high AC voltage: Logic 1 DQ and DM 127(6 1. $OOYROWDJHVDUHUHIHUHQFHGWR95()95()LV95()&$IRUFRQWUROFRP- 3. PDQGDQGDGGUHVV$OOVOHZUDWHVDQGVHWXSKROGWLPHVDUHVSHFLILHGDW ,QSXWKROGWLPLQJSDUDPHWHUVt,+DQG t'+DUHUHIHUHQFHGDW9IL'& 9,+'&QRW95()$& WKH'5$0EDOO95()LV95()'4IRU'4DQG'0LQSXWV 4. 2. ,QSXWVHWXSWLPLQJSDUDPHWHUVtIS and t'6DUHUHIHUHQFHGDW9IL$& 6LQJOHHQGHG LQSXW VOHZ UDWH 9QV PD[LPXP LQSXW YROWDJH VZLQJ XQGHUWHVWLVP9SHDNWRSHDN 9,+$&QRW95()'& LOGIC Devices Incorporated www.logicdevices.com 25 High Performance, Integrated Memory Module Product May 3, 2012 LDS-L9D364M64SBG2-G L9D364M64SBG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) OPERATING CONDITIONS FIGURE 6 - INPUT SIGNAL VIL and VIH levels with ringback 1.90V VDDQ + 0.4V narrow pulse width 1.50V VDDQ Minimum VIL and VIH levels VIH (AC) 0.925V 0.925V VIH (AC) VIH (DC) VIH (DC) 0.850V 0.850V 0.780V 0.765V 0.750V 0.735V 0.720V 0.780V 0.765V 0.750V 0.735V 0.720V VREF + AC noise VREF + DC error VREF + DC error VREF + AC noise 0.650V VIL (DQ) 0.575V VIL (AC) 0.650V VIL (DC) 0.575V VIL (AC) VSS 0.0V VSS 0.4V narrow pulse width -0.40V Notes: LOGIC Devices Incorporated www.logicdevices.com 1. Numbers in diagrams reflect nominal values. 26 High Performance, Integrated Memory Module Product May 3, 2012 LDS-L9D364M64SBG2-G L9D364M64SBG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) AC OVERSHOOT/UNDERSHOOT SPECIFICATION TABLE 20: CONTROL AND ADDRESS PINS Parameter PACKAGE OUTLINE DIMENSIONS DDR3-800 DDR3-1066 9 9 9 9 9 9 9 9 9 9 Maximum overshoot area above VDD VHH)LJXUH 9QV 9QV 9QV 9QV 9QV Maximum undershoot area below Vss VHH)LJXUH 9QV 9QV 9QV 9QV 9QV Maximum peak amplitude allowed for overshoot area DDR3-1333 DDR3-1600 DDR3-1866 VHH)LJXUH Maximum peak amplitude allowed for underrshoot area VHH)LJXUH TABLE 21: CLOCK, DATA, STROBE, AND MASK PINS Parameter Maximum peak amplitude allowed for overshoot area PACKAGE OUTLINE DIMENSIONS DDR3-800 DDR3-1066 9 9 DDR3-1333 DDR3-1600 9 9 DDR3-1866 9 9 9 9 9 9 9QV 9QV 9QV 9QV 9QV 9QV 9QV 9QV 9QV 9QV VHH)LJXUH Maximum peak amplitude allowed for undershoot area VHH)LJXUH Maximum overshoot area above VDD/ VDDQ VHH)LJXUH Maximum undershoot area below Vss/ VssQ VHH)LJXUH FIGURE 7 & 8: OVERSHOOT/UNDERSHOOT SPECIFICATIONS Maximum amplitude Volts (V) Figure 7: Overshoot Overshoot area VDD/VDDQ Time (ns) Time (ns) Figure 8: Undershoot VSS/VSSQ Volts (V) Maximum amplitude LOGIC Devices Incorporated www.logicdevices.com Undershoot area High Performance, Integrated Memory Module Product May 3, 2012 LDS-L9D364M64SBG2-G L9D364M64SBG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) TABLE 22: DIFFERENTIAL INPUT OPERATING CONDITIONS (CKXP, ACKAGE CKX\, DQS X, AND DQSX\) OUTLINE DIMENSIONS Parameter/Condition Symbol MIN MAX UNITS NOTES Differential input voltage, logic high - slew 9,+',))$&VOHZ QD P9 4 Differential input voltage, logic low - slew 9IL ',))$&VOHZ QD -200 P9 4 Differential input voltage, logic high 9,+',))$& [9,+$&95() 9DD9DDQ P9 5 Differential input voltage, logic low 9IL ',))$& 9VV9VVQ [95()9IL$& P9 6 9,; 95()'& 95()'& P9 9,; 95()'& 95()'& P9 96+( 9DD49,+$& 9DDQ P9 5 9DD9,+$& 9DD 9VVQ 9DD49IL$& P9 6 9VV 9DD-9IL$& Differential input crossing voltage relative to VDD/2 for DQS, DQS\, CK, CK\ Differential input crossing voltage relative to VDD/2 for CK, CK\ Single-ended high level for strobes Single-ended high level for CK, CK\ Single-ended low level for strobes 96(/ Single-ended low level for CK, CK\ 127(6 1. &ORFN LV UHIHUHQFHG WR 9DD' DQG 9VV 'DWD VWUREH LV UHIHUHQFHG WR 6. 9DD4DQG9VV4 0,1OLPLWLVUHODWLYHWRVLQJOHHQGHGVLJQDOVWKHXQGHUVKRRWVSHFLILFDWLRQVDUHDSSOLFDEOH 2. 5HIHUHQFHLV95()&$'&IRUFORFNDQGIRU95()'4'&IRUVWUREH 7KHW\SLFDOYDOXHRI9,;$&LVH[SHFWHGWREHDERXW[9DDRIWKH 3. 'LIIHUHQWLDOLQSXWVOHZUDWH 9PV 4. 'HILQHVVOHZUDWHUHIHUHQFHSRLQWVUHODWLYHWRLQSXWFURVVLQJYROWDJHV 5. 0$; OLPLW LV UHODWLYH WR VLQJOHHQGHG VLJQDOV WKH RYHUVKRRW VSHFLILFD- 9,;H[WHQGHGUDQJHLVRQO\DOORZHGZKHQWKHIROORZLQJFRQGLWLRQVDUH WLRQVDUHDSSOLFDEOH PHW7KHVLQJOHHQGHGLQSXWVLJQDOVDUHPRQRWRQLFKDYHWKHVLQJOH WUDQVPLWWLQJGHYLFHDQG9,;$&LVH[SHFWHGWRWUDFNYDULDWLRQVLQ9DD. 9,;$& LQGLFDWHV WKH YROWDJH DW ZKLFK GLIIHUHQWLDO LQSXW VLJQDOV PXVW FURVV 8. 7KH9,;H[WHQGHGUDQJHP9LVDOORZHGRQO\IRUWKHFORFNDQGWKLV HQGHGVZLQJ96(/96(+RIDWOHDVW9DDP9DQGWKHGLIIHUHQWLDO VOHZUDWHRI&.&.?LVJUHDWHUWKDQ9QV LOGIC Devices Incorporated www.logicdevices.com 28 High Performance, Integrated Memory Module Product May 3, 2012 LDS-L9D364M64SBG2-G L9D364M64SBG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) OVERSHOOT/UNDERSHOOT SPECIFICATIONS FIGURE 9 - VIX FOR DIFFERENTIAL SIGNALS VDD, VDDQ VDD, VDDQ CK#, DQS# CK#, DQS# VIX X VIX VDD/2, VDDQ/2 X VDD/2, VDDQ/2 X VIX VIX X CK, DQS CK, DQS VSS, VSSQ VSS, VSSQ FIGURE 10 - SINGLE-ENDED REQUIREMENTS FOR DIFFERENTIAL SIGNALS V DD or VDD Q VSEH (MIN) V DD /2 or VDD Q/2 VSEH CK or DQS VSEL (MAX) VSEL VSS or VSS Q LOGIC Devices Incorporated www.logicdevices.com 29 High Performance, Integrated Memory Module Product May 3, 2012 LDS-L9D364M64SBG2-G L9D364M64SBG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) OVERSHOOT/UNDERSHOOT SPECIFICATIONS FIGURE 11 - DEFINITION OF DIFFERENTIAL AC-SWING AND tDVAC t DVAC V IHDIFF ( A C) MIN V IHDIFF (MIN) V IHDIFF ( DC) MIN CK - CK# DQ S - DQS # 0.0 V ILDIFF ( DC) MAX V ILDIFF (MAX) V ILDIFF ( A C) MAX t DVAC half cycle TABLE 23: DIFFERENTIAL INPUT OPERATING CONDITIONS (tDVAC) FOR CK X, CKD X\, DQSX, AND DQSX\ PACKAGE OUTLINE IMENSIONS %HORZ9IL$& tDVAC (ps) at [VIHDIFF(AC) to VILDiff(AC)] LOGIC Devices Incorporated Slew Rate (V/ns) 350mV 300mV -4.0 4.0 3.0 50 2.0 38 163 1.9 34 162 1.6 29 161 1.4 22 159 1.2 13 155 1.0 0 150 <1.0 0 150 www.logicdevices.com 30 High Performance, Integrated Memory Module Product May 3, 2012 LDS-L9D364M64SBG2-G L9D364M64SBG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) SLEW RATE DEFINITIONS FOR SINGLE-ENDED INPUT SIGNALS +ROGt,+DQGt'+QRPLQDOVOHZUDWHIRUDULVLQJVLJQDOLVGHILQHGDVWKHVOHZ UDWHEHWZHHQWKHODVWFURVVLQJRI9IL'&0$;DQGWKHILUVWFURVVLQJRI95(). +ROGt,+DQGt'+QRPLQDOVOHZUDWHIRUDIDOOLQJVLJQDOLVGHILQHGDVWKHVOHZ UDWHEHWZHHQWKHODVWFURVVLQJRI9,+'&0,1DQGWKHILUVWFURVVLQJRI95(). 6HWXS tIS and t'6 QRPLQDO VOHZ UDWH IRU D ULVLQJ VLJQDO LV GHILQHG DV WKH VOHZUDWHEHWZHHQWKHODVWFURVVLQJRI95()DQGWKHILUVWFURVVLQJ9,+$& 0,1 6HWXS tIS and t'6 QRPLQDO VOHZ UDWH IRU D IDOOLQJ VLJQDO LV GHILQHG DVWKHVOHZUDWHEHWZHHQWKHODVWFURVVLQJRI95()DQWKHILUVWFURVVLQJRI 9IL$&0$; TABLE 24: SINGLE-ENDED INPUT SLEW RATE Measured Input Slew Rate (Linear Signals) Input PACKAGE OUTLINE DIMENSIONS Edge From To 5LVLQJ 95() 9,+$&0,1 Falling 95() 9IL$&0$; 5LVLQJ 9IL'&0D[ 95() Setup Calculation 9,+$&0,195() 95()9IL$&0$; 'TFS 95()9IL'&0$; '7)+ Hold Falling 9,+'&0,1 95() 9,+'&0,195() '756+ LOGIC Devices Incorporated www.logicdevices.com 31 High Performance, Integrated Memory Module Product May 3, 2012 LDS-L9D364M64SBG2-G L9D364M64SBG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) SLEW RATE DEFINITIONS FOR SINGLE-ENDED INPUT SIGNALS FIGURE 12 - NOMINAL SLEW RATE DEFINITION FOR SINGLE-ENDED INPUT SIGNALS ΔTRS Setup Single-ended input voltage (DQ, CMD, ADDR) VIH(AC) MIN VIH(DC) MIN VREFDQ or VREFCA VIL(DC) MAX VIL(AC) MAX ΔTFS ΔTRH Hold Single-ended input voltage (DQ, CMD, ADDR) VIH(AC) MIN VIH(DC) MIN VREFDQ or VREFCA VIL(DC) MAX VIL(AC) MAX ΔTFH LOGIC Devices Incorporated www.logicdevices.com 32 High Performance, Integrated Memory Module Product May 3, 2012 LDS-L9D364M64SBG2-G L9D364M64SBG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) SLEW RATE DEFINITIONS FOR DIFFERENTIAL INPUT SIGNALS ,QSXWVOHZUDWHIRUGLIIHUHQWLDOVLJQDOV&.[&.[?8'46[8'46[?/'46[DQG/'46[?DUHGHILQHGDQGPHDVXUHGDVVKRZQLQ7DEOH7KHQRPLQDOVOHZ UDWHIRUDULVLQJVLJQDOLVGHILQHGDVWKHVOHZUDWHEHWZHHQ9IL',))0$;DQG9,+',))0,17KHQRPLQDOVOHZUDWHIRUDIDOOLQJVLJQDOLVGHILQHGDVWKHVOHZ UDWHEHWZHHQ9,+',))0,1DQG9IL',))0$; TABLE 25: DIFFERENTIAL INPUT SLEW RATE DEFINITION Measured Input Slew Rate (Linear Signals) Input Edge PACKAGE OUTLINE DIMENSIONS From 5LVLQJ 95() To Calculation 9,+',))0,1- 9IL',))0$; 9,+$&0,1 '75',)) CK and DQS Reference 9,+',))0,1 9IL',))0$; Falling 95() 9,/$&0$; '7)',)) FIGURE 13 - NOMINAL DIFFERENTIAL INPUT SLEW RATE DEFINITION FOR DQS, DQS# AND CK, CK# Differential input voltage (DQS, DQS#; CK, CK#) ΔTR DIFF VIH(DIFF) MIN 0 VIL(DIFF) MAX ΔTFDIFF LOGIC Devices Incorporated www.logicdevices.com 33 High Performance, Integrated Memory Module Product May 3, 2012 LDS-L9D364M64SBG2-G L9D364M64SBG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) ODT CHARACTERISTICS FIGURE 14 - ODT LEVELS AND I-V CHARACTERISTICS Chip in termination mode 2'7uV HIIHFWLYH UHVLVWDQFH 5TT LV GHILQHG E\ 05> DQG @ 2'7 LV DSSOLHGWRWKH'4[8'0[/'0[8'46[8'46[?/'46[DQG/'46[? EDOOV7KH2'7WDUJHWYDOXHVDUHOLVWHGLQ7DEOH ODT VDD Q IPU IOUT = IPD - IPU To other circuitry such as RCV, . . . RTTPU DQ IOUT R TTPD VOUT IPD VSSQ TABLE 26: ON-DIE TERMINATION DC ELECTRICAL CHARACTERISTICS Parameter/Condition Symbol RTTHIIHFWLYHLPSHGDQFH RTTB()) 'HYLDWLRQRI90ZLWKUHVSHFWWR9DD4 '90 MIN TYP MAX UNITS NOTES % 1, 2, 3, 4 1, 2, 4 6HH7DEOH -5 5 127(6 1. 7ROHUDQFH OLPLWV DUH DSSOLFDEOH DIWHU D SURSHU =4 FDOLEUDWLRQ KDV EHHQ 3. 0HDVXUHYROWDJH90DWWKHWHVWHGSLQZLWKQRORDG SHUIRUPHGDWDVWDEOHWHPSHUDWXUHDQGYROWDJH9DD4 9DD9VV49VV 5HIHUWRv2'76HQVLWLYLW\wRQSDJHLIHLWKHUWKHWHPSHUDWXUHRUYROWDJH '90 FKDQJHVDIWHUFDOLEUDWLRQ 2. [90 [ 9DDQ 0HDVXUHPHQWGHILQLWLRQIRU5TT$SSO\9,+$&WRDSLQXQGHUWHVWDQG PHDVXUHWKHFXUUHQW,>9,+$&@WKHQDSSO\9IL$&WRSLQXQGHUWHVWDQG 4. )RU H[WHQGHG 0,/WHPS GHYLFHV WKH PLQLPXP YDOXHV DUH GHUDWHG E\ ZKHQWKHGHYLFHLVEHWZHHQ&DQG&T$ PHDVXUHFXUUHQW,>9IL$&@ 9IL$&9IL$& RTT = LOGIC Devices Incorporated ,>9,+$&,9IL$&@ www.logicdevices.com 34 High Performance, Integrated Memory Module Product May 3, 2012 LDS-L9D364M64SBG2-G L9D364M64SBG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) TABLE 27: RTT EFFECTIVE IMPEDANCES MR1 [9,6,2] RTT PACKAGE OUTLINE DIMENSIONS Resistor RTT1203'240 0, 1, 0 120: RTT12038240 120: RTT603'120 0, 0, 1 60: RTT6038240 60: RTT403'80 0, 1, 1 40: RTT403880 40: RTT303'60 1, 0, 1 30: RTT303860 30: RTT203'40 1, 0, 0 20: RTT203840 20: LOGIC Devices Incorporated www.logicdevices.com VOUT MIN TYP MAX UNITS [9DDQ 0.6 1.0 1.1 5=4 [9DDQ 0.9 1.0 1.1 5=4 [9DDQ 0.9 1.0 1.4 5=4 [9DDQ 0.9 1.0 1.4 5=4 [9DDQ 0.9 1.0 1.1 5=4 [9DDQ 0.9 1.0 1.1 5=4 9IL$&WR9,+$& 0.9 1.0 1.6 5=4 [9DDQ 0.6 1.0 1.1 5=4 [9DDQ 0.9 1.0 1.1 5=4 [9DDQ 0.9 1.0 1.4 5=4 [9DDQ 0.9 1.0 1.4 5=4 [9DDQ 0.9 1.0 1.1 5=4 [9DDQ 0.9 1.0 1.1 5=4 9IL$&WR9,+$& 0.9 1.0 1.6 5=4 [9DDQ 0.6 1.0 1.1 5=4 [9DDQ 0.9 1.0 1.1 5=4 [9DDQ 0.9 1.0 1.4 5=4 [9DDQ 0.9 1.0 1.4 5=4 [9DDQ 0.9 1.0 1.1 5=4 [9DDQ 0.9 1.0 1.1 5=4 9IL$&WR9,+$& 0.9 1.0 1.6 5=4 [9DDQ 0.6 1.0 1.1 5=4 [9DDQ 0.9 1.0 1.1 5=4 [9DDQ 0.9 1.0 1.4 5=4 [9DDQ 0.9 1.0 1.4 5=4 [9DDQ 0.9 1.0 1.1 5=4 [9DDQ 0.9 1.0 1.1 5=4 9IL$&WR9,+$& 0.9 1.0 1.6 5=4 [9DDQ 0.6 1.0 1.1 5=4 [9DDQ 0.9 1.0 1.1 5=4 [9DDQ 0.9 1.0 1.4 5=4 [9DDQ 0.9 1.0 1.4 5=4 [9DDQ 0.9 1.0 1.1 5=4 [9DDQ 0.9 1.0 1.1 5=4 9IL$&WR9,+$& 0.9 1.0 1.6 5=4 35 High Performance, Integrated Memory Module Product May 3, 2012 LDS-L9D364M64SBG2-G L9D364M64SBG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) ODT SENSITIVITY ,IHLWKHUWKHWHPSHUDWXUHRUYROWDJHFKDQJHVDIWHU,2FDOLEUDWLRQWKHWROHUDQFHOLPLWVOLVWHGLQ7DEOHFDQEHH[SHFWHGWRZLGHQDFFRUGLQJWR7DEOHVDQG TABLE 28: ODT SENSITIVITY DEFINITION Symbol RTT MIN 0.9 - dRTTG7[G5TTG9[>'9@ MAX UNITS 5=4 G5TTG7[>'7@G5TTG9[>'9@ TABLE 29 - ODT TEMPERATURE & VOLTAGE SENSITIVITY Change MIN MAX UNITS dRTTdT 0 1.5 0 dRTTdV 0 0.15 0 FIGURE 15 - ODT TIMING REFERENCE LOAD ODT TIMING DEFINITIONS 2'7ORDGLQJGLIIHUVIURPWKDWXVHGLQ$&WLPLQJPHDVXUHPHQWV7ZRSDUDPHWHUVGHILQHZKHQ2'7WXUQVRQRURIIV\QFKURQRXVO\WZRGHILQHZKHQ2'7 WXUQVRQRURII$V\QFKURQRXVO\DQGDQRWKHUGHILQHVZKHQ2'7WXUQVRQRU RIIG\QDPLFDOO\7DEOHRXWOLQHVDQGSURYLGHVGHILQLWLRQDQGPHDVXUHPHQW UHIHUHQFHVHWWLQJVIRUHDFKSDUDPHWHU DUT CK, CK# 2'7 WXUQRQ WLPH EHJLQV ZKHQ WKH RXWSXW OHDYHV +,*+= DQG 2'7 UHVLVWDQFHEHJLQVWRWXUQRQ2'7WXUQRIIWLPHEHJLQVZKHQWKHRXWSXWOHDYHV /2:=DQG2'7UHVLVWDQFHEHJLQVWRWXUQRII VREF DQ, DM DQS, DQS# ZQ VDDQ/2 RTT = 25Ω VTT = VSSQ Timing reference point RZQ = 240Ω VSSQ LOGIC Devices Incorporated www.logicdevices.com 36 High Performance, Integrated Memory Module Product May 3, 2012 LDS-L9D364M64SBG2-G L9D364M64SBG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) ODT TIMING DEFINITIONS TABLE 30: ODT TIMING DEFINITIONS Symbol PACKAGE OUTLINE DIMENSIONS End Point Definition Figure 5LVLQJHGJHRI&.&.?GHILQHGE\WKHHQGSRLQWRI2'7/RQ Begin Point Definition ([WUDSRODWHGSRLQWDW9VV4 )LJXUHRQSDJH tAOF 5LVLQJHGJHRI&.&.?GHILQHGE\WKHHQGSRLQWRI2'7/RII ([WUDSRODWHGSRLQWDW95TT_NORM )LJXUHRQSDJH tAONPD 5LVLQJHGJHRI&.&.?ZLWK2'7ILUVWEHLQJUHJLVWHUHG+,*+ ([WUDSRODWHGSRLQWDW9VV4 )LJXUHRQSDJH 5LVLQJHGJHRI&.&.?ZLWK2'7ILUVWEHLQJUHJLVWHUHG/2: ([WUDSRODWHGSRLQWDW95TT_NOM )LJXUHRQSDJH 5LVLQJHGJHRI&.&.?GHILQHGE\WKHHQGSRLQWRI2'7/&1: ([WUDSRODWHGSRLQWVDW95TTB:5DQG95TT_NOM )LJXUHRQSDJH tAON tAOFPD tADC 2'7/&:1RU2'7/&:1 TABLE 31: REFERENCE SETTINGS FOR ODT TIMING MEASUREMENTS PACKAGE OUTLINE DIMENSIONS Measured Parameter RTT_NORM Setting tAON tAOF tAONPD VSW1 VSW2 5=4: RTT_WR_Setting QD P9 P9 5=4: QD P9 P9 5=4: QD P9 P9 5=4: QD P9 P9 5=4: QD P9 P9 5=4: QD P9 P9 tAOFPD 5=4: QD P9 P9 5=4: QD P9 P9 tADC 5=4: 5=4: P9 P9 FIGURE 16 - tAON AND tAOF DEFINITIONS t AON t AOF Begin point: Rising edge of CK - CK# defined by the end point of ODTL off Begin point: Rising edge of CK - CK# defined by the end point of ODTL on CK CK VDDQ/2 CK# CK# t AON t AOF End point: Extrapolated point at VRTT_NOM TSW 2 VRTT_NOM TSW 1 TSW 1 TSW 1 VSW 2 DQ, DM DQS, DQS# VSS Q VSW 2 VSW 1 VSW 1 VSS Q End point: Extrapolated point at VSS Q LOGIC Devices Incorporated www.logicdevices.com High Performance, Integrated Memory Module Product May 3, 2012 LDS-L9D364M64SBG2-G L9D364M64SBG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) ODT CHARACTERISTICS FIGURE 17 - tAONPD AND tAOFPD DEFINITION t AONPD t AOFPD Begin point: Rising edge of CK - CK# with ODT first registered HIGH Begin point: Rising edge of CK - CK# with ODT first registered LOW CK CK VDD Q/2 CK# CK# t AONPD t AOFPD End point: Extrapolated point at VRTT_NOM VRTT_NOM TSW 2 TSW 2 TSW 1 TSW 1 VSW 2 VSW 2 DQ, DM DQS, DQS# VSW 1 VSW1 VSS Q VSS Q End point: Extrapolated point at VSS Q FIGURE 18 - tADC DEFINITION Begin point: Rising edge of CK - CK# defined by the end point of ODTLCNW Begin point: Rising edge of CK - CK# defined by the end point of ODTLCNW4 or ODTLCNW8 CK VDDQ/2 CK# t ADC VRTT_NOM DQ, DM DQS, DQS# End point: Extrapolated point at VRTT_NOM t ADC VRTT_NOM TSW 21 TSW 11 VSW 2 TSW 22 TSW 12 VSW 1 VRTT_WR End point: Extrapolated point at VRTT_WR VSS Q LOGIC Devices Incorporated www.logicdevices.com 38 High Performance, Integrated Memory Module Product May 3, 2012 LDS-L9D364M64SBG2-G L9D364M64SBG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) OUTPUT DRIVER IMPEDANCE FIGURE 19 - OUTPUT DRIVER 34 OHM OUTPUT DRIVER IMPEDANCE 7KH:GULYHU05>@ LVWKHGHIDXOWGULYHU8QOHVVRWKHUZLVHVWDWHG DOOWLPLQJVDQGVSHFLILFDWLRQVOLVWHGKHUHLQDSSO\WRWKH:GULYHURQO\,WV LPSHGDQFH 5ON LV GHILQHG E\ WKH YDOXH RI WKH H[WHUQDO UHIHUHQFH UHVLVWRU 5=4DVIROORZV5ON 5=4ZLWKQRPLQDO5=4 :DQGLVDFWXally 34.3:7KH:RXWSXWGULYHULPSHGDQFHFKDUDFWHULVWLFVDUHOLVWHG LQ7DEOH Chip in drive mode Output driver VDDQ IPU To other circuitry such as RCV, . . . RONPU DQ IOUT RONPD IPD VOUT VSSQ TABLE 32: 34: DRIVER IMPEDANCE CHARACTERISTICS MR1[5,1] RON RESISTOR RON34PD 0, 1 34.3: RON34PU Pull-Up/Pull-Down mismatch (MMPUPD) PACKAGE OUTLINE DIMENSIONS VOUT MIN TYP MAX UNITS NOTES 9DDQ 0.6 1.0 1.1 5=4 1 9DDQ 0.9 1.0 1.1 5=4 1 9DDQ 0.9 1.0 1.4 5=4 1 9DDQ 0.9 1.0 1.4 5=4 1 9DDQ 0.9 1.0 1.1 5=4 1 9DDQ 0.6 1.0 1.1 5=4 1 9DDQ -10 QD 10 % 1, 2 127(6 1. 7ROHUDQFHOLPLWVDVVXPH5=4RI:DQGDUHDSSOLFDEOHDIWHUSURSHU=4FDOLEUDWLRQKDVEHHQSHUIRUPHGDWDVWDEOHWHPSHUDWXUHDQGYROWDJH 9DD4 9DD9VV4 9VV5HIHUWRv2KPGULYHVHQVLWLYLW\wLIHLWKHUWKHWHPSHUDWXUHRUWKHYROWDJHFKDQJHVDIWHUFDOLEUDWLRQ 2. 0HDVXUHPHQWGHILQLWLRQIRUPLVPDWFKEHWZHHQSXOOXSDQGSXOOGRZQ00383'0HDUXUHERWK52138 and R213'DW[9DDQ: MM38' = R2138 - R213' RONNOM LOGIC Devices Incorporated www.logicdevices.com 39 High Performance, Integrated Memory Module Product May 3, 2012 LDS-L9D364M64SBG2-G L9D364M64SBG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) 34 OHM OUTPUT DRIVER IMPEDANCE 34 OHM DRIVER 7KH:GULYHUuVFXUUHQWUDQJHKDVEHHQFDOFXODWHGDQGVXPPDUL]HGLQ7DEOHIRU9DD 97DEOHIRU9DD 9DQG7DEOHIRU9DD 97KH LQGLYLGXDOSXOOXSDQGSXOOGRZQUHVLVWRUV5213'DQG52138DUHGHILQHGDVIROORZVZLWKWKH,PSHGDQFH&DOFXODWLRQVOLVWHGLQ7DEOH xRON3' 9287>,287@52138LVWXUQHGRII xRON38 9DD49287>,287@5213'LVWXUQHGRII TABLE 33: 34: DRIVER PULL-UP AND PULL-DOWN IMPEDANCE CALCULATIONS PACKAGE OUTLINE DIMENSIONS MR1[5,1] RON RON MIN RZQ = 240:±1% RZQ = (240:±1%)/7 RESISTOR RON34PD 0, 1 34.3: RON34PU TYP MAX UNITS 240 242.4 : 33.9 34.3 34.6 : VOUT MIN TYP MAX 9DDQ 2.04 34.3 38.1 UNITS : 9DDQ 30.5 34.3 38.1 : 9DDQ 30.5 34.3 48.5 : 9DDQ 30.5 34.3 48.5 : 9DDQ 30.5 34.3 38.1 : 9DDQ 20.4 34.3 38.1 : TABLE 34: 34: DRIVER IOH/IOL CHARACTERISTICS: VDD = VPDD Q = 1.5V ACKAGE OUTLINE DIMENSIONS MR1[5,1] RON RESISTOR RON34PD 0, 1 34.3: RON34PU VOUT MIN TYP MAX UNITS IOL#[9DDQ 8.8 P$ IOL#[9DDQ 24.6 21.9 P$ IOL#[9DDQ 39.3 35 24.8 P$ IOL#[9DDQ 39.3 35 24.8 P$ IOL#[9DDQ 24.6 21.9 P$ IOL#[9DDQ 8.8 P$ TABLE 35: 34: DRIVER IOH/IOL CHARACTERISTICS: VDD=VDD Q=1.575V PACKAGE OUTLINE DIMENSIONS MR1[5,1] RON RESISTOR RON34PD 0, 1 34.3: RON34PU LOGIC Devices Incorporated www.logicdevices.com VOUT MIN TYP IOL#[9DDQ 15.5 9.2 8.3 P$ IOL#[9DDQ 25.8 23 P$ IOL#[9DDQ 41.2 36.8 26 P$ IOL#[9DDQ 41.2 36.8 26 P$ IOL#[9DDQ 25.8 23 P$ IOL#[9DDQ 15.5 9.2 8.3 P$ 40 MAX UNITS High Performance, Integrated Memory Module Product May 3, 2012 LDS-L9D364M64SBG2-G L9D364M64SBG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) 34 OHM OUTPUT DRIVER IMPEDANCE TABLE 36: 34: DRIVER IOH/IOL CHARACTERISTICS: VDD=VDD Q=1.425V PACKAGE OUTLINE DIMENSIONS MR1[5,1] RON RESISTOR RON34PD 0, 1 34.3: RON34PU VOUT MIN TYP MAX UNITS IOL#[9DDQ 14 8.3 P$ IOL#[9DDQ 23.3 20.8 P$ IOL#[9DDQ 33.3 23.5 P$ IOL#[9DDQ 33.3 23.5 P$ IOL#[9DDQ 23.3 20.8 P$ IOL#[9DDQ 14 8.3 P$ 34: OUTPUT DRIVER SENSITIVITY ,IHLWKHUWKHWHPSHUDWXUHRUYROWDJHFKDQJHVDIWHU=4FDOLEUDWLRQWKHWROHUDQFHOLPLWVOLVWHGLQ7DEOHFDQEHH[SHFWHGWRZLGHQDFFRUGLQJWR7DEOHDQG TABLE 37: 34: OUTPUT DRIVER SENSITIVITY DEFINITION Symbol MIN MAX UNITS RON @ 0.8 x VDDQ 0.9 - dRONG7+[>'7@G5ONG9+[>'9@ 1.1 - dRONG7+[>'7@G5ONG9+[>'9@ 5=4 RON @ 0.5 x VDDQ 0.9 - dRONG70[>'7@G5ONG90[>'9@ 1.1 - dRONG70[>'7@G5ONG90[>'9@ 5=4 RON @ 0.2 x VDDQ 0.9 - dRONG7/[>'7@G5ONG9/[>'9@ 1.1 - dRONG7/[>'7@G5ONG9/[>'9@ 5=4 TABLE 38: 34: OUTPUT DRIVER VOLTAGE AND TEMPERATURE SENSITIVITY Change MIN MAX UNITS dRONdTM 0 1.5 & dRONdVM 0 0.13 P9 dRONdTL 0 1.5 & dRONdVL 0 0.13 P9 dRONdTH 0 1.5 & dRONdVH 0 0.13 P9 LOGIC Devices Incorporated www.logicdevices.com 41 High Performance, Integrated Memory Module Product May 3, 2012 LDS-L9D364M64SBG2-G L9D364M64SBG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) ALTERNATIVE 40 OHM DRIVER TABLE 39 - 40: DRIVER IMPEDANCE CHARACTERISTICS MR1[5,1] RON RESISTOR RON40PD 0, 1 40.0: RON40PU Pull-Up/Pull-Down mismatch (MMPUPD) PACKAGE OUTLINE DIMENSIONS VOUT MIN TYP MAX UNITS NOTES 9DDQ 0.6 1.0 1.1 5=4 1 9DDQ 0.9 1.0 1.1 5=4 1 9DDQ 0.9 1.0 1.4 5=4 1 9DDQ 0.9 1.0 1.4 5=4 1 9DDQ 0.9 1.0 1.1 5=4 1 9DDQ 0.6 1.0 1.1 5=4 1 9DDQ -10 QD 10 % 1, 2 127(6 1. 7ROHUDQFHOLPLWVDVVXPH5=4RI:DQGDUHDSSOLFDEOHDIWHUSURSHU=4FDOLEUDWLRQKDVEHHQSHUIRUPHGDWDVWDEOHWHPSHUDWXUHDQGYROWDJH 9DD4 9DD9VV4 9VV5HIHUWRv2KPGULYHVHQVLWLYLW\wLIHLWKHUWKHWHPSHUDWXUHRUWKHYROWDJHFKDQJHVDIWHUFDOLEUDWLRQ 2. 0HDVXUHPHQWGHILQLWLRQIRUPLVPDWFKEHWZHHQSXOOXSDQGSXOOGRZQ00383'0HDUXUHERWK5ON38DQG5ON3'DW[9DDQ: MM383' = R2138 - R213' [ RONNOM 40: OUTPUT DRIVER SENSITIVITY ,IHLWKHUWKHWHPSHUDWXUHRUYROWDJHFKDQJHVDIWHU,2FDOLEUDWLRQWKHWROHUDQFHOLPLWVOLVWHGLQ7DEOHFDQEHH[SHFWHGWRZLGHQDFFRUGLQJWR7DEOHDQG TABLE 40: 40: OUTPUT DRIVER SENSITIVITY DEFINITION Symbol MIN MAX UNITS RON @ 0.8 x VDDQ 0.9 - dRONG7+[>'7@G5ONG9+[>'9@ 1.1 - dRONG7+[>'7@G5ONG9+[>'9@ 5=4 RON @ 0.5 x VDDQ 0.9 - dRONG70[>'7@G5ONG90[>'9@ 1.1 - dRONG70[>'7@G5ONG90[>'9@ 5=4 RON @ 0.2 x VDDQ 0.9 - dRONG7/[>'7@G5ONG9/[>'9@ 1.1 - dRONG7/[>'7@G5ONG9/[>'9@ 5=4 LOGIC Devices Incorporated www.logicdevices.com 42 High Performance, Integrated Memory Module Product May 3, 2012 LDS-L9D364M64SBG2-G L9D364M64SBG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) ALTERNATIVE 40 OHM DRIVER TABLE 41: 40: OUTPUT DRIVER VOLTAGE AND TEMPERATURE SENSITIVITY Change MIN MAX dRONdTM 0 1.5 UNITS & dRONdVM 0 0.15 P9 dRONdTL 0 1.5 & dRONdVL 0 0.15 P9 dRONdTH 0 1.5 & dRONdVH 0 0.15 P9 OUTPUT CHARACTERISTICS AND OPERATING CONDITIONS 7KH6'5$0XVHVERWKVLQJOHHQGHGDQGGLIIHUHQWLDORXWSXWGULYHUV7KHVLQJOHHQGHGRXWSXWGULYHULVVXPPDUL]HGLQ7DEOHZKLOHWKHGLIIHUHQWLDORXWSXW GULYHULVVXPPDUL]HGLQ7DEOH TABLE 42: SINGLE-ENDED OUTPUT DRIVER CHARACTERISTICS PACKAGE OUTLINE DIMENSIONS Parameter/Condition Output leakage current:'4DUHGLVDEOHG Symbol MIN UNITS NOTES I2= -5 MAX 5 X$ 1 6546( 2.5 6 9QV 1, 2, 3, 4 9d9287d9DD42'7LVGLVDEOHG2'7LV+,*+ Output slew rate:6LQJOHHQGHGIRUULVLQJDQGIDOOLQJ HGJHVPHDVXUHEHWZHHQ9OL$& 95()[9DDQ DQG92+$& 95()[9DDQ Single-ended DC high-level output voltage 92+'& [9DDQ 9 1, 2, 5 Single-ended DC mid-point level output voltage 9OM'& [9DDQ 9 1, 2, 5 Single-ended DC low-point level output voltage 9OL'& [9DDQ 9 1, 2, 5 Single-ended DC high-point level output voltage 92+$& 977[9DDQ 9 1, 2, 3, 6 Single-ended DC low-point level output voltage 9OL$& 977[9DDQ 9 1, 2, 3, 6 Delta RON between pull-up and pull-down for DQ/DQS MM383' % Test load for AC timing and output slew rates -10 10 3 2XWSXWWR9TT9DD4YLD:UHVLVWRU 127(6 1. 5=4RI:ZLWK5=4HQDEOHGGHIDXOW:GULYHUDQGLVDSSOL- 5. 6HH7DEOHRQSDJH,9FXUYHOLQHDULW\'RQRWXVH$&7HVWORDG FDEOH DIWHU SURSHU =4 FDOLEUDWLRQ KDV EHHQ SHUIRUPHG DW D VWDEOH WHP- 6. 6HH7DEOHRQSDJHIRURXWSXWVOHZUDWH SHUDWXUHDQGYROWDJH9DD4 9DD9VV4 9VV 6HH7DEOHRQSDJHIRUDGGLWLRQDOLQIRUPDWLRQ 2. 9TT 9DD4 8. 6HH )LJXUH RQ SDJH IRU DQ H[DPSOH RI D VLQJOHHQGHG RXWSXW 3. 6HH)LJXUHRQSDJHIRUWKHWHVWORDGFRQILJXUDWLRQ 4. VLJQDO 7KH9QVPD[LPXPLVDSSOLFDEOHIRUDVLQJOH'4VLJQDOZKHQLWLVVZLWFKLQJIURPHLWKHU+,*+WR/2:RU/2:WR+,*+ZKLOHWKHUHPDLQLQJ'4 VLJQDOVLQWKHVDPHE\WHODQHDUHFRPELQDWLRQVWKHPD[LPXPOLPLWRI9 QVPD[LPXPLVUHGXFHGWR9QV LOGIC Devices Incorporated www.logicdevices.com 43 High Performance, Integrated Memory Module Product May 3, 2012 LDS-L9D364M64SBG2-G L9D364M64SBG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) TABLE 43: DIFFERENTIAL OUTPUT DRIVER CHARACTERISTICS PACKAGE OUTLINE DIMENSIONS Parameter/Condition Output leakage current:'4DUHGLVDEOHG Symbol MIN MAX UNITS NOTES I2= -5 5 X$ 1 SRQDIFF 5 12 9QV 1 92;$& 95()-150 95() P9 1, 2, 3 9d9287d9DD42'7LV+,*+ Output slew rate:'LIIHUHQWLDOIRUULVLQJDQGIDOOLQJHGJHV PHDVXUHEHWZHHQ9OL',))$& [9DD4DQG92+ $& [9DDQ Output differential cross-point voltage Differential high-level output voltage 92+',))$& [9DDQ 9 1, 4 Differential low-level output voltage 9OL',))$& [9DDQ 9 1, 4 % 1, 5 Delta RON between pull-up and pull-down for DQ/DQS MM383' -10 10 2XWSXWWR9TT9DD4YLD:UHVLVWRU Test load for AC timing and output slew rates 3 127(6 1. 5=4RI:ZLWK5=4HQDEOHGGHIDXOW:GULYHUDQGLVDSSOL- 4. 6HH7DEOHRQSDJHIRUWKHRXWSXWVOHZUDWH FDEOH DIWHU SURSHU =4 FDOLEUDWLRQ KDV EHHQ SHUIRUPHG DW D VWDEOH WHP- 5. 6HH7DEOHRQSDJHIRUDGGLWLRQDOLQIRUPDWLRQ SHUDWXUHDQGYROWDJH9DD4 9DD9VV4 9VV 6. 6HH)LJXUHRQSDJHIRUDQH[DPSOHRIDGLIIHUHQWLDORXWSXWVLJQDO 2. 95() 9DD4 3. 6HH)LJXUHRQSDJHIRUWKHWHVWORDGFRQILJXUDWLRQ FIGURE 20 - DQ OUTPUT SIGNAL MAX output VOH(AC) VOL(AC) MIN output LOGIC Devices Incorporated www.logicdevices.com 44 High Performance, Integrated Memory Module Product May 3, 2012 LDS-L9D364M64SBG2-G L9D364M64SBG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) OUTPUT CHARACTERISTICS AND OPERATING CONDITIONS FIGURE 21 - DIFFERENTIAL OUTPUT SIGNAL MAX output VOH(DIFF) X VOX(AC) MAX X X VOX(AC) MIN X VOL(DIFF) MIN output REFERENCE OUTPUT LOAD )LJXUHUHSUHVHQWVWKHHIIHFWLYHUHIHUHQFHORDGRI:XVHGLQGHILQLQJWKHUHOHYDQWGHYLFH$&WLPLQJSDUDPHWHUVH[FHSW2'7UHIHUHQFHWLPLQJDVZHOODVWKH RXWSXWVOHZUDWHPHDVXUHPHQWV,WLVQRWLQWHQGHGWREHDSUHFLVHUHSUHVHQWDWLRQRIDSDUWLFXODUV\VWHPHQYLURQPHQWRUDGHSLFWLRQRIWKHDFWXDOORDGSUHVHQWHG E\DQ\VSHFLILF,QGXVWU\WHVWV\VWHPDSSDUDWXV6\VWHPGHVLJQHUVVKRXOGXVH,%,6RURWKHUVLPXODWLRQWRROVWRFRUUHODWHWKHWLPLQJUHIHUHQFHORDGSUHVHQWHGRU H[KLELWHGRQWKHV\VWHPRUV\VWHPHQYLURQPHQW FIGURE 22 - REFERENCE OUTPUT LOAD FOR AC TIMING AND OUTPUT SLEW RATE DUT VREF DQ DQS DQS# VDDQ/2 RTT = 25Ω VTT = VDDQ/2 Timing Reference Point ZQ RZQ = 240Ω VSS LOGIC Devices Incorporated www.logicdevices.com 45 High Performance, Integrated Memory Module Product May 3, 2012 LDS-L9D364M64SBG2-G L9D364M64SBG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) SLEW RATE DEFINITIONS FOR SINGLE-ENDED OUTPUT SIGNALS 7KHVLQJOHHQGHGRXWSXWGULYHULVVXPPDUL]HGLQ7DEOH:LWKWKHUHIHUHQFHORDGIRUWLPLQJPHDVXUHPHQWVWKHRXWSXWVOHZUDWHIRUIDOOLQJDQGULVLQJHGJHV LVGHILQHGDQGPHDVXUHGEHWZHHQ9OL$&DQG92+$&IRUVLQJOHHQGHGVLJQDOVDVLQGLFDWHGLQ7DEOHDQG)LJXUH TABLE 44: SINGLE-ENDED OUTPUT SLEW RATE Measured Output Slew Rate (Linear Signals) Output PACKAGE OUTLINE DIMENSIONS Edge From To 5LVLQJ 9OL$& 92+$& Falling 92+$& 9OL$& Calculation 92+$&9OL $& '756( DQ 92+$&9OL$& '7)6( FIGURE 23 - NOMINAL SLEW RATE DEFINITION FOR SINGLE-ENDED OUTPUT SIGNALS ΔTRSE VOH(AC) VTT VOL(AC) ΔTFSE LOGIC Devices Incorporated www.logicdevices.com 46 High Performance, Integrated Memory Module Product May 3, 2012 LDS-L9D364M64SBG2-G L9D364M64SBG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) SLEW RATE DEFINITIONS FOR DIFFERENTIAL OUTPUT SIGNALS 7KHGLIIHUHQWLDORXWSXWGULYHULVVXPPDUL]HGLQ7DEOH:LWKWKHUHIHUHQFHORDGIRUWLPLQJPHDVXUHPHQWVWKHRXWSXWVOHZUDWHIRUIDOOLQJDQGULVLQJHGJHVLV GHILQHGDQGPHDVXUHGEHWZHHQ9OL$&DQG92+$&IRUGLIIHUHQWLDOVLJQDOVDVVKRZQLQ7DEOHDQG)LJXUH TABLE 45: DIFFERENTIAL OUTPUT SLEW RATE DEFINITION Measured Output Slew Rate (Linear Signals) Output PACKAGE OUTLINE DIMENSIONS Edge From To 5LVLQJ 9OL',))$& 92+',))$& Falling 92+',))$& 9OL',))$& Calculation 92+',))$&9OL ',))$& 'TRDIFF DQS, DQS\ 92+',))$&9OL',))$& 'TFDIFF FIGURE 24 - NOMINAL DIFFERENTIAL OUTPUT SLEW RATE DEFINITION FOR DQS, DQS# VOH(DIFF) AC 0 VOL(DIFF) AC ΔTFDIFF LOGIC Devices Incorporated www.logicdevices.com High Performance, Integrated Memory Module Product May 3, 2012 LDS-L9D364M64SBG2-G L9D364M64SBG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) TABLE 46: SPEED BINS PACKAGE OUTLINE DIMENSIONS ''5''5''5''5''5 >&:/ @>&:/ @>&:/ @>&:/ @>&:/ @ Parameter Symbol MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX UNITS NOTES t5&' 15 - 15 - 15 - 15 - 15 - QV 35(&+$5*(FRPPDQGSHULRG t53 15 - 15 - 15 - 15 - 15 - QV $&7,9$7(WR$&7,9$7(RU5()5(6+FRPPDQGSHULRG t5& 52.5 - 52.5 $&7,9$7(WRLQWHUQDO5($'RU:5,7(GHOD\WLPH $&7,9$7(WR35(&+$5*(FRPPDQGSHULRG &/ &/ &/ &/ t5$6 &:/ t&.$9* &:/ t&.$9* PV 3 3.3 3 - 51 - 51 - 51 - QV PV 36 PV 36 PV 36 PV QV 1 3.3 3 3.3 3 3.3 3 3.3 QV 2 QV 3 QV 3 QV 2 &:/ t&.$9* &:/ t&.$9* &:/ t&.$9* QV 3 &:/ t&.$9* QV 3 &:/ t&.$9* &:/ t&.$9* &:/ 2.5 3.3 2.5 3.3 2.5 3.3 2.5 3.3 2.5 3.3 QV 3 QV 2,3 t&.$9* QV 3 &:/ t&.$9* QV 3 &:/ t&.$9* &:/ t&.$9* 1.5 5,6 6XSSRUWHG&/6HWWLQJV 5, 6, 8 5, 6, 8, 10 6XSSRUWHG&:/6HWWLQJV 1.5 5, 6, 8, 10 QV 3 1.5 QV 2,3 5, 6, 8, 10 &. &. 127(6 1. t5(),GHSHQGVRQt23(5 2. 7KH &/ DQG &:/ VHWWLQJ UHVXOW LQ t&. UHTXLUHPHQWV :KHQ PDNLQJ D VHOHFWLRQRI t&.ERWK&/DQG&:/UHTXLUHPHQWVHWWLQJVQHHGWREHIXO- 3. 5HVHUYHGILOOHGEORFNVVHWWLQJVDUHQRWDOORZHG ILOOHG LOGIC Devices Incorporated www.logicdevices.com 48 High Performance, Integrated Memory Module Product May 3, 2012 LDS-L9D364M64SBG2-G LOGIC Devices Incorporated www.logicdevices.com 49 Cumulave error across Cycle-to-Cycle JITTER Clock absolute LOW pulse width Clock absolute HIGH pusle width 3 Cycles 4 Cycles 5 Cycles 6 Cycles 7 Cycles 8 Cycles 9 Cycles 10 Cycles 11 Cycles 12 Cycles 2 Cycles n = 13, 14 … 49, 50 Cycles DLL LOCKED DLL LOCKING Parameter TC = 0˚C to <85˚C TC = 85˚C to 105˚C TC = >105˚C to ≤125˚C Clock period average: DLL enable mode HIGH pulse width average LOW pulse width average DLL LOCKED Clock period JITTER DLL LOCKING Clock absolute period Clock period average: DLL disable mode t t CK (AVG) CKDLL_DIS ERR3PERR t ERRnPER ERR4PERR t ERR5PERR t ERR6PERR t ERR7PERR t ERR8PERR t ERR9PERR t ERR10PERR t ERR11PERR t ERR12PERR t t JITCC t JITCC, LCK t ERR2PERR t CL (ABS) CH (ABS) t t CH (AVG) t CL (AVG) t JITPER t JITPER, LCK t CLK (ABS) t Symbol -175 -194 -209 -222 -232 -241 -249 -257 -263 -269 -147 0.43 0.43 0.47 0.47 -100 -90 200 180 175 194 209 222 232 241 249 257 263 269 147 - - 0.53 0.53 100 90 -25 (DDR3-800) [CWL=2.5; 6-6-6] MIN MAX 8 7800 8 3900 8 2900 0.53 0.53 90 80 0.47 0.47 -80 -70 0.53 0.53 80 70 0.47 0.47 -70 -60 See SPEED BIN TABLE (#49) for tCK range allowed 0.53 0.53 70 60 -157 -175 -188 -200 -209 -217 -224 -231 -237 -242 -132 0.43 0.43 132 - 0.43 0.43 160 140 - 0.43 0.43 140 120 -103 -118 118 -122 157 -140 140 -136 175 -155 155 -147 188 -168 168 -155 200 -177 177 -163 209 -186 186 -169 217 -193 193 -175 224 -200 200 -180 231 -205 205 -184 237 -210 210 -188 242 -215 215 tERRnPER MIN = (1+0.68ln[n]) x tJITPER MIN tERRnPER MAX = (1+0.68ln[n]) x tJITPER MAX 180 160 - 122 136 147 155 163 169 175 180 184 188 103 - - MIN=tCK (AVG) MIN+tJITPER MIN; MAX=tCK (AVG)MAX+tJITPER MAX 0.47 0.47 -90 -80 -105 -117 -126 -133 -139 -145 -150 -154 -158 -161 -88 0.43 0.43 0.47 0.47 -60 -50 120 100 105 117 126 133 139 145 150 154 158 161 88 - - 0.53 0.53 60 50 -19 (DDR3-1066) -15 (DDR3-1333) -12 (DDR3-1600) -11 (DDR3-1866) [CWL=1.875; 8-8-8] [CWL=1.5; 10-10-10] [CWL=1.25; 11-11-11] [CWL=1.07; 13-13-13] MIN MAX MIN MAX MIN MAX MIN MAX 8 7800 8 7800 8 7800 8 7800 8 3900 8 3900 8 3900 8 3900 8 2900 8 2900 8 2900 8 2900 ps ps ps ps ps ps ps ps ps ps ps ps ps ps tCK (AVG) tCK (AVG) ns CK CK ps ps ps ns Units 17 17 17 17 17 17 17 17 17 17 17 16 16 17 15 14 10,11 12 12 13 13 Notes 9,42 9,42 9,42 L9D364M64SBG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) TABLE 47 (SHEET 1 OF 6) - ELECTRICAL CHARACTERISTICS AND AC OPERATING CONDITIONS High Performance, Integrated Memory Module Product May 3, 2012 LDS-L9D364M64SBG2-G LOGIC Devices Incorporated www.logicdevices.com 50 DQS, DQS\ DIFFERENTIAL READ postamble DQS, DQS\ DIFFERENTIAL Output HIGH me DQS, DQS\ DIFFERENTIAL Output LOW me DQS, DQS\ LOW-Z me (RL-1) DQS, DQS\ HIGH-Z me (RL+BL/2) DQS, DQS\ DIFFERENTIAL READ preamble DQS, DQS\ RISING to/from RISING CK, CK\ when DLL is disabled DQS, DQS\ RISING to/from RISING CK, CK\ DQS,DQS\ RISING to CK, CK\ RISING DQS, DQS\ DIFFERENTIAL Input Low pulse width DQS, DQS\ DIFFERENTIAL Input HIGH pulse width DQS, DQS\ FALLING Setup to CK, CK\ RISING DQS, DQS\ FALLING Hold from CK, CK\ RISING DQS, DQS\ DIFFERENTIAL WRITE preamble DQS, DQS\ DIFFERENTIAL WRITE postamble QH t RPST DQSCK t DQSK DLL_DIS t QSH t QSL t LZ (DQS) t HZ (DQS) t RPRE t DQSS DQSL t DQSH t DSS t DSH t WPRE t WPST t t HZ (DQ) t t DQSQ DIPW LZ (DQ) t t DH AC100 DS AC150 DS AC175 DQ HIGH-A me from CK, CK\ t t t t Base (specificaon) VREF @ 1V/ns Base (specificaon) VREF @ 1V/ns Base (specificaon) VREF @ 1V/ns Symbol DQ LOW-Z me from CK, CK\ DQ Output HOLD me from DQS, DQS\ DQS, DQS\ to DQ SKEW, per access Data HOLD me from DQS, DQS\ Minimum Data Pulse Width Data SETUP me to DQS, DQS\ Data SETUP me to DQS, DQS\ Parameter 400 -600 0.38 0.3 0.38 0.38 -800 0.9 1 Note 27 400 400 Note 24 10 0.3 0.38 0.38 -600 0.9 1 400 DQ Strobe Input Timing -0.25 0.25 -0.25 0.45 0.55 0.45 0.45 0.55 0.45 0.2 0.2 0.2 0.2 0.9 0.9 0.3 0.3 DQ Strobe Output Timing -400 400 -300 - -800 0.38 Note 27 300 300 Note 24 10 300 0.25 0.55 0.55 - 300 300 - 0.3 0.4 0.4 -500 0.9 1 -255 -0.25 0.45 0.45 0.2 0.2 0.9 0.3 - -500 0.38 Note 27 250 250 Note 24 10 255 0.25 0.55 0.55 - 250 250 - 225 225 Note 24 0.4 0.4 -450 0.9 Note 27 10 0.3 225 1 0.27 0.55 0.55 - 225 225 - -225 -0.27 0.45 0.45 0.18 0.18 0.9 0.3 - -450 0.38 0.3 0.4 0.4 -390 0.9 1 -195 -0.27 0.45 0.45 0.18 0.18 0.9 0.3 - -390 0.38 Note 27 195 195 Note 24 10 195 0.27 0.55 0.55 - 190 190 - -12 (DDR3-1600) -11 (DDR3-1866) -25 (DDR3-800) -19 (DDR3-1066) -15 (DDR3-1333) [CWL=1.875; 8-8-8] [CWL=1.5; 10-10-10] [CWL=1.25; 11-11-11] [CWL=1.07; 13-13-13] [CWL=2.5; 6-6-6] MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX DQ Input Timing 65 75 25 200 250 200 10 150 125 75 30 160 275 275 250 180 45 100 150 100 65 145 200 250 200 165 360 535 600 490 400 DQ Output Timing 85 100 200 150 125 CK CK CK ps ps CK ns ps CK CK CK CK CK CK CK ps ps tCK (AVG) ps ps ps ps ps ps ps ps Units 23,27 21 21 22,23 22,23 23,24 26 23 25 25 25 22,23 22,23 21 18,19 19,20 18,19 19,20 18,19 19,20 41 Notes L9D364M64SBG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) TABLE 47 (SHEET 2 OF 6) - ELECTRICAL CHARACTERISTICS AND AC OPERATING CONDITIONS High Performance, Integrated Memory Module Product May 3, 2012 LDS-L9D364M64SBG2-G LOGIC Devices Incorporated www.logicdevices.com 51 2KB page size 1KB page size RRD MULTIPURPOSE REGISTER READ burst end to mode register set for mulpurpose register exit t MPRR MOD MRD t MODE REGISTER SET command cycle me MODE REGISTER SET command update delay DAL RTP t CCD t t - - 30 40 MIN=greater of 4CK or 7.5ns MIN = 15ns; MAX = n/a 30 45 MIN = 1CK; MAX = n/a MIN = 4CK; MAX = n/a MIN = greater of 12CK or 15ns; MAX = n/a MIN = WR + tRP/tCK (AVG); MAX = n/a MIN = greater of 4CK or 7.5ns; MAX = n/a 37.5 50 MIN = greater of 4CK or 7.5ns; MAX = n/a MIN = 4CK; MAX = n/a - MIN=greater of 4CK or 10ns WTR WR 40 50 - 512 512 45 65 220 240 170 190 320 340 120 140 220 240 560 620 See "Speed Bin Table (#49) for tRCD See "Speed Bin Table (#49) for tRP See "Speed Bin Table (#49) for tRAS See "Speed Bin Table (#49) for tRC MIN=greater of 4CK MIN=greater of 4CK MIN=greater of 4CK MIN=greater of 4CK or 6ns or 10ns or 7.5ns or 6ns 512 125 300 275 425 200 300 780 - MIN=greater of 4CK or 5ns MIN=greater of 4CK or 6ns 25 35 - 512 65 200 150 275 100 200 535 -12 (DDR3-1600) -11 (DDR3-1866) -19 (DDR3-1066) -15 (DDR3-1333) [CWL=1.875; 8-8-8] [CWL=1.5; 10-10-10] [CWL=1.25; 11-11-11] [CWL=1.07; 13-13-13] MIN MAX MIN MAX MIN MAX MIN MAX t t FAW t t t RCD t RP t RAS t RCD t Auto precharge WRITE recovery + PRECHARGE me Delay from start of internal WRITE transacon to internal READ command READ-to-PRECHARE me CAS\-to-CAS\ command delay WRITE recovery me Four ACTIVATE windows for 1KB page size Four ACTIVATE windows for 2KB page size ACTIVATE-to-ACTIVATE minimum command period DLL Locking me Base (specificaon) CTRL, CMD, ADDR setup to CK, VREF @ 1V/ns CK\ Base (specificaon) CTRL, CMD, ADDR setup to CK, VREF @ 1V/ns CK\ Base (specificaon) CTRL, CMD, ADDR hold to CK, VREF @ 1V/ns CK\ Minimum CTRL, CMD, ADDR pulse width ACTIVATE to Internal READ or WRITE delay PRECHARGE command period ACTIVATE-to-PRECHARGE command period ACTIVATE-to-ACTIVATE command period Parameter -25 (DDR3-800) [CWL=2.5; 6-6-6] Symbol MIN MAX Command and Address Timing t 512 DLLK 200 t IS AC175 375 350 t IS AC150 500 275 t IH DC100 375 t 900 IPW CK CK CK CK CK CK CK CK ns ns CK CK CK ps ps ps ps ps ps ps ns ns ns ns Units 31,34 31,32,33 31 31 31 31 28 29,30 20,30 29,30 20,30 29,30 20,30 41 31 31 31,32 31 Notes L9D364M64SBG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) TABLE 47 (SHEET 3 OF 6) - ELECTRICAL CHARACTERISTICS AND AC OPERATING CONDITIONS High Performance, Integrated Memory Module Product May 3, 2012 LDS-L9D364M64SBG2-G LOGIC Devices Incorporated www.logicdevices.com 52 Valid clocks before SELF REFRESH exit, POWER-DOWN exit, or RESET exit Valid clocks aer SELF REFRESH entry or POWER-DOWN entry MINIMUM CKE LOW pulse width for SELF REFRESH entry to SELF REFRESH exit ming EXIT SELF REFRESH TO commands requiring a locked DLL Exit SELF REFRESH TO commands not requiring a locked DLL Maximum REFRESH period/interval Maximum REFRESH period TC ≤ 85˚C TC >85˚C ≤ 105˚C TC >105˚C ≤ 125˚C TC ≤ 85˚C TC >85˚C ≤ 105˚C TC >105˚C ≤ 125˚C REFRESH-to-ACTIVATE or REFRESH command period RESET\ LOW to power supplies stable RESET\ LOW to I/O and RTT HIGH-Z Begin power supply ramp to power supplies stable Exit RESET from CKE HIGH to a valid command Normal operaon POWER-UP and RESET operaon ZQCS command: Short Calibraon Time ZQCL command: Long Calibraon me Parameter t ZQINIT t XPR t t XS REFI - RFC CKSRE CKESR XSDLL t t CKSRX t t RPS IOZ t t VDDPR t t ZQOPER t ZQCS t Symbol - 512 - 512 - 512 - ms ns ms CK CK CK CK MIN = greater of 5CK or 10ns; MAX = n/a MIN = greater of 5CK or 10ns; MAX = n/a MIN = CKE (MIN) + CK; MAX = n/a t MIN = DLLK (MIN); MAX = n/a t CK CK CK CK CK ns - - ms ms ms μs μs μs 256 64 512 64 (1X) 32 (2X) 24 7.8 3.9 2.9 - Units MIN = 110; MAX = 9 x tREFI MIN = greater of 5CK or tRFC + 10ns; MAX = n/a SELF REFRESH Timing REFRESH Timing MIN = 0; MAX = 200 MIN = n/a; MAX = 200 MIN = n/a; MAX = 200 256 256 256 256 64 64 64 64 Inializaon and RESET Timing MIN = greater of 5CK or tRFC + 10ns; MAX = n/a 512 -25 (DDR3-800) -19 (DDR3-1066) -15 (DDR3-1333) -12 (DDR3-1600) -11 (DDR3-1866) [CWL=2.5; 6-6-6] [CWL=1.875; 8-8-8] [CWL=1.5; 10-10-10] [CWL=1.25; 11-11-11] [CWL=1.07; 13-13-13] MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX Calibraon Timing 28 36 36 36 36 36 36 35 Notes L9D364M64SBG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) TABLE 47 (SHEET 4 OF 6) - ELECTRICAL CHARACTERISTICS AND AC OPERATING CONDITIONS High Performance, Integrated Memory Module Product May 3, 2012 LDS-L9D364M64SBG2-G LOGIC Devices Incorporated www.logicdevices.com 53 XP XPDLL t t MIN = Greater of 10CK or 24ns; MAX = n/a MIN = Greater of 3CK or 6.0ns; MAX = n/a MIN = WL + 2 + WR + 1 CK CK CK CK CK MIN = WL + 4 + WR + 1 CK CK CK CK CK CK MIN = WL + 4 + WR/ CK (AVG) t MIN = 2 MIN = 2 CK MIN = WL + 2 + tWR/tCK (AVG) t MIN = RL + 4 + 1 MIN = tMOD (MIN) MIN = 1 MIN = 1 MIN = 1 ANPD + XPDLL t CK t Greater of tANPD or tRFC - REFRESH command to CKE LOW me CK CK CK CK MIN = 2 Greater of 3CK or 5ns Units WL - 1CK Greater of 3CK or Greater of 3CK or 5.625ns 5ns MIN = 1; MAX = n/a MIN = tCKE (MIN); MAX = 60ms Greater of 3CK or 5.625ns -19 (DDR3-1066) -15 (DDR3-1333) -12 (DDR3-1600) -11 (DDR3-1866) [CWL=1.875; 8-8-8] [CWL=1.5; 10-10-10] [CWL=1.25; 11-11-11] [CWL=1.07; 13-13-13] MIN MAX MIN MAX MIN MAX MIN MAX MIN = Greater of 3CK or 7.5ns; MAX = n/a WRAPDEN POWER-DOWN Exit Timing t BC4MRS WRPDEN WRPDEN RDPDEN WRAPDEN BC4MRS t t BL8 (OTF, MRS) BC4OTF BL8 (OTF, MRS) BC4OTF t DLL on, any valid command, or DLL off to commands not requiring DLL locked PRECHARGE POWER-DOWN with DLL off to command requiring DLL locked WRITE with AUTO PRECHARGE command to POWER-DOWN entry WRITE Command to POWERDOWN entry t READ/READ with AUTO PRECHARGE commant to POWER-DOWN entry REFPDEN t MRSPDEN t REFRESH command to POWER-DOWN entry MRS command to POWER-DOWN entry PRPDEN ACTPDEN t t PRECHARGE/PRECHARGE ALL command to POWER-DOWN entry ACTIVATE command to POWER-DOWN entry PDX POWER-DOWN Entry MINIMUM Timing POWER-DOWN exit period: ODT either synchronous or asynchronous ANPD PDE t POWER-DOWN entry period: ODT eher synchronous or asynchronous Begin POWER-DOWN period prior to CKE registered HIGH Command pass disable delay POWER-DOWN entry to POWER-DOWN exit ming CKE MIN pulse width Parameter -25 (DDR3-800) [CWL=2.5; 6-6-6] Symbol MIN MAX POWER-DOWN Timing Greater of 3CK or t CKE (MIN) 7.5ns t CPDED t PD 28 37 Notes L9D364M64SBG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) TABLE 47 (SHEET 5 OF 6) - ELECTRICAL CHARACTERISTICS AND AC OPERATING CONDITIONS High Performance, Integrated Memory Module Product May 3, 2012 LDS-L9D364M64SBG2-G LOGIC Devices Incorporated www.logicdevices.com 54 First DQS, DQS\ RISING edge DQS; DQS\ delay WRITE Leveling SETUP from rising CK, CK\ crossing to rising DQS, DQS\ crossing WRITE Leveling HOLD from rising DQS, DQS\ crossing to rising CK, CK\ crossing WRITE Leveling output delay WRITE Leveling output error RTT_NOM-to=RTT_WR change skew RTT_WR-to-RTT_NOM change skew - BC4 RTT_WR-to-RTT_NOM change skew - BC8 RTT dynamic change skew ODT HIGH me without WRITE command or with WRITE command and BC8 ODT HIGH me without WRITE command or with WRITE command and BC4 Asynchronous RTT TURN-OFF delay (POWER-DOWN with DLL OFF) Asynchronous RTT TURN-ON delay (POWER-DOWN with DLL OFF) t -300 0.3 250 0.7 MIN = 2; MAX = 8.5 MIN = 2; MAX = 8.5 -250 0.3 WLH WLO t WLOE t t WLS 0 0 325 325 40 25 t WLMRD WLDQSEN t 0.3 ADC t 9 2 - - 0 0 245 245 0.7 0.3 WRITE Leveling Timing 40 25 9 2 - - - 0 0 195 195 40 25 9 2 - - - WL - 2CK 4CK + ODTL OFF 6CK + ODTL OFF 0.3 0.7 MIN = 4; MAX = n/a 0.7 300 0.7 ODTH4 Dynamic ODT Timing 400 0.7 MIN = 6; MAX = n/a -400 0.3 ODTH8 AOFPD ODTLCNW ODTLCNW4 ODTLCNW8 t AONPD t t AON AOF ODTL on ODTL off RTT synchronous TURN-ON delay RTT synchronous TURN-OFF delay RTT TURN-ON from ODTL ON reference RTT TURN-OFF from ODTL OFF reference t Symbol Parameter 0 0 165 165 40 25 0.3 -225 0.3 7.5 2 - - - 0.7 225 0.7 0 0 140 140 40 25 0.3 -195 0.3 7.5 2 - - - 0.7 195 0.7 -25 (DDR3-800) -19 (DDR3-1066) -15 (DDR3-1333) -12 (DDR3-1600) -11 (DDR3-1866) [CWL=2.5; 6-6-6] [CWL=1.875; 8-8-8] [CWL=1.5; 10-10-10] [CWL=1.25; 11-11-11] [CWL=1.07; 13-13-13] MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX ODT Timing ns ns ps ps CK CK CK CK CK CK CK CK ns ns CK CK ps CK Units 39 40 38 38 40 23,38 39,40 Notes L9D364M64SBG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) TABLE 47 (SHEET 6 OF 6) - ELECTRICAL CHARACTERISTICS AND AC OPERATING CONDITIONS High Performance, Integrated Memory Module Product May 3, 2012 LDS-L9D364M64SBG2-G L9D364M64SBG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) NOTES 1. 3DUDPHWHUVDUHDSSOLFDEOHZLWK&d T$ d&DQG9DD9DD4 99 2. $OOYROWDJHVDUHUHIHUHQFHGWR9VV 3. 2XWSXWWLPLQJVDUHRQO\YDOLGIRU5ONRXWSXWEXIIHUVHOHFWLRQ 4. 8QLW t&. $9* UHSUHVHQWV WKH DFWXDO t&. $9* RI WKH LQSXW FORFN XQGHURSHUDWLRQ8QLW&.UHSUHVHQWVRQHFORFNF\FOHRIWKHLQSXWFORFN FRXQWLQJWKHDFWXDOFORFNHGJHV 5. 6. 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VIH(AC) = VREF(DC) + 175mV, VIL(AC) = VREF(DC) - 175mV CMD/ADDR Slew Rate V/ns CK, CK\ Differential Slew Rate 4.0V/ns 3.0V/ns 2.0V/ns 1.8V/ns 1.6V/ns 1.4V/ns 1.2V/ns 1.0V/ns 'tIS 'tIH 'tIS 'tIH 'tIS 'tIH 'tIS 'tIH 'tIS 'tIH 'tIS 'tIH 'tIS 'tIH 'tIS 'tIH 2.0 88 50 88 50 88 50 96 58 96 66 112 120 84 128 100 1.5 59 34 50 34 59 34 42 50 83 58 91 68 99 84 1.0 0 0 0 0 0 0 8 8 8 16 24 24 32 34 40 50 0.9 -2 -4 -2 -4 -2 -4 6 4 6 12 22 20 30 30 38 46 0.8 -6 -10 -6 -10 -6 -10 2 -2 2 6 18 14 26 24 34 40 -11 -16 -11 -16 -11 -16 -3 -8 -3 0 13 8 21 18 29 34 0.6 -26 -26 -26 -9 -18 -9 -10 -2 15 8 23 24 0.5 -35 -40 -35 -40 -35 -40 -32 -24 -11 -16 -2 -6 5 10 0.4 -62 -60 -62 -60 -62 -60 -54 -52 -54 -44 -38 -36 -30 -26 -22 -10 LOGIC Devices Incorporated www.logicdevices.com High Performance, Integrated Memory Module Product May 3, 2012 LDS-L9D364M64SBG2-G L9D364M64SBG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) TABLE 50: DERATING VALUES FOR tIS/tIH – AC150/DC100-BASED Shaded cells indicate slew-rate combinations not supported 'tIS, 'tIH Derating (ps) - AC/DC-Based, AC150 Threshold; VIH(AC) = VREF(DC) + 150mV, VIL(AC) = VREF(DC) - 150mV CMD/ADDR Slew Rate V/ns CK, CK\ Differential Slew Rate 4.0V/ns 3.0V/ns 2.0V/ns 1.8V/ns 1.6V/ns 1.4V/ns 1.2V/ns 1.0V/ns 'tIS 'tIH 'tIS 'tIH 'tIS 'tIH 'tIS 'tIH 'tIS 'tIH 'tIS 'tIH 'tIS 'tIH 'tIS 'tIH 2.0 50 50 50 83 58 91 66 99 84 115 100 1.5 50 34 50 34 50 34 58 42 66 50 58 82 68 90 84 1.0 0 0 0 0 0 0 8 8 16 16 24 24 32 34 40 50 0.9 0 -4 0 -4 0 -4 8 4 16 12 24 20 32 30 40 46 0.8 0 -10 0 -10 0 -10 8 -2 16 6 24 14 32 24 40 40 0 -16 0 -16 0 -16 8 -8 16 0 24 8 32 18 40 34 0.6 -1 -26 -1 -26 -1 -26 -18 15 -10 23 -2 31 8 39 24 0.5 -10 -40 -10 -40 -10 -40 -2 -32 6 -24 14 -16 22 -6 30 10 0.4 -25 -60 -25 -60 -25 -60 -52 -9 -44 -1 -36 -26 15 -10 TABLE 51: MINIMUM REQUIRED TIME tVAC ABOVE VIH(AC) FOR A VALID TRANSITION Below VIL(AC) tVAC Slew Rate (V/ns) at 175mV(ps) tVAC at 150mV(ps) >2.0 2.0 1.5 50 1.0 38 163 0.9 34 162 0.8 29 161 22 159 0.6 13 155 0.5 0 150 0 150 LOGIC Devices Incorporated www.logicdevices.com 58 High Performance, Integrated Memory Module Product May 3, 2012 LDS-L9D364M64SBG2-G L9D364M64SBG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) FIGURE 25 - NOMINAL SLEW RATE AND tVAC FOR tIS (COMMAND AND ADDRESS – CLOCK) t IS t IH t IS t IH CK CK# DQS# DQS VDDQ t VAC VIH(AC) MIN VREF to AC region VIH(DC) MIN Nominal slew rate VREF(DC) Nominal slew rate VIL(DC) MAX VREF to AC region VIL(DC) MAX t VAC VSS ∆TF Setup slew rate falling signal ∆TR VREF(DC) - VIL(AC) MAX Setup slew rate risin g signal = ∆TF Notes: LOGIC Devices Incorporated VIH(AC) MIN - V REF(DC) = ∆TR 1. Both the clock and the strobe are drawn on different time scales. www.logicdevices.com 59 High Performance, Integrated Memory Module Product May 3, 2012 LDS-L9D364M64SBG2-G L9D364M64SBG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) FIGURE 26 - NOMINAL SLEW RATE FOR tIH (COMMAND AND ADDRESS – CLOCK) t IS t IH t IS t IH CK CK# DQS# DQS VDDQ VIH(AC) MIN VIH(DC) MIN Nominal slew rate DC to V REF region VREF(DC) Nominal slew rate DC to V REF region VIL(DC) MAX VIL(AC) MAX VSS ∆TF ∆TR Hol d slew rate = rising signal VREF(DC) - VIL(DC) MAX Hol d slew rate falling signal = ∆TR Notes: LOGIC Devices Incorporated www.logicdevices.com VIH(DC) MIN - V REF(DC) ∆TF 1. Both the clock and the strobe are drawn on different time scales. 60 High Performance, Integrated Memory Module Product May 3, 2012 LDS-L9D364M64SBG2-G L9D364M64SBG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) FIGURE 27 - TANGENT LINE FOR tIS (COMMAND AND ADDRESS – CLOCK) t IS t IH t IS t IH CK CK# DQS# DQS VDDQ t VAC Nominal line VIH(AC) MIN VREF to AC region VIH(DC) MIN Tangent line VREF(DC) Tangent line VIL(DC) MAX VREF to AC region VIL(AC) MAX Nominal line t VAC ∆TR VSS Setup slew rate rising signal = ∆TF Notes: LOGIC Devices Incorporated Tangent line (V IH [ DC] MIN - VREF[ DC ]) ∆TR Tangent line (VREF [ DC] - V IL[ AC] MAX) Setup slew rate falling signal = ∆TF 1. Both the clock and the strobe are drawn on different time scales. www.logicdevices.com 61 High Performance, Integrated Memory Module Product May 3, 2012 LDS-L9D364M64SBG2-G L9D364M64SBG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) FIGURE 28 - TANGENT LINE FOR tIH (COMMAND AND ADDRESS – CLOCK) t IS t IH t IS t IH CK CK# DQS # DQS VDDQ VIH(AC) MIN Nominal line VIH(DC) MIN DC to V REF region Tangent line VREF(DC) DC to V REF region Tangent line Nominal line VIL( DC) MAX VIL( AC) MAX VSS ∆TR ∆TR Hol d slew rate rising signal = Tangent line (V REF [ DC] - V IL[ DC] MAX) Hol d slew rate falling signal = Tangent line (V IH [ DC] MIN - VREF[ DC]) ∆TR ∆TF Notes: LOGIC Devices Incorporated 1. Both the clock and the strobe are drawn on different time scales. www.logicdevices.com 62 High Performance, Integrated Memory Module Product May 3, 2012 LDS-L9D364M64SBG2-G L9D364M64SBG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) DATA SETUP, HOLD AND DERATING 7KHWRWDO t'6VHWXSWLPHDQGt'+KROGWLPHUHTXLUHGLVFDOFXODWHGE\DGGLQJWKHGDWDVKHHWt'6EDVHDQGt'+EDVHYDOXHVVHH7DEOHWRWKH'tDS and 't'+GHUDWLQJYDOXHVVHH7DEOHUHVSHFWLYHO\ $OWKRXJKWKHWRWDOVHWXSWLPHIRUVORZVOHZUDWHVPLJKWEHQHJDWLYHDYDOLGLQSXWVLJQDOLVVWLOOUHTXLUHGWRFRPSOHWHWKHWUDQVLWLRQDQGWRUHDFK9,+9IL$&)RU VOHZUDWHVZKLFKIDOOEHWZHHQWKHYDOXHVOLVWHGLQ7DEOHWKHGHUDWLQJYDOXHVPD\EHREWDLQHGE\OLQHDULQWHUSRODWLRQ 6HWXSt'6QRPLQDOVOHZUDWHIRUDULVLQJVLJQDOLVGHILQHGDVWKHVOHZUDWHEHWZHHQWKHODVWFURVVLQJRI95()'&DQGWKHILUVWFURVVLQJRI9,+$&0,16HWXS t'6QRPLQDOVOHZUDWHIRUDIDOOLQJVLJQDOLVGHILQHGDVWKHVOHZUDWHEHWZHHQWKHODVWFURVVLQJRI95()'&DQGWKHILUVWFURVVLQJRI9IL$&0$;,IWKHDFWXDO VLJQDOLVDOZD\VHDUOLHUWKDQWKHQRPLQDOVOHZUDWHOLQHEHWZHHQWKHVKDGHGv95()'&WR$&UHJLRQwXVHWKHQRPLQDOVOHZUDWHGHUDWLQJYDOXHVHH)LJXUH ,IWKHDFWXDOVLJQDOLVODWHUWKDQWKHQRPLQDOVOHZUDWHOLQHDQ\ZKHUHEHWZHHQWKHVKDGHGv95()'&WR$&UHJLRQwWKHVOHZUDWHRIDWDQJHQWOLQHWRWKHDFWXDO VLJQDOIURPWKH$&OHYHOWRWKH'&OHYHOLVXVHGIRUWKHGHUDWLQJYDOXHVHH)LJXUH +ROGt'+QRPLQDOVOHZUDWHIRUDULVLQJVLJQDOLVGHILQHGDVWKHVOHZUDWHEHWZHHQWKHODVWFURVVLQJRI9IL'&0$;DQGWKHILUVWFURVVLQJRI95()'&+ROG t'+QRPLQDOVOHZUDWHIRUDIDOOLQJVLJQDOLVGHILQHGDVWKHVOHZUDWHEHWZHHQWKHODVWFURVVLQJRI9,+'&0,1DQGWKHILUVWFURVVLQJRI95()'&,IWKHDFWXDO VLJQDOLVDOZD\VODWHUWKDQWKHQRPLQDOVOHZUDWHOLQHEHWZHHQWKHVKDGHGv'&WR95()'&UHJLRQwXVHWKHQRPLQDOVOHZUDWHIRUGHUDWLQJYDOXHVHH)LJXUH ,IWKHDFWXDOVLJQDOLVHDUOLHUWKDQWKHQRPLQDOVOHZUDWHOLQHDQ\ZKHUHEHWZHHQWKHVKDGHGv'&WR95()'&UHJLRQwWKHVOHZUDWHRIDWDQJHQWOLQHWRWKH DFWXDOVLJQDOIURPWKHv'&WR95()'&UHJLRQwLVXVHGIRUWKHGHUDWLQJYDOXHVHH)LJXUH TABLE 52: DATA SETUP AND HOLD VALUES AT 1V/NS (DQSX, DQSX\ AT 2V/NS) - AC/DC BASED DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600 DDR3-1866 UNITS REFERENCE tDS(base)AC175 Symbol 25 - - - SV 9,+$&9IL$& tDS(base)AC175 150 100 - - - SV 9,+$&9IL$& tDS(base)DC150 - - 30 10 10 SV 9,+$&9IL$& tDS(base)DC150 - - 65 45 45 SV 9,+$&9IL$& TABLE 53: DERATING VALUE FOR tDS/tDH – AC175/DC100 - BASED Shaded cells indicate slew-rate combinations not supported ǻtDS, ǻtDH Derating (ps) – AC175/D100-Based DQ Slew Rate V/ns DQS, DQS# Differential Slew Rate 4.0V/ns 3.0V/ns 2.0V/ns 1.8V/ns 2.0 88 50 88 50 88 50 1.5 59 34 59 34 59 34 42 1.0 0 0 0.9 0.8 1.4V/ns 1.2V/ns 1.0V/ns 0 0 0 0 8 8 16 16 -2 -4 -2 -4 6 4 14 12 22 20 -6 -10 2 -2 10 6 18 14 26 24 -3 -8 5 0 13 8 21 18 29 34 -1 -10 -2 15 8 23 24 -11 -16 -2 -6 5 10 -30 -26 -22 -10 0.6 0.5 0.4 LOGIC Devices Incorporated 1.6V/ns 'tDS 'tDH 'tDS 'tDH 'tDS 'tDH 'tDS 'tDH 'tDS 'tDH 'tDS 'tDH 'tDS 'tDH 'tDS 'tDH www.logicdevices.com 63 High Performance, Integrated Memory Module Product May 3, 2012 LDS-L9D364M64SBG2-G L9D364M64SBG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) TABLE 54: DERATING VALUE FOR tDS/tDH – AC150/DC100 - BASED Shaded cells indicate slew-rate combinations not supported ǻtDS, ǻtDH Derating (ps) – AC150/DC100-Based DQ Slew Rate V/ns DQS, DQS# Differential Slew Rate 4.0V/ns 3.0V/ns 2.0V/ns 1.8V/ns 1.6V/ns 1.4V/ns 1.2V/ns 1.0V/ns 'tDS 'tDH 'tDS 'tDH 'tDS 'tDH 'tDS 'tDH 'tDS 'tDH 'tDS 'tDH 'tDS 'tDH 'tDS 'tDH 2.0 50 50 50 1.5 50 34 50 34 50 34 58 42 1.0 0 0 0 0 0 0 8 8 16 16 0 -4 0 -4 8 4 16 12 24 20 0 -10 8 -2 16 6 24 14 32 24 8 -8 16 0 24 8 32 18 40 34 15 -10 23 -2 31 8 39 24 14 -16 22 -6 30 10 -26 15 -10 0.9 0.8 0.6 0.5 0.4 TABLE 55: REQUIRED TIME tVAC ABOVE VIH(AC) (BELOW VIL[AC]) FOR A VALID TRANSITION tVAC Slew Rate (V/ns) at 175mV(ps) [MIN] tVAC at 150mV(ps) [MIN] >2.0 2.0 1.5 50 1.0 38 163 0.9 34 162 0.8 29 161 22 159 0.6 13 155 0.5 0 150 0 150 LOGIC Devices Incorporated www.logicdevices.com 64 High Performance, Integrated Memory Module Product May 3, 2012 LDS-L9D364M64SBG2-G L9D364M64SBG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) FIGURE 29 - NOMINAL SLEW RATE AND tVAC FOR tDS (DQ – STROBE) CK CK# DQS# DQS t DS t DH t DS t DH VDDQ t VAC VIH(AC) MIN VREF to AC region VIH(DC) MIN Nominal slew rate VREF(DC) Nominal slew rate VIL(DC) MAX VREF to AC region VIL(AC) MAX t VAC VSS ∆TF Setup slew rate = rising signal Notes: LOGIC Devices Incorporated ∆TR VREF(DC) - VIL(AC) MAX ∆TF Setup slew rate = rising signal VIH(AC) MIN - VREF (DC) ∆TR 1. Both the clock and the strobe are drawn on different time scales. www.logicdevices.com 65 High Performance, Integrated Memory Module Product May 3, 2012 LDS-L9D364M64SBG2-G L9D364M64SBG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) FIGURE 30 - NOMINAL SLEW RATE FOR tDH (DQ – STROBE) CK CK# DQS# DQS t DS t DH t DS t DH VDDQ VIH(AC) MIN VIH(DC) MIN Nominal slew rate DC to V REF region VREF(DC) Nominal slew rate DC to V REF region VIL(DC) MAX VIL(AC) MAX VSS ∆TF ∆TR Hold slew rate = rising signal Notes: LOGIC Devices Incorporated VREF(DC) - VIL(DC) MAX ∆TR Hold slew rate = falling signal VIH(DC) MIN - V REF(DC) ∆TF 1. Both the clock and the strobe are drawn on different time scales. www.logicdevices.com 66 High Performance, Integrated Memory Module Product May 3, 2012 LDS-L9D364M64SBG2-G L9D364M64SBG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) FIGURE 31 - NOMINAL SLEW RATE AND tVAC FOR tDS (DQ – STROBE) CK CK# DQS# DQS t DS t DH t DS t DH VDDQ Nominal line t VAC VIH(AC) MIN VREF to AC region VIH(DC) MIN Tangent line VREF(DC) Tangent line VIL(DC) MAX VREF to AC region VIL(AC) MAX Nominal line t VAC ∆TR VSS Setup slew rate rising signal = Tangent line (V IH[ AC ] MIN - V REF [ DC]) ∆TR ∆TF Setup slew rate falling signal = Tangent line (V REF[ DC] - V IL[ AC] MAX) ∆TF Notes: LOGIC Devices Incorporated 1. Both the clock and the strobe are drawn on different time scales. www.logicdevices.com High Performance, Integrated Memory Module Product May 3, 2012 LDS-L9D364M64SBG2-G L9D364M64SBG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) FIGURE 32 - NOMINAL SLEW RATE FOR tDH (DQ – STROBE) CK CK# DQS# DQS t DS t DH t DS t DH VDDQ VIH(AC) MIN Nominal line VIH(DC) MIN DC to VREF region Tangent line VREF(DC) DC to VREF region Tangent line Nominal line VIL(DC) MAX VIL(AC) MAX VSS ∆TR Notes: LOGIC Devices Incorporated ∆TF Tangent line (V REF[ DC] - V IL[ DC] MAX) Hol d slew rate falling signal = Hol d slew rate falling signal = ∆TR Tangent line (V IH [ DC] MIN - VREF[ DC]) ∆TF 1. Both the clock and the strobe are drawn on different time scales. www.logicdevices.com 68 High Performance, Integrated Memory Module Product May 3, 2012 LDS-L9D364M64SBG2-G L9D364M64SBG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) COMMANDS TRUTH TABLE TABLE 56: TRUTH TABLE - COMMAND PACKAGE OUTLINE DIMENSIONS CKE Function Symbol Prev Cycle Next Cycle CS\ RAS\ CAS\ WE\ BA[2:0] An A12 A10 A[11,0:0] Notes Mode Register Set MRS + + L L L L %$ REFRESH 5() + + L L L + 9 9 9 9 9 SELF REFRESH entry 65( + L L L L + 9 9 9 9 9 6 SELF REFRESH exit 65; L + + L 9 + 9 + 9 + 9 9 9 9 9 35( + + L L L L 9%$ 9 9 L 9 35($ + + L L L L 9 9 9 + 9 $&7 + + L L L + %$ :5 + + L + + L %$ 5)8 9 L &$ 8 %&27) :56 + + L + + L %$ 5)8 L L &$ 8 BL8OTF :56 + + L + + L %$ 5)8 + L &$ 8 BL8MRS %&056 :5$3 + + L + + L %$ 5)8 9 + &$ 8 %&27) :5$36 + + L + + L %$ 5)8 L + &$ 8 BL8OTF :5$36 + + L + + L %$ 5)8 + + &$ 8 BL8MRS %&056 RD + + L + + + %$ 5)8 9 L &$ 8 %&27) RDS4 + + L + + + %$ 5)8 L L &$ 8 BL8OTF RDS8 + + L + + + %$ 5)8 + L &$ 8 Single-Bank PRECHARGE PRECHARGE all banks Bank ACTIVATE BL8MRS %&056 WRITE WRITE with AUTO PRECHARGE READ READ with AUTO PRECHARGE &$ 5'$3 + + L + + + %$ 5)8 9 + &$ 8 %&27) 5'$36 + + L + + + %$ 5)8 L + &$ 8 BL8OTF BL8MRS %&056 5'$36 + + L + + + %$ 5)8 + + &$ 8 NO OPERATION 123 + + L + + + 9 9 9 9 9 9 Device DESELECTED '(6 + + + ; ; ; ; ; ; ; ; 3'( + + 9 + 9 + 9 + 9 10 POWER-DOWN entry + 9 + 9 9 9 9 9 9 6 9 9 9 9 9 6,11 12 3'; L + L + L + ZQ CALIBRATION LONG =4&/ + + L + + L ; ; ; + ; ZQ CALIBRATION SHORT =4&6 + + L + + L ; ; ; L ; POWER-DOWN exit L 127(6 1. &RPPDQGVDUHGHILQHGE\VWDWHVRI&6?5$6?&$6?:(?DQG&.(DW 8. WKHULVLQJHGJHRIWKHFORFN7KH06%RI%$5$DQG&$DUHGHYLFH GHQVLW\DQGFRQILJXUDWLRQGHSHQGHQW 2. %XUVW 5($'V RU :5,7(V FDQQRW EH WHUPLQDWHG RU LQWHUUXSWHG 056 IL[HGDQG27)%/%&DUHGHILQHGLQ05 9. 7KHSXUSRVHRIWKH123FRPPDQGLVWRSUHYHQWWKH6'5$0IURPUHJ- 5(6(7?LV/2:HQDEOHGDQGXVHGRQO\IRUDV\QFKURQRXV5(6(77KXV LVWHULQJDQ\XQZDQWHGFRPPDQGV$123ZLOOQRWWHUPLQDWHDQGRSHUD- 5(6(7?PXVWEHKHOG+,*+GXULQJDQ\QRUPDORSHUDWLRQ WLRQWKDWLVLQH[HFXWLRQ 3. 7KHVWDWHRI2'7GRHVQRWDIIHFWWKHVWDWHVGHVFULEHGLQWKLVWDEOH 10. 7KH'(6DQG123FRPPDQGVSHUIRUPVLPLODUO\ 4. 2SHUDWLRQVDSSO\WRWKHEDQNGHILQHGE\WKHEDQNDGGUHVV)RU056%$ 11. 7KH 32:(5'2:1 PRGH GRHV QRW SHUIRUP DQ\ 5()5(6+ RSHUD- VHOHFWVRQHRIIRXUPRGHUHJLVWHUV WLRQV 5. v9wPHDQVv+wRUv/wDGHILQHGORJLFOHYHODQGv;wPHDQVv'RQuW&DUHw 6. 6HH7DEOHIRUDGGLWLRQDOLQIRUPDWLRQRQ&.(WUDQVLWLRQ PDQGGXULQJLQLWLDOL]DWLRQRU=423(5=4&/FRPPDQGDIWHULQLWLDOL]D- 6(/)5()5(6+H[LWLVDV\QFKURQRXV WLRQ LOGIC Devices Incorporated www.logicdevices.com 12. 69 =4 &$/,%5$7,21 /21* LV XVHG IRU HLWKHU =4,17 ILUVW =4&/ FRP- High Performance, Integrated Memory Module Product May 3, 2012 LDS-L9D364M64SBG2-G L9D364M64SBG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) TABLE 57: TRUTH TABLE - CKE CKE Current State 3 (n-1) (n) Previous Cycle 4 Present Cycle 4 (RAS\, CAS\, WE\, CS\) Command 5 Action 5 Notes L L v'RQuW&DUHw 0DLQWDLQ32:(5'2:1 1,2 L + '(6RU123 32:(5'2:1H[LW 1,2 POWER-DOWN SELF REFRESH L L v'RQuW&DUHw 0DLQWDLQ6(/)5()5(6+ 1,2 Bank(s) ACTIVE + + '(6RU123 6(/)5()5(6+H[LW 1,2 READING + L '(6RU123 $FWLYH32:(5'2:1HQWU\ 1,2 WRITING + L '(6RU123 32:(5'2:1HQWU\ 1,2 PRECHARGING + L '(6RU123 32:(5'2:1HQWU\ 1,2 REFRESHING + L '(6RU123 35(&+$5*(32:(5'2:1HQWU\ 1,2 All Banks IDLE + L '(6RU123 35(&+$5*(32:(5'2:1HQWU\ 1,2,6 + L 5()5(6+ 6(/)5()5(6+ 127(6 1. $OOVWDWHVDQGVHTXHQFHVQRWVKRZQDUHLOOHJDORUUHVHUYHGXQOHVVH[SOLF- 4. LWO\GHVFULEHGHOVHZKHUHLQWKLVGRFXPHQW 2. VWDWHRI&.(DWWKHSUHYLRXVFORFNHGJH t&.(0,1PHDQV&.(PXVWEHUHJLVWHUHGDWPXOWLSOHFRQVHFXWLYHSRVL- 5. &200$1'LVWKHFRPPDQGUHJLVWHUHGDWWKHFORFNHGJHPXVWEHD WLYHFORFNHGJHV&.(PXVWUHPDLQDWWKHYDOLGLQSXWOHYHOWKHHQWLUHWLPH OHJDO FRPPDQG DV GHILQHG LQ 7DEOH $FWLRQ LV D UHVXOW RI &20- LWWDNHVWRDFKLHYHWKHUHTXLUHGQXPEHURIUHJLVWUDWLRQFORFNV7KXVDIWHU 0$1'2'7GRHVQRWDIIHFWWKHVWDWHVGHVFULEHGLQWKLVWDEOHDQGLV DQ\&.(WUDQVLWLRQ&.(PD\QRWWUDQVLWLRQIURPLWVYDOLGOHYHOGXULQJWKH WLPHSHULRGRIt,6t&.(0,1t,+ 3. &.(QLVWKHORJLFVWDWHRI&.(DWFORFNHGJHQ&.(QZDVWKH QRWOLVWHG 6. ,GOHVWDWH DOOEDQNVDUHFORVHGQRGDWDEXUVWVDUHLQSURJUHVV&.(LV &XUUHQWVWDWH 7KHVWDWHRIWKH6'5$0LPPHGLDWHO\SULRUWRFORFNHGJH +,*+DQGDOOWLPLQJVIURPSUHYLRXVRSHUDWLRQVDUHVDWLVILHG$OO6(/) n. 5()5(6+H[LWDQG32:(5'2:1H[LWSDUDPHWHUVDUHDOVRVDWLVILHG NO OPERATION (NOP) DESELECT (DES) 7KH'(6FRPPDQG&6?+,*+SUHYHQWVQHZFRPPDQGVIURPEHLQJH[HFXWHGE\WKH6'5$02SHUDWLRQVDOUHDG\LQSURJUHVVDUHQRWDIIHFWHG 7KH123FRPPDQG&6?/2:SUHYHQWVXQZDQWHGFRPPDQGVIURPEHLQJ UHJLVWHUHG GXULQJ LGOH RU ZDLW VWDWHV 2SHUDWLRQV DOUHDG\ LQ SURJUHVV DUH QRWDIIHFWHG ZQ CALIBRATION ZQ Calibration LONG (ZQCL) 7KH=4&/FRPPDQGLVXVHGWRSHUIRUPWKHLQLWLDOFDOLEUDWLRQGXULQJDSRZHUXSLQLWLDOL]DWLRQDQGUHVHWVHTXHQFH7KLVFRPPDQGPD\EHLVVXHGDWDQ\WLPHE\ WKHFRQWUROOHUGHSHQGLQJRQWKHV\VWHPHQYLURQPHQW7KH=4&/FRPPDQGWULJJHUVWKHFDOLEUDWLRQHQJLQHLQVLGHWKH6'5$0$IWHUFDOLEUDWLRQLVDFKLHYHGWKH FDOLEUDWHGYDOXHVDUHWUDQVIHUUHGIURPWKHFDOLEUDWLRQHQJLQHWRWKH6'5$0,2ZKLFKDUHUHIOHFWHGDVXSGDWHG5ONDQG2'7YDOXHV 7KH6'5$0LVDOORZHGDWLPLQJZLQGRZGHILQHGE\HLWKHU t=4,1,7RU t=423(5WRSHUIRUPWKHIXOOFDOLEUDWLRQDQGWUDQVIHURIYDOXHV:KHQ=4&/LVLVVXHG GXULQJWKHLQLWLDOL]DWLRQVHTXHQFHWKHWLPLQJSDUDPHWHUW=4,1,7PXVWEHVDWLVILHG:KHQLQLWLDOL]DWLRQLVFRPSOHWHVXEVHTXHQW=4&/FRPPDQGVUHTXLUHWKH WLPLQJSDUDPHWHUt=423(5WREHVDWLVILHG ZQ Calibration SHORT (ZQCS) 7KH=4&6FRPPDQGLVXVHGWRSHUIRUPSHULRGLFFDOLEUDWLRQVWRDFFRXQWIRUVPDOOYROWDJHDQGWHPSHUDWXUHYDULDWLRQV7KHVKRUWHUWLPLQJZLQGRZLVSURYLGHG WRSHUIRUPWKHUHGXFHGFDOLEUDWLRQDQGWUDQVIHURIYDOXHVDVGHILQHGE\WLPLQJSDUDPHWHUt=4&6$=4&6FRPPDQGFDQHIIHFWLYHO\FRUUHFWDPLQLPXPRI RON and RTTLPSHGDQFHHUURUVZLWKLQFORFNF\FOHVDVVXPLQJWKHPD[LPXPVHQVLWLYLWLHVVSHFLILHGLQ7DEOHDQG7DEOH LOGIC Devices Incorporated www.logicdevices.com High Performance, Integrated Memory Module Product May 3, 2012 LDS-L9D364M64SBG2-G L9D364M64SBG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) ACTIVATE READ 7KH $&7,9$7( FRPPDQG LV XVHG WR RSHQ RU $&7,9$7( D URZ LQ D SDUWLFXODU EDQN IRU D VXEVHTXHQW DFFHVV 7KH YDOXH RQ WKH %$ >@ LQSXWVVHOHFWVWKHEDQNDQGWKHDGGUHVVSURYLGHGRQLQSXWV$>Q@VHOHFWV WKHURZ7KLVURZUHPDLQVRSHQRU$&7,9(IRUDFFHVVHVXQWLOD35(&+$5*(FRPPDQGLVLVVXHGWRWKDWEDQN 7KH5($'FRPPDQGLVXVHGWRLQLWLDWHDEXUVW5($'DFFHVVWRDQ$&7,9( URZ 7KH DGGUHVV SURYLGHG RQ LQSXWV $>@ VHOHFWV WKH VWDUWLQJ FROXPQ DGGUHVVGHSHQGLQJRQWKHEXUVWOHQJWKDQGEXUVWW\SHVHOHFWHGVHHWDEOH 7KHYDOXHRQLQSXW$GHWHUPLQHVZKHWKHURUQRWDXWRSUHFKDUJHLV XVHG,IDXWRSUHFKDUJHLVVHOHFWHGWKHURZEHLQJDFFHVVHGZLOOEH35(&+$5*('DWWKHHQGRIWKH5($'EXUVW,I$87235(&+$5*(LVQRW VHOHFWHGWKHURZZLOOUHPDLQRSHQIRUVXEVHTXHQWDFFHVVHV7KHYDOXHRQ LQSXW$LIHQDEOHGLQWKH02'(5(*,67(5ZKHQWKH5($'FRPPDQG LVLVVXHGGHWHUPLQHVZKHWKHU%&FKRSRU%/LVXVHG$IWHUD5($' FRPPDQGLVLVVXHGWKH5($'EXUVWPD\QRWEHLQWHUUXSWHG$VXPPDU\ RI5($'FRPPDQGVLVVKRZQLQ7DEOH $35(&+$5*(FRPPDQGPXVWEHLVVXHGEHIRUHRSHQLQJDGLIIHUHQWURZ LQWKHVDPHEDQN TABLE 58: READ COMMAND SUMMARY CKE Function READ READ with AUTO PRECHARGE Symbol BL8MRS %&056 RD %&27) RDS4 Prev Cycle Next Cycle CS\ RAS\ CAS\ WE\ + L + BA[2:0] L + %$ + L + L + %$ + An A12 A10 A[11,0:0] Notes 5)8 9 L &$ 5)8 L L &$ BL8OTF RDS8 + L L + %$ 5)8 + L &$ BL8MRS %&056 5'$3 + L + L + %$ 5)8 9 + &$ + L + %$ 5)8 L + &$ + L + %$ 5)8 + + &$ %&27) 5'$36 + L BL8OTF 5'$36 + L WRITE 7KH:5,7(FRPPDQGLVXVHGWRLQLWLDWHDEXUVW:5,7(DFFHVVWRDQ$&7,9(URZ7KHYDOXHRQWKH%$>@LQSXWVVHOHFWVWKHEDQN7KHYDOXHRQLQSXW$ GHWHUPLQHVZKHWKHURUQRW$87235(&+$5*(LVXVHG7KHYDOXHRQLQSXW$LIHQDEOHGLQWKH02'(5(*,67(5>05@ZKHQWKH:5,7(FRPPDQGLV LVVXHGGHWHUPLQHVZKHWKHU%&FKRSRU%/LVXVHG7KH:5,7(FRPPDQGVXPPDU\LVVKRZQLQ7DEOH TABLE 59: WRITE COMMAND SUMMARY CKE Function Symbol BL8MRS %&056 WRITE WRITE with AUTO PRECHARGE :5 Prev Cycle Next Cycle CS\ RAS\ CAS\ WE\ BA[2:0] An A12 A10 A[11,0:0] Notes + L + L L %$ 5)8 9 L &$ + %&27) :56 + L L L %$ 5)8 L L &$ BL8OTF :56 + L + L L %$ 5)8 + L &$ + BL8MRS %&056 :5$3 + L L L %$ 5)8 9 + &$ %&27) :5$36 + L + L L %$ 5)8 L + &$ + L + L L %$ 5)8 + + &$ BL8OTF LOGIC Devices Incorporated :5$36 www.logicdevices.com High Performance, Integrated Memory Module Product May 3, 2012 LDS-L9D364M64SBG2-G L9D364M64SBG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) PRECHARGE REFRESH 7KH35(&+$5*(FRPPDQGLVXVHGWR'($&7,9$7(WKHRSHQURZLQD SDUWLFXODUEDQNRULQDOOEDQNV7KHEDQNVDUHDYDLODEOHIRUDVXEVHTXHQW URZDFFHVVDWDVSHFLILHGWLPHt53DIWHUWKH35(&+$5*(FRPPDQGLV LVVXHGH[FHSWLQWKHFDVHRIFRQFXUUHQW$87235(&+$5*($5($'RU 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EHJLQVZKHQWKH5()5(6+FRPPDQGLVUHJLVWHUHGDQGHQGV t5)&0,1 later. 7RDOORZIRULPSURYHGHIILFLHQF\LQVFKHGXOLQJDQGVZLWFKLQJEHWZHHQWDVNV VRPHIOH[LELOLW\LQWKHDEVROXWH5()5(6+LQWHUYDOLVSURYLGHG$PD[LPXP RIHLJKW5()5(6+FRPPDQGVFDQEHSRVWHGWRDQ\JLYHQ6'5$0PHDQLQJWKDWWKHPD[LPXPDEVROXWHLQWHUYDOEHWZHHQDQ\5()5(6+FRPPDQG DQG WKH QH[W 5()5(6+ FRPPDQG LV QLQH WLPHV WKH PD[LPXP DYHUDJH LQWHUYDO UHIUHVK UDWH 6(/) 5()5(6+ PD\ EH HQWHUHG ZLWK XS WR HLJKW 5()5(6+FRPPDQGVEHLQJSRVWHG$IWHUH[LWLQJ6(/)5()5(6+ZKHQ HQWHUHGZLWKSRVWHG5()5(6+FRPPDQGVDGGLWLRQDOSRVWLQJRI5()5(6+ FRPPDQGV LV DOORZHG WR WKH H[WHQW WKH PD[LPXP QXPEHU RI FXPXODWLYH SRVWHG5()5(6+FRPPDQGVERWKSUHDQGSRVW6(/)5()5(6+GRHV QRWH[FHHGHLJKW5()5(6+FRPPDQGV FIGURE 33 - REFRESH MODE T0 T2 T1 T3 T4 Ta0 Ta1 Tb0 Tb1 Valid 1 Valid 1 NOP1 NOP1 Tb2 CK# CK t CK t CH t CL Valid 1 CKE Command NOP 1 PRE NOP 1 NOP 1 REF NOP 1 REF 2 ACT Address RA All banks A10 RA One bank Bank(s) 3 BA[2:0] BA DQS, DQS# 4 DQ4 DM 4 t RP t RFC (MIN) t RFC 2 Indicates A Break in Time Scale Notes: LOGIC Devices Incorporated Don’t Care 1. NOP commands are shown for ease of illustration; other valid commands may be possible at these times. CKE must be active during the PRECHARGE, ACTIVATE, and REFRESH commands, but may be inactive at other times (see “Power-Down Mode” on page 153). www.logicdevices.com High Performance, Integrated Memory Module Product May 3, 2012 LDS-L9D364M64SBG2-G L9D364M64SBG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) SELF REFRESH 7KH6(/)5()5(6+FRPPDQGLVXVHGWRUHWDLQGDWDLQWKH6'5$0HYHQLIWKHUHVWRIWKHV\VWHPLVSRZHUHGGRZQ:KHQLQWKH6(/)5()5(6+PRGHWKH 6'5$0UHWDLQVGDWDZLWKRXWH[WHUQDOFORFNLQJ7KH6(/)5()5(6+PRGHLVDOVRDFRQYHQLHQWPHWKRGXVHGWRHQDEOHGLVDEOHWKH'//DVZHOODVWRFKDQJH WKHFORFNIUHTXHQF\ZLWKLQWKHDOORZHGV\QFKURQRXVRSHUDWLQJUDQJH$OOSRZHUVXSSO\LQSXWVLQFOXGLQJ95()&$DQG95()'4PXVWEHPDLQWDLQHGDWYDOLGOHYHOV XSRQHQWU\H[LWDQGGXULQJ6(/)5()5(6+PRGHRSHUDWLRQ$OOSRZHUVXSSO\LQSXWVLQFOXGLQJ95()&$DQG95()'4PXVWEHPDLQWDLQHGDWYDOLGOHYHOVXSRQ HQWU\H[LWDQGGXULQJ6(/)5()5(6+PRGHXQGHUFHUWDLQFRQGLWLRQV x9VV95()'49DDLVPDLQWDLQHG x95()'4LVYDOLGDQGVWDEOHSULRUWR&.(JRLQJEDFN+,*+ x7KHILUVW:5,7(RSHUDWLRQPD\QRWRFFXUHDUOLHUWKDQFORFNVDIWHU95()'4LVYDOLG x$OORWKHU6(/)5()5(6+PRGHH[LWWLPHUHTXLUHPHQWVDUHPHW DLL DISABLE MODE ,IWKH'//LVGLVDEOHGE\WKH02'(5(*,67(505>@FDQEHVZLWFKHGGXULQJLQLWLDOL]DWLRQRUODWHUWKH6'5$0LVWDUJHWHGEXWQRWJXDUDQWHHGWRRSHUDWH VLPLODUO\WRWKH1250$/PRGHZLWKDIHZQRWDEOHH[FHSWLRQV x x x 7KH6'5$0VXSSRUWVRQO\RQHYDOXHRI&$6ODWHQF\&/ DQGRQHYDOXHRI&$6:5,7(ODWHQF\&:/ '//',6$%/(PRGHDIIHFWVWKH5($'GDWDFORFNWRGDWDVWUREHUHODWLRQVKLSt'46&.EXWQRWWKH5($'GDWDWRGDWDVWUREHUHODWLRQVKLS tDQSQ, t4+6SHFLDODWWHQWLRQLVQHHGHGWROLQHWKH5($'GDWDXSZLWKWKHFRQWUROOHUWLPHGRPDLQZKHQWKH'//LVGLVDEOHG ,Q1250$/RSHUDWLRQ'//RQ t'46&.VWDUWVIURPWKHULVLQJFORFNHGJH$/&/F\FOHVDIWHUWKH5($'FRPPDQG,Q'//',6$%/( PRGH t'46&.VWDUWV$/ &/yF\FOHVDIWHUWKH5($'FRPPDQG$GGLWLRQDOO\ZLWKWKH'//GLVDEOHGWKHYDOXHRI t'46&.FRXOGEH ODUJHUWKDQt&. 7KH2'7IHDWXUHLVQRWVXSSRUWHGGXULQJ'//',6$%/(PRGHLQFOXGLQJG\QDPLF2'77KH2'7UHVLVWRUVPXVWEHGLVDEOHGE\FRQWLQXRXVO\UHJLVWHULQJWKH 2'7EDOO/2:E\SURJUDPPLQJ5TT_NORM MR1[9,6,2] and RTTB:505>@WRvwZKLOHLQ'//',6$%/(PRGH 6SHFLILFVWHSVPXVWEHIROORZHGWRVZLWFKEHWZHHQWKH'//HQDEOHDQG'//',6$%/(PRGHVGXHWRDJDSLQWKHDOORZHGFORFNUDWHVEHWZHHQWKHWZRPRGHV t&.>$9*@0$;DQG t&.>'//',6$%/(@0,1UHVSHFWLYHO\7KHRQO\WLPHWKHFORFNLVDOORZHGWRFURVVWKLVFORFNUDWHJDSLVGXULQJ6(/)5()5(6+PRGH 7KXVWKHUHTXLUHGSURFHGXUHIRUVZLWFKLQJIURPWKH'//(1$%/(WR'//',6$%/(PRGHLVWRFKDQJHIUHTXHQF\FXULQJVHOIUHIUHVKVHH)LJXUH 1. 2. 3. 4. 5. 6WDUWLQJIURPWKH,'/(VWDWHDOOEDQNVDUH35(&+$5*('DOOWLPLQJVDUHIXOILOOHG2'7LVWXUQHGRIIDQG5TT_NOM and RTTB:5DUH +,*+=VHW05>@WRvwWR',6$%/(WKH'// (QWHU6(/)5()5(6+PRGHDIWHUt02'KDVEHHQVDWLVILHG $IWHUt&.65(LVVDWLVILHGFKDQJHWKHIUHTXHQF\WRWKHGHVLUHGFORFNUDWH 6(/)5()5(6+PD\EHH[LWHGZKHQWKHFORFNLVVWDEOHGZLWKWKHQHZIUHTXHQF\IRUt&.65; 7KH6'5$0ZLOOEHUHDG\IRULWVQH[WFRPPDQGLQWKH'//',6$%/(PRGHDIWHUWKHJUHDWHURItMRD or t02'KDVEHHQVDWLVILHG$=4&/ FRPPDQGVKRXOGEHLVVXHGZLWKDSSURSULDWHWLPLQJPHWDVZHOO LOGIC Devices Incorporated www.logicdevices.com High Performance, Integrated Memory Module Product May 3, 2012 LDS-L9D364M64SBG2-G L9D364M64SBG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) FIGURE 34 - DLL ENABLE MODE TO DLL DISABLE MODE T0 T1 Ta0 Ta1 Tb0 Tc0 Td0 Td1 Te0 Te1 Tf0 CK# CK Vali d 1 CKE Command MRS2 6 NOP SRE 3 t MOD SRX 4 NOP t CKSRE t CKSRX 8 7 NOP MRS5 NOP Vali d 1 t MOD t XS t CKESR ODT 9 Vali d 1 Indicates a Break in Time Scale 127(6 1. $Q\YDOLGFRPPDQG 2. 'LVDEOH'//E\VHWWLQJ05>@WRvw 3. :DLWt;6WKHQVHW05>@WRvwWRHQDEOH'// 4. :DLWt05'WKHQVHW05>@WRvwWREHJLQ'//5(6(7 5. :DLWt05'XSGDWHUHJLVWHUV&/&:/DQGZULWHUHFRYHU\PD\EHQHFHVVDU\ 6. :DLWt02'DQ\YDOLGFRPPDQG 6WDUWLQJZLWKWKHLGOHVWDWH 8. &KDQJHIUHTXHQF\ 9. &ORFNPXVWEHVWDEOHDWOHDVWt&.65; 10. 6WDWLF/2:LQFDVH5TT_NOM or RTTB:5LVHQDEOHGRWKHUZLVHVWDWLF/2:RU+,*+ Don ’t Care $VLPLODUSURFHGXUHLVUHTXLUHGIRUVZLWFKLQJIURPWKH'//GLVDEOHPRGHEDFNWRWKH'//HQDEOHPRGH7KLVDOVRUHTXLUHVFKDQJLQJWKHIUHTXHQF\GXULQJVHOI UHIUHVKPRGHVHH)LJXUHRQSDJH 6WDUWLQJIURPWKHLGOHVWDWHDOOEDQNVDUHSUHFKDUJHGDOOWLPLQJVDUHIXOILOOHG2'7LVWXUQHGRIIDQG5TT_NOM and RTTB:5DUH+LJK= HQWHUVHOIUHIUHVKPRGH $IWHUt&.65(LVVDWLVILHGFKDQJHWKHIUHTXHQF\WRWKHQHZFORFNUDWH 6HOIUHIUHVKPD\EHH[LWHGZKHQWKHFORFNLVVWDEOHZLWKWKHQHZIUHTXHQF\IRUt&.65;$IWHUt;6LVVDWLVILHGXSGDWHWKHPRGHUHJLVWHUV ZLWKWKHDSSURSULDWHYDOXHV$WDPLQLPXPVHW05>@WRvwWRHQDEOHWKH'//:DLWt05'WKHQVHW05>@WRvwWRHQDEOH'//5(6(7 $IWHUDQRWKHUt05'GHOD\LVVDWLVILHGWKHQXSGDWHWKHUHPDLQLQJPRGHUHJLVWHUVZLWKWKHDSSURSULDWHYDOXHV 7KH'5$0ZLOOEHUHDG\IRULWVQH[WFRPPDQGLQWKH'//HQDEOHPRGHDIWHUWKHJUHDWHURItMRD or t02'KDVEHHQVDWLVILHG+RZHYHU EHIRUHDSSO\LQJDQ\FRPPDQGRUIXQFWLRQUHTXLULQJDORFNHG'//DGHOD\RIt'//.DIWHU'//5(6(7PXVWEHVDWLVILHG$=4&/FRPPDQG VKRXOGEHLVVXHGZLWKWKHDSSURSULDWHWLPLQJVPHWDVZHOO LOGIC Devices Incorporated www.logicdevices.com High Performance, Integrated Memory Module Product May 3, 2012 LDS-L9D364M64SBG2-G L9D364M64SBG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) FIGURE 35- DLL DISABLE MODE TO DLL ENABLE MODE T0 Ta0 Ta1 Tb0 Tc0 Tc1 Td0 Te0 Tf0 Tg0 Th0 CK# CK CKE Vali d t DLLK Command SRE1 NOP SRX2 NOP t CKSRE 7 t CKSRX 9 8 MRS3 t XS MRS4 t MRD MRS5 Vali d 6 t MRD ODTL off + 1 × t CK t CKESR ODT10 Indicates a Break in Time Scale Don ’t Care 127(6 1. (QWHU6(/)5()5(6+ 2. ([LW6(/)5()5(6+ 3. :DLWt;6WKHQVHW05>@WRvwWRHQDEOH'// 4. :DLWt05'WKHQVHW05>@WRvwWREHJLQ'//5(6(7 5. :DLWt05'XSGDWHUHJLVWHUV&/&:/DQGZULWHUHFRYHU\PD\EHQHFHVVDU\ 6. :DLWt02'DQ\YDOLGFRPPDQG 6WDUWLQJZLWKWKHLGOHVWDWH 8. &KDQJHIUHTXHQF\ 9. &ORFNPXVWEHVWDEOHDWOHDVWt&.65; 10. 6WDWLF/2:LQFDVH5TT_NOM or RTTB:5LVHQDEOHGRWKHUZLVHVWDWLF/2:RU+,*+ 7KHFORFNIUHTXHQF\UDQJHIRUWKH'//GLVDEOHPRGHLVVSHFLILHGE\WKHSDUDPHWHU t&.'//B',6'XHWRODWHQF\FRXQWHUDQGWLPLQJUHVWULFWLRQVRQO\&/ DQG&:/ DUHVXSSRUWHG '//GLVDEOHPRGHZLOODIIHFWWKHUHDGGDWDFORFNWRGDWDVWUREHUHODWLRQVKLSt'46&.EXWQRWWKHGDWDVWUREHWRGDWDUHODWLRQVKLStDQSQ, t4+6SHFLDODWWHQWLRQLVQHHGHGWRWKHFRQWUROOHUWLPHGRPDLQ &RPSDUHGWRWKH'//RQPRGHZKHUH t'46&.VWDUWVIURPWKHULVLQJFORFNHGJH$/&/F\FOHVDIWHUWKH5($'FRPPDQGWKH'//GLVDEOHPRGH t'46&. VWDUWV$/&/F\FOHVDIWHUWKH5($'FRPPDQGVHH)LJXUHRQSDJH :5,7(RSHUDWLRQVIXQFWLRQVLPLODUO\EHWZHHQWKH'//HQDEOHDQG'//GLVDEOHPRGHVKRZHYHU2'7IXQFWLRQDOLW\LVQRWDOORZHGZLWK'//GLVDEOHPRGH LOGIC Devices Incorporated www.logicdevices.com High Performance, Integrated Memory Module Product May 3, 2012 LDS-L9D364M64SBG2-G L9D364M64SBG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) FIGURE 36 - DLL DISABLE tDQSCK TIMING T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 READ NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP CK# CK Command Add ress Vali d RL = AL + C L = 6 (C L = 6, AL = 0) CL = 6 DQS, DQS# DLL on DI b DQ BL8 DLL on DI b+1 DI b+2 DI b+3 DI b+4 DI b+5 DI b+6 DI b+7 RL (DLLdisable) = AL + (C L - 1) = 5 t DQSCK (DLL_DIS) MIN DQS, DQS# DLL off DI b DQ BL8 DLL disable DI b+1 DI b+2 DI b+3 DI b+4 DI b+5 DI b+6 DI b+7 DI b+3 DI b+4 DI b+5 DI b+6 t DQSCK (DLL_ DIS) MAX DQS, DQS# DLL off DI b DQ BL8 DLL disable DI b+1 DI b+2 DI b+7 Transitioning Data Don ’t Care INPUT CLOCK FREQUENCY CHANGE :KHQWKH''56'5$0LVLQLWLDOL]HGLWUHTXLUHVWKHFORFNWREHVWDEOHGXULQJPRVW1250$/VWDWHVRIRSHUDWLRQ7KLVPHDQVWKDWDIWHUWKHFORFNIUHTXHQF\ KDVEHHQVHWWRWKHVWDEOHVWDWHWKHFORFNSHULRGLVQRWDOORZHGWRGHYLDWHH[FHSWZKDWLVDOORZHGIRUE\WKHFORFNMLWWHUDQGVSUHDGVSHFWUXPFORFNLQJ66& VSHFLILFDWLRQV 7KHLQSXWFORFNIUHTXHQF\FDQEHFKDQJHGIURPRQHVWDEOHFORFNUDWHWRDQRWKHUXQGHUWZRFRQGLWLRQV6(/)5()5(6+PRGHDQG35(&+$5*(SRZHUGRZQ PRGH2XWVLGHRIWKHVHWZRPRGHVLWLVLOOHJDOWRFKDQJHWKHFORFNIUHTXHQF\)RUWKH6(/)5()5(6+PRGHFRQGLWLRQZKHQWKH''56'5$0KDVEHHQ VXFFHVVIXOO\SODFHGLQWR6(/)5()5(6+PRGHDQG t&.65(KDVEHHQVDWLVILHGWKHVWDWHRIWKHFORFNEHFRPHVDv'RQuW&DUHw:KHQWKHFORFNEHFRPHVD v'RQuW&DUHwFKDQJLQJWKHFORFNIUHTXHQF\LVSHUPLVVLEOHSURYLGHGWKHQHZFORFNIUHTXHQF\LVVWDEOHSULRUWRt&.65;:KHQHQWHULQJDQGH[LWLQJVHOIUHIUHVK PRGHIRUWKHVROHSXUSRVHRIFKDQJLQJWKHFORFNIUHTXHQF\WKH6(/)5()5(6+HQWU\DQGH[LWVSHFLILFDWLRQVPXVWVWLOOEHPHW 7KH35(&+$5*(SRZHUGRZQPRGHFRQGLWLRQLVZKHQWKH''56'5$0LVLQ35(&+$5*(SRZHUGRZQPRGHHLWKHUIDVWH[LWPRGHRUVORZH[LWPRGH (LWKHU2'7PXVWEHDWDORJLF/2:RU5TT_NOM and RTTB:5PXVWEHGLVDEOHGYLD05DQG057KLVHQVXUHV5TT_NOM and RTTB:5DUHLQDQRIIVWDWH SULRUWRHQWHULQJ35(&+$5*(SRZHUGRZQPRGHZKLOHPDLQWDLQLQJ&.(DWDORJLF/2:$PLQLPXPRIt&.65(PXVWRFFXUDIWHU&.(JRHV/2:EHIRUHWKH FORFNIUHTXHQF\FDQFKDQJH7KH''56'5$0LQSXWFORFNIUHTXHQF\LVDOORZHGWRFKDQJHRQO\ZLWKLQWKHPLQLPXPDQGPD[LPXPRSHUDWLQJIUHTXHQF\VSHFLILHGIRUWKHSDUWLFXODUVSHHGWHPSHUDWXUHJUDGHt&.>$9*@0,1WRt&.>$9*@0$;GHYLFH'XULQJWKHLQSXWFORFNIUHTXHQF\FKDQJH&.(PXVWEHKHOGDWD VWDEOH/2:OHYHO:KHQWKHLQSXWFORFNIUHTXHQF\LVFKDQJHGDVWDEOHFORFNPXVWEHSURYLGHGWRWKH6'5$0t&.65;EHIRUH35(&+$5*(SRZHUGRZQPD\ EHH[LWHG$IWHU35(&+$5*(SRZHUGRZQLVH[LWHGDQGt;3KDVEHHQVDWLVILHGWKH'//PXVWEHUHVHWYLDWKH056'HSHQGLQJRQWKHQHZFORFNIUHTXHQF\ DGGLWLRQDO056FRPPDQGVPD\QHHGWREHLVVXHG'XULQJWKH'//ORFNWLPH5TT_NOM and RTTB:5PXVWUHPDLQLQDQRIIVWDWH$IWHUWKH'//ORFNWLPH WKH6'5$0LVUHDG\WRRSHUDWHZLWKDQHZFORFNIUHTXHQF\SHULRG7KLVSURFHVVLVGHSLFWHGLQ)LJXUH LOGIC Devices Incorporated www.logicdevices.com High Performance, Integrated Memory Module Product May 3, 2012 LDS-L9D364M64SBG2-G L9D364M64SBG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) FIGURE 37- CHANGE FREQUENCY DURING PRECHARGE POWER-DOWN Previous clock frequency T0 T1 T2 New clock fre quency Ta0 Tb0 Tc1 Tc0 Td0 Td1 Te0 Te1 CK# CK t CH t CL t CH t CK t CK t CKSRE t IS t IH t CH b t CK b t CL b t CH b b b t CL t CK b b t CKSRX t CKE t IH CKE t IS t CPDED Command t CL b NOP NOP NOP NOP NOP Address MRS Valid NOP Valid DLL RESET t AOFPD/ t AOF t XP t IH t IS ODT DQS, DQS# High-Z High-Z DQ DM t DLLK Enter precharge power-down mode Frequency change Exit precharge power-down mode Indicates a Break in Time Scale Don’t Care 127(6 1. $SSOLFDEOHIRUERWKVORZH[LWDQGIDVWH[LWSUHFKDUJHSRZHUGRZQPRGHV 2. t$2)3' DQG t$2) PXVW EH VDWLVILHG DQG RXWSXWV +LJK= SULRU WR 7 VHH v2Q'LH 7HUPLQDWLRQ 2'7wRQSDJHIRUH[DFWUHTXLUHPHQWV 3. ,IWKH5TTB120IHDWXUHZDVHQDEOHGLQWKHPRGHUHJLVWHUSULRUWRHQWHULQJSUHFKDUJHSRZHUGRZQ PRGH WKH 2'7 VLJQDO PXVW EH FRQWLQXRXVO\ UHJLVWHUHG /2: HQVXULQJ 5TT LV LQ DQ RII VWDWH ,I WKH5TTB120IHDWXUHZDVGLVDEOHGLQWKHPRGHUHJLVWHUSULRUWRHQWHULQJSUHFKDUJHSRZHUGRZQ PRGH5TTZLOOUHPDLQLQWKHRIIVWDWH7KH2'7VLJQDOFDQEHUHJLVWHUHGHLWKHU/2:RU+,*+LQ WKLVFDVH LOGIC Devices Incorporated www.logicdevices.com High Performance, Integrated Memory Module Product May 3, 2012 LDS-L9D364M64SBG2-G L9D364M64SBG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) WRITE LEVELING )RUEHWWHUVLJQDOLQWHJULW\''56'5$0PHPRU\VXEV\VWHPGHVLJQVKDYHDGRSWHGXVHRIIO\E\WRSRORJ\IRUWKHFRPPDQGVDGGUHVVHVFRQWUROVLJQDOVDQG FORFNV:5,7(OHYHOLQJLVDVFKHPHIRUWKHPHPRU\FRQWUROOHUWRGHVNHZWKH'46[VWUREH'46['46[?WR&.UHODWLRQVKLSDWWKH6'5$0ZLWKDVLPSOH IHHGEDFNIHDWXUHSURYLGHGLWE\WKH''56'5$0LWVHOI:5,7(OHYHOLQJLVJHQHUDOO\XVHGDVSDUWRIWKHLQLWLDOL]DWLRQSURFHVVLIUHTXLUHG)RU1250$/ 6'5$0RSHUDWLRQWKLVIHDWXUHPXVWEHGLVDEOHG7KLVLVWKHRQO\6'5$0RSHUDWLRQZKHUHWKH'46IXQFWLRQVDVDQLQSXWWRFDSWXUHWKHLQFRPLQJFORFNDQG WKH'4VIXQFWLRQDVRXWSXWVWRUHSRUWWKHVWDWRIWKHFORFN1RWHWKDWQRQVWDQGDUG2'7VFKHPHVDUHUHTXLUHG 7KHPHPRU\FRQWUROOHUXVLQJWKH:5,7(OHYHOLQJSURFHGXUHPXVWKDYHDGMXVWDEOHGHOD\VHWWLQJRQLWV'46VWUREHWRDOLJQWKHULVLQJHGJHRI'46WRWKHFORFN DWWKH6'5$0SLQV7KLVLVDFFRPSOLVKHGZKHQWKH6'5$0DV\QFKURQRXVO\IHHGVEDFNWKH&.VWDWXVYLDWKH'4EXVDQGVDPSOHVZLWKWKHULVLQJHGJHRI '467KHFRQWUROOHUUHSHDWHGO\GHOD\VWKH'46VWUREHXQWLOD&.WUDQVLWLRQIURPvwWRvwLVGHWHFWHG7KH'46GHOD\HVWDEOLVKHGWKURXJKWKLVSURFHGXUH KHOSVHQVXUHtDQSS, tDSS, and t'6+VSHFLILFDWLRQVLQV\VWHPVWKDWXVHIO\E\WRSRORJ\E\GHVNHZLQJWKHWUDFHOHQJWKPLVPDWFK$FRQFHSWXDOWLPLQJRIWKLV SURFHGXUHLVVKRZQLQ)LJXUH FIGURE 38- WRITE LEVELING CONCEPT T0 T1 T2 T3 T4 T5 T6 T7 CK# CK Source Differential DQS Tn T0 T1 T2 T3 T4 T5 T4 T5 T6 CK# CK Destination Differential DQS 0 DQ Destination Tn T0 T1 0 T2 T3 T6 CK# CK Push DQS to capture 0–1 transition Differential DQS 1 DQ 1 Don’t Care LOGIC Devices Incorporated www.logicdevices.com High Performance, Integrated Memory Module Product May 3, 2012 LDS-L9D364M64SBG2-G L9D364M64SBG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) WRITE LEVELING :KHQ:5,7(OHYHOLQJLVHQDEOHGWKHULVLQJHGJHRI'46VDPSOHV&.DQGWKHULPH'4RXWSXWVWKHVDPSOHG&.uVVWDWXV7KHSULPH'4IRUHDFKRIWKH ZRUGVFRQWDLQHGLQWKHL02'LV'4IRUWKHORZE\WH'4IRUWKHKLJKE\WH,WRXWSXWVWKHVWDWXVRI&.VDPSOHGE\/'46[DQG8'46[$OORWKHU'4V '4>@'4>@IRUWKHORZZRUG'4>@'4>@IRUWKHQH[WZRUG'4>@'4>@IRUWKHQH[WDQG'4>@'4>@IRUWKH+,*+ZRUG FRQWLQXHWRGULYH/2:7ZRSULPH'4RQHDFKRIWKHZRUGVFRQWDLQHGLQWKH/',L02'DOORZHDFKE\WHODQHWREHOHYHOHGLQGHSHQGHQWO\ WRITE LEVELING PROCEDURE $PHPRU\FRQWUROOHULQLWLDWHVWKH6'5$0:5,7(/HYHOLQJPRGHE\VHWWLQJWKH05>@WRDvwDVVXPLQJWKHRWKHUSURJUDPPDEOHIHDWXUHV050505 DQG05DUHILUVWVHWDQGWKH'//LVIXOO\UHVHWDQGORFNHG7KH'4EDOOVHQWHUWKH:5,7(/HYHOLQJPRGHJRLQJIURPDv+,*+=wVWDWHWRDQXQGHILQHGGULYLQJVWDWHVRWKH'4EXVVKRXOGQRWEHGULYHQ'XULQJ:5,7(/HYHOLQJPRGHRQO\WKH123DQG'(6FRPPDQGVDUHDOORZHG7KHPHPRU\FRQWUROOHUVKRXOG DWWHPSWWROHYHORQO\RQHUDQNDWDWLPHWKXVWKHRXWSXWVRIRWKHUUDQNVVKRXOGEHGLVDEOHGE\VHWWLQJ05>@WRDvw7KHPHPRU\FRQWUROOHUPD\DVVHUW 2'7DIWHUDt02'GHOD\DVWKH6'5$0ZLOOEHUHDG\WRSURFHVVWKH2'7/RQGHOD\:/t&.SURYLGHGLWGRHVQRWYLRODWHWKHDIRUHPHQWLRQHG tMOD delay UHTXLUHPHQW 7KHPHPRU\FRQWUROOHUPD\GULYH/'46[8'46[/2:DQG/'46[?8'46[?+,*+DIWHUt:/'46(1KDVEHHQVDWLVILHG7KHFRQWUROOHUPD\EHJLQWRWRJJOH /'46[8'46[DIWHUt:/05'RQH/>8@'46VWRJJOHLV'46VWUDQVLWLRQLQJIURPD/2:VWDWHWRD+,*+VWDWHZLWK/>8@'46[?WUDQVLWLRQLQJIURPD+,*+VWDWH WRD/2:VWDWHWKHQERWKWUDQVLWLRQEDFNWRWKHLURULJLQDOVWDWHV$WDPLQLPXP2'7/RQDQGt$21PXVWEHVDWLVILHGDWOHDVWRQHFORFNSULRUWR'46WRJJOLQJ $IWHUt:/05'DQG'46/2:SUHDPEOHt:35(KDYHEHHQVDWLVILHGWKHPHPRU\FRQWUROOHUPD\SURYLGHHLWKHUDVLQJOH'46[WRJJOHRUPXOWLSOH'46[WRJJOHV WRVDPSOH&.IRUDJLYHQ'46[WR&.VNHZ(DFK'46WRJJOHPXVWQRWYLRODWHt'46/0,1DQGt'46+0,1VSHFLILFDWLRQVt'46/0$;DQGt'46+0$; VSHFLILFDWLRQVDUHQRWDSSOLFDEOHGXULQJ:5,7(OHYHOLQJPRGH7KH'46[PXVWEHDEOHWRGLVWLQJXLVKWKH&.uVULVLQJHGJHZLWKLQt:/6DQGt:/+7KHSULPH '4ZLOORXWSXWWKH&.uVVWDWXVDV\QFKURQRXVO\IURPWKHDVVRFLDWHG'46[ULVLQJHGJH&.FDSWXUHZLWKLQ t:/27KHUHPDLQLQJ'4VWKDWDOZD\VGULYH/2: ZKHQ'46LVWRJJOLQJPXVWEH/2:ZLWKLQt:/2(DIWHUWKHILUVWt:/2LVVDWLVILHGWKHSULPH'4VJRLQJ/2:$VSUHYLRXVO\QRWHG'46[LVDQLQSXWDQGQRW DQRXWSXWGXULQJWKLVSURFHVV)LJXUHGHSLFWVWKHEDVLFWLPLQJSDUDPHWHUVIRUWKHRYHUDOOZULWHOHYHOLQJSURFHGXUH 7KHPHPRU\FRQWUROOHUZLOOOLNHO\VDPSOHHDFKDSSOLFDEOHSULPH'4VWDWHDQGGHWHUPLQHZKHWKHUWRLQFUHPHQWRUGHFUHPHQWLW'46GHOD\VHWWLQJ$IWHUWKH PHPRU\FRQWUROOHUSHUIRUPVHQRXJK'46[WRJJOHVWRGHWHFWWKH&.uVvwWUDQVLWLRQWKHPHPRU\FRQWUROOHUVKRXOGORFNWKH'46GHOD\VHWWLQJIRUWKH6'5$0 L02'GHYLFH$IWHUORFNLQJWKH'46VHWWLQJOHYHOLQJIRUWKHUDQNZLOOKDYHEHHQDFKLHYHGDQGWKH:5,7(OHYHOLQJPRGHIRUWKHUDQNVKRXOGEHGLVDEOHGRU UHSURJUDPPHGLI:5,7(OHYHOLQJRIDQRWKHUUDQNIROORZV LOGIC Devices Incorporated www.logicdevices.com High Performance, Integrated Memory Module Product May 3, 2012 LDS-L9D364M64SBG2-G L9D364M64SBG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) FIGURE 39- WRITE LEVELING SEQUENCE T1 T2 t WLS t WLH CK# CK Command MRS1 NOP2 NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP t MOD ODT t WLDQSEN t DQSL3 t DQSH3 t DQSL3 t DQSH3 Differential DQS4 t WLMRD t WLO t WLO Prime DQ 5 t WLO t WLOE Early remaining DQ t WLO Late remaining DQ Indicates a Break in Time Scale Undefined Driving Mode Don’t Care 127(6 1. 056/RDG05WRHQWHUZULWHOHYHOLQJPRGH 2. 123123RU'(6 3. '46'46QHHGVWRIXOILOOPLQLPXPSXOVHZLGWKUHTXLUHPHQWV t'46+0,1DQG t'46/0,1DV GHILQHGIRUUHJXODUZULWHV7KHPD[LPXPSXOVHZLGWKLVV\VWHPGHSHQGHQW 4. 'LIIHUHQWLDO'46LVWKHGLIIHUHQWLDOGDWDVWUREH'46'467LPLQJUHIHUHQFHSRLQWVDUHWKH]HUR FURVVLQJV7KHVROLGOLQHUHSUHVHQWV'46WKHGRWWHGOLQHUHSUHVHQWV'46 5. '5$0GULYHVOHYHOLQJIHHGEDFNRQDSULPH'4'4IRU[DQG[7KHUHPDLQLQJ'4DUHGULYHQ /2:DQGUHPDLQLQWKLVVWDWHWKURXJKRXWWKHOHYHOLQJSURFHGXUH WRITE LEVELING EXIT MODE $IWHUWKH''56'5$0L02'KDVEHHQ:5,7(OHYHOHGWKHFRQWUROOHUPXVWH[LWIURP:5,7(/HYHOLQJPRGHEHIRUHWKH1250$/PRGHFDQEHXVHG)LJXUH GHSLFWVDJHQHUDOSURFHGXUHLQH[LWLQJ:5,7(/HYHOLQJ$IWHUWKHODVWULVLQJ'46FDSWXULQJDvwDW7WKHPHPRU\FRQWUROOHUVKRXOGVWRSGULYLQJWKH'46 VLJQDOVDIWHUt:/20$;GHOD\SOXVHQRXJKGHOD\WRHQDEOHWKHPHPRU\FRQWUROOHUWRFDSWXUHWKHDSSOLFDEOHSULPH'4VWDWHDWy7E7KH'4EDOOVEHFRPH XQGHILQHGZKHQ'46QRORQJHUUHPDLQV/2:DQGWKH\UHPDLQXQGHILQHGXQWLOt02'DIWHUWKH056FRPPDQGDW7H 7KH2'7LQSXWVKRXOGEHGHDVVHUWHG/2:VXFKWKDW2'7/RII0,1H[SLUHVDIWHUWKH'46[LVQRORQJHUGULYLQJ/2::KHQ2'7/2:VDWLVILHV tIS, ODT PXVWEHNHSW/2:DWy7EXQWLOWKH6'5$0LVUHDG\IRUHLWKHUDQRWKHUUDQNWREHOHYHOHGRUXQWLOWKH1250$/PRGHFDQEHXVHG$IWHU'46WHUPLQDWLRQLV VZLWFKHGRII:5,7(OHYHOPRGHVKRXOGEHGLVDEOHGYLDWKH056FRPPDQGDWT$$IWHUt02'LVVDWLVILHGDW7HDQ\YDOLGFRPPDQGPD\EHUHJLVWHUHG E\WKH6'5$06RPH056FRPPDQGVPD\EHLVVXHGDIWHUt05'DW7G LOGIC Devices Incorporated www.logicdevices.com 80 High Performance, Integrated Memory Module Product May 3, 2012 LDS-L9D364M64SBG2-G L9D364M64SBG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) FIGURE 40- EXIT WRITE LEVELING T0 T1 T2 Ta0 Tb0 Tc0 Tc1 Tc2 Td0 Td1 Te0 Te1 NOP NOP NOP NOP NOP NOP NOP M RS NOP t MRD Valid NOP Valid CK# CK Command Add ress Valid MR1 t IS Valid t MOD ODT ODTL off R TT DQS, R TT DQS# t AOF (MIN) RTT_NOM t AOF (MAX) DQS, DQS# RTT_DQ t WLO + t WLOE DQ CK = 1 Indicates a Break in Time Scale Undefined Driving Mode Transitioning Don ’t Care Notes: 1. The DQ result, “= 1,” between Ta0 and Tc0, is a result of the DQS, DQS# signals capturing CK HIGH just after the T0 state. LOGIC Devices Incorporated www.logicdevices.com 81 High Performance, Integrated Memory Module Product May 3, 2012 LDS-L9D364M64SBG2-G L9D364M64SBG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) OPERATIONS Initialization 7KHIROORZLQJVHTXHQFHLVUHTXLUHGIRUSRZHUXSDQGLQLWLDOL]DWLRQDVVKRZQLQ)LJXUH 1. $SSO\SRZHU5(6(7?LVUHFRPPHQGHGWREHEHORZ[9DD4GXULQJSRZHUUDPSWRHQVXUHWKHRXWSXWVUHPDLQGLVDEOHG+,*+=DQG 2'7RII5TTLVDOVR+,*+=$OORWKHULQSXWVLQFOXGLQJ2'7PD\EHXQGHILQHG 'XULQJSRZHUXSHLWKHURIWKHIROORZLQJFRQGLWLRQVPD\H[LVWDQGPXVWEHPHW xCondition A: x9DDDQG9DD4DUHGULYHQIURPDVLQJOHSRZHUVRXUFHDQGDUHUDPSHGZLWKDPD[LPXPGHOWDYROWDJHEHWZHHQWKHPRI'9dP9 6ORSHUHYHUVDORIDQ\SRZHUVXSSO\VLJQDOLVDOORZHG7KHYROWDJHOHYHOVRQDOOEDOOVRWKHUWKDQ9DD9DD49VVDQG9VV4PXVWEH OHVVWKDQRUHTXDOWR9DD4DQG9DDRQRQHVLGHDQGPXVWEHJUHDWHUWKDQRUHTXDOWR9VV4DQG9VVRQWKHRWKHUVLGH x%RWK9DDDQG9DD4SRZHUVXSSOLHVUDPSWR9DD0,1DQG9DD40,1ZLWKLQt9DD35 PV x%RWK9DDDQG9DD4SRZHUVXSSOLHVUDPSWR9DD0,1DQG9DD40,1ZLWKLQt9DD35 PV x95()'4WUDFNV9DD[95()&$WUDFNV9DD[ x9TTLVOLPLWHGWR9ZKHQWKHSRZHUUDPSLVFRPSOHWHDQGLVQRWDSSOLHGGLUHFWO\WRWKHGHYLFHKRZHYHUt97'VKRXOGEH JUHDWHUWKDQRUHTXDOWR]HURWRDYRLGGHYLFHODWFKXS x&RQGLWLRQ% x9DDPD\EHDSSOLHGEHIRUHRUDWWKHVDPHWLPHDV9DDQ. x9DD4PD\EHDSSOLHGEHIRUHRUDWWKHVDPHWLPHDV9TT95()'4DQG95()&$. x1RVORSHUHYHUVDOVDUHDOORZHGLQWKHSRZHUVXSSO\UDPSIRUWKLVFRQGLWLRQ 2. 8QWLOVWDEOHSRZHUPDLQWDLQ5(6(7?/2:WRHQVXUHWKHRXWSXWVUHPDLQGLVDEOHG+,*+=$IWHUWKHSRZHULVVWDEOH5(6(7?PXVWEH /2:IRUDWOHDVWVWREHJLQWKHLQLWLDOL]DWLRQSURFHVV2'7ZLOOUHPDLQLQWKH+,*+=VWDWHZKLOH5(6(7?LV/2:DQGXQWLO&.(LV UHJLVWHUHG+,*+ 3. &.(PXVWEH/2:QVSULRUWR5(6(7?WUDQVLWLRQLQJ+,*+ 4. $IWHU5(6(7?WUDQVLWLRQV+,*+ZDLWVPLQXVRQHFORFNZLWK&.(/2: 5. $IWHUWKLV&.(/2:WLPH&.(PD\EHEURXJKW+,*+V\QFKURQRXVO\DQGRQO\123RU'(6FRPPDQGVPD\EHLVVXHG7KHFORFNPXVWEH SUHVHQWDQGYDOLGIRUDWOHDVWQVDQGDPLQLPXPRIILYHFORFNVDQG2'7PXVWEHGULYHQ/2:DWOHDVWW,6SULRUWR&.(EHLQJUHJLVWHUHG +,*+:KHQ&.(LVUHJLVWHUHG+,*+LWPXVWEHFRQWLQXRXVO\UHJLVWHUHG+,*+XQWLOWKHIXOOLQLWLDOL]DWLRQSURFHVVLVFRPSOHWH 6. $IWHU&.(LVUHJLVWHUHG+,*+DQGDIWHUt;35KDVEHHQVDWLVILHG056FRPPDQGVPD\EHLVVXHG,VVXHDQ056/2$'02'(FRPPDQG WR05ZLWKWKHDSSOLFDEOHVHWWLQJVSURYLGH/2:WR%$DQG%$DQG+,*+WR%$ ,VVXHDQ056FRPPDQGWR05ZLWKWKHDSSOLFDEOHVHWWLQJV 8. ,VVXHDQ056FRPPDQGWR05ZLWKWKHDSSOLFDEOHVHWWLQJVLQFOXGLQJHQDEOLQJWKH'//DQGFRQILJXULQJ2'7 9. ,VVXHDQG056FRPPDQGWR05ZLWKWKHDSSOLFDEOHVHWWLQJVLQFOXGLQJD'//5(6(7FRPPDQG t'//.F\FOHVRIFORFNLQSXWDUH UHTXLUHGWRORFNWKH'// 10. ,VVXHD=4&/FRPPDQGWRFDOLEUDWH5TTDQG521YDOXHVIRUWKHSURFHVVYROWDJHWHPSHUDWXUH3973ULRUWR1250$/RSHUDWLRQt=4,1,7 PXVWEHVDWLVILHG 11. :KHQtDLLK and t=4,1,7KDYHEHHQVDWLVILHGWKH''56'5$0ZLOOEHUHDG\IRUQRUPDORSHUDWLRQ LOGIC Devices Incorporated www.logicdevices.com 82 High Performance, Integrated Memory Module Product May 3, 2012 LDS-L9D364M64SBG2-G L9D364M64SBG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) FIGURE 41- INITIALIZATION SEQUENCE T (MAX) = 200ms VDD VDDQ VTT See power-up c onditions in the initialization sequence text, set up 1 VREF Power-up ramp t VTD Sta ble and vali d clo ck T0 T1 t CK Tc0 Tb0 Ta0 Td0 CK# CK t CKSRX t CL t CL t IOz = 20ns RESET# t IS T (MIN) = 10ns Valid CKE Valid ODT t IS Command NOP MRS MRS MRS MRS ZQCL Add ress Code Code Code Code A10 Code Code Code Code BA0 = L BA1 = H BA2 = L BA0 = H BA1 = H BA2 = L BA0 = H BA1 = L BA2 = L BA0 = L BA1 = L BA2 = L Valid DM BA[2:0] Valid Valid A10 = H Valid DQS DQ RTT T = 200μs (MIN) T = 500μs (MIN) MR2 All voltage supplies valid and stable t MRD t MRD t MRD t XPR MR3 MR1 with DLL ena ble t MOD MR0 with DLL reset t ZQ INIT ZQ cali bration t DLLK DRAM ready for external commands Normal operation Indicates a Break in Time Scale LOGIC Devices Incorporated www.logicdevices.com 83 Don ’t Care High Performance, Integrated Memory Module Product May 3, 2012 LDS-L9D364M64SBG2-G L9D364M64SBG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) MODE REGISTERS 0RGHUHJLVWHUV0505DUHXVHGWRGHILQHYDULRXVPRGHVRISURJUDPPDEOHRSHUDWLRQRIWKH''56'5$0L02'$PRGHUHJLVWHULVSURJUDPPHGYLD WKH02'(5(*,67(56(7056FRPPDQGGXULQJLQLWLDOL]DWLRQDQGLWUHWDLQVWKHVWRUHGLQIRUPDWLRQH[FHSWIRU05>@ZKLFKLVVHOIFOHDULQJXQWLOLWLVHLWKHU UHSURJUDPPHG5(6(7?JRHV/2:RUXQWLOWKHGHYLFHORVHVSRZHU &RQWHQWVRIDPRGHUHJLVWHUFDQEHDOWHUHGE\UHH[HFXWLQJWKH056FRPPDQG,IWKHXVHUFKRRVHVWRPRGLI\RQO\DVXEVHWRIWKHPRGHUHJLVWHUuVYDULDEOHV DOOYDULDEOHVPXVWEHSURJUDPPHGZKHQWKH056FRPPDQGLVLVVXHG5HSURJUDPPLQJWKHPRGHUHJLVWHUZLOOQRWDOWHUWKHFRQWHQWVRIWKHPHPRU\DUUD\ SURYLGHGLWLVSHUIRUPHGFRUUHFWO\ 7KH056FRPPDQGFDQRQO\EHLVVXHGRUUHLVVXHGZKHQDOOEDQNVDUHLGOHDQGLQWKH35(&+$5*('VWDWHt53LVVDWLVILHGDQGQRGDWDEXUVWVDUHLQSURJUHVV$IWHUDQ056FRPPDQGKDVEHHQLVVXHGWZRSDUDPHWHUVPXVWEHVDWLVILHGtMRD and tMOD. 7KHFRQWUROOHUPXVWZDLWt05'EHIRUHLQLWLDWLQJDQ\VXEVHTXHQW056FRPPDQGVVHH)LJXUH FIGURE 42- MRS-TO-MRS COMMAND TIMING (tMRD) T0 T1 T2 Ta0 Ta1 Ta2 MRS1 NOP NOP NOP NOP MRS2 CK# CK Command t MRD Add ress Valid Valid CKE 3 Indicates a Break in Time Scale Don ’t Care 127(6 1. 3ULRUWRLVVXLQJWKH056FRPPDQGDOOEDQNVPXVWEHLGOHDQGSUHFKDUJHGt530,1PXVWEHVDWLVILHG DQGQRGDWDEXUVWVFDQEHLQSURJUHVVWKHOHYHOLQJSURFHGXUH 2. t05'VSHFLILHVWKH056WR056FRPPDQGPLQLPXPF\FOHWLPH 3. &.( PXVW EH UHJLVWHUHG +,*+ IURP WKH 056 FRPPDQG XQWLO t0563'(1 0,1 VHH v3RZHU'RZQ 0RGHwRQSDJH 4. )RUD&$6ODWHQF\FKDQJHt;3'//WLPLQJPXVWEHPHWEHIRUHDQ\QRQ056FRPPDQG 7KHFRQWUROOHUPXVWDOVRZDLW t02'EHIRUHLQLWLDWLQJDQ\QRQ056FRPPDQGVH[FOXGLQJ123DQG'(6DVVKRZQLQ)LJXUHRQSDJH7KH'5$0 UHTXLUHVt02'LQRUGHUWRXSGDWHWKHUHTXHVWHGIHDWXUHVZLWKWKHH[FHSWLRQRI'//5(6(7ZKLFKUHTXLUHVDGGLWLRQDOWLPH8QWLOt02'KDVEHHQVDWLVILHGWKH XSGDWHGIHDWXUHVDUHWREHDVVXPHGXQDYDLODEOH LOGIC Devices Incorporated www.logicdevices.com 84 High Performance, Integrated Memory Module Product May 3, 2012 LDS-L9D364M64SBG2-G L9D364M64SBG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) FIGURE 43- MRS-TO-NONMRS COMMAND TIMING (tMOD) T1 T2 t WLS t WLH CK# CK Command MRS1 NOP2 NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP t MOD ODT t WLDQSEN t DQSL3 t DQSH3 t DQSL3 t DQSH3 Differential DQS4 t WLMRD t WLO t WLO Prime DQ 5 t WLO t WLOE Early remaining DQ t WLO Late remaining DQ Indicates a Break in Time Scale Undefined Driving Mode Don’t Care 127(6 1. 3ULRUWRLVVXLQJWKH056FRPPDQGDOOEDQNVPXVWEHLGOHWKH\PXVWEHSUHFKDUJHGt53PXVWEH VDWLVILHGDQGQRGDWDEXUVWVFDQEHLQSURJUHVV 2. 3ULRUWR7DZKHQt02'0,1LVEHLQJVDWLVILHGQRFRPPDQGVH[FHSW123'(6PD\EHLVVXHG 3. ,I577ZDVSUHYLRXVO\HQDEOHG2'7PXVWEHUHJLVWHUHG/2:DW7VRWKDW2'7/LVVDWLVILHGSULRU WR7D2'7PXVWDOVREHUHJLVWHUHG/2:DWHDFKULVLQJ&.HGJHIURP7XQWLO t02'0,1LV VDWLVILHGDW7D 4. &.( PXVW EH UHJLVWHUHG +,*+ IURP WKH 056 FRPPDQG XQWLO t0563'(1 0,1 DW ZKLFK WLPH SRZHUGRZQPD\RFFXUVHHv3RZHU'RZQ0RGHwRQSDJH MODE REGISTER 0 (MR0) 7KHEDVHUHJLVWHU05LVXVHGWRGHILQHYDULRXV''5L02'PRGHVRIRSHUDWLRQ7KHVHGHILQLWLRQVLQFOXGHWKHVHOHFWLRQRIDEXUVWOHQJWKEXUVWW\SH&$6 ODWHQF\RSHUDWLQJPRGH'//5(6(7:5,7(UHFRYHU\DQG35(&+$5*(SRZHUGRZQPRGHDVVKRZQLQ)LJXUH LOGIC Devices Incorporated www.logicdevices.com 85 High Performance, Integrated Memory Module Product May 3, 2012 LDS-L9D364M64SBG2-G L9D364M64SBG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) MODE REGISTER 0 (MR0) BURST TYPE BURST LENGTH $FFHVVHVZLWKLQDJLYHQEXUVWPD\EHSURJUDPPHGWRHLWKHUDVHTXHQWLDO RUDQLQWHUOHDYHGRUGHU7KHEXUVWW\SHLVVHOHFWHGYLD05>@DVVKRZQ LQ)LJXUH7KHRUGHULQJRIDFFHVVHVZLWKLQDEXUVWLVGHWHUPLQHGE\WKH EXUVW OHQJWK WKH EXUVW W\SH DQG WKH VWDUWLQJ FROXPQ DGGUHVV DV VKRZQ LQ7DEOH''5RQO\VXSSRUWVELWEXUVWFKRSDQGELWEXUVWDFFHVV PRGHV )XOO LQWHUOHDYHGDGGUHVV RUGHULQJ LVVXSSRUWHG IRU5($'VZKLOH :5,7(VDUHUHVWULFWHGWRQLEEOH%&RUZRUG%/ERXQGDULHV %XUVW OHQJWK LV GHILQHG E\ 05>@ VHH )LJXUH 5($' DQG :5,7( DFFHVVHV WR WKH ''5 6'5$0 L02' DUH EXUVWRULHQWHG ZLWK WKH EXUVW OHQJWKEHLQJSURJUDPPDEOHWRvwFKRSPRGHvwIL[HGEXUVWRUVHOHFWDEOH XVLQJ $ GXULQJ D 5($':5,7( FRPPDQG RQ WKH IO\ 7KH EXUVW OHQJWK GHWHUPLQHV WKH PD[LPXP QXPEHU RI FROXPQ ORFDWLRQV WKDW FDQ EH DFFHVVHGIRUDJLYHQ5($'RU:5,7(FRPPDQG:KHQ05>@LVVHWWR vwGXULQJD5($':5,7(FRPPDQGLI$ WKHQ%&FKRSPRGHLV VHOHFWHG,I$ WKHQ%/PRGHLVVHOHFWHG6SHFLILFWLPLQJGLDJUDPV DQG WXUQDURXQG EHWZHHQ 5($':5,7( DUH VKRZQ LQ WKH 5($':5,7( VHFWLRQVRIWKLVGRFXPHQW :KHQ D 5($' RU :5,7( FRPPDQG LV LVVXHG D EORFN RI FROXPQV HTXDO WRWKHEXUVWOHQJWKLVHIIHFWLYHO\VHOHFWHG$OODFFHVVHVIRUWKDWEXUVWWDNH SODFHZLWKLQWKLVEORFNPHDQLQJWKDWWKHEXUVWZLOOZUDSZLWKLQWKHEORFNLI DERXQGDU\LVUHDFKHG7KHEORFNLVXQLTXHO\VHOHFWHGE\$>L@ZKHQWKH EXUVW OHQJWK LV VHW WR vw DQG E\ $>L@ ZKHQ WKH EXUVW OHQJWK LV VHW WR vw ZKHUH$LLVWKHPRVWVLJQLILFDQWFROXPQDGGUHVVELWIRUDJLYHQVWDUWLQJORFDWLRQZLWKLQWKHEORFN7KHSURJUDPPHGEXUVWOHQJWKDSSOLHVWRERWK5($' DQG:5,7(EXUVWV FIGURE 44- MODE REGISTER 0 (MR0) DEFINITIONS BA2 BA 1 BA 0 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address bus 16 15 14 13 12 11 10 0 0 01 PD WR Mode register 0 (MR0) 9 01 M15 M14 8 7 6 5 4 3 2 DLL 01 CAS# latency BT 01 1 0 BL M1 M0 Mode Register 0 0 0 1 Burst Length Fixed BL8 0 0 Mode register 0 (MR0) 0 1 Mode register 1 (MR1) M12 Precharge PD 1 0 Mode register 2 (MR2) 0 DLL off (slow exit) 0 No 1 0 Fixed BC4 (chop) 1 1 Mode register 3 (MR3) 1 DLL on (fast exit) 1 Yes 1 1 Reserved LOGIC Devices Incorporated Write Recovery M6 M5 M4 4 or 8 (on-the-fly via A12) CAS Latency M3 READ Burst Type 0 0 0 Reserved 0 0 0 Reserved 0 Sequential (nibble) 0 0 1 5 0 0 1 5 1 Interleaved 0 1 0 6 0 1 0 6 0 1 1 7 0 1 1 7 1 0 0 8 1 0 0 8 1 0 1 10 1 0 1 9 1 1 0 12 1 1 0 10 1 1 1 Reserved 1 1 1 11 M11 M10 M9 Notes: M8 DLL Reset 1. MR0[16, 13, 7, 2] are reserved for future use and must be programmed to “0.” www.logicdevices.com 86 High Performance, Integrated Memory Module Product May 3, 2012 LDS-L9D364M64SBG2-G L9D364M64SBG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) TABLE 60: BURST ORDER Burst Length Read/Write &+23 Starting Column Address (A[2,1,0]) 5($' :5,7( 8 5($' :5,7( 000 001 Burst Type (Decimal) Type = Sequential Type = Interleaved ==== 1,2 ==== ==== 1,2 010 ==== ==== 1,2 011 ==== ==== 1,2 100 ==== ==== 1,2 101 ==== ==== 1,2 110 ==== ==== 1,2 111 ==== ==== 1,2 99 ;;;; ;;;; 1,3,4 99 ;;;; ;;;; 1,3,4 000 1 001 1 010 1 011 1 100 1 101 1 110 1 111 1 1,3 999 127(6 1. ,QWHUQDO5($'DQG:5,7(RSHUDWLRQVVWDUWDWWKHVDPHSRLQWLQWLPHIRU %&DVWKH\GRIRU%/ DLL RESET 2. = 'DWDDQG6WUREHRXWSXWGULYHUVLQWULVWDWH 3. ; w'RQuW&DUHw WRITE RECOVERY '//5(6(7LVGHILQHGE\05>@VHH)LJXUH3URJUDPPLQJ05>@ WRvwDFWLYDWHVWKH'//5(6(7IXQFWLRQ05>@LVVHOIFOHDULQJPHDQLQJ LW UHWXUQV WR D YDOXH RI vw DIWHU WKH '// 5(6(7 IXQFWLRQ KDV EHHQ initiated. :5,7(5(&29(5<WLPHLVGHILQHGE\05>@VHH)LJXUH:5,7( 5(&29(5< YDOXHV RI RU PD\ EH XVHG E\ SURJUDPPLQJ 05>@7KHXVHULVUHTXLUHGWRSURJUDPWKHFRUUHFWYDOXHRI:5,7( 5(&29(5<DQGLVFDOFXODWHGE\GLYLGLQJt:5QVE\t&.QVDQGURXQGLQJ XS D QRQLQWHJHU YDOXH WR WKH QH[W LQWHJHU :5 F\FOHV URXQGXS t:5>QV@t&.>QV@ $Q\WLPHWKH'//5(6(7IXQFWLRQKDVEHHQLQLWLDWHG&.(PXVWEH+,*+ DQG WKH FORFN KHOG VWDEOH IRU t'//. FORFN F\FOHV EHIRUH D 5($' FRPPDQGFDQEHLVVXHG7KLVLVWRDOORZWLPHIRUWKHLQWHUQDOFORFNWREH V\QFKURQL]HGZLWKWKHH[WHUQDOFORFN)DLOLQJWRZDLWIRUV\QFKURQL]DWLRQ WRRFFXUPD\UHVXOWLQLQYDOLGRXWSXWWLPLQJVSHFLILFDWLRQVVXFKDVt'46&. WLPLQJV LOGIC Devices Incorporated Notes ==== www.logicdevices.com High Performance, Integrated Memory Module Product May 3, 2012 LDS-L9D364M64SBG2-G L9D364M64SBG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) CAS Latency (CL) PRECHARGE POWER-DOWN (PRECHARGE PD) 7KH35(&+$5*(3'ELWDSSOLHVRQO\ZKHQ35(&+$5*(SRZHUGRZQ PRGHLVEHLQJXVHG:KHQ05>@LVVHWWRvwWKH'//LVRIIGXULQJ 35(&+$5*(SRZHUGRZQSURYLGLQJDORZHUVWDQGE\FXUUHQWPRGHKRZHYHU t;3'// PXVW EH VDWLVILHG ZKHQ H[LWLQJ :KHQ 05>@ LV VHW WR vwWKH'//FRQWLQXHVWRUXQGXULQJ35(&+$5*(SRZHUGRZQPRGHWR HQDEOH D IDVWHU H[LW RI 35(&+$5*( SRZHUGRZQ PRGH KRZHYHU t;3 PXVWEHVDWLVILHGZKHQH[LWLQJVHH3RZHU'RZQPRGHRQ3DJH 7KH&/LVGHILQHGE\05>@DVVKRZQLQ)LJXUH&$6ODWHQF\LVWKH GHOD\DVPHDVXUHGLQFORFNF\FOHVEHWZHHQWKHLQWHUQDO5($'FRPPDQG DQGWKHDYDLODELOLW\RIWKHILUVWELWRIYDOLGRXWSXWGDWD7KH&/FDQEHVHW WRRU''56'5$0L02'VGRQRWVXSSRUWKDOIFORFNODWHQFLHV ([DPSOHVRI&/ DQG&/ DUHVKRZQLQ)LJXUHEHORZ,IDQLQWHUQDO 5($'FRPPDQGLVUHJLVWHUHGDWFORFNHGJHQDQGWKH&$6ODWHQF\LVP FORFNVWKHGDWDZLOOEHDYDLODEOHQRPLQDOO\FRLQFLGHQWZLWKFORFNHGJHQP 7DEOHLQGLFDWHVWKH&/VVXSSRUWHGDWDYDLODEOHRSHUDWLQJIUHTXHQFLHV FIGURE 45- READ LATENCY T0 T1 T2 T3 T4 T5 T6 T7 T8 READ NOP NOP NOP NOP NOP NOP NOP NOP CK# CK Command AL = 0, CL = 6 DQS, DQS# DI n DQ DI n+1 DI n+2 DI n+3 DI n+4 T0 T1 T2 T3 T4 T5 T6 T7 T8 READ NOP NOP NOP NOP NOP NOP NOP NOP CK# CK Command AL = 0, CL = 8 DQS, DQS# DI n DQ Transitioning Data Don’t Care 127(6 1. )RULOOXVWUDWLRQSXUSRVHVRQO\&/ DQG&/ DUHVKRZQ2WKHU&/YDOXHVDUH SRVVLEOH 2. LOGIC Devices Incorporated 6KRZQZLWKQRPLQDOt'46&.DQGQRPLQDOtDSDQ. www.logicdevices.com 88 High Performance, Integrated Memory Module Product May 3, 2012 LDS-L9D364M64SBG2-G L9D364M64SBG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) MODE REGISTER 1 (MR1) 7KH 02'( 5(*,67(5 05 FRQWUROV DGGLWLRQDO IXQFWLRQV DQG IHDWXUHV QRW DYDLODEOH LQ WKH RWKHU PRGH UHJLVWHUV 4 2)) 287387 ',6$%/( '// (1$%/('//',6$%/(5TTB120YDOXH2'7:5,7(/(9(/,1*3267('&$6$'',7,9(ODWHQF\DQG287387'5,9(675(1*7+7KHVHIXQFWLRQV DUHFRQWUROOHGYLDWKHELWVVKRZQLQ)LJXUHEHORZ7KH05UHJLVWHULVSURJUDPPHGYLDWKH05FRPPDQGDQGUHWDLQVWKHVWRUHGLQIRUPDWLRQXQWLOLWLV UHSURJUDPPHGXQWLO5(6(7?JRHV/2:WUXHRUXQWLOWKHGHYLFHORVHVSRZHU5HSURJUDPPLQJWKH05UHJLVWHUZLOOQRWDOWHUWKHFRQWHQWVRIWKHPHPRU\ DUUD\SURYLGHGWKHRSHUDWLRQLVSHUIRUPHGFRUUHFWO\ 7KH05UHJLVWHUPXVWEHORDGHGZKHQDOOEDQNVDUHLGOHDQGQREXUVWVDUHLQSURJUHVV7KHFRQWUROOHUPXVWVDWLVI\WKHVSHFLILHGWLPLQJSDUDPHWHUVtMRD and t02'EHIRUHLQLWLDWLQJDVXEVHTXHQWRSHUDWLRQ FIGURE 46- MODE REGISTER 1 (MR1) DEFINITION BA2 BA 1 BA 0 A13 A12 A11 A10 A9 A 8 A7 A6 A5 A4 A3 A 2 A1 A0 Address bus 16 15 14 13 12 11 10 9 8 7 6 5 01 0 1 01 Q Off TDQS 01 RTT 01 WL RTT ODS M15 M14 4 3 2 1 0 AL RTT ODS DLL Mode register 1 (MR1) Mode Register 0 0 Mode register set 0 (MR0) M12 Q Off M11 TDQS 0 1 Mode register set 1 (MR1) 0 Enabled 0 Disabled 1 0 Mode register set 2 (MR2) 1 Disabled 1 Enabled 1 1 Mode register set 3 (MR3) RTT_NOM (ODT)2 M0 DLL Enable 0 Enable (normal) 1 Disable M5 M1 Output Drive Strength RTT_NOM (ODT)3 M7 Write Levelization M9 M6 M2 Non-Writes Writes 0 Disable (normal) 0 0 0 RTT_NOM disabled RTT_NOM disabled 1 Enable 0 0 1 RZQ/4 (60Ω [NOM]) RZQ/4 (60Ω [NOM]) 0 0 RZQ/6 (40Ω [NOM]) 0 1 RZQ/7 (34Ω [NOM]) 1 0 Reserved 1 1 Reserved 0 1 0 RZQ/2 (120Ω [NOM]) RZQ/2 (120Ω [NOM]) 0 1 1 RZQ/6 (40Ω [NOM]) RZQ/6 (40Ω [NOM]) M4 M3 Additive Latency (AL) 1 0 0 RZQ/12 (20Ω [NOM]) n/a 0 0 Disabled (AL = 0) 1 0 1 RZQ/8 (30Ω [NOM]) n/a 0 1 AL = CL - 1 1 1 0 Reserved Reserved 1 0 AL = CL - 2 1 1 1 Reserved Reserved 1 1 Reserved 127(6 1. 2. 05>@DUHUHVHUYHGIRUIXWXUHXVHDQGPXVWEHSURJUDPPHGWRvw 'XULQJZULWHOHYHOLQJLI05>@DQG05>@DUHvwWKHQDOO5TTB120YDOXHVDUHDYDLODEOH IRUXVH 3. 'XULQJZULWHOHYHOLQJLI05>@LVDvwEXW05>@LVDvwWKHQRQO\5TTB120ZULWHYDOXHV DUHDYDLODEOHIRUXVH LOGIC Devices Incorporated www.logicdevices.com 89 High Performance, Integrated Memory Module Product May 3, 2012 LDS-L9D364M64SBG2-G L9D364M64SBG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) ON-DIE TERMINATION (ODT) DLL ENABLE/DLL DISABLE 7KH'//PD\EHHQDEOHGRUGLVDEOHGE\SURJUDPPLQJ05>@GXULQJWKH /2$' 02'( FRPPDQG DV VKRZQ LQ )LJXUH SUHYLRXV SDJH 7KH '//PXVWEHHQDEOHGIRU1250$/RSHUDWLRQ'//(1$%/(LVUHTXLUHG GXULQJSRZHUXSLQLWLDOL]DWLRQDQGXSRQUHWXUQLQJWR1250$/RSHUDWLRQ DIWHUKDYLQJ',6$%/('WKH'//IRUWKHSXUSRVHRIGHEXJJLQJRUHYDOXDWLRQ(1$%/,1*WKH'//VKRXOGDOZD\VEHIROORZHGE\UHVHWWLQJWKH'// XVLQJWKHDSSURSULDWH/2$'02'(FRPPDQG 2'7UHVLVWDQFH5TTB120LVGHILQHGE\05>@VHH)LJXUH7KH RTT WHUPLQDWLRQ YDOXH DSSOLHV WR WKH '4[ /'0[ 8'0[ />8@'46[ DQG />8@'46[?7KH''5GHYLFHDUFKLWHFWXUHVXSSRUWVPXOWLSOH5TTWHUPLQDWLRQYDOXHVEDVHGRQ5=4QZKHUHQFDQEHRUDQG5=4LV:. 8QOLNH''5''52'7PXVWEHWXUQHGRIISULRUWR5($',1*GDWDRXW DQGPXVWUHPDLQRIIGXULQJ5($'EXUVW5TTB120WHUPLQDWLRQLVDOORZHG DQ\WLPHDIWHUWKH'5$0LVLQLWLDOL]HGFDOLEUDWHGDQGQRWSHUIRUPLQJ5($' DFFHVVHV RU LQ 6(/) 5()5(6+ PRGH $GGLWLRQDOO\ :5,7( DFFHVVHV ZLWKG\QDPLF2'7HQDEOHG5TTB:5WHPSRUDULO\UHSODFHV5TTB120ZLWK RTTB:5 ,IWKH'//LVHQDEOHGSULRUWRHQWHULQJ6(/)5()5(6+PRGHWKH'//LV DXWRPDWLFDOO\',6$%/('ZKHQHQWHULQJ6(/)5()5(6+RSHUDWLRQDQG LVDXWRPDWLFDOO\5((1$%/('DQG5(6(7XSRQH[LWRI6(/)5()5(6+ ,I WKH '// LV ',6$%/(' SULRU WR HQWHULQJ 6(/) 5()5(6+ WKH '// UHPDLQV',6$%/('HYHQXSRQH[LWRIWKH6(/)5()5(6+RSHUDWLRQXQWLO LWKDVEHHQ5((1$%/('DQG5(6(7 7KHDFWXDOHIIHFWLYHWHUPLQDWLRQ5TTB())PD\EHGLIIHUHQWIURPWKH5TT WDUJHWHGYDOXHGXHWRQRQOLQHDULW\RIWKHWHUPLQDWLRQ)RU5TTB())YDOXHV DQGFDOFXODWLRQVVHHWKH21',(7(50,1$7,212'7GHVFULSWLRQODWHU LQWKLV'6 7KH6'5$0LVQRWWHVWHGQRUGRHV/',ZDUUDQWFRPSOLDQFHZLWK1250$/ PRGHWLPLQJVRUIXQFWLRQDOLW\ZKHQWKH'//LVGLVDEOHG$QDWWHPSWKDV EHHQPDGHIRUWKH6'5$0WRRSHUDWHLQWKH1250$/PRGHZKHQHYHU SRVVLEOHZKHQWKH'//LVGLVDEOHGKRZHYHUE\LQGXVWU\VWDQGDUGVWKH IROORZLQJH[FHSWLRQVKDYHEHHQREVHUYHGGHILQHGDQGOLVWHG 7KH 2'7 IHDWXUH LV GHVLJQHG WR LPSURYH VLJQDO LQWHJULW\ RI WKH PHPRU\ GHYLFHE\HQDEOLQJWKH''56'5$0FRQWUROOHUWRLQGHSHQGHQWO\WXUQ21 2))2'7IRUDQ\RUDOOGHYLFHVLQWKHHQGGHVLJQVDUUD\7KH2'7LQSXW FRQWUROSLQLVXVHGWRGHWHUPLQHZKHQ5TT LVWXUQHGRQ2'7/RQDQGRII 2'7/RIIDVVXPLQJ2'7KDVEHHQ(1$%/('YLD05>@ 1. 2'7LV127$//2:('WREHXVHG 2. 7KH287387'$7$LVQRORQJHUHGJHDOLJQHGWRWKHFORFN 3. &/DQG&:/FDQRQO\EHVL[FORFNV 7LPLQJVIRU2'7DUHGHWDLOHGLQWKHv21',(7HUPLQDWLRQ2'7wGHVFULSWLRQODWHULQWKLV'6 :KHQWKH'//LV',6$%/('WLPLQJDQGIXQFWLRQDOLW\FDQYDU\IURPWKH 1250$/ RSHUDWLRQDO VSHFLILFDWLRQV ZKHQ WKH '// LV HQDEOHG ',6$%/,1*WKH'//DOVRLPSOLHVWKHQHHGWRFKDQJHWKHFORFNIUHTXHQF\ WRITE LEVELING OUTPUT DRIVE STRENGTH 7KH:5,7(/(9(/,1*IXQFWLRQLVHQDEOHGE\05>@DVVKRZQLQ)LJXUH :5,7(/(9(/,1*LVXVHGGXULQJLQLWLDOL]DWLRQWRGHVNHZWKH'46[ VWUREH WR FORFN RIIVHW DV D UHVXOW RI IO\E\ WRSRORJ\ GHVLJQV )RU EHWWHU VLJQDO LQWHJULW\ VRPH HQG XVH GHVLJQV RI ''5 GHYLFHV DGRSWHG IO\E\ WRSRORJ\IRUWKHFRPPDQGVDGGUHVVHVFRQWUROVLJQDOVDQGFORFNV 7KH ''5 6'5$0 L02' XVHV D SURJUDPPDEOH LPSHGDQFH RXWSXW EXIIHU7KHGULYHVWUHQJWKPRGHUHJLVWHUVHWWLQJLVGHILQHGE\05>@ 5=4:>120@LVWKHSULPDU\RXWSXWGULYHULPSHGDQFHVHWWLQJIRUWKH GHYLFH7RFDOLEUDWHWKHRXWSXWGULYHULPSHGDQFHDQGH[WHUQDOSUHFLVLRQ UHVLVWRU5=4LVFRQQHFWHGEHWZHHQWKH=4EDOODQG9VV47KHYDOXHRI WKHUHVLVWRULV: 7KH IO\E\ WRSRORJ\ EHQHILWV IURP D UHGXFHG QXPEHU RI VWXEV DQG WKHLU OHQJWKV KRZHYHU IO\E\ WRSRORJ\ LQGXFHV IOLJKW WLPH VNHZ EHWZHHQ WKH FORFNDQG'46[VWUREHDQG'4[DWHDFK6'5$0LQWKHDUUD\&RQWUROOHUVZLOOKDYHDGLIILFXOWWLPHPDLQWDLQLQJtDQSS, tDSS and t'6+VSHFLILFDWLRQVZLWKRXWVXSSRUWLQJ:5,7(/(9(/,1*LQV\VWHPVZKLFKXVHIO\E\ WRSRORJ\EDVHGGHVLJQV:5,7(/(9(/,1*WLPLQJDQGGHWDLOHGRSHUDWLRQ LQIRUPDWLRQLVSURYLGHGLQv:5,7(/(9(/,1* 7KHRXWSXWLPSHGDQFHLVVHWGXULQJLQLWLDOL]DWLRQ$GGLWLRQDOLPSHGDQFH FDOLEUDWLRQXSGDWHVGRQRWDIIHFWGHYLFHRSHUDWLRQDQGDOOGDWDVKHHWWLPLQJVDQGFXUUHQWVSHFLILFDWLRQVDUHPHWGXULQJDQXSGDWH 7RPHHWWKH:VSHFLILFDWLRQWKHRXWSXWGULYHVWUHQJWKPXVWEHVHWWR 34:GXULQJLQLWLDOL]DWLRQ7RREWDLQDFDOLEUDWHGRXWSXWGULYHULPSHGDQFH DIWHUSRZHUXSWKH''5L02'6'5$0QHHGVDFDOLEUDWLRQFRPPDQG WKDWLVSDUWRIWKHLQLWLDOL]DWLRQDQGUHVHWSURFHGXUH OUTPUT ENABLE/DISABLE 7KH 287387 (1$%/( IXQFWLRQ LV GHILQHG E\ 05>@ DV VKRZQ LQ )LJXUH:KHQHQDEOHG05>@ DOORXWSXWV'4['46['46[? DUHWULVWDWHG7KHRXWSXW',6$%/(IHDWXUHLVLQWHQGHGWREHXVHGGXULQJ IDD FKDUDFWHUL]DWLRQ RI WKH 5($' FXUUHQW DQG GXULQJ t'466 PDUJLQLQJ :5,7(/(9(/,1*RQO\ LOGIC Devices Incorporated www.logicdevices.com 90 High Performance, Integrated Memory Module Product May 3, 2012 LDS-L9D364M64SBG2-G L9D364M64SBG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) POSTED CAS ADDITIVE LATENCY (AL) $/LVVXSSRUWHGWRPDNHWKHFRPPDQGDQGGDWDEXVHIILFLHQWIRUVXVWDLQDEOHEDQGZLGWKVLQ''565$0V05>@GHILQHWKHYDOXHRI$/VHH)LJXUH 05>@HQDEOHVWKHXVHUWRSURJUDPWKH''56'5$0ZLWKDQ$/ &/RU&/ :LWKWKLVIHDWXUHWKH''56'5$0HQDEOHVD5($'RU:5,7(FRPPDQGWREHLVVXHGDIWHUWKH$&7,9$7(FRPPDQGIRUWKDWEDQNSULRUWRt5&'0,17KH RQO\UHVWULFWLRQLV$&7,9$7(WR5($'RU:5,7($/t t5&'0,1PXVWEHVDWLVILHG$VVXPLQJt5&'0,1 &/DW\SLFDODSSOLFDWLRQXVLQJWKLVIHDWXUHVHWV $/ &/yt&. t5&'0,1t&.7KH5($'RU:5,7(FRPPDQGLVKHOGIRUWKHWLPHRIWKH$/EHIRUHLWLVUHOHDVHGLQWHUQDOO\WRWKH''56'5$0L02' GHYLFH5($'ODWHQF\5/LVFRQWUROOHGE\WKHVXPRIWKH$/DQG&$6ODWHQF\&/5/ $/&/:5,7(ODWHQF\:/LVWKHVXPRI&$6:5,7(ODWHQF\DQG $/:/ $/&:/VHHv02'(5(*,67(505w([DPSOHVRI5($'DQG:5,7(ODWHQFLHVDUHVKRZQLQ)LJXUHDQG)LJXUH FIGURE 47- READ LATENCY (AL = 5, CL = 6) BC4 T0 T1 ACTIVE n READ n T2 T6 T11 T12 T13 T14 NOP NOP NOP NOP NOP NOP CK# CK Command t RCD (MIN) DQS, DQS# AL = 5 CL = 6 DO n DQ DO n+1 DO n+2 DO n+3 RL = AL + CL = 11 Indicates a Break in Time Scale LOGIC Devices Incorporated www.logicdevices.com 91 Transitioning Data Don’t Care High Performance, Integrated Memory Module Product May 3, 2012 LDS-L9D364M64SBG2-G L9D364M64SBG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) MODE REGISTER 2 (MR2) 7KH02'(5(*,67(505FRQWUROVDGGLWLRQDOIXQFWLRQVDQGIHDWXUHVQRWDYDLODEOHLQWKHRWKHUPRGHUHJLVWHUV7KHVHDGGLWLRQDOIXQFWLRQVDUH&$6 :5,7(ODWHQF\&:/$8726(/)5()5(6+$656(/)5()5(6+7(03(5$785(657DQG'<1$0,&2'75TTB:57KHVHIXQFWLRQVDUHFRQWUROOHGYLDWKHELWVVKRZQLQ)LJXUH7KH05LVSURJUDPPHGYLDWKH056FRPPDQGDQGZLOOUHWDLQWKHVWRUHGLQIRUPDWLRQXQWLOLWLVSURJUDPPHGDJDLQRU XQWLOWKHGHYLFHORVHVSRZHU5HSURJUDPPLQJWKH05UHJLVWHUZLOOQRWDOWHUWKHFRQWHQWVRIWKHPHPRU\DUUD\SURYLGHGWKDWWKHRSHUDWLRQKDVEHHQSHUIRUPHG FRUUHFWO\7KH05UHJLVWHUPXVWEHORDGHGZKHQDOOEDQNVDUHLGOHDQGQRGDWDEXUVWVDUHLQSURJUHVVDQGWKHPHPRU\FRQWUROOHUPXVWZDLWIRUWKHVSHFLILHG WLPHtMRD and t02'EHIRUHLQLWLDWLQJDVXEVHTXHQWRSHUDWLRQ FIGURE 48- MODE REGISTER 2 (MR2) DEFINITION BA2 BA 1 BA 0 A13 A12 A11 A10 A9 A8 A7 A 6 A5 A4 A3 A2 A1 A0 Address bus 16 15 14 13 12 11 10 9 8 7 6 0 01 01 01 RTT_WR 01 SRT ASR Mode Register 2 (MR2) 5 01 1 M15 M14 Mode Register M5 M4 M3 2 1 0 01 01 01 CAS Write Latency (CWL) 5 CK (t CK ≥ 2.5ns) 0 Mode register set 0 (MR0) 0 Normal (0° C to 85° C) 0 0 0 0 1 Mode register set 1 (MR1) 1 Extended (0°C to 95° C) 0 0 1 1 0 Mode register set 2 (MR2) 0 1 0 6 CK (2.5ns > t CK ≥ 1.875ns) 7 CK (1.875ns > t CK ≥ 1.5ns) 1 1 Mode register set 3 (MR3) 0 1 1 8 CK (1.5ns > t CK ≥ 1.25ns) 1 0 0 Reserved 1 0 1 Reserved 1 1 0 Reserved 1 1 1 Reserved 0 LOGIC Devices Incorporated 3 0 M10 M9 Notes: M7 Self Refresh Temperature 4 CWL 0 Dynamic ODT ( R TT_WR ) RTT_WR disabled RZQ/4 0 1 1 0 RZQ/2 1 1 Reserved M6 0 Auto Self Refresh (Optional) Disabled: Manual 1 Enabled: Automatic 1. MR2[16, 13:11, 8, and 2:0] are reserved for future use and must all be programmed to “0.” www.logicdevices.com 92 High Performance, Integrated Memory Module Product May 3, 2012 LDS-L9D364M64SBG2-G L9D364M64SBG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) CAS WRITE LATENCY (CWL) &:/LVGHILQHGE\05>@DQGLVWKHGHOD\LQFORFNF\FOHVIURPWKHUHOHDVLQJRIWKHLQWHUQDO:5,7(WRWKHODWFKLQJRIWKHILUVWGDWDLQ&:/PXVWEHFRUUHFWO\ VHWWRWKHFRUUHVSRQGLQJRSHUDWLQJFORFNIUHTXHQF\VHH)LJXUH7KHRYHUDOO:5,7(/$7(1&<:/LVHTXDOWR&:/$/VHH)LJXUH FIGURE 49- CAS WRITE LATENCY BC4 T0 T1 ACTIVE n WRITE n T2 T6 T11 T12 T13 T14 NOP NOP NOP NOP NOP NOP CK# CK Command t RCD (MIN) DQS, DQS# AL = 5 CWL = 6 DI n DQ DI n+1 DI n+2 DI n+3 WL = AL + CWL = 11 Indicates A Break in Time Scale Transitioning Data Don’t Care RSWLRQDOH[WHQGHGWHPSHUDWXUHUDQJHRI&ZKLOHLQ6(/)5()5(6+ PRGH7KHVWDQGDUG6(/)5()5(6+FXUUHQWWHVWVSHFLILHVWHVWFRQGLWLRQV WRQRUPDODPELHQWWHPSHUDWXUH&RQO\PHDQLQJLI657LVHQDEOHGWKH VWDQGDUG6(/)5()5(6+FXUUHQWVSHFLILFDWLRQVGRQRWDSSO\ AUTO SELF REFRESH (ASR) 0RGHUHJLVWHU05>@LVXVHGWR',6$%/((1$%/(WKH$65IXQFWLRQ :KHQ$65LV',6$%/('WKH6(/)5()5(6+PRGHuV5()5(6+UDWH LVDVVXPHGWREHDWWKHQRUPDO&OLPLWFRPPRQO\UHIHUUHGWRDVWKH ;5()5(6+UDWH,QWKH',6$%/('PRGH$65UHTXLUHVWKHXVHUWR HQVXUHWKH6'5$0QHYHUH[FHHGVD7$RI&ZKLOHLQ6(/)5()5(6+ XQOHVVWKHXVHUHQDEOHVWKH657IHDWXUHOLVWHGEHORZVXSSRUWLQJDQHOHYDWHGWHPSXSWR&ZKLOHLQ6(/)5()5(6+ SRT vs. ASR ,IWKHQRUPDODPELHQWWHPSHUDWXUHOLPLWRI&LVQRWH[FHHGHGWKHQQHLWKHU 657 QRU $65 LV UHTXLUHG DQG ERWK FDQ EH ',6$%/(' WKURXJKRXW RSHUDWLRQ,IWKHH[WHQGHGWHPSHUDWXUHRSWLRQLVXVHGWKHXVHULVUHTXLUHG WR SURYLGH D ; UHIUHVK UDWH GXULQJ PDQXDO UHIUHVK IRU ([WHQGHG WHPS GHYLFHVRU;UHIUHVKUDWHIRU0LOWHPSGHYLFHV657DQG$65VKRXOGEH HQDEOHGIRUDXWRPDWLF5()5(6+VHUYLFHVRQDOOGHYLFHVXVHGLQWHPSHUDWXUHHQYLURQPHQWVd& 7KH VWDQGDUG 6(/) 5()5(6+ FXUUHQW WHVW VSHFLILHV WHVW FRQGLWLRQV WR QRUPDODPELHQWWHPSHUDWXUH&RQO\PHDQLQJLI$65LVHQDEOHGWKH VWDQGDUG6(/)5()5(6+FXUUHQWVSHFLILFDWLRQGRHVQRWDSSO\VHHWKH v(;7(1'('7(03(5$785(86$*(wGHVFULSWLRQODWHULQWKLV'6 657IRUFHVWKH6'5$0WRVZLWFKWKHLQWHUQDO6(/)5()5(6+UDWHIURP ;WR;6(/)5()5(6+LVSHUIRUPHGDW;UHJDUGOHVVRIT$. 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MODE REGISTER 3 (MR3) DEFINITION BA2 BA 1 BA 0 A13 A12 A11 A10 A9 16 01 A8 A7 A 6 A5 A4 A3 0 MPR Enable Normal DRAM operations 2 1 Mode register set 1 (MR1) 1 Dataflow from MPR 0 Mode register set 2 (MR2) 1 Mode register set 3 (MR3) 0 0 0 1 1 A1 A0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 1 01 01 01 01 01 01 01 01 01 01 01 MPR MPR_RF Mo de register set (MR0) M15 M14 A2 Mode Register M2 M1 M0 Address bus Mode register 3 (MR3) 0 0 MPR READ Function Predefined pattern 3 0 1 Reserved 1 0 Reserved 1 1 Reserved 127(6 LOGIC Devices Incorporated 1. 05>DQG@DUHUHVHUYHGIRUIXWXUHXVHDQGPXVWDOOEHSURJUDPPHGWRvw 2. :KHQ035FRQWUROLVVHWIRUQRUPDO'5$0RSHUDWLRQ05>@ZLOOEHLJQRUHG 3. ,QWHQGHGWREHXVHGIRU5($'V\QFKURQL]DWLRQ www.logicdevices.com 94 High Performance, Integrated Memory Module Product May 3, 2012 LDS-L9D364M64SBG2-G L9D364M64SBG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) MULTIPURPOSE REGISTER (MPR) 7KH08/7,385326(5(*,67(5IXQFWLRQLVXVHGWRRXWSXWDSUHGHILQHGV\VWHPWLPLQJFDOLEUDWLRQELWVHTXHQFH%LWLVWKHPDVWHUELWWKDWHQDEOHVRUGLVDEOHV DFFHVVWRWKH035UHJLVWHUDQGELWVDQGGHWHUPLQHZKLFKPRGHWKH035LVSODFHGLQ7KHEDVLFFRQFHSWRIWKHPXOWLSXUSRVHUHJLVWHULVVKRZQLQ)LJXUH ,I05>@LVDvwWKHQWKH035DFFHVVLVGLVDEOHGDQGWKH6'5$0RSHUDWHVLQQRUPDOPRGH+RZHYHULI05>@LVDvwWKHQ6'5$0QRORQJHURXWSXWV QRUPDOUHDGGDWDEXWRXWSXWV035GDWDDVGHILQHGE\05>@,I05>@LVHTXDOWRvwWKHQDSUHGHILQHGUHDGSDWWHUQIRUV\VWHPFDOLEUDWLRQLVVHOHFWHG 7RHQDEOHWKH035WKH056FRPPDQGLVLVVXHGWR05DQG05>@ VHH7DEOH3ULRUWRLVVXLQJWKH056FRPPDQGDOOEDQNVPXVWEHLQWKHLGOHVWDWH DOOEDQNVDUHSUHFKDUJHGDQGt53LVPHW:KHQWKH035LVHQDEOHGDQ\VXEVHTXHQW5($'RU5'$3FRPPDQGVDUHUHGLUHFWHGWRWKHPXOWLSXUSRVHUHJLVWHU 7KHUHVXOWLQJRSHUDWLRQZKHQHLWKHUD5($'RUD5'$3FRPPDQGLVLVVXHGLVGHILQHGE\05>@ZKHQ035LVHQDEOHGVHH7DEOH:KHQWKH035LV HQDEOHGRQO\5($'RU5'$3FRPPDQGVDUHDOORZHGXQWLODVXEVHTXHQW056FRPPDQGLVLVVXHGZLWKWKH035GLVDEOHG05>@ 32:(5'2:16(/) 5()5(6+DQGDQ\RWKHU1215($'RU5'$3FRPPDQGLVQRWDOORZHG7KH5(6(7IXQFWLRQLVVXSSRUWHGGXULQJ035HQDEOHPRGH FIGURE 51 - MULTIPURPOSE REGISTER (MPR) BLOCK DIAGRAM Memory core MR3[2] = 0 (MPR off) Multipurpose register pre defined data for READs MR3[2] = 1 (MPR on) DQ, DM, DQ S, DQS# 127(6 1. $SUHGHILQHGGDWDSDWWHUQFDQEHUHDGRXWRIWKH035ZLWKDQH[WHUQDO5($'FRPPDQG 2. 05>@GHILQHVZKHWKHUWKHGDWDIORZFRPHVIURPWKHPHPRU\FRUHRUWKH035:KHQWKHGDWD IORZ LV GHILQHG WKH 035 FRQWHQWV FDQ EH UHDG RXW FRQWLQXRXVO\ ZLWK D UHJXODU 5($' RU 5'$3 FRPPDQG LOGIC Devices Incorporated www.logicdevices.com 95 High Performance, Integrated Memory Module Product May 3, 2012 LDS-L9D364M64SBG2-G L9D364M64SBG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) TABLE 61: BURST ORDER MR3[2] MPR 0 MR3[1:0] MPR READ Function Function v'RQuW&DUHw 1RUPDO2SHUDWLRQQR035WUDQVDFWLRQ$OOVXEVHTXHQW5($'VFRPHIURP WKH6'5$0PHPRU\DUUD\$OOVXEVHTXHQW:5,7(VJRWRWKH6'5$0 PHPRU\DUUD\ 1 $>@6HH7DEOH (QDEOH035PRGHVXEVHTXHQW5($'5'$3FRPPDQGVGHILQHGE\ELWV and 2. MPR FUNCTIONAL DESCRIPTION 7KH035-('(&GHILQLWLRQDOORZVIRUHLWKHUDSULPH'4IRUORZHUE\WHDQG'4IRUWKHXSSHUE\WHRIHDFKRIWKHZRUGVFRQWDLQHGLQWKH/',L02'WRRXWSXW WKH035GDWDZLWKWKHUHPDLQLQJ'4VGULYHQ/2:RUIRUDOO'4VWRRXWSXWWKH035GDWD7KH035UHDGRXWVXSSRUWVIL[HG5($'EXUVWDQG5($'EXUVWFKRS 056DQG27)YLD$%&ZLWKUHJXODU5($'ODWHQFLHVDQG$&WLPLQJVDSSOLFDEOH7KLVSURYLGLQJWKH'//LVORFNHGDVUHTXLUHG 035DGGUHVVLQJIRUDYDOLG0355($'LVDVIROORZV x$>@PXVWEHVHWWRvwDVWKHEXUVWRUGHULVIL[HGSHUQLEEOH x$VHOHFWVWKHEXUVWRUGHU x%/$LVVHWWRvwDQGWKHEXUVWRUGHULVIL[HGWR x)RUEXUVWFKRSFDVHVWKHEXUVWRUGHULVVZLWFKHGRQWKHQLEEOHEDVHDQG x$ EXUVWRUGHU x$ EXUVWRUGHU x%XUVWRUGHUELWWKHILUVWELWLVDVVLJQHGWR/6%DQGEXUVWRUGHUELWWKHODVWELWLVDVVLJQHGWR06% x$>@DUHDv'RQuW&DUHw x$LVDv'RQuW&DUHw x$LVDv'RQuW&DUHw x$6HOHFWVEXUVWFKRSPRGHRQWKHIO\LIHQDEOHGZLWKLQ05 x$LVDv'RQuW&DUHw x%$>@DUHDv'RQuW&DUHw LOGIC Devices Incorporated www.logicdevices.com 96 High Performance, Integrated Memory Module Product May 3, 2012 LDS-L9D364M64SBG2-G L9D364M64SBG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) MPR REGISTER ADDRESS DEFINITIONS and BURSTING ORDER 7KH035FXUUHQWO\VXSSRUWVDVLQJOHGDWDIRUPDW7KLVGDWDIRUPDWLVDSUHGHILQHG5($'SDWWHUQIRUV\VWHPFDOLEUDWLRQ7KHSUHGHILQHGSDWWHUQLVDOZD\VD UHSHDWLQJELWSDWWHUQ ([DPSOHVRIWKHGLIIHUHQWW\SHRISUHGHILQHG5($'SDWWHUQEXUVWVDUHVKRZQLQ)LJXUHVDQG TABLE 62: BURST ORDER MR3[2] MR3[1:0] Function Burst Length 00 5($'SUHGHILQHGSDWWHUQIRU BL8 1 Read A[2:0] 000 Burst Order and Data Pattern %XUVW2UGHU 3UHGHILQHGSDWWHUQ V\VWHPFDOLEUDWLRQ %& 000 %XUVW2UGHU 3UHGHILQHGSDWWHUQ %& 100 %XUVW2UGHU 3UHGHILQHGSDWWHUQ 1 1 1 LOGIC Devices Incorporated 01 5)8 10 5)8 11 5)8 www.logicdevices.com QD QD QD QD QD QD QD QD QD QD QD QD QD QD QD QD QD QD QD QD QD QD QD QD QD QD QD High Performance, Integrated Memory Module Product May 3, 2012 LDS-L9D364M64SBG2-G LOGIC Devices Incorporated www.logicdevices.com 98 DQ Notes: 0 A [ 15:13] DQS, DQS# 0 A12/BC# 0 A10/AP 0 00 A[9:3] A 11 1 A2 1 0 MRS A[1:0] t RP Ta0 3 PREA T0 Bank add ress Command CK# CK NOP NOP Tc5 NOP Tc6 t MPRR MRS Tc7 0 0 Vali d 1 Val i d 0 0 00 Val i d Vali d Vali d 0 NOP Tc4 02 NOP Tc3 Vali d NOP Tc2 02 RL NOP Tc1 3 NOP Tc0 Vali d READ1 Tb1 1. READ with BL8 either by MRS or OTF. 2. Memory controller must drive 0 on A[2:0]. t MOD Tb0 Indicates a Break in Time Scale t MOD NOP Tc8 NOP Tc9 Don ’t Care Valid Tc10 L9D364M64SBG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) Figure 52 - MPR System Read Calibration with BL8: Fixed Burst Order Single Readout High Performance, Integrated Memory Module Product May 3, 2012 LDS-L9D364M64SBG2-G LOGIC Devices Incorporated www.logicdevices.com 99 DQ Notes: 0 A[15:13] DQS, DQS# 0 A12/BC# 0 A10/AP 0 00 A[9:3] A11 1 A2 1 0 MRS A[1:0] t RP Ta 3 PREA T0 Bank add ress Command CK# CK RL NOP Tc6 NOP Tc7 t MPRR NOP Tc9 Indicates a Break in Time Scale NOP Tc8 0 00 0 Vali d 3 MRS Tc10 Vali d RL Vali d 0 0 NOP Tc5 Vali d 1 NO Tc4 Vali d NOP Tc3 0 NOP Tc2 Vali d Vali d NOP Tc1 Vali d Vali d Vali d 12 02 Vali d 02 02 READ1 Vali d t CCD Vali d READ1 Tc0 1. READ with BL8 either by MRS or OTF. 2. Memory controller must drive 0 on A[2:0]. t MOD Tb Vali d Don ’t Care t MOD Td L9D364M64SBG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) Figure 53 - MPR System Read Calibration with BL8: Fixed Burst Order, Back-to-Back Readout High Performance, Integrated Memory Module Product May 3, 2012 LDS-L9D364M64SBG2-G LOGIC Devices Incorporated www.logicdevices.com 100 DQ DQS, DQS# Notes: 1. 2. 3. 4. Vali d 1 0 0 Vali d 1 Val i d 0 A 11 A12/BC# A[15:13] Vali d Val i d 0 1 RL Vali d NOP Tc1 NOP Tc2 RL NOP Tc3 READ with BC4 either by MRS or OTF. Memory controller must drive 0 on A[1:0]. A2 = 0 selects lower 4 nibble bits 0 . . . 3. A2 = 1 selects upper 4 nibble bits 4 . . . 7. Vali d Vali d Vali d A 10/A P Val i d 00 14 03 A [ 9:3] 02 1 Vali d READ1 02 t CCD Vali d READ1 0 t MOD Tc0 A2 MRS Tb A[1:0] t RF Ta 3 PREA T0 Bank add ress Command CK# CK NOP Tc4 NOP Tc5 NOP Tc6 NOP Tc7 t MPRR 0 0 0 0 00 0 Vali d 3 MRS Tc8 t MOD NOP Tc10 Indicates a Break in Time Scale NOP Tc9 Don ’t Care Valid Td L9D364M64SBG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) Figure 54 - MPR System Read Calibration with BC4: Lower Nibble, Then Upper Nibble High Performance, Integrated Memory Module Product May 3, 2012 LDS-L9D364M64SBG2-G LOGIC Devices Incorporated www.logicdevices.com 101 DQ DQS, DQS# A [ 15:13] 0 0 A12/BC# 0 A 10/A P 0 00 A [ 9:3] A 11 1 A2 1 0 MRS A[1:0] t RF Ta 3 PREA T0 Bank add ress Command CK# CK t MOD RL Vali d Vali d 1 Vali d 1 Val i d Vali d Vali d Val i d Val i d Vali d 04 13 Val i d 02 02 READ1 Vali d t CCD Tc0 Vali d READ1 Tb Notes: NOP Tc1 1. 2. 3. 4. RL NOP Tc3 NOP Tc4 NOP Tc5 NOP Tc6 READ with BC4 either by MRS or OTF. Memory controller must drive 0 on A[1:0]. A2 = 1 selects upper 4 nibble bits 4 . . . 7. A2 = 0 selects lower 4 nibble bits 0 . . . 3. NOP Tc2 t MPRR NOP Tc7 0 0 0 0 00 0 t MOD NOP Tc9 Indicates a Break in Time Scale Vali d 3 MR S Tc8 NOP Tc10 Don ’t Care Valid Td L9D364M64SBG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) Figure 55 - MPR System Read Calibration with BC4: Upper Nibble, Then Lower Nibble High Performance, Integrated Memory Module Product May 3, 2012 LDS-L9D364M64SBG2-G L9D364M64SBG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) MPR READ PREDEFINED PATTERN 7KHSUHGHWHUPLQHG5($'FDOLEUDWLRQSDWWHUQLVDIL[HGSDWWHUQRI7KHIROORZLQJLVDQH[DPSOHRIXVLQJWKH5($'RXWSUHGHWHUPLQHG5($' FDOLEUDWLRQSDWWHUQ7KHH[DPSOHLVWRSHUIRUPPXOWLSOH5($'6IURPWKH08/7,385326(5(*,67(5035LQRUGHUWRGRV\VWHPOHYHO5($'WLPLQJFDOLEUDWLRQEDVHGRQWKHSUHGHWHUPLQHGDQGVWDQGDUGL]HGSDWWHUQ 7KHIROORZLQJSURWRFRORXWOLQHVWKHVWHSVXVHGWRSHUIRUPWKH5($'FDOLEUDWLRQ x3UHFKDUJHDOOEDQNV x$IWHUt53LVVDWLVILHGVHW05605>@ DQG05>@ 7KLVUHGLUHFWVDOOVXEVHTXHQW5($'VDQG/RDGVWKHSUHGHILQHGSDWWHUQLQWR WKH035$VVRRQDVtMRD and t02'DUHVDWLVILHGWKH035LVDYDLODEOH x'DWD:5,7(RSHUDWLRQVDUHQRWDOORZHGXQWLOWKH035UHWXUQVWRWKHQRUPDO6'5$0VWDWH x,VVXHD5($'ZLWKEXUVWRUGHULQIRUPDWLRQDOORWKHUDGGUHVVSLQVDUHv'RQuW&DUHw x$>@ GDWDEXUVWRUGHULVIL[HGVWDUWLQJDWQLEEOH x$ IRU%/EXUVWRUGHULVIL[HGDV x$ XVH%/ x$IWHU5/ $/&/WKH6'5$0EXUVWVRXWWKHSUHGHILQHG5($'FDOLEUDWLRQSDWWHUQ x7KHPHPRU\FRQWUROOHUUHSHDWVWKHFDOLEUDWLRQ5($'VXQWLO5($'GDWDFDSWXUHDWWKHPHPRU\FRQWUROOHULVRSWLPL]HG x$IWHUWKHODVW0355($'EXUVWDQGDIWHU t0355KDVEHHQVDWLVILHGLVVXH05605>@ DQG05>@ v'RQuW&DUHwWRWKHQRUPDO 6'5$0VWDWH$OOVXEVHTXHQW5($'DQG:5,7(DFFHVVHVZLOOEHUHJXODU5($'6DQG:5,7(6IURPWRWKH6'5$0DUUD\ x:KHQ tMRD and t02'DUHVDWLVILHGIURPWKHODVW056WKHUHJXODU6'5$0FRPPDQGVVXFKDV$&7,9$7(D0HPRU\EDQNIRUUHJXODU 5($'RU:5,7(DFFHVVDUHSHUPLWWHG MODE REGISTER SET (MRS) 7KHPRGHUHJLVWHUVDUHORDGHGYLDLQSXWV%$>@$>@%$>@GHWHUPLQHVZKLFKPRGHUHJLVWHULVSURJUDPPHG x%$ x%$ x%$ x%$ %$ %$ %$ %$ %$ %$ %$ %$ IRU05 IRU05 IRU05 IRU05 7KH056FRPPDQGFDQRQO\EHLVVXHGRUUHLVVXHGZKHQDOOEDQNVDUHLGOHDQGLQWKHSUHFKDUJHGVWDWHt53LVVDWLVILHGDQGQRGDWDEXUVWVDUHLQ SURJUHVV7KHFRQWUROOHUPXVWZDLWWKHVSHFLILHGWLPHt05'EHIRUHLQLWLDWLQJDVXEVHTXHQWRSHUDWLRQVXFKDVDQ$&7,9$7(FRPPDQG7KHUHLVDOVR DUHVWULFWLRQDIWHULVVXLQJDQ056FRPPDQGZLWKUHJDUGWRZKHQWKHXSGDWHGIXQFWLRQVEHFRPHDYDLODEOH7KLVSDUDPHWHULVVSHFLILHGE\t02'%RWK tMRD and t02'SDUDPHWHUVDUHVKRZQLQ)LJXUHDQG9LRODWLQJHLWKHURIWKHVHUHTXLUHPHQWVZLOOUHVXOWLQXQVSHFLILHGRSHUDWLRQ ZQ CALIBRATION 7KH=4&$/,%5$7,21FRPPDQGLVXVHGWRFDOLEUDWHWKH6'5$0RXWSXWGULYHUV521DQG2'7YDOXHV5TTRYHUSURFHVVYROWDJHDQGWHPSHUDWXUHSURYLGHGDGHGLFDWHG:H[WHUQDOUHVLVWRULVFRQQHFWHGIURPWKH6'5$0uV=4EDOOWR9VV4 ''56'5$0VQHHGDORQJHUWLPHWRFDOLEUDWH5ONDQG2'7DWSRZHUXS,1,7,$/,=$7,21DQG6(/)5()5(6+H[LWDQGDUHODWLYHO\VKRUWHUWLPHWRSHUIRUP SHULRGLFFDOLEUDWLRQV''56'5$0GHILQHVWZR=4&$/,%5$7,21FRPPDQGV=4&$/,%5$7,21/21*=4&/DQG=4&$/,%5$7,216+257=4&6 $QH[DPSOHRI=4&$/,%5$7,21WLPLQJLVVKRZQLQ)LJXUH $OOEDQNVPXVWEH35(&+$5*('DQGt53PXVWEHPHWEHIRUH=4&/RU=4&6FRPPDQGVFDQEHLVVXHGWRWKH6'5$01RRWKHUDFWLYLWLHVRWKHUWKDQDQRWKHU =4&/RU=4&6FRPPDQGPD\EHLVVXHGWRWKH6'5$0FDQEHSHUIRUPHGRQWKH6'5$0DUUD\E\WKHFRQWUROOHUIRUWKHGXUDWLRQRI t=4,1,7RU t=423(5 7KHTXLHWWLPHRQWKH6'5$0DUUD\KHOSVDFFXUDWHO\FDOLEUDWH5ONDQG2'7$IWHU6'5$0FDOLEUDWLRQLVDFKLHYHGWKH6'5$0VKRXOGGLVDEOHWKH=4EDOOuV FXUUHQWFRQVXPSWLRQSDWKWRUHGXFHRYHUDOOSRZHUXVDJH =4&$/,%5$7,21FRPPDQGVFDQEHLVVXHGLQSDUDOOHOWR'//5(6(7DQGORFNLQJWLPH8SRQ6(/)5()5(6+H[LWDQH[SOLFLW=4&/LVUHTXLUHGLI=4&$/,%5$7,21LVGHVLUHG ,QGXDOUDQNV\VWHPGHVLJQVWKDWVKDUHWKH=4UHVLVWRUEHWZHHQGHYLFHVWKHFRQWUROOHUPXVWQRWDOORZRYHUODSRIt=4,17t=423(5RUt=4&6EHWZHHQUDQNV LOGIC Devices Incorporated www.logicdevices.com 102 High Performance, Integrated Memory Module Product May 3, 2012 LDS-L9D364M64SBG2-G L9D364M64SBG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) FIGURE 56 - ZQ CALIBRATION TIMING (ZQCL AND ZQCS) T0 T1 Ta0 Ta1 Ta2 Ta3 Tb0 Tb1 Tc0 Tc1 Tc2 ZQCL NOP NOP NOP Valid Vali d ZQCS NOP NOP NOP Valid Address Vali d Vali d Vali d A10 Vali d Vali d Vali d CK# CK Command CKE 1 Vali d Vali d 1 Vali d ODT 2 Vali d Vali d 2 Vali d DQ 3 A ctivities 3 High-Z Activities High-Z t ZQ INIT or t ZQ OPER t ZQCS Indicates a Break in Time Scale Don ’t Care 127(6 1. &.(PXVWEHFRQWLQXRXVO\UHJLVWHUHG+,*+GXULQJWKHFDOLEUDWLRQSURFHGXUH 2. 2'7PXVWEHGLVDEOHGYLDWKH2'7VLJQDORUWKH056GXULQJWKHFDOLEUDWLRQSURFHGXUH 3. $OOGHYLFHVFRQQHFWHGWRWKH'4EXVVKRXOGEH+LJK=GXULQJFDOLEUDWLRQ ACTIVATE %HIRUHDQ\5($'RU:5,7(FRPPDQGVFDQEHLVVXHGWRDEDQNZLWKLQWKH6'5$0D52:LQWKDWEDQNPXVWEHRSHQHG$&7,9$7('7KLVLVDFFRPSOLVKHG YLDWKH$&7,9$7(FRPPDQGZKLFKVHOHFWVERWKWKH%$1.DQGWKH52:WREH$&7,9$7(' $IWHUD52:LVRSHQHGZLWKDQ$&7,9$7(FRPPDQGD5($'RU:5,7(FRPPDQGPD\EHLVVXHGWRWKDW52:VXEMHFWWRWKHt5&'VSHFLILFDWLRQ+RZHYHULI WKHDGGLWLYHODWHQF\LVSURJUDPPHGFRUUHFWO\D5($'RU:5,7(FRPPDQGPD\EHLVVXHGSULRUWRt5&'0,1,QWKLVRSHUDWLRQWKH6'5$0HQDEOHVD5($' RU:5,7(FRPPDQGWREHLVVXHGDIWHUWKH$&7,9$7(FRPPDQGIRUWKDWEDQNEXWSULRUWRt5&'0,1VHHv3267('&$6$'',7,9(/$7(1&<$/t5&' 0,1VKRXOGEHGLYLGHGE\WKHFORFNSHULRGDQGURXQGHGXSWRWKHQH[WZKROHQXPEHUWRGHWHUPLQHWKHHDUOLHVWFORFNHGJHDIWHUWKH$&7,9$7(FRPPDQGRQ ZKLFKWKH5($'RU:5,7(FRPPDQGFDQEHHQWHUHG7KHVDPHSURFHGXUHLVXVHGWRFRQYHUWRWKHUVSHFLILFDWLRQOLPLWVIURPWLPHXQLWVWRFORFNF\FOHV :KHQDWOHDVWRQHEDQNLVRSHQDQ\5($'WR5($'FRPPDQGGHOD\RU:5,7(WR:5,7(FRPPDQGGHOD\LVUHVWULFWHGWRt&&'0,1 $ VXEVHTXHQW $&7,9$7( FRPPDQG WR D GLIIHUHQW 52: LQ WKH VDPH %$1. FDQ RQO\ EH LVVXHG DIWHU WKH SUHYLRXV $&7,9( 52: KDV EHHQ FORVHG 35(&+$5*('7KHPLQLPXPWLPHLQWHUYDOEHWZHHQVXFFHVVLYH$&7,9$7(FRPPDQGVWRWKHVDPH%$1.LVGHILQHGE\t5& $VXEVHTXHQW$&7,9$7(FRPPDQGWRDQRWKHU%$1.FDQEHLVVXHGZKLOHWKHILUVW%$1.LVEHLQJDFFHVVHGZKLFKUHVXOWVLQDUHGXFWLRQRIWRWDO52:$&&(66 RYHUKHDG7KHPLQLPXPWLPHLQWHUYDOEHWZHHQVXFFHVVLYH$&7,9$7(FRPPDQGVPD\EHLVVXHGLQDJLYHQt)$:0,1SHULRGDQGWKHt55'0,1UHVWULFWLRQ VWLOODSSOLHV7KHt)$:0,1SDUDPHWHUDSSOLHVUHJDUGOHVVRIWKHQXPEHURI%$1.6DOUHDG\RSHQHGRUFORVHG LOGIC Devices Incorporated www.logicdevices.com 103 High Performance, Integrated Memory Module Product May 3, 2012 LDS-L9D364M64SBG2-G L9D364M64SBG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) FIGURE 57 - EXAMPLE: MEETING tRRD (MIN) AND tRCD (MIN) T0 T1 T2 T3 T4 T5 T8 T9 T10 T11 Command ACT NOP NOP ACT NOP NOP NOP NOP NOP RD/WR Add ress Row BA[2:0] Bank x CK# CK Row Col Bank y Bank y t RRD t RCD Indicates a Break in Time Scale Don ’t Care FIGURE 58 - EXAMPLE: tFAW CK# T0 T1 T4 T5 T8 T9 T10 T11 T19 T20 ACT NOP ACT NOP A CT NOP ACT NOP NOP A CT CK Command Add ress BA[2:0] Row Bank a Row Row Row Row Bank b Bank c Bank d Bank ye t RRD t FAW Indicates a Break in Time Scale LOGIC Devices Incorporated www.logicdevices.com 104 Don ’t Care High Performance, Integrated Memory Module Product May 3, 2012 LDS-L9D364M64SBG2-G L9D364M64SBG2 4.0 Gb, DDR3, 64 M x 64 Integrated Module (IMOD) READ 5($'EXUVWVDUHLQLWLDWHGZLWKD5($'FRPPDQG7KHVWDUWLQJ&2/801DQG%$1.DGGUHVVHVDUHSURYLGHGZLWKWKH5($'FRPPDQGDQG $87235(&+$5*(LVHLWKHUHQDEOHGRUGLVDEOHGIRUWKDWEXUVWDFFHVV,I$87235(&+$5*(LVHQDEOHGWKH52:EHLQJDFFHVVHGLVDXWRPDWLFDOO\35(&+$5*('DW WKHFRPSOHWLRQRIWKHEXUVWVHTXHQFH,I$87235(&+$5*(LVGLVDEOHGWKH52:ZLOOEHOHIWRSHQDIWHUWKHFRPSOHWLRQRIWKHEXUVW 'XULQJ5($'EXUVWVWKHYDOLGGDWDRXWHOHPHQWIURPWKHVWDUWLQJFROXPQDGGUHVVLVDYDLODEOHDW5($'/$7(1&<5/FORFNVODWHU5/LVGHILQHGDVWKHVXP RI3267('&$6$'',7,9(/$7(1&<$/DQG&$6/$7(1&<&/5/ $/&/7KHYDOXHRI$/DQG&/LVSURJUDPPDEOHLQWKHPRGHUHJLVWHUYLDWKH 056FRPPDQG(DFKVXEVHTXHQWGDWDRXWHOHPHQWZLOOEHYDOLGQRPLQDOO\DWWKHQH[WSRVLWLYHRUQHJDWLYHFORFNHGJHWKDWLVDWWKHQH[WFURVVLQJRI&.DQG &.?)LJXUHVKRZVDQH[DPSOHRI5/EDVHGRQD&/VHWWLQJRIDVZHOODV$/ FIGURE 59 - READ LATENCY T0 T7 T8 T9 T10 T11 T12 T12 Command READ NOP NOP NOP NOP NOP NO