L9D232M64SBG5
L9D232M72SBG5
L9D232M80SBG5
L9D264M64SBG5
L9D264M72SBG5
L9D264M80SBG5
2 - 5.0 Gb, DDR2, 32 M [64 M] x 64/72/80 Integrated Memory Module (IMOD)
FAST, LOW POWER, HIGH DENSITY, WIDE WORD MEMORY
Benefits
FEATURES
DDR2 25mm2 Module [iMOD]:
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L9D2xxMxxSBG5 Product Offerings:
PART NUMBER:
L9D232M64SBG5
L9D232M72SBG5
DENSITY:
DEPTH:
WORD WIDTHS:
*E
32M
[
*E
32M
DDR2
DDR2
10.5mm x
10.5mm x
32M
12.5mm
12.5mm
84 ball
84 ball
0
FBGA
FBGA
[
DDR2
10.5mm x
[
12.5mm
84 ball
[
FBGA
DDR2
10.5mm x
L9D232M80SBG512.5mm
84 ball
L9D264M64SBG5 FBGA
DDR2
10.5mm x
*E
12.5mm
84 ball
*E
FBGA
L9D264M72SBG5
*E
0
[
L9D264M80SBG5
*E
0
[
L9D264M80SBG5
L9D2xxMxxSBG5 Available Timings:
CLOCK:
CYCLE TIME:
DATA RATE:
DDR2-800
0+]
QV
0EV
DDR2-667
0+]
DDR2
QVDDR2
DDR2-533
10.5mm x
0+]
12.5mm
84 ball
FBGA
10.5mm x
QV
12.5mm
84 ball
FBGA
0EV
DDR2
10.5mm x
0EV
12.5mm
84 ball
FBGA
integrated module products
LOGIC Devices Incorporated
www.logicdevices.com
1
High Performance, Integrated Memory Module Product
September 16, 2013 LDS-L9D2xxMxxSBG5 Rev E
L9D232M64SBG5
2.0 Gb, DDR2, 32 M x 64 Integrated Memory Module (IMOD)
BALL /SIGNAL LOCATION DIAGRAM:
FIGURE 1A - SDRAM : DDR2 PINOUT TOP VIEW
1
A
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
DQ0
DQ14
DQ15
VSS
VSS
A9
A10
A11
A8
VDDQ
VDDQ
DQ16
DQ17
DQ31
VSS
A
A0
A7
A6
A1
VDD
VDD
DQ18
DQ19
DQ29
DQ30
B
VSS
VSS
DQ20
DQ21
DQ27
DQ28
C
B
DQ1
DQ2
DQ12
DQ13
VSS
VSS
C
DQ3
DQ4
DQ10
DQ11
VDD
VDD
D
DQ6
DQ5
DQ8
DQ9
VDDQ
VDDQ
A12
NC
VSS
NC
VSS
VSS
DQ22
DQ23
DQ26
DQ25
D
E
DQ7
LDM0
VDD
UDM0
UDQS3
LDQS0
UDQS0
BA0
BA1
LDQS1
UDQS1
Vref
LDM1
VSS
NC
DQ24
E
F
CAS0\
WE0\
VDD
CLK0
LDQS3
UDQS3\ LDQS0\
UDQS0\
DNU
UDQS1\
LDQS1\
RAS1\
WE1\
VSS
UDM1
CLK1
F
G
CS0\
RAS0\
VDD
CKE0
CLK0\
LDQS3\
VSSQ
VSSQ
VSSQ
VSSQ
NC
CAS1\
CS1\
VSS
CLK1\
CKE1
G
H
VSS
VSS
VDD
VDDQ
VSSDL
NC
VSSQ
VSSQ
VSSQ
VSSQ
NC
VDDL
VSS
VSS
VDDQ
VDD
H
J
VSS
VSS
VDD
VDDQ
VSS
NC
VSSQ
VSSQ
VSSQ
VSSQ
NC
VDD
VSS
VSS
VDDQ
VDD
J
K
CLK3\
CKE3
VDD
CS3\
RFU
RFU
VSSQ
VSSQ
VSSQ
VSSQ
DNU
CLK2\
CKE2
VSS
RAS2\
CS2\
K
L
NC
CLK3
VDD
CAS3\
RAS3\
ODT
RFU
NC
NC
LDQS2\ UDQS2\
LDQS2
CLK2
VSS
WE2\
CAS2\
L
M
DQ56
UDM3
VDD
WE3\
LDM3
NC
VDD
RFU
RFU
RFU
RFU
NC
UDM2
VSS
LDM2
DQ39
M
N
DQ57
DQ58
DQ55
DQ54
NC
NC
RFU
RFU
RFU
RFU
RFU
UDQS2
DQ41
DQ40
DQ37
DQ38
N
P
DQ60
DQ59
DQ53
DQ52
VSS
VSS
RFU
RFU
RFU
RFU
VDD
VDD
DQ43
DQ42
DQ36
DQ35
P
R
DQ62
DQ61
DQ51
DQ50
VDD
VDD
RFU
RFU
RFU
RFU
VSS
VSS
DQ45
DQ44
DQ34
DQ33
R
T
VSS
DQ63
DQ49
DQ48
VDDQ
VDDQ
RFU
RFU
RFU
RFU
VSS
VSS
DQ47
DQ46
DQ32
VDD
T
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A2
A5
A4
A3
GND (Core)
V+ (Core Power)
UNPOPULATED
Address
CNTRL
GND (I/O)
V+ (I/O Power)
NC
DNU
RFU
VSSDL
VDDL
DATA (I/O)
REF Level
LOGIC Devices Incorporated
www.logicdevices.com
2
High Performance, Integrated Memory Module Product
September 16, 2013 LDS-L9D2xxMxxSBG5 Rev E
L9D232M72SBG5
2.2 Gb, DDR2, 32 M x 72 Integrated Memory Module (IMOD)
BALL /SIGNAL LOCATION DIAGRAM:
FIGURE 1B - SDRAM : DDR2 PINOUT TOP VIEW
1
A
4
5
6
7
8
9
DQ0
2
DQ14
3
DQ15
VSS
VSS
A9
A10
A11
10
A8
VDDQ
11
12
13
14
15
16
VDDQ
DQ16
DQ17
DQ31
VSS
A
B
DQ1
DQ2
DQ12
DQ13
VSS
VSS
A0
A7
A6
A1
VDD
VDD
DQ18
DQ19
DQ29
DQ30
B
C
DQ3
DQ4
DQ10
DQ11
VDD
VDD
A2
A5
A4
A3
VSS
VSS
DQ20
DQ21
DQ27
DQ28
C
D
DQ6
DQ5
DQ8
DQ9
VDDQ
VDDQ
VSS
VSS
DQ22
DQ23
DQ26
DQ25
D
E
DQ7
LDM0
VDD
UDM0
UDQS3
LDQS0
NC
DQ24
E
F
CAS0\
WE0\
VDD
CLK0
LDQS3
UDQS3\ LDQS0\
G
CS0\
RAS0\
VDD
CKE0
CLK0\
LDQS3\
H
VSS
VSS
VDD
VDDQ
VSSDL
J
VSS
VSS
VDD
VDDQ
K
CLK3\
CKE3
VDD
L
NC
CLK3
M
DQ56
N
A12
UDQS0
NC
VSS
NC
BA0
BA1
LDQS1
UDQS1
Vref
LDM1
VSS
UDQS0\
DNU
UDQS1\
LDQS1\
RAS1\
WE1\
VSS
UDM1
CLK1
F
VSSQ
VSSQ
VSSQ
VSSQ
NC
CAS1\
CS1\
VSS
CLK1\
CKE1
G
NC
VSSQ
VSSQ
VSSQ
VSSQ
NC
VDDL
VSS
VSS
VDDQ
VDD
H
VSS
NC
VSSQ
VSSQ
VSSQ
VSSQ
NC
VDD
VSS
VSS
VDDQ
VDD
J
CS3\
LDQS4
UDQS4\
VSSQ
VSSQ
VSSQ
VSSQ
DNU
CLK2\
CKE2
VSS
RAS2\
CS2\
K
VDD
CAS3\
RAS3\
ODT
LDQS4\
NC
NC
LDQS2\
UDQS2\
LDQS2
CLK2
VSS
WE2\
CAS2\
L
UDM3
VDD
WE3\
LDM3
CKE4
NC
CLK4
CAS4\
WE4\
RAS4\
CS4\
UDM2
VSS
LDM2
DQ39
M
DQ57
DQ58
DQ55
DQ54
UDQS4
CLK4\
RFU
RFU
DQ71
DQ70
LDM4
UDQS2
DQ41
DQ40
DQ37
DQ38
N
P
DQ60
DQ59
DQ53
DQ52
VSS
VSS
RFU
RFU
DQ69
DQ68
VDD
VDD
DQ43
DQ42
DQ36
DQ35
P
R
DQ62
DQ61
DQ51
DQ50
VDD
VDD
RFU
RFU
DQ67
DQ66
VSS
VSS
DQ45
DQ44
DQ34
DQ33
R
T
VSS
DQ63
DQ49
DQ48
VDDQ
VDDQ
RFU
RFU
DQ65
DQ64
VSS
VSS
DQ47
DQ46
DQ32
VDD
T
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
GND (Core)
V+ (Core Power)
UNPOPULATED
Address
CNTRL
GND (I/O)
V+ (I/O Power)
NC
DNU
RFU
VSSDL
VDDL
DATA (I/O)
REF Level
LOGIC Devices Incorporated
www.logicdevices.com
3
High Performance, Integrated Memory Module Product
September 16, 2013 LDS-L9D2xxMxxSBG5 Rev E
L9D232M80SBG5
2.5 Gb, DDR2, 32 M x 80 Integrated Memory Module (IMOD)
BALL /SIGNAL LOCATION DIAGRAM:
FIGURE 1C - SDRAM : DDR2 PINOUT TOP VIEW
1
A
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
DQ0
DQ14
DQ15
VSS
VSS
A9
A10
A11
A8
VDDQ
VDDQ
DQ16
DQ17
DQ31
VSS
A
B
DQ1
DQ2
DQ12
DQ13
VSS
VSS
A0
A7
A6
A1
VDD
VDD
DQ18
DQ1
DQ29
DQ30
B
C
DQ3
DQ4
DQ10
DQ11
VDD
VDD
A2
A5
A4
A3
VSS
VSS
DQ20
DQ21
DQ27
DQ28
C
D
DQ6
DQ5
DQ8
DQ9
VDDQ
VDDQ
A12
NC
VSS
NC
VSS
VSS
DQ22
DQ23
DQ26
DQ25
D
E
DQ7
LDM0
VDD
UDM0
UDQS3
LDQS0
UDQS0
BA0
BA1
LDQS1
UDQS1
Vref
LDM1
VSS
NC
DQ24
E
F
CAS0\
WE0\
VDD
CLK0
LDQS3
UDQS3\ LDQS0\
UDQS0\
DNU
UDQS1\
LDQS1\
RAS1\
WE1\
VSS
UDM1
CLK1
F
G
CS0\
RAS0\
VDD
CKE0
CLK0\
LDQS3\
VSSQ
VSSQ
VSSQ
VSSQ
NC
CAS1\
CS1\
VSS
CLK1\
CKE1
G
H
VSS
VS S
VDD
VDDQ
VSSDL
NC
VSSQ
VSSQ
VSSQ
VSSQ
NC
VDDL
VSS
VSS
VDDQ
VDD
H
J
VSS
VS S
VDD
VDDQ
VSS
NC
VSSQ
VSSQ
VSSQ
VSSQ
NC
VDD
VSS
VSS
VDDQ
VDD
J
K
CLK3\
CKE3
VDD
CS3\
LDQS4
UDQS4\
VSSQ
VSSQ
VSSQ
VSSQ
DNU
CLK2\
CKE2
VSS
RAS2\
CS2\
K
L
NC
CLK3
VDD
CAS3\
RAS3\
ODT
LDQS4\
NC
NC
LDQS2
CLK2
VSS
WE2\
CAS2\
L
M
DQ56
UDM3
VDD
WE3\
LDM3
CKE4
UDM4
CLK4
CAS4\
WE4\
RAS4\
CS4\
UDM2
VSS
LDM2
DQ39
M
N
DQ57
DQ58
DQ55
DQ54
UDQS4
CLK4\
DQ73
DQ72
DQ71
DQ70
LDM4
UDQS2
DQ41
DQ40
DQ37
DQ38
N
P
DQ60
DQ59
DQ53
DQ52
VSS
VSS
DQ75
DQ74
DQ69
DQ68
VDD
VDD
DQ43
DQ42
DQ36
DQ35
P
R
DQ62
DQ61
DQ51
DQ50
VDD
VDD
DQ77
DQ76
DQ67
DQ66
VSS
VSS
DQ45
DQ44
DQ34
DQ33
R
T
VSS
DQ63
DQ49
DQ48
VDDQ
VDDQ
DQ79
DQ78
DQ65
DQ64
VSS
VSS
DQ47
DQ46
DQ32
VDD
T
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
LDQS2\ UDQS2\
GND (Core)
V+ (Core Power)
UNPOPULATED
Address
GND (I/O)
V+ (I/O Power)
NC
DNU
VSSDL
VDDL
DATA (I/O)
REF Level
LOGIC Devices Incorporated
www.logicdevices.com
CNTRL
High Performance, Integrated Memory Module Product
September 16, 2013 LDS-L9D2xxMxxSBG5 Rev E
L9D264M64SBG5
4.0 Gb, DDR2, 64 M x 64 Integrated Memory Module (IMOD)
BALL /SIGNAL LOCATION DIAGRAM:
FIGURE 1D- SDRAM : DDR2 PINOUT TOP VIEW
1
A
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
DQ0
DQ14
DQ15
VSS
VSS
A9
A10
A11
A8
VDDQ
VDDQ
DQ16
DQ17
DQ31
VSS
A
A0
A7
A6
A1
VDD
VDD
DQ18
DQ19
DQ29
DQ30
B
VSS
VSS
DQ20
DQ21
DQ27
DQ28
C
B
DQ1
DQ2
DQ12
DQ13
VSS
VSS
C
DQ3
DQ4
DQ10
DQ11
VDD
VDD
D
DQ6
DQ5
DQ8
DQ9
VDDQ
VDDQ
A12
NC
BA2
NC
VSS
VSS
DQ22
DQ23
DQ26
DQ25
D
E
DQ7
LDM0
VDD
UDM0
UDQS3
LDQS0
UDQS0
BA0
BA1
LDQS1
UDQS1
Vref
LDM1
VSS
NC
DQ24
E
F
CAS0\
WE0\
VDD
CLK0
LDQS3
UDQS3\ LDQS0\
UDQS0\
DNU
UDQS1\
LDQS1\
RAS1\
WE1\
VSS
UDM1
CLK1
F
G
CS0\
RAS0\
VDD
CKE0
CLK0\
LDQS3\
VSSQ
VSSQ
VSSQ
VSSQ
NC
CAS1\
CS1\
VSS
CLK1\
CKE1
G
H
VSS
VSS
VDD
VDDQ
VSSDL
NC
VSSQ
VSSQ
VSSQ
VSSQ
NC
VDDL
VSS
VSS
VDDQ
VDD
H
J
VSS
VSS
V DD
VDDQ
VSS
NC
VSSQ
VSSQ
VSSQ
VSSQ
NC
VDD
VSS
VSS
VDDQ
VDD
J
K
CLK3\
CKE3
VDD
CS3\
RFU
RFU
VSSQ
VSSQ
VSSQ
VSSQ
DNU
CLK2\
CKE2
VSS
RAS2\
CS2\
K
L
NC
CLK3
VDD
CAS3\
RAS3\
ODT
RFU
NC
NC
LDQS2
CLK2
VSS
WE2\
CAS2\
L
M
DQ56
UDM3
VDD
WE3\
LDM3
NC
VDD
RFU
RFU
RFU
RFU
NC
UDM2
VSS
LDM2
DQ39
M
N
DQ57
DQ58
DQ55
DQ54
NC
NC
RFU
RFU
RFU
RFU
RFU
UDQS2
DQ41
DQ40
DQ37
DQ38
N
P
DQ60
DQ59
DQ53
DQ52
VSS
VSS
RFU
RFU
RFU
RFU
VDD
VDD
DQ43
DQ42
DQ36
DQ35
P
R
DQ62
DQ61
DQ51
DQ50
VDD
VDD
RFU
RFU
RFU
RFU
VSS
VSS
DQ45
DQ44
DQ34
DQ33
R
T
V SS
DQ63
DQ49
DQ48
VDDQ
VDDQ
RFU
RFU
RFU
RFU
VSS
VSS
DQ47
DQ46
DQ32
VDD
T
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A2
A5
A4
A3
LDQS2\ UDQS2\
GND (Core)
V+ (Core Power)
UNPOPULATED
Address
CNTRL
GND (I/O)
V+ (I/O Power)
NC
DNU
RFU
VSSDL
VDDL
DATA (I/O)
REF Level
LOGIC Devices Incorporated
www.logicdevices.com
5
High Performance, Integrated Memory Module Product
September 16, 2013 LDS-L9D2xxMxxSBG5 Rev E
L9D264M72SBG5
4.5 Gb, DDR2, 64 M x 72 Integrated Memory Module (IMOD)
BALL /SIGNAL LOCATION DIAGRAM:
FIGURE 1E- SDRAM : DDR2 PINOUT TOP VIEW
1
A
4
5
6
7
8
9
DQ0
2
DQ14
3
DQ15
VSS
VSS
A9
A10
A11
10
A8
VDDQ
11
12
13
14
15
16
VDDQ
DQ16
DQ17
DQ31
VSS
A
B
DQ1
DQ2
DQ12
DQ13
VSS
VSS
A0
A7
A6
A1
VDD
VDD
DQ18
DQ19
DQ29
DQ30
B
C
DQ3
DQ4
DQ10
DQ11
VDD
VDD
A2
A5
A4
A3
VSS
VSS
DQ20
DQ21
DQ27
DQ28
C
D
DQ6
DQ5
DQ8
DQ9
VDDQ
VDDQ
VSS
VSS
DQ22
DQ23
DQ26
DQ25
D
E
DQ7
LDM0
VDD
UDM0
UDQS3
LDQS0
NC
DQ24
E
F
CAS0\
WE0\
VDD
CLK0
LDQS3
UDQS3\ LDQS0\
G
CS0\
RAS0\
VDD
CKE0
CLK0\
LDQS3\
H
VSS
VSS
VDD
VDDQ
VSSDL
J
VS S
VSS
VDD
VDDQ
K
CLK3\
CKE3
VDD
L
NC
CLK3
M
DQ56
N
A12
UDQS0
NC
BA2
NC
BA0
BA1
LDQS1
UDQS1
Vref
LDM1
VSS
UDQS0\
DNU
UDQS1\
LDQS1\
RAS1\
WE1\
VSS
UDM1
CLK1
F
VSSQ
VSSQ
VSSQ
VSSQ
NC
CAS1\
CS1\
VSS
CLK1\
CKE1
G
NC
VSSQ
VSSQ
VSSQ
VSSQ
NC
VDDL
VSS
VSS
VDDQ
VDD
H
VSS
NC
VSSQ
VSSQ
VSSQ
VSSQ
NC
VDD
VSS
VSS
VDDQ
VDD
J
CS3\
LDQS4
UDQS4\
VSSQ
VSSQ
VSSQ
VSSQ
DNU
CLK2\
CKE2
VSS
RAS2\
CS2\
K
VDD
CAS3\
RAS3\
ODT
LDQS4\
NC
NC
LDQS2\
UDQS2\
LDQS2
CLK2
VSS
WE2\
CAS2\
L
UDM3
VDD
WE3\
LDM3
CKE4
VDD
CLK4
CAS4\
WE4\
RAS4\
CS4\
UDM2
VSS
LDM2
DQ39
M
DQ57
DQ58
DQ55
DQ54
UDQS4
CLK4\
RFU
RFU
DQ71
DQ70
LDM4
UDQS2
DQ41
DQ40
DQ37
DQ38
N
P
DQ60
DQ59
DQ53
DQ52
VSS
VSS
RFU
RFU
DQ69
DQ68
VDD
VDD
DQ43
DQ42
DQ36
DQ35
P
R
DQ62
DQ61
DQ51
DQ50
VDD
VDD
RFU
RFU
DQ67
DQ66
VSS
VSS
DQ45
DQ44
DQ34
DQ33
R
T
VSS
DQ63
DQ49
DQ48
VDDQ
VDDQ
RFU
RFU
DQ65
DQ64
VSS
VSS
DQ47
DQ46
DQ32
VDD
T
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
GND (Core)
V+ (Core Power)
UNPOPULATED
Address
CNTRL
GND (I/O)
V+ (I/O Power)
NC
DNU
RFU
VSSDL
VDDL
DATA (I/O)
REF Level
LOGIC Devices Incorporated
www.logicdevices.com
6
High Performance, Integrated Memory Module Product
September 16, 2013 LDS-L9D2xxMxxSBG5 Rev E
L9D264M80SBG5
5.0 Gb, DDR2, 64 M x 80 Integrated Memory Module (IMOD)
BALL /SIGNAL LOCATION DIAGRAM:
FIGURE 1F- SDRAM : DDR2 PINOUT TOP VIEW
1
A
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
DQ0
DQ14
DQ15
VSS
VSS
A9
A10
A11
A8
VDDQ
VDDQ
DQ16
DQ17
DQ31
VSS
A
B
DQ1
DQ2
DQ12
DQ13
VSS
VSS
A0
A7
A6
A1
VDD
VDD
DQ18
DQ19
DQ29
DQ30
B
C
DQ3
DQ4
DQ10
DQ11
VDD
VDD
A2
A5
A4
A3
VSS
VSS
DQ20
DQ21
DQ27
DQ28
C
D
DQ6
DQ5
DQ8
DQ9
VDDQ
VDDQ
A12
NC
BA2
NC
VSS
VSS
DQ22
DQ23
DQ26
DQ25
D
E
DQ7
LDM0
VDD
UDM0
UDQS3
LDQS0
UDQS0
BA0
BA1
LDQS1
UDQS1
Vref
LDM1
VSS
NC
DQ24
E
F
CAS0\
WE0\
VDD
CLK0
LDQS3
UDQS3\ LDQS0\
UDQS0\
DNU
UDQS1\
LDQS1\
RAS1\
WE1\
VSS
UDM1
CLK1
F
G
CS0\
RAS0\
VDD
CKE0
CLK0\
LDQS3\
VSSQ
VSSQ
VSSQ
VSSQ
NC
CAS1\
CS1\
VSS
CLK1\
CKE1
G
H
VSS
VSS
VDD
VDDQ
VSSDL
NC
VSSQ
VSSQ
VSSQ
VSSQ
NC
VDDL
VSS
VSS
VDDQ
VDD
H
J
VSS
VSS
VDD
VDDQ
VSS
NC
VSSQ
VSSQ
VSSQ
VSSQ
NC
VDD
VSS
VSS
VDDQ
VDD
J
K
CLK3\
CKE3
VDD
CS3\
LDQS4
UDQS4\
VSSQ
VSSQ
VSSQ
VSSQ
DNU
CLK2\
CKE2
VSS
RAS2\
CS2\
K
L
NC
CLK3
VDD
CAS3\
RAS3\
ODT
LDQS4\
NC
NC
LDQS2
CLK2
VSS
WE2\
CAS2\
L
M
DQ56
UDM3
VDD
WE3\
LDM3
CKE4
UDM4
CLK4
CAS4\
WE4\
RAS4\
CS4\
UDM2
VSS
LDM2
DQ39
M
N
DQ57
DQ58
DQ55
DQ54
UDQS4
CLK4\
DQ73
DQ72
DQ71
DQ70
LDM4
UDQS2
DQ41
DQ40
DQ37
DQ38
N
P
DQ60
DQ59
DQ53
DQ52
VSS
VSS
DQ75
DQ74
DQ69
DQ68
VDD
VDD
DQ43
DQ42
DQ36
DQ35
P
R
DQ62
DQ61
DQ51
DQ50
VDD
VDD
DQ77
DQ76
DQ67
DQ66
VSS
VSS
DQ45
DQ44
DQ34
DQ33
R
T
VSS
DQ63
DQ49
DQ48
VDDQ
VDDQ
DQ79
DQ78
DQ65
DQ64
VSS
VSS
DQ47
DQ46
DQ32
VDD
T
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
LDQS2\ UDQS2\
GND (Core)
V+ (Core Power)
UNPOPULATED
Address
GND (I/O)
V+ (I/O Power)
NC
DNU
VSSDL
VDDL
DATA (I/O)
REF Level
LOGIC Devices Incorporated
www.logicdevices.com
CNTRL
High Performance, Integrated Memory Module Product
September 16, 2013 LDS-L9D2xxMxxSBG5 Rev E
L9D232M64SBG5
L9D232M72SBG5
L9D232M80SBG5
L9D264M64SBG5
L9D264M72SBG5
L9D264M80SBG5
2 - 5.0 Gb, DDR2, 32 M [64 M] x 64/72/80 Integrated Memory Module (IMOD)
TABLE 1: PIN/BALL LOCATIONS AND DESCRIPTIONS
Ball Assignments
Symbol
L6
2'7
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CLK0, CLK0\, CLK1, CK1\
L13, K12, L2, K1
CLK2, CLK2\, CLK3, CLK3\
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LOGIC Devices Incorporated
www.logicdevices.com
Type
Description
CNTL Input On-Die Termination:5HJLVWHUHG+LJKHQDEOHVRQGDWDEXVWHUPLQDWLRQ
CNTL Input 'LIIHUHQWLDOLQSXWFORFNVRQHVHWIRUHDFK[ELWV
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CNTL Input &KLS6HOHFWVRQHIRUHDFKELWVRIWKHGDWDEXVZLGWK
CNTL Input &RPPDQGLQSXWZKLFKDORQJZLWK&$6?:(?DQG&6?GHILQHRSHUDWLRQV
CNTL Input &RPPDQGLQSXWZKLFKDORQJZLWK5$6?:(?DQG&6?GHILQHRSHUDWLRQV
CNTL Input &RPPDQGLQSXWZKLFKDORQJZLWK5$6?&$6?DQG&6?GHILQHRSHUDWLRQV
CNTL Input 2QH'DWD0DVNFQWOIRUHDFKXSSHUELWVRID[ZRUG
CNTL Input 2QH'DWD0DVNFQWOIRUHDFKORZHUELWVRID[ZRUG
CNTL Input 'DWD6WUREHLQSXWIRUXSSHUE\WHRIHDFK[ZRUG
CNTL Input 'LIIHUHQWLDOLQSXWRI8'46[RQO\XVHGZKHQ'LIIHUHQWLDO'46PRGHLVHQDEOHG
CNTL Input 'DWD6WUREHLQSXWIRUORZHUE\WHRIHDFK[ZRUG
CNTL Input 'LIIHUHQWLDOLQSXWRI/'46[RQO\XVHGZKHQ'LIIHUHQWLDO'46PRGHLVHQDEOHG
Input
Future Input
Input
Supply
Supply
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Supply
,23RZHU6XSSO\
Supply
*URXQGUHWXUQ
High Performance, Integrated Memory Module Product
September 16, 2013 LDS-L9D2xxMxxSBG5 Rev E
L9D232M64SBG5
L9D232M72SBG5
L9D232M80SBG5
L9D264M64SBG5
L9D264M72SBG5
L9D264M80SBG5
2 - 5.0 Gb, DDR2, 32 M [64 M] x 64/72/80 Integrated Memory Module (IMOD)
TABLE 1: PIN/BALL LOCATIONS AND DESCRIPTIONS CONTINUED
Ball Assignments
5777
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H5
H12
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LOGIC Devices Incorporated
Symbol
9VV4
966'/
9''/
D0, D1, D2, D3
''''
''''
''''
''''
D20, D21, D22, D23
''''
''''
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''''
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D60, D61, D62, D63
''''
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NC
DO NOT USE
unpopulated
www.logicdevices.com
Type
Supply
Description
,2*URXQGUHWXUQ
Supply
'//3RZHU
Supply
'//*URXQG
Input/Output 'DWDELGLUHFWLRQDOLQSXW2XWSXWSLQV
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9
High Performance, Integrated Memory Module Product
September 16, 2013 LDS-L9D2xxMxxSBG5 Rev E
L9D232M64SBG5
2.0 Gb, DDR2, 32 M x 64 Integrated Memory Module (IMOD)
FIGURE 2A - FUNCTIONAL BLOCK DIAGRAM
LOGIC Devices Incorporated
www.logicdevices.com
DQ 0
!
!
!
DQ 7
DQ 32
!
!
!
DQ 39
DQ 8
!
!
!
DQ 15
DQ 40
!
!
!
DQ 47
10
VSS
VSSQ
DQ 16
!
!
!
DQ 23
DQ 8
!
!
!
DQ 15
DQ 24
!
!
!
DQ 31
VSS
ODT
VDD
VDDQ
VREF
D3
512Mb
DQ 0
!
!
!
DQ 7
VSSQ
CS\
CKE
CK
CK\
RAS\
CAS\
WE\
LDQS
LDQS\
UDQS
UDQS\
LDM
UDM
VDDQ
CS3\
CKE3
CLK3
CLK3\
RAS3\
CAS3\
WE3\
LDQS3
LDQS3\
UDQS3
UDQS3\
LDM3
UDM3
ODT
DQ 15
D1
512Mb
VDD
DQ 15
CS\
CKE
CK
CK\
RAS\
CAS\
WE\
LDQS
LDQS\
UDQS
UDQS\
LDM
UDM
VREF
DQ 7
DQ 8
VSS
DQ 7
DQ 8
CS1\
CKE1
CLK1
CLK1\
RAS1\
CAS1\
WE1\
LDQS1
LDQS1\
UDQS1
UDQS1\
LDM1
UDM1
ABA
VSS
VSSQ
DQ 0
VSSQ
ODT
VDD
VDDQ
VREF
D2
512Mb
DQ 0
VDDQ
ODT
D0
512Mb
VDD
ABA
CS\
CKE
CK
CK\
RAS\
CAS\
WE\
LDQS
LDQS\
UDQS
UDQS\
LDM
UDM
A
VREF
CS2\
CKE2
CLK2
CLK2\
RAS2\
CAS2\
WE2\
LDQS2
LDQS2\
UDQS2
UDQS2\
LDM2
UDM2
CS\
CKE
CK
CK\
RAS\
CAS\
WE\
LDQS
LDQS\
UDQS
UDQS\
LDM
UDM
ABA
CS0\
CKE0
CLK0
CLK0\
RAS0\
CAS0\
WE0\
LDQS0
LDQS0\
UDQS0
UDQS0\
LDM0
UDM0
A
ABA
VSSQ
VSS
VDDQ
VDD
ODT
VREF
A0-A12,
BA0-1
DQ 0
!
!
!
DQ 7
DQ 48
!
!
!
DQ 55
DQ 8
!
!
!
DQ 15
DQ 56
!
!
!
DQ 63
High Performance, Integrated Memory Module Product
September 16, 2013 LDS-L9D2xxMxxSBG5 Rev E
L9D232M72SBG5
2.2 Gb, DDR2, 32 M x 72 Integrated Memory Module (IMOD)
FIGURE 2B - FUNCTIONAL BLOCK DIAGRAM
DQ 0
!
!
!
DQ 7
DQ 32
!
!
!
DQ 39
DQ 8
!
!
!
DQ 15
DQ 40
!
!
!
DQ 47
DQ 8
!
!
!
DQ 15
DQ 24
!
!
!
DQ 31
VSS
VSSQ
ODT
VDD
D4
256Mb
VDDQ
CS\
CKE
CK
CK\
RAS\
CAS\
WE\
LDQS
LDQS\
UDQS
UDQS\
LDM
VREF
ABA
VSS
VSSQ
DQ 16
!
!
!
DQ 23
VSS
ODT
VDD
VDDQ
VREF
D3
512Mb
DQ 0
!
!
!
DQ 7
CS4\
CKE4
CLK4
CLK4\
RAS4\
CAS4\
WE4\
LDQS4
LDQS4\
UDQS4
UDQS4\
LDM4
DQ 0
!
!
!
DQ 7
DQ 64
!
!
!
DQ 71
VSSQ
CS\
CKE
CK
CK\
RAS\
CAS\
WE\
LDQS
LDQS\
UDQS
UDQS\
LDM
UDM
VDDQ
CS3\
CKE3
CLK3
CLK3\
RAS3\
CAS3\
WE3\
LDQS3
LDQS3\
UDQS3
UDQS3\
LDM3
UDM3
ODT
DQ 15
D1
512Mb
VDD
DQ 15
CS\
CKE
CK
CK\
RAS\
CAS\
WE\
LDQS
LDQS\
UDQS
UDQS\
LDM
UDM
VREF
DQ 7
DQ 8
VSS
DQ 7
DQ 8
CS1\
CKE1
CLK1
CLK1\
RAS1\
CAS1\
WE1\
LDQS1
LDQS1\
UDQS1
UDQS1\
LDM1
UDM1
ABA
VSS
VSSQ
DQ 0
VSSQ
ODT
VDD
VDDQ
VREF
D2
512Mb
DQ 0
VDDQ
ODT
D0
512Mb
VDD
ABA
CS\
CKE
CK
CK\
RAS\
CAS\
WE\
LDQS
LDQS\
UDQS
UDQS\
LDM
UDM
A
A
VREF
CS2\
CKE2
CLK2
CLK2\
RAS2\
CAS2\
WE2\
LDQS2
LDQS2\
UDQS2
UDQS2\
LDM2
UDM2
CS\
CKE
CK
CK\
RAS\
CAS\
WE\
LDQS
LDQS\
UDQS
UDQS\
LDM
UDM
ABA
CS0\
CKE0
CLK0
CLK0\
RAS0\
CAS0\
WE0\
LDQS0
LDQS0\
UDQS0
UDQS0\
LDM0
UDM0
A
ABA
VSSQ
VSS
VDDQ
VDD
ODT
VREF
A0-A12,
BA0-1
DQ 0
!
!
!
DQ 7
DQ 48
!
!
!
DQ 55
DQ 8
!
!
!
DQ 15
DQ 56
!
!
!
DQ 63
1.
LOGIC Devices Incorporated
www.logicdevices.com
11
High Performance, Integrated Memory Module Product
September 16, 2013 LDS-L9D2xxMxxSBG5 Rev E
L9D232M80SBG5
2.5 Gb, DDR2, 32 M x 80 Integrated Memory Module (IMOD)
FIGURE 2C - FUNCTIONAL BLOCK DIAGRAM
LOGIC Devices Incorporated
DQ 0
!
!
!
DQ 7
DQ 32
!
!
!
DQ 39
DQ 8
!
!
!
DQ 15
DQ 40
!
!
!
DQ 47
www.logicdevices.com
12
DQ 8
!
!
!
DQ 15
DQ 24
!
!
!
DQ 31
VSS
VSSQ
ODT
VDD
D4
512Mb
VDDQ
CS\
CKE
CK
CK\
RAS\
CAS\
WE\
LDQS
LDQS\
UDQS
UDQS\
LDM
UDM
VREF
ABA
VSS
VSSQ
ODT
VDD
VDDQ
VREF
D3
512Mb
DQ 16
!
!
!
DQ 23
VSS
CS\
CKE
CK
CK\
RAS\
CAS\
WE\
LDQS
LDQS\
UDQS
UDQS\
LDM
UDM
DQ 0
!
!
!
DQ 7
CS4\
CKE4
CLK4
CLK4\
RAS4\
CAS4\
WE4\
LDQS4
LDQS4\
UDQS4
UDQS4\
LDM4
UDM4
DQ 0
!
!
!
DQ 7
DQ 64
!
!
!
DQ 71
DQ 8
!
!
!
DQ 15
DQ 72
!
!
!
DQ 79
VSSQ
CS3\
CKE3
CLK3
CLK3\
RAS3\
CAS3\
WE3\
LDQS3
LDQS3\
UDQS3
UDQS3\
LDM3
UDM3
VDD
DQ 15
VDDQ
DQ 15
D1
512Mb
ODT
DQ 7
DQ 8
CS\
CKE
CK
CK\
RAS\
CAS\
WE\
LDQS
LDQS\
UDQS
UDQS\
LDM
UDM
VREF
DQ 7
CS1\
CKE1
CLK1
CLK1\
RAS1\
CAS1\
WE1\
LDQS1
LDQS1\
UDQS1
UDQS1\
LDM1
UDM1
ABA
VSS
VSSQ
DQ 0
DQ 8
VSS
VDDQ
VDD
D2
512Mb
DQ 0
VSSQ
ODT
VDD
VDDQ
VREF
D0
512Mb
ODT
ABA
CS\
CKE
CK
CK\
RAS\
CAS\
WE\
LDQS
LDQS\
UDQS
UDQS\
LDM
UDM
A
A
VREF
CS2\
CKE2
CLK2
CLK2\
RAS2\
CAS2\
WE2\
LDQS2
LDQS2\
UDQS2
UDQS2\
LDM2
UDM2
CS\
CKE
CK
CK\
RAS\
CAS\
WE\
LDQS
LDQS\
UDQS
UDQS\
LDM
UDM
ABA
CS0\
CKE0
CLK0
CLK0\
RAS0\
CAS0\
WE0\
LDQS0
LDQS0\
UDQS0
UDQS0\
LDM0
UDM0
A
ABA
VSSQ
VSS
VDDQ
VDD
ODT
VREF
A0-A12,
BA0-1
DQ 0
!
!
!
DQ 7
DQ 48
!
!
!
DQ 55
DQ 8
!
!
!
DQ 15
DQ 56
!
!
!
DQ 63
High Performance, Integrated Memory Module Product
September 16, 2013 LDS-L9D2xxMxxSBG5 Rev E
L9D264M64SBG5
4.0 Gb, DDR2, 64 M x 64 Integrated Memory Module (IMOD)
FIGURE 2D - FUNCTIONAL BLOCK DIAGRAM
LOGIC Devices Incorporated
www.logicdevices.com
D2
1024Mb
DQ 0
!
!
!
DQ 7
DQ 32
!
!
!
DQ 39
DQ 8
!
!
!
DQ 15
DQ 40
!
!
!
DQ 47
13
VSS
VSSQ
ODT
VDD
VDDQ
VREF
D3
1024Mb
DQ 16
!
!
!
DQ 23
DQ 8
!
!
!
DQ 15
DQ 24
!
!
!
DQ 31
VSS
CS\
CKE
CK
CK\
RAS\
CAS\
WE\
LDQS
LDQS\
UDQS
UDQS\
LDM
UDM
DQ 0
!
!
!
DQ 7
VSSQ
CS3\
CKE3
CLK3
CLK3\
RAS3\
CAS3\
WE3\
LDQS3
LDQS3\
UDQS3
UDQS3\
LDM3
UDM3
VDD
DQ 15
VDDQ
DQ 15
D1
1024Mb
ODT
DQ 7
DQ 8
CS\
CKE
CK
CK\
RAS\
CAS\
WE\
LDQS
LDQS\
UDQS
UDQS\
LDM
UDM
VREF
DQ 7
CS1\
CKE1
CLK1
CLK1\
RAS1\
CAS1\
WE1\
LDQS1
LDQS1\
UDQS1
UDQS1\
LDM1
UDM1
ABA
VSS
VDDQ
VSSQ
DQ 0
DQ 8
VSS
VDDQ
DQ 0
VSSQ
VDD
VREF
ODT
ODT
D0
1024Mb
VDD
ABA
CS\
CKE
CK
CK\
RAS\
CAS\
WE\
LDQS
LDQS\
UDQS
UDQS\
LDM
UDM
A
VREF
CS2\
CKE2
CLK2
CLK2\
RAS2\
CAS2\
WE2\
LDQS2
LDQS2\
UDQS2
UDQS2\
LDM2
UDM2
CS\
CKE
CK
CK\
RAS\
CAS\
WE\
LDQS
LDQS\
UDQS
UDQS\
LDM
UDM
ABA
CS0\
CKE0
CLK0
CLK0\
RAS0\
CAS0\
WE0\
LDQS0
LDQS0\
UDQS0
UDQS0\
LDM0
UDM0
A
ABA
VSSQ
VSS
VDDQ
VDD
ODT
VREF
A0-A12,
BA0-2
DQ 0
!
!
!
DQ 7
DQ 48
!
!
!
DQ 55
DQ 8
!
!
!
DQ 15
DQ 56
!
!
!
DQ 63
High Performance, Integrated Memory Module Product
September 16, 2013 LDS-L9D2xxMxxSBG5 Rev E
L9D264M72SBG5
4.5 Gb, DDR2, 64 M x 72 Integrated Memory Module (IMOD)
FIGURE 2E - FUNCTIONAL BLOCK DIAGRAM
LOGIC Devices Incorporated
DQ 0
!
!
!
DQ 7
DQ 32
!
!
!
DQ 39
DQ 8
!
!
!
DQ 15
DQ 40
!
!
!
DQ 47
www.logicdevices.com
CS\
CKE
CK
CK\
RAS\
CAS\
WE\
LDQS
LDQS\
UDQS
UDQS\
LDM
UDM
DQ 8
!
!
!
DQ 15
DQ 24
!
!
!
DQ 31
VSS
VSSQ
ODT
VDD
D4
512Mb
VDDQ
CS\
CKE
CK
CK\
RAS\
CAS\
WE\
LDQS
LDQS\
UDQS
UDQS\
LDM
VREF
ABA
VSS
VSSQ
ODT
VDD
VDDQ
VREF
D3
1024Mb
DQ 16
!
!
!
DQ 23
VSS
CS3\
CKE3
CLK3
CLK3\
RAS3\
CAS3\
WE3\
LDQS3
LDQS3\
UDQS3
UDQS3\
LDM3
UDM3
DQ 0
!
!
!
DQ 7
CS4\
CKE4
CLK4
CLK4\
RAS4\
CAS4\
WE4\
LDQS4
LDQS4\
UDQS4
UDQS4\
LDM4
DQ 0
!
!
!
DQ 7
DQ 64
!
!
!
DQ 71
VSSQ
DQ 15
VDDQ
DQ 15
ODT
DQ 8
D1
1024Mb
VDD
DQ 7
VSS
DQ 7
DQ 8
CS\
CKE
CK
CK\
RAS\
CAS\
WE\
LDQS
LDQS\
UDQS
UDQS\
LDM
UDM
VREF
DQ 0
CS1\
CKE1
CLK1
CLK1\
RAS1\
CAS1\
WE1\
LDQS1
LDQS1\
UDQS1
UDQS1\
LDM1
UDM1
ABA
VSS
VSSQ
DQ 0
VSSQ
ODT
VDD
VDDQ
VREF
D2
1024Mb
VDDQ
ODT
D0
1024Mb
VDD
ABA
CS\
CKE
CK
CK\
RAS\
CAS\
WE\
LDQS
LDQS\
UDQS
UDQS\
LDM
UDM
A
A
VREF
CS2\
CKE2
CLK2
CLK2\
RAS2\
CAS2\
WE2\
LDQS2
LDQS2\
UDQS2
UDQS2\
LDM2
UDM2
CS\
CKE
CK
CK\
RAS\
CAS\
WE\
LDQS
LDQS\
UDQS
UDQS\
LDM
UDM
ABA
CS0\
CKE0
CLK0
CLK0\
RAS0\
CAS0\
WE0\
LDQS0
LDQS0\
UDQS0
UDQS0\
LDM0
UDM0
A
ABA
VSSQ
VSS
VDDQ
VDD
ODT
VREF
A0-A12,
BA0-2
DQ 0
!
!
!
DQ 7
DQ 48
!
!
!
DQ 55
DQ 8
!
!
!
DQ 15
DQ 56
!
!
!
DQ 63
High Performance, Integrated Memory Module Product
September 16, 2013 LDS-L9D2xxMxxSBG5 Rev E
L9D264M80SBG5
5.0 Gb, DDR2, 64 M x 80 Integrated Memory Module (IMOD)
FIGURE 2F - FUNCTIONAL BLOCK DIAGRAM
LOGIC Devices Incorporated
DQ 0
!
!
!
DQ 7
DQ 32
!
!
!
DQ 39
DQ 8
!
!
!
DQ 15
DQ 40
!
!
!
DQ 47
www.logicdevices.com
15
DQ 8
!
!
!
DQ 15
DQ 24
!
!
!
DQ 31
VSS
VSSQ
VDD
ODT
D4
1024Mb
VDDQ
CS\
CKE
CK
CK\
RAS\
CAS\
WE\
LDQS
LDQS\
UDQS
UDQS\
LDM
UDM
VREF
ABA
VSS
VSSQ
VDD
ODT
VDDQ
VREF
D3
1024Mb
DQ 16
!
!
!
DQ 23
CS4\
CKE4
CLK4
CLK4\
RAS4\
CAS4\
WE4\
LDQS4
LDQS4\
UDQS4
UDQS4\
LDM4
UDM4
DQ 0
!
!
!
DQ 7
DQ 64
!
!
!
DQ 71
DQ 8
!
!
!
DQ 15
DQ 72
!
!
!
DQ 79
VSSQ
CS\
CKE
CK
CK\
RAS\
CAS\
WE\
LDQS
LDQS\
UDQS
UDQS\
LDM
UDM
DQ 0
!
!
!
DQ 7
VSS
CS3\
CKE3
CLK3
CLK3\
RAS3\
CAS3\
WE3\
LDQS3
LDQS3\
UDQS3
UDQS3\
LDM3
UDM3
VDD
DQ 15
VDDQ
DQ 15
D1
1024Mb
ODT
DQ 7
DQ 8
CS\
CKE
CK
CK\
RAS\
CAS\
WE\
LDQS
LDQS\
UDQS
UDQS\
LDM
UDM
VREF
DQ 7
DQ 8
CS1\
CKE1
CLK1
CLK1\
RAS1\
CAS1\
WE1\
LDQS1
LDQS1\
UDQS1
UDQS1\
LDM1
UDM1
ABA
VSS
VDD
VSSQ
DQ 0
VSSQ
VDDQ
VDD
D2
1024Mb
DQ 0
VSS
ODT
VDDQ
VREF
D0
1024Mb
ODT
ABA
CS\
CKE
CK
CK\
RAS\
CAS\
WE\
LDQS
LDQS\
UDQS
UDQS\
LDM
UDM
A
A
VREF
CS2\
CKE2
CLK2
CLK2\
RAS2\
CAS2\
WE2\
LDQS2
LDQS2\
UDQS2
UDQS2\
LDM2
UDM2
CS\
CKE
CK
CK\
RAS\
CAS\
WE\
LDQS
LDQS\
UDQS
UDQS\
LDM
UDM
ABA
CS0\
CKE0
CLK0
CLK0\
RAS0\
CAS0\
WE0\
LDQS0
LDQS0\
UDQS0
UDQS0\
LDM0
UDM0
A
ABA
VSSQ
VSS
VDDQ
VDD
ODT
VREF
A0-A12,
BA0-2
DQ 0
!
!
!
DQ 7
DQ 48
!
!
!
DQ 55
DQ 8
!
!
!
DQ 15
DQ 56
!
!
!
DQ 63
High Performance, Integrated Memory Module Product
September 16, 2013 LDS-L9D2xxMxxSBG5 Rev E
LOGIC Devices Incorporated
www.logicdevices.com
A0-A12
BA0-BA1
WE#
CAS#
RAS#
CS#
CK#
CK
CKE
ODT
16
Command
decode
Address
register
16
Mode registers
Control
logic
13
10
3
Refresh
counter
13
2
Rowaddress
MUX
16
Columnaddress
counter/
latch
Bank
control
logic
13
Bank 3
2
8
Rowaddress
latch
and
decoder
8,192
Bank 2
Bank 1
Bank 0
Column
decoder
256
(x64)
I/O gating
DM mask logic
16,384
Sense Amplifiers
amplifier
Memory array
(8,192 x 256 x 64)
Bank 0
Bank 3
Bank 2
Bank 1
COL0, COL1
64
CK, CK#
64
64
CK out
CK in
WRITE
FIFO
and
drivers
Read
latch
64
8
Data
16
16
16
16
16
16
16
16
16
16
2
16
2
2
2
2
16
Input
registers
4
DRVRS
DLL
4
16
2
RCVRS
CK, CK#
UDQS, UDQS#
LDQS, LDQS#
DATA
16
2
2
2
DQS
generator
MUX
COL0, COL1
R1
R1
SW1
VSSQ
R2
R2
SW2
R2
R2
R1
SW2
R1
R2
R2
SW2
SW2
ODT control
SW1
R1
R1
SW1
SW1
R3
R3
SW3
R3
R3
SW3
R3
R3
SW3
SW3
VDDQ
UDM, LDM
UDQS, UDQS#
LDQS, LDQS#
DQ0-DQ15
L9D232M64SBG5
L9D232M72SBG5
L9D232M80SBG5
L9D264M64SBG5
L9D264M72SBG5
L9D264M80SBG5
2 - 5.0 Gb, DDR2, 32 M [64 M] x 64/72/80 Integrated Memory Module (IMOD)
FIGURE 2G - 32 MEG X 16 INTERNAL DIE CONFIGURATION FUNCTIONAL BLOCK DIAGRAM
High Performance, Integrated Memory Module Product
September 16, 2013 LDS-L9D2xxMxxSBG5 Rev E
LOGIC Devices Incorporated
www.logicdevices.com
A0-A12
BA0-BA2
WE#
CAS#
RAS#
CS#
CK#
CK
CKE
ODT
16
Command
decode
Address
register
16
Mode registers
Control
logic
13
10
3
Refresh
counter
13
2
Rowaddress
MUX
Columnaddress
counter/
latch
Bank
control
logic
13
Bank 4
Bank 3
2
8
Rowaddress
latch
and
decoder
8,192
Bank 2
Bank 1
Bank 0
Bank 7
Bank 6
Bank 5
Bank 1
Column
decoder
256
(x64)
I/O gating
DM mask logic
16,384
Sense Amplifiers
amplifier
Memory array
(8,192 x 256 x 64)
Bank 0
Bank 4
Bank 3
Bank 2
COL0, COL1
Bank 7
Bank 6
Bank 5
64
CK, CK#
64
64
CK out
CK in
WRITE
FIFO
and
drivers
Read
latch
64
8
Data
16
16
16
16
16
16
16
16
16
16
2
16
2
2
2
2
16
Input
registers
4
DRVRS
DLL
4
16
2
RCVRS
CK, CK#
UDQS, UDQS#
LDQS, LDQS#
DATA
16
2
2
2
DQS
generator
MUX
COL0, COL1
R1
R1
SW1
VSSQ
R2
R2
SW2
R2
R2
R1
SW2
R1
R2
R2
SW2
SW2
ODT control
SW1
R1
R1
SW1
SW1
R3
R3
SW3
R3
R3
SW3
R3
R3
SW3
SW3
VDDQ
UDM, LDM
UDQS, UDQS#
LDQS, LDQS#
DQ0-DQ15
L9D232M64SBG5
L9D232M72SBG5
L9D232M80SBG5
L9D264M64SBG5
L9D264M72SBG5
L9D264M80SBG5
2 - 5.0 Gb, DDR2, 32 M [64 M] x 64/72/80 Integrated Memory Module (IMOD)
FIGURE 2H - 64 MEG X 16 INTERNAL DIE CONFIGURATION FUNCTIONAL BLOCK DIAGRAM
High Performance, Integrated Memory Module Product
September 16, 2013 LDS-L9D2xxMxxSBG5 Rev E
LOGIC Devices Incorporated
www.logicdevices.com
A0-A12
BA0-BA1
WE#
CAS#
RAS#
CS#
CK#
CK
CKE
ODT
17
Command
decode
Address
register
17
Mode registers
Control
logic
14
10
3
Refresh
counter
14
2
Rowaddress
MUX
Columnaddress
counter/
latch
Bank
control
logic
14
Bank 3
2
8
Rowaddress
latch
and
decoder
16,384
Bank 2
Bank 1
Bank 0
Column
decoder
256
(x32)
I/O gating
DM mask logic
8,192
Sense Amplifiers
amplifier
Memory array
(16,384 x 256 x 32)
Bank 0
Bank 3
Bank 2
Bank 1
COL0, COL1
32
CK, CK#
32
32
CK out
CK in
WRITE
FIFO
and
drivers
Read
latch
32
4
Data
8
8
8
8
8
8
8
8
8
8
8
2
8
2
2
2
2
Input
registers
2
DRVRS
DLL
8
2
2
RCVRS
CK, CK#
UDQS, UDQS#
LDQS, LDQS#
DATA
8
2
2
2
DQS
generator
MUX
COL0, COL1
R1
R1
SW1
VSSQ
R2
R2
SW2
R2
R2
R1
SW2
R1
R2
R2
SW2
SW2
ODT control
SW1
R1
R1
SW1
SW1
R3
R3
SW3
R3
R3
SW3
R3
R3
SW3
SW3
VDDQ
DM
RDQS
RDQS#
DQS, DQS#
DQ0-DQ7
L9D232M64SBG5
L9D232M72SBG5
L9D232M80SBG5
L9D264M64SBG5
L9D264M72SBG5
L9D264M80SBG5
2 - 5.0 Gb, DDR2, 32 M [64 M] x 64/72/80 Integrated Memory Module (IMOD)
FIGURE 2I - 64 MEG X 8 INTERNAL DIE CONFIGURATION FUNCTIONAL BLOCK DIAGRAM
High Performance, Integrated Memory Module Product
September 16, 2013 LDS-L9D2xxMxxSBG5 Rev E
LOGIC Devices Incorporated
www.logicdevices.com
A0-A12
BA0-BA2
WE#
CAS#
RAS#
CS#
CK#
CK
CKE
ODT
17
Command
decode
Address
register
17
Mode registers
Control
logic
14
10
3
Refresh
counter
14
2
Rowaddress
MUX
19
Columnaddress
counter/
latch
Bank
control
logic
14
Bank 4
Bank 3
2
8
Rowaddress
latch
and
decoder
16,384
Bank 2
Bank 1
Bank 0
Bank 7
Bank 6
Bank 5
Bank 1
Column
decoder
256
(x32)
I/O gating
DM mask logic
8,192
Sense Amplifiers
amplifier
Memory array
(16,384 x 256 x 32)
Bank 0
Bank 4
Bank 3
Bank 2
COL0, COL1
Bank 7
Bank 6
Bank 5
32
CK, CK#
32
32
CK out
CK in
WRITE
FIFO
and
drivers
Read
latch
32
4
Data
8
8
8
8
8
8
8
8
8
8
8
2
2
2
2
8
Input
registers
2
DRVRS
DLL
8
2
2
RCVRS
CK, CK#
UDQS, UDQS#
LDQS, LDQS#
DATA
8
2
2
2
2
DQS
generator
MUX
COL0, COL1
R1
R1
SW1
VSSQ
R2
R2
SW2
R2
R2
R1
SW2
R1
R2
R2
SW2
SW2
ODT control
SW1
R1
R1
SW1
SW1
R3
R3
SW3
R3
R3
SW3
R3
R3
SW3
SW3
VDDQ
DM
RDQS
RDQS#
DQS, DQS#
DQ0-DQ7
L9D232M64SBG5
L9D232M72SBG5
L9D232M80SBG5
L9D264M64SBG5
L9D264M72SBG5
L9D264M80SBG5
2 - 5.0 Gb, DDR2, 32 M [64 M] x 64/72/80 Integrated Memory Module (IMOD)
FIGURE 2J - 128 MEG X 8 INTERNAL DIE CONFIGURATION FUNCTIONAL BLOCK DIAGRAM
High Performance, Integrated Memory Module Product
September 16, 2013 LDS-L9D2xxMxxSBG5 Rev E
L9D232M64SBG5
L9D232M72SBG5
L9D232M80SBG5
L9D264M64SBG5
L9D264M72SBG5
L9D264M80SBG5
2 - 5.0 Gb, DDR2, 32 M [64 M] x 64/72/80 Integrated Memory Module (IMOD)
FEATURES
TABLE 2: ADDRESSING
LDI iMOD Addressing
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5HIUHVK&RXQW
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TABLE 3: KEY PARAMETERS
LDI
Speed
Part Number
Grade
L9D2xxMxxSBG5[C, I, E, M]25
25
L9D2xxMxxSBG5[C, I, E, M]3
/'[[0[[6%*>&,(0@
Data Rate [Mbps]
tCKAVG
CL=3
CL=4
CL=5
CL=6
QV
533
3
QV
533
QV
533
C = Commercial&RPPHUFLDOFODVVLQWHJUDWHGFRPSRQHQWIXOO\DFURVV&WR&
I = Industrial,QGXVWULDOFODVVLQWHJUDWHGFRPSRQHQWIXOO\DFURVV&WR&
E = Extended([WHQGHGFODVVLQWHJUDWHGFRPSRQHQWRSHUDEOHDFURVV&WR&
M = Mil-Temp0LO7HPSHUDWXUHRQO\FODVVLQWHJUDWHGFRPSRQHQWRSHUDEOHDFURVV&WR&
LOGIC Devices Incorporated
www.logicdevices.com
20
High Performance, Integrated Memory Module Product
September 16, 2013 LDS-L9D2xxMxxSBG5 Rev E
L9D232M64SBG5
L9D232M72SBG5
L9D232M80SBG5
L9D264M64SBG5
L9D264M72SBG5
L9D264M80SBG5
2 - 5.0 Gb, DDR2, 32 M [64 M] x 64/72/80 Integrated Memory Module (IMOD)
FEATURES
FIGURE 3 - DDR2 PART NUMBERS
Sample Part Number:
L9D2
xxM
L9D2xxMxxSBG5
BG5
xxS
Temp
LOGIC DDR2
Integrated Module
Word = 32M
64M
Speed
CLK
25 x 25 x 1.7mm
255 Ball
Array
Core Frequency MHz
267
533
3
333
667
25
400
800
Temperature
Wordwidth = x64
x72
x80
Code
Commercial (0oC to 70oC)
S= Single Channel
Data Rate Mbs
38
C
Industrial (-40oC to 85oC)
I
Extended (-40oC to 105oC)
E
Military (-55oC to 125oC)
M
Note: Not all options can be combined. Please see our Part Catalog for available offerings.
LOGIC Devices Incorporated
www.logicdevices.com
21
High Performance, Integrated Memory Module Product
September 16, 2013 LDS-L9D2xxMxxSBG5 Rev E
L9D232M64SBG5
L9D232M72SBG5
L9D232M80SBG5
L9D264M64SBG5
L9D264M72SBG5
L9D264M80SBG5
2 - 5.0 Gb, DDR2, 32 M [64 M] x 64/72/80 Integrated Memory Module (IMOD)
GENERAL DESCRIPTION
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7KHSLSHOLQHGPXOWLEDQNHGDUFKLWHFWXUHRIWKH''56'5$0DUFKLWHFWXUH
DOORZVIRUFRQFXUUHQWRSHUDWLRQVWKHUHIRUHSURYLGLQJKLJKHIIHFWLYHEDQGZLGWKE\KLGLQJURZ35(&+$5*(DQGDFWLYDWLRQWLPH
GENERAL NOTES
x7KHIXQFWLRQDOLW\DQGWKHWLPLQJOLVWHGLQ/',uV/'[[*[[%*GDWDVKHHW
DUHIRUWKH'//HQDEOHGPRGHRIRSHUDWLRQ
x7KURXJKRXWWKHGDWDVKHHWWKHYDULRXVILJXUHVDQGWH[WUHIHUWR'4'4[[
DVv'4w7KH'4WHUPLVWREHLQWHUSUHWHGDVDQ\RUDOORIWKHv>@>@w
'4OLQHVSUHVHQWLQWKLVSURGXFWGHILQLWLRQ
x,QIHUHQFHWRFRPSOHWHIXQFWLRQDOLW\LVGHVFULEHGWKURXJKRXWWKLVGRFXPHQW
$Q\SDJHRUGLVFXVVLRQZLWKLQDSDJHPD\KDYHEHHQVLPSOLILHGWRFRQYH\
vWKHwWRSLFDQGPD\QRWEHLQFOXVLYHRIDOOUHTXLUHPHQWV
7KH *E ''5 6'5$0 RSHUDWHG IURP D GLIIHUHQWLDO FORFN &/.[
&/.[? WKH FURVVLQJ RI &/.[ JRLQJ +,*+ DQG &/.[? JRLQJ /2: ZLOO EH
UHIHUUHGWRDVWKHSRVLWLYHHGJHRI&/.&RPPDQGVDGGUHVVDQGFRQWURO
VLJQDOVDUHUHJLVWHUHGDWHYHU\SRVLWLYHHGJHRI&/.,QSXWGDWDLVUHJLVWHUHGRQERWKHGJHVRI['46DQGRXWSXWGDWDLVUHIHUHQFHGWRERWKHGJHV
RI['46DVZHOODVWRERWKHGJHVRI&/.5($'DQG:5,7(DFFHVVHV
WRWKH''5PHPRU\DUHEXUVWRULHQWHGDFFHVVHVVWDUWDWDVHOHFWHGORFDWLRQDQGFRQWLQXHIRUDSURJUDPPHGQXPEHURIORFDWLRQVLQDSURJUDPPHG
VHTXHQFH$FFHVVHVEHJLQZLWKWKHUHJLVWUDWLRQRIDQ$&7,9(FRPPDQG
LOGIC Devices Incorporated
www.logicdevices.com
22
High Performance, Integrated Memory Module Product
September 16, 2013 LDS-L9D2xxMxxSBG5 Rev E
L9D232M64SBG5
L9D232M72SBG5
L9D232M80SBG5
L9D264M64SBG5
L9D264M72SBG5
L9D264M80SBG5
2 - 5.0 Gb, DDR2, 32 M [64 M] x 64/72/80 Integrated Memory Module (IMOD)
STATE DIAGRAM
FIGURE 4 - SIMPLIFIED STATE DIAGRAM
CKE L
Power
applied
Power
on
Reset
Procedure
MRS, MPR,
write
leveling
Initialization
Self
refresh
SRE
ZQCL
MRS
SRX
From any
state
RESET
ZQ
Calibration
REF
ZQCL/ZQCS
Idle
Refreshing
PDE
ACT
PDX
Active
PowerDown
Preharge
PowerDown
Activating
PDX
CKE L
CKE L
PDE
Bank
Active
WRITE
WRITE
READ
WRITE AP
READ AP
READ
Writing
READ
Reading
WRITE
READ AP
WRITE AP
WRITE AP
READ AP
PRE, PREA
Writing
PRE, PREA
PRE, PREA
Preharging
Reading
Automatic
Sequence
Command
Sequence
ACT = ACTIVATE
MPR = Multipurpose register
MRS = Mode register set
PDE = Power-down entry
PDX = Power-down exit
PRE = PRECHARGE
LOGIC Devices Incorporated
www.logicdevices.com
PREA=PRECHARGE ALL
READ = RD, RDS4, RDS8
READ AP = RDAP, RDAPS4, RDAPS8
REF = REFRESH
RESET = START RESET PROCEDURE
SRE = Self refresh entry
23
SRX = Self refresh exit
WRITE = WR, WRS4, WRS8
WRITE AP = WRAP, WRAPS4, WRAPS8
ZQCL = ZQ LONG CALIBRATION
ZQCS = ZQ SHORT CALIBRATION
High Performance, Integrated Memory Module Product
September 16, 2013 LDS-L9D2xxMxxSBG5 Rev E
L9D232M64SBG5
L9D232M72SBG5
L9D232M80SBG5
L9D264M64SBG5
L9D264M72SBG5
L9D264M80SBG5
2 - 5.0 Gb, DDR2, 32 M [64 M] x 64/72/80 Integrated Memory Module (IMOD)
FIGURE 5 - MECHANICAL DRAWING
25 ± 0.1
L9D264M80SBG5
1.2 MAX
0.6 ± 0.1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
2.975
NOM
19.05
NOM
25 ± 0.1
1.27
NOM
2.975
NOM
2.975 NOM
2.975 NOM
255 x 0.75 NOM
1.27 NOM
1RWH$OOGLPHQVLRQVLQPP
LOGIC Devices Incorporated
www.logicdevices.com
High Performance, Integrated Memory Module Product
September 16, 2013 LDS-L9D2xxMxxSBG5 Rev E
L9D232M64SBG5
L9D232M72SBG5
L9D232M80SBG5
L9D264M64SBG5
L9D264M72SBG5
L9D264M80SBG5
2 - 5.0 Gb, DDR2, 32 M [64 M] x 64/72/80 Integrated Memory Module (IMOD)
TABLE 4: ABSOLUTE MAXIMUM DC RATINGS
Symbol
Parameter
9DD
9ROWDJHRQ9DDSLQUHODWLYHWR9VV
9IN9287
MIN
MAX
UNIT
9
9ROWDJHRQDQ\SLQUHODWLYHWR9VV
9
767*
6WRUDJH7HPSHUDWXUH
°C
7&$6(
'HYLFH2SHUDWLQJ7HPSHUDWXUH
,QSXW/HDNDJHFXUUHQW$Q\LQSXW99IN9DD
9REFLQSXW99IN92WKHUSLQVQRWXQGHU
WHVW 9
II
°C
&0'$'55$6?&$6?:(?&6?&.(
$
CK, CK\
$
DM
-5
5
$
I4=
-5
5
$
I95()
$
TABLE 5: RECOMMENDED DC OPERATING CONDITIONS
PACKAGE OUTLINE DIMENSIONS
Parameter
Symbol
6XSSO\9ROWDJH
,25HIHUHQFH9ROWDJH
,27HUPLQDWLRQ9ROWDJH
MIN
TYP
MAX
UNITS
9DD
9
95()'&
[9DD
[9DD
[9DD
9
977
95()'&
95()'&
95()'&
9
127(6
/',uV''53%*$L02'LQWHUQDOO\WLHV9DDDQG9DD4WRJHWKHUDVZHOODV9VVDQG9VV4
9REFLVH[SHFWHGWRHTXDO9DDRIWKHWUDQVPLWWLQJGHYLFHDQGWRWUDFNYDULDWLRQVLQWKH'&OHYHORIWKHVDPH3HDNWR3HDN
YDULDWLRQVLQWKH'&OHYHORIWKHVDPH3HDNWR3HDNQRLVHQRQFRPPRQPRGHRQ9REFPD\QRWH[FHHGSHUFHQWRIWKH'&
YDOXH3HDNWR3HDN$&QRLVHRQ9REFPD\QRWH[FHHGSHUFHQWRI9REF'&7KLVPHDVXUHPHQWLVWREHWDNHQDWWKH
QHDUHVW9REFE\SDVVFDSDFLWRU
977LVQRWDSSOLHGGLUHFWO\WRWKHGHYLFH977LVDV\VWHPVXSSO\IRUVLJQDOWHUPLQDWLRQUHVLVWRUVLVH[SHFWHGWREHVHWHTXDOWR9REF,
DQGPXVWWUDFNYDULDWLRQVLQWKH'&OHYHORI9REF
LOGIC Devices Incorporated
www.logicdevices.com
25
High Performance, Integrated Memory Module Product
September 16, 2013 LDS-L9D2xxMxxSBG5 Rev E
L9D232M64SBG5
L9D232M72SBG5
L9D232M80SBG5
L9D264M64SBG5
L9D264M72SBG5
L9D264M80SBG5
2 - 5.0 Gb, DDR2, 32 M [64 M] x 64/72/80 Integrated Memory Module (IMOD)
TABLE 6: INPUT, INPUT/OUTPUT CAPACITANCE
Parameter
PACKAGE OUTLINE DIMENSIONS
Symbol
MIN
TYP
MAX
,QSXWFDSDFLWDQFH&.[DQG&.[?
CCK
UNITS NOTES
pF
1
,QSXWFDSDFLWDQFH$[%$[2'7
CI
20
25
30
pF
1
CIO
pF
1
,QSXW2XWSXWFDSDFLWDQFH
'4[/'46[/'46[?8'46[8'46[?/'0[8'0[
&6[?5$6[?&$6[?:([?&.([
127(6
7KLVSDUDPHWHULVVDPSOHG9DD 999DD4 9DDLQWHUQDOO\WLHG9REF 9VVI 0+]7F &
9287'& 9DD9RXWSHDNWRSHDN 9['0[LQSXWLVJURXSHGZLWK,2EDOOVUHIOHFWLQJWKHIDFWWKDWWKH\DUHPDWFKHGLQORDGLQJ
7KHFDSDFLWDQFHSHUEDOOJURXSZLOOQRWGLIIHUE\PRUHWKDQWKLVPD[LPXPDPRXQWIRUDQ\JLYHQL02'GHYLFH
TABLE 7: GENERAL IDD PARAMETERS
25
3
IDD Parameters
800Mbps
667Mbps
UNITS
CL (IDD
6
5
tCK
tRCD (IDD
15
15
QV
tRC (IDD
60
60
QV
tRRD (IDD
10
10
QV
tCK (IDD
3
QV
t5$6,DD
QV
t53,DD
QV
tRFC (IDD
15
15
QV
t)$:,DD
105
105
QV
TABLE 8: IDD7 TIMING PATTERNS (4 - BANK INTERLEAVE READ OPERATION)
LOGIC Devices Incorporated
Speed Grade
IDD7 Timing Patterns
25
$05$0''$15$1''$25$2''$35$3 D D D D D D D D D D
3
$05$0''$15$1''$25$2''$35$3 D D D D D D
www.logicdevices.com
26
High Performance, Integrated Memory Module Product
September 16, 2013 LDS-L9D2xxMxxSBG5 Rev E
L9D232M64SBG5
L9D232M72SBG5
L9D232M80SBG5
L9D264M64SBG5
L9D264M72SBG5
L9D264M80SBG5
2 - 5.0 Gb, DDR2, 32 M [64 M] x 64/72/80 Integrated Memory Module (IMOD)
TABLE 9: DDR2 IDD SPECIFICATIONS AND CONDITIONS
Parameter
0ESV
0ESV
Symbol
25
3
IDD0
P$
IDD1
P$
,''3
35
35
P$
,''4
130
130
P$
IDD2N
150
130
P$
,''3
100
50
50
P$
IDD3N
160
P$
,'':
P$
,''5
625
P$
IDD5
P$
IDD6
IDD6L
35
25
35
25
P$
,''
1300
1150
P$
UNITS
2SHUDWLQJ&XUUHQW2QHEDQNDFWLYHSUHFKDUJH
tCL=tCK(IDDtRC=tRC(IDDt5$6 t5$60,1,DD&.(LV+,*+&6?LV+,*+
EHWZHHQYDOLGFRPPDQGV$GGUHVVEXVVZLWFKLQJ'DWDEXVVZLWFKLQJ
2SHUDWLQJ&XUUHQW2QHEDQNDFWLYH5($'SUHFKDUJHFXUUHQW
I287 PD%/ &/ &/IDD$/ tCK = tCK(IDDtRCtRC(IDDt5$6 t5$6
MIN(IDDtRCD=tRCD(IDD&.(LV+,*+&6?LV+,*+EHWZHHQYDOLGFRPPDQGV$GGUHVVEXVLVVZLWFKLQJ'DWDEXVLVVZLWFKLQJ
3UHFKDUJH32:(5'2:1FXUUHQW
$OOEDQNVLGOHtCK-tCK(IDD&.(LV/2:2WKHUFRQWURODQGDGGUHVVEXV
LQSXWVDUHVWDEOH'DWDEXVLQSXWVDUHIORDWLQJ
3UHFKDUJHTXLHW67$1'%<FXUUHQW
$OOEDQNVLGOHtCK=tCK(IDD&.(LV+,*+&6?LV+,*+2WKHUFRQWURODQG
DGGUHVVEXVLQSXWVDUHVWDEOH'DWDEXVLQSXWVDUHIORDWLQJ
3UHFKDUJH67$1'%<FXUUHQW
$OOEDQNVLGOHtCK-=tCK(IDD&.(LV+,*+&6?LV+,*+2WKHUFRQWURODQG
DGGUHVVEXVLQSXWVDUHVZLWFKLQJ'DWDEXVLQSXWVDUHVZLWFKLQJ
$FWLYH32:(5'2:1FXUUHQW
MRS[12]=0
MRS[12]=1
$FWLYH67$1'%<FXUUHQW
$OOEDQNVRSHQtCK=tCK(IDDt5$60$;,DDt53 t53,DD&.(LV+,*+
&6?LV+,*+EHWZHHQYDOLGFRPPDQGV2WKHUFRQWURODQGDGGUHVVEXVLQSXWV
DUHVZLWFKLQJ'DWDEXVLQSXWVDUHVZLWFKLQJ
2SHUDWLQJ%XUVW:5,7(FXUUHQW
$OOEDQNVRSHQFRQWLQXRXVEXUVWZULWHV%/ &/ &/,DDt53 t53,DD
&.(LV+,*+&6?LV+,*+EHWZHHQYDOLGFRPPDQGV$GGUHVVEXVLQSXWVDUH
VZLWFKLQJ'DWDEXVLQSXWVDUHVZLWFKLQJ
2SHUDWLQJ%XUVW5($'FXUUHQW
$OOEDQNVRSHQFRQWLQXRXVEXUVW5($'6,RXW P$%/ &/ &/IDD
$/ tCL=tCK(IDDt5$6 t5$60$;IDDt53 t53IDD&.(LV+,*+CS\
LV+,*+EWZYDOLGFRPPDQGV$GGUHVVDQG'DWDEXVLQSXWVVZLWFKLQJ
%XUVW5()5(6+FXUUHQW
tCK=tCK(IDDUHIUHVKFRPPDQGDWHYHU\tRFC(IDDLQWHUYDO&.(LV+,*+
&6?LV+,*+EWZYDOLGFRPPDQGV2WKHUFRQWURO$GGUHVVDQG'DWDEXV
LQSXWVDUHVZLWFKLQJ
6HOI5()5(6+FXUUHQW
&.DQG&.?DW9&.(d 92WKHUFRQWURODGGUHVVDQGGDWDLQSXWVDUH
IORDWLQJ
2SHUDWLQJEDQN,QWHUOHDYH5($'FXUUHQW
$OOEDQNLQWHUOHDYLQJ5($'6,287 P$%/ &/ &/,DD$/ tRCD(IDD
1xtCK(IDDtCK=tCK(IDDtRC=tRC(IDDtRRD=tRRD(IDD&.(LV+,*+
&6?LV+,*+EHWZHHQYDOLGFRPPDQGV$GGUHVVEXVLQSXWVDUHVWDEOHGXULQJ
GHVHOHFWV'DWDEXVLQSXWVDUHVZLWFKLQJ
LOGIC Devices Incorporated
www.logicdevices.com
High Performance, Integrated Memory Module Product
September 16, 2013 LDS-L9D2xxMxxSBG5 Rev E
L9D232M64SBG5
L9D232M72SBG5
L9D232M80SBG5
L9D264M64SBG5
L9D264M72SBG5
L9D264M80SBG5
2 - 5.0 Gb, DDR2, 32 M [64 M] x 64/72/80 Integrated Memory Module (IMOD)
TABLE 10: AC TIMING SPECIFICATIONS
[I] 25
[I, E, M] 3
0+]
0ESV
0+]
0ESV
UNITS NOTES
Parameter
CL=6
CL=5
&/ Data Strobe-In
Data
Strobe-Out
Clock Jitter
CLOCK
&ORFN&\FOH7LPH
MAX
MIN
MAX
tCK$9*
3
3
tCK$9*
tCK$9*
tCH$9*
&ORFN/RZ7LPH
tCL$9*
t+3
+DOI&ORFN3HULRG
$EVROXWHtCK
tCKDEV
$EVROXWHt&.KLJKOHYHOZLGWK
tCHDEV
$EVROXWHt&.ORZOHYHOZLGWK
tCLDEV
&ORFN-LWWHU3HULRG
t-,73(5
&ORFN-LWWHU+DOI3HULRG
t-,7'7<
0,1 /HVVHURI t&+DQGt&/0$; QD
MIN = t&.$9*0,1t-,73(50,10$; t&.$9*0$;t-,73(50$;
MIN = t&.$9*0,1[t&+$9*0,1t-,73(50,1
0$; t&.$9*0$;[t&+$9*0$;t-,7'7<0$;
MIN = t&.$9*0,1[t&+$9*0,1t-,73(50,1
&XPXODWLYH-LWWHUHUURUF\FOHV
tERR3(5
&XPXODWLYH-LWWHUHUURUF\FOHV
tERR3(5
&XPXODWLYH-LWWHUHUURUF\FOHV
tERR3(5
&XPXODWLYH-LWWHUHUURUF\FOHV
tERR3(5
'46RXWSXWDFFHVVWLPHIURP&.&.?
t'46&.
'465($'SUHDPEOH
t535(
'465($'SRVWDPEOH
t5367
'46/RZ=ZLQGRZIURP&.&.?
-100
-100
t'466
'46LQSXWKLJKSXOVHZLGWK
t'46+
'46LQSXWORZSXOVHZLGWK
t'46/
'46IDOOLQJHGJHWR&.ULVLQJVHWXSWLPH
'46IDOOLQJHGJHIURP&.ULVLQJKROGWLPH
100
100
-125
-125
150
200
300
350
-250
-350
250
250
350
0,1 [ t&.0$; [tCK
0,1 [t&.0$; [tCK
MIN = t$&0,10$; t$&0$;
0,1 [t&.0$; [tCK
0,1 [ t&.0$; QD
0,1 [ t&.0$; QD
0,1 [ t&.0$; QD
0,1 [ t&.0$; QD
tDSS
tDSH
t:35(6
0,1 0$; QD
'46:5,7(SUHDPEOH
t:35(
'46:5,7(SRVWDPEOH
t:367
0,1 [ t&.0$; QD
0,1 [ t&.0$; [ tCK
0,1 :/ t'4660$; :/t'466
:5,7(SUHDPEOHVHWXSWLPH
'46'4VNHZ'46WRODVW'4YDOLGSHUJURXSSHUDFFHVV
'4KROGIURPQH[W'46VWUREH
t$&
t'464
t4+6
'4'46+ROG'46WRILUVW'4WRJRQRQYDOLGSHUDFFHVV
t4+
'DWDRXW+LJK=ZLQGRZIURP&.&.?
t+=
'4/RZ=ZLQGRZIURP&.&.?
t/=
'DWDYDOLGRXWSXWZLQGRZ'9:
t'9:
'4DQG'0LQSXWVHWXSWLPHUHODWLYHWR'46
tDSB
'4DQG'0LQSXWKROGWLPHUHODWLYHWR'46
tDHB
'4DQG'0LQSXWVHWXSWLPHUHODWLYHWR'46
tDS$
'4DQG'0LQSXWKROGWLPHUHODWLYHWR'46
tDH$
'4DQG'0LQSXWSXOVHZLGWKIRUHDFKLQSXW
t',3:
LOGIC Devices Incorporated
www.logicdevices.com
QV
6-9
tCK
10
SV
SV
SV
11
SV
125
125
200
-150
-200
-300
-350
t/=
3RVLWLYH'46ODWFKLQJHGJHWRDVVRF&ORFNHGJH
UNITS NOTES
0$; t&.$9*0$;[t&+$9*0$;t-,7'7<0$;
t-,7CC
&ORFN-LWWHU&\FOHWR&\FOH
'4RXWSXWDFFHVVWLPHIURP&.&.?
Data-Out
MIN
&ORFN+LJK7LPH
:5,7(FRPPDQGWRILUVW'46ODWFKLQJWUDQVLWLRQ
Data-In
Symbol
-
200
300
-
MIN = t+3t4+60$; QD
0,1 QD0$; t$&0$;
MIN = 2 x t$&0,10$; t$&0$;
MIN = t4+t'4640$; QD
50
125
250
250
-
100
300
300
0,1 [t&.0$; QD
-
SV
SV
SV
SV
SV
SV
SV
SV
tCK
tCK
SV
tCK
tCK
tCK
tCK
tCK
SV
tCK
tCK
tCK
SV
SV
SV
SV
SV
SV
SV
SV
SV
SV
SV
tCK
12
13
15
15
15,16
15
19
19,21,22
19
19,21,29
19,21,22
26,30,31
26,30,31
26,30,31
26,30,31
High Performance, Integrated Memory Module Product
September 16, 2013 LDS-L9D2xxMxxSBG5 Rev E
L9D232M64SBG5
L9D232M72SBG5
L9D232M80SBG5
L9D264M64SBG5
L9D264M72SBG5
L9D264M80SBG5
2 - 5.0 Gb, DDR2, 32 M [64 M] x 64/72/80 Integrated Memory Module (IMOD)
TABLE 10: AC TIMING SPECIFICATIONS CONTINUED
COMMAND AND ADDRESS
0+]
0ESV
0+]
0ESV
MIN
MAX
MIN
$GGUHVVDQG&RQWUROLQSXWSXOVHZLGWKIRUHDFKLQSXW
t,3:
$GGUHVVDQG&RQWUROLQSXWVHWXSWLPH
tISB
$GGUHVVDQG&RQWUROLQSXWKROGWLPH
tIHB
250
2
55
10
15
15
-
200
2
55
10
15
50
15
$GGUHVVDQG&RQWUROLQSXWVHWXSWLPH
tIS$
$GGUHVVDQG&RQWUROLQSXWKROGWLPH
tIH$
tCCD
&$6?WR&$6?FRPPDQGGHOD\
tRC
$&7,9(WR$&7,9(FRPPDQGVDPHEDQN
$&7,9(EDQNDWR$&7,9(EDQNE&RPPDQG
tRRD
$&7,9(WR5($'RU:5,7(GHOD\
tRCD
%DQNDFWLYDWHSHULRG
t)$:
$&7,9(WR35(&+$5*(
t5$6
,QWHUQDO5($'WR35(&+$5*(FRPPDQGGHOD\
t573
:5,7(UHFRYHU\WLPH
t:5
$XWR35(&+$5*(:5,7(UHFRYHU\35(&+$5*(WLPH
t'$/
,QWHUQDO:5,7(WR5($'FRPPDQGGHOD\
t:75
t53
35(&+$5*(FRPPDQGSHULRG
35(&+$5*($//FRPPDQGSHULRG
t53$
/2$'02'(FRPPDQG&\FOHWLPH
tMRD
&.(/2:WR&.&.?XQFHUWDLQW\
REFRESH
[I, E, M] 3
Symbol
Parameter
S. REFRESH
[I] 25
ODT
-
MIN = t:5t530$; QD
15
2
-
15
2
-
MIN limit = t,6t&.t,+0$;OLPLW QD
t'(/$<
tRFC
-
-
$YHUDJHSHULRGLF5()5(6+LQWHUYDO>LQGXVWULDOWHPS@
tREF[I]
$YHUDJHSHULRGLF5()5(6+LQWHUYDO>H[WHQGHGWHPS@
tREF[E]
$YHUDJHSHULRGLF5()5(6+LQWHUYDO>PLOLWDU\WHPS@
tREF[M]
-
-
5()5(6+WR$&7,9(RU5()5(6+WR5()5(6+
UNITS NOTES
tCK
SV
SV
SV
SV
tCK
QV
tCK
QV
QV
QV
QV
QV
QV
QV
QV
QV
tCK
QV
QV
31,33
31,33
31,33
31,33
FRPPDQGLQWHUYDO
([LW6(/)5()5(6+WR1215($'FRPPDQG
t;615
MIN limit = t5)&0,10$;OLPLW QD
([LW6(/)5()5(6+WR5($'FRPPDQG
t;65'
([LW6(/)5()5(6+WLPLQJUHIHUHQFH
t,6;5
0,1OLPLW 0$;OLPLW QD
MIN limit = t,60$;OLPLW QD
2'7WXUQRQGHOD\
t$21'
2'7WXUQRQGHOD\
t$21
2
t$&0,1
t$&0$;
t$&0,1
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High Performance, Integrated Memory Module Product
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High Performance, Integrated Memory Module Product
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2 - 5.0 Gb, DDR2, 32 M [64 M] x 64/72/80 Integrated Memory Module (IMOD)
TABLE 11: ODT ELECTRICAL CHARACTERISTICS
Parameter/Condition
RTT effective impedance value for 75 : setting
PACKAGE OUTLINE DIMENSIONS
Symbol
MIN
TYP
MAX
UNITS
NOTES
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90
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150
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TABLE 12: INPUT DC LOGIC LEVELS
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MIN
MAX
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TABLE 13: INPUT AC LOGIC LEVELS
Parameter/Condition
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P9
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9IH$&
9REF (DC
9DD4
P9
,QSXW/2:ORJLFYROWDJH
9IL$&
-300
9REF (DC
P9
,QSXW/2:ORJLFYROWDJH
9IL$&
-300
9REF (DC
P9
127(69DD4PYDOORZHGSURYLGHG9LVQRWH[FHHGHG
LOGIC Devices Incorporated
www.logicdevices.com
32
High Performance, Integrated Memory Module Product
September 16, 2013 LDS-L9D2xxMxxSBG5 Rev E
L9D232M64SBG5
L9D232M72SBG5
L9D232M80SBG5
L9D264M64SBG5
L9D264M72SBG5
L9D264M80SBG5
2 - 5.0 Gb, DDR2, 32 M [64 M] x 64/72/80 Integrated Memory Module (IMOD)
OPERATING CONDITIONS
FIGURE 6 - SINGLE ENDED INPUT SIGNAL LEVELS
1,150mV
VIH (AC)
1,025mV
VIH (DC)
936mV
918mV
900mV
882mV
864mV
VREF + AC noise
VREF + DC error
VREF - DC error
VREF - AC noise
775mV
VIL (DQ)
650mV
VIL (AC)
1RWH1XPEHUVLQGLDJUDPUHIOHFWQRPLQDO''5''5YDOXHV
LOGIC Devices Incorporated
www.logicdevices.com
33
High Performance, Integrated Memory Module Product
September 16, 2013 LDS-L9D2xxMxxSBG5 Rev E
L9D232M64SBG5
L9D232M72SBG5
L9D232M80SBG5
L9D264M64SBG5
L9D264M72SBG5
L9D264M80SBG5
2 - 5.0 Gb, DDR2, 32 M [64 M] x 64/72/80 Integrated Memory Module (IMOD)
TABLE 14: DIFFERENTIAL INPUT LOGIC LEVEL
Parameter/Condition
PACKAGE OUTLINE DIMENSIONS
Symbol
MIN
MAX
UNITS
NOTES
'&LQSXWVLJQDO9ROWDJH
9IN'&
-300
9DD4
P9
1,6
'&GLIIHUHQWLDOLQSXW9ROWDJH
9ID'&
250
9DD4
P9
2,6
$&GLIIHUHQWLDOLQSXW9ROWDJH
9ID$&
500
9DD4
P9
3,6
$&GLIIHUHQWLDOFURVVSRLQW9ROWDJH
9,;$&
[9DD4
[9DD4
P9
,QSXWPLGSRLQW9ROWDJH
903'&
950
P9
5
127(6
9IN'&VSHFLILHVWKHDOORZDEOH'&H[HFXWLRQRIHDFKLQSXWRIGLIIHUHQ-
7KHW\SLFDOYDOXHRI9,;$&LVH[SHFWHGWREHDERXW[9DD4RIWKH
WLDOSDLUVXFKDV&.[&.[?'46['46[?/'46[/'46[?8'46[
WUDQVPLWWLQJGHYLFHDQG9,;$&LVH[SHFWHGWRWUDFNYDULDWLRQVLQ9DD4
DQG8'46[?
9,;$& LQGLFDWHV WKH YROWDJH DW ZKLFK GLIIHUHQWLDO LQSXW VLJQDOV PXVW
FURVVDVVKRZQLQ)LJXUH
9ID'&VSHFLILHVWKHLQSXWGLIIHUHQWLDOYROWDJH>9759&3@UHTXLUHGIRU
VZLWFKLQJZKHUHLQSXWVXFKDV&.[?'46[?/'46[?DQG8'46[?
903'&VSHFLILHVWKHLQSXWGLIIHUHQWLDOFRPPRQPRGHYROWDJH975
OHYHO 7KH PLQLPXP YDOXH LV HTXDO WR 9IH'& 9IL'& 'LIIHUHQWLDO
9&3ZKHUH975LVWKHWUXHLQSXW&.['46[OHYHODQG9&3LVWKH
LQSXWVLJQDOOHYHOVDUHVKRZLQ)LJXUH
FRPSOHPHQWDU\LQSXW&.[?'46[?
9ID$&VSHFLILHVWKHLQSXWGLIIHUHQWLDOYROWDJH>9759&3@UHTXLUHGIRU
9DD4PYDOORZHGSURYLGHG9LVQRWH[FHHGHG
VZLWFKLQJ ZKHUH 975 LV WKH WUXH LQSXW VXFK DV &.[ '46[ /'46[
DQG8'46[OHYHO7KHPLQLPXPYDOXHLVHTXDOWR9IH'&LVHTXDOWR
9IH$&9IL$&DVVKRZQLQ7DEOH
LOGIC Devices Incorporated
www.logicdevices.com
High Performance, Integrated Memory Module Product
September 16, 2013 LDS-L9D2xxMxxSBG5 Rev E
L9D232M64SBG5
L9D232M72SBG5
L9D232M80SBG5
L9D264M64SBG5
L9D264M72SBG5
L9D264M80SBG5
2 - 5.0 Gb, DDR2, 32 M [64 M] x 64/72/80 Integrated Memory Module (IMOD)
FIGURE 7 - DIFFERENTIAL INPUT SIGNAL LEVELS
VIN(DC)max1
2.1V
VDDQ = 1.8V
CP2
1.075V
X
VMP(DC) 3 VIX(AC)4 V ID(DC) 5
0.9V
0.725V
X
VID(AC) 6
TR 2
VIN(DC)min 1
–0.30V
1RWHV75DQG&3PD\QRWEHPRUHSRVLWLYHWKDQ9DD49RUPRUHQHJDWLYHWKDQ9;;9
75UHSUHVHQWVWKH&.'465'46/'46DQG8'46VLJQDOV&3UHSUHVHQWV&.'46
5'46/'46DQG8'46VLJQDOV
7KLVSURYLGHVDPLQLPXPRIP9WRDPD[LPXPRIP9DQGLVH[SHFWHGWREH9DD4
75DQG&3PXVWFURVVLQWKLVUHJLRQ
75DQG&3PXVWPHHWDWOHDVW9ID'&PLQZKHQVWDWLFDQGLVFHQWHUHGDURXQG903'&
75DQG&3PXVWKDYHDPLQLPXPP9SHDNWRSHDNVZLQJ
1XPEHUVLQGLDJUDPUHIOHFWQRPLQDOYDOXHV9DD4 9
LOGIC Devices Incorporated
www.logicdevices.com
35
.
High Performance, Integrated Memory Module Product
September 16, 2013 LDS-L9D2xxMxxSBG5 Rev E
L9D232M64SBG5
L9D232M72SBG5
L9D232M80SBG5
L9D264M64SBG5
L9D264M72SBG5
L9D264M80SBG5
2 - 5.0 Gb, DDR2, 32 M [64 M] x 64/72/80 Integrated Memory Module (IMOD)
TABLE 15: DIFFERENTIAL AC OUTPUT PARAMETERS
PACKAGE OUTLINE DIMENSIONS
Parameter
$&GLIIHUHQWLDOFURVVSRLQW9ROWDJH
Symbol
MIN
MAX
UNITS
92;$&
[9DD4
[9DD4
P9
9VZLQJ
1
-
P9
$&GLIIHUHQWLDO9ROWDJHVZLQJ
NOTES
1,6
127(6
7KHW\SLFDOYDOXHRI92;$&LVH[SHFWHGWREHDERXW[9DD4RIWKHWUDQVPLWWLQJGHYLFHDQG92;$&LVH[SHFWHGWRWUDFN
YDULDWLRQVLQ9DD492;$&LQGLFDWHVWKHYROWDJHDWZKLFKGLIIHUHQWLDORXWSXWVLJQDOVPXVWFURVV
FIGURE 8 - DIFFERENTIAL OUTPUT SIGNAL LEVELS
VDDQ
V TR
Crossing point
Vswing
VOX
VCP
VSSQ
TABLE 16: OUTPUT DC CURRENT DRIVE
Parameter/Condition
PACKAGE OUTLINE DIMENSIONS
VALUE
UNITS
NOTES
2XWSXW0,1VRXUFH'&FXUUHQW
Symbol
IoH
9DD'&
P9
2XWSXW0,1VLQN'&FXUUHQW
IoL
9REF'&
P9
127(6
For lOH'&9DD4 99287 P992879DD4,OHPXVW
EHOHVVWKDQ:IRUYDOXHVRI9287EHWZHHQ9DD4DQG9DD4
P9
For lOL'&9DD4 99287 P99RXWOOLPXVWEHOHVVWKDQ
21:IRUYDOXHVRI9287EHWZHHQ9DQGP9
7KH'&YDOXHRI9REFDSSOLHGWRWKHUHFHLYLQJGHYLFHLVVHWWR977
LOGIC Devices Incorporated
www.logicdevices.com
36
7KHYDOXHVRIOOH'&DQGOOL'&DUHEDVHGRQWKHFRQGLWLRQVJLYHQ
LQ1RWHVDQG7KH\DUHXVHGWRWHVWGHYLFHGULYHFXUUHQWFDSDELOLW\
WRHQVXUH9IH0,1SOXVDQRLVHPDUJLQDQG9IL0$;PLQXVDQRLVH
PDUJLQDUHGHOLYHUHGWRDQ667/BUHFHLYHU7KHDFWXDOFXUUHQW
YDOXHVDUHGHULYHGE\VKLIWLQJWKHGHVLUHGGULYHURSHUDWLQJSRLQWVHH
RXWSXW,9FXUYHVDORQJD:ORDGOLQHWRGHILQHDFRQYHQLHQWGULYHU
FXUUHQWIRUPHDVXUHPHQW
High Performance, Integrated Memory Module Product
September 16, 2013 LDS-L9D2xxMxxSBG5 Rev E
L9D232M64SBG5
L9D232M72SBG5
L9D232M80SBG5
L9D264M64SBG5
L9D264M72SBG5
L9D264M80SBG5
2 - 5.0 Gb, DDR2, 32 M [64 M] x 64/72/80 Integrated Memory Module (IMOD)
TABLE 17: OUTPUT CHARACTERISTICS
PACKAGE OUTLINE DIMENSIONS
Parameter
MIN
TYP
MAX
UNITS NOTES
2XWSXW,PSHGDQFH
6HH2XWSXW'ULYHU&KDUDFWHULVWLFV
:
1,2
3XOOXSDQGSXOOGRZQPLVPDWFK
0
-
:
1,2,3
-
5
9QV
2XWSXWVOHZUDWH
127(6
$EVROXWHVSHFLILFDWLRQV&d7C d&9DD4 9
9DD 99
FIGURE 9 - OUTPUT SLEW RATE LOAD
,PSHGDQFHPHDVXUHPHQWFRQGLWLRQVIRURXWSXWVRXUFH'&FXUUHQW
9DD4 9RXW P992879DD4OOHPXVWEHOHVVWKDQ
:IRUYDOXHVRI9RXWEHWZHHQ9DD4DQG9DD4P97KH
LPSHGDQFHPHDVXUHPHQWFRQGLWLRQIRURXWSXWVLQN'&FXUUHQW9DD4
99RXW P99RXWOROPXVWEHOHVVWKDQ:IRUYDOXHVRI
9287EHWZHHQ9DQGP9
0LVPDWFKLVDQGDEVROXWHYDOXHEHWZHHQSXOOXSDQGSXOOGRZQERWK
DUHPHDVXUHGDWWKHVDPHWHPSHUDWXUHDQGYROWDJH
2XWSXWVOHZUDWHIRUIDOOLQJDQGULVLQJHGJHVLVPHDVXUHGEHWZHHQ
977P9DQG977P9IRUVLQJOHHQGHGVLJQDOV)RUGLIIHUHQWLDOVLJQDOV'46['46[?RXWSXWVOHZUDWHLVPHDVXUHGEHWZHHQ
'46['46[? P92XWSXWVOHZUDWHLVJXDUDQWHHGE\GHVLJQ
EXWLVQRWQHFHVVDULO\WHVWHGRQHDFKGHYLFH
7KHDEVROXWHYDOXHRIWKHVOHZUDWHDVPHDVXUHGIURP9IL'&0$;
WR9IH'&0,1LVHTXDOWRRUJUHDWHUWKDQWKHVOHZUDWHDVPHDVXUHG
IURP9IL$&0$;WR9IH$&0,17KLVLVJXDUDQWHHGE\GHVLJQ
$OOGHYLFHV,1'8675,$/(;7(1'('DQG0,/7(03GHYLFHV
UHTXLUHDQDGGLWLRQDO9QVLQWKH0$;OLPLWZKHQ7FLVEHWZHHQ
&DQG&
LOGIC Devices Incorporated
www.logicdevices.com
VTT = V DDQ/2
25 Ω
Output
(VOUT)
Reference
point
High Performance, Integrated Memory Module Product
September 16, 2013 LDS-L9D2xxMxxSBG5 Rev E
L9D232M64SBG5
L9D232M72SBG5
L9D232M80SBG5
L9D264M64SBG5
L9D264M72SBG5
L9D264M80SBG5
2 - 5.0 Gb, DDR2, 32 M [64 M] x 64/72/80 Integrated Memory Module (IMOD)
FIGURE 10 - FULL STRENGTH PULL DOWN CHARACTERISTICS
120
100
IOUT (mA)
80
60
40
20
0
0.0
0.5
1.0
1.5
VOUT (V)
TABLE 18: FULL STRENGTH PULL-DOWN CURRENT (mA)
Voltage (V)
LOGIC Devices Incorporated
PACKAGE OUTLINE DIMENSIONS
MIN
TYP
MAX
UNITS
P$
P$
P$
P$
P$
P$
P$
P$
P$
P$
P$
P$
P$
P$
P$
P$
P$
P$
P$
P$
www.logicdevices.com
High Performance, Integrated Memory Module Product
September 16, 2013 LDS-L9D2xxMxxSBG5 Rev E
L9D232M64SBG5
L9D232M72SBG5
L9D232M80SBG5
L9D264M64SBG5
L9D264M72SBG5
L9D264M80SBG5
2 - 5.0 Gb, DDR2, 32 M [64 M] x 64/72/80 Integrated Memory Module (IMOD)
FIGURE 11 - FULL STRENGTH PULL UP CHARACTERISTICS
0
–20
IOUT (mA)
–40
–60
–80
–100
–120
0
0.5
1.0
1.5
VDDQ - VOUT (V)
TABLE 19: FULL STRENGTH PULL-UP CURRENT (mA)
Voltage (V)
LOGIC Devices Incorporated
PACKAGE OUTLINE DIMENSIONS
MIN
TYP
MAX
UNITS
P$
P$
P$
P$
P$
P$
P$
P$
P$
P$
P$
P$
P$
P$
P$
P$
P$
P$
P$
P$
www.logicdevices.com
39
High Performance, Integrated Memory Module Product
September 16, 2013 LDS-L9D2xxMxxSBG5 Rev E
L9D232M64SBG5
L9D232M72SBG5
L9D232M80SBG5
L9D264M64SBG5
L9D264M72SBG5
L9D264M80SBG5
2 - 5.0 Gb, DDR2, 32 M [64 M] x 64/72/80 Integrated Memory Module (IMOD)
FIGURE 12 - REDUCED STRENGTH PULL DOWN CHARACTERISTICS
70
60
IOUT (mV)
50
40
30
20
10
0
0.0
0.5
1.0
1.5
VOUT (V)
TABLE 20: REDUCED STRENGTH PULL-DOWN CURRENT (mA) PACKAGE OUTLINE DIMENSIONS
Voltage (V)
LOGIC Devices Incorporated
MIN
TYP
MAX
UNITS
P$
P$
P$
P$
P$
P$
P$
P$
P$
P$
P$
P$
P$
P$
P$
P$
P$
P$
P$
P$
www.logicdevices.com
High Performance, Integrated Memory Module Product
September 16, 2013 LDS-L9D2xxMxxSBG5 Rev E
L9D232M64SBG5
L9D232M72SBG5
L9D232M80SBG5
L9D264M64SBG5
L9D264M72SBG5
L9D264M80SBG5
2 - 5.0 Gb, DDR2, 32 M [64 M] x 64/72/80 Integrated Memory Module (IMOD)
FIGURE 13 - REDUCED STRENGTH PULL UP CHARACTERISTICS
0
–10
IOUT (mV)
–20
–30
–40
–50
–60
–70
0.0
0.5
1.0
1.5
VDDQ - VOUT (V)
TABLE 21: REDUCED STRENGTH PULL-UP CURRENT (mA)
Voltage (V)
LOGIC Devices Incorporated
PACKAGE OUTLINE DIMENSIONS
MIN
TYP
MAX
UNITS
P$
P$
P$
P$
P$
P$
P$
P$
P$
P$
P$
P$
P$
P$
P$
P$
P$
P$
P$
P$
www.logicdevices.com
High Performance, Integrated Memory Module Product
September 16, 2013 LDS-L9D2xxMxxSBG5 Rev E
L9D232M64SBG5
L9D232M72SBG5
L9D232M80SBG5
L9D264M64SBG5
L9D264M72SBG5
L9D264M80SBG5
2 - 5.0 Gb, DDR2, 32 M [64 M] x 64/72/80 Integrated Memory Module (IMOD)
TABLE 22: INPUT CLAMP CHARACTERISTICS
Voltage (V) Across Clamp
PACKAGE OUTLINE DIMENSIONS
MIN Power Clamp Current
MIN Ground Clamp Current
UNITS
P$
P$
P$
P$
P$
P$
P$
P$
P$
P$
P$
P$
P$
P$
P$
P$
P$
P$
P$
FIGURE 14 - INPUT CLAMP CHARACTERISTICS
Minimum Clamp Current (mA)
25
20
15
10
5
0
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8
Voltage Across Clamp (V)
LOGIC Devices Incorporated
www.logicdevices.com
High Performance, Integrated Memory Module Product
September 16, 2013 LDS-L9D2xxMxxSBG5 Rev E
L9D232M64SBG5
L9D232M72SBG5
L9D232M80SBG5
L9D264M64SBG5
L9D264M72SBG5
L9D264M80SBG5
2 - 5.0 Gb, DDR2, 32 M [64 M] x 64/72/80 Integrated Memory Module (IMOD)
TABLE 23: ADDRESS AND CONTROLS PINS
PACKAGE OUTLINE DIMENSIONS
SPECIFICATIONS
Parameter
25
3
UNITS
9
0D[LPXPSHDNDPSOLWXGHDOORZHGIRUXQGHUVKRRWDUHDVHH)LJXUH
9
0D[LPXPRYHUVKRRWDUHDDERYH9DD VHH)LJXUH
9QV
0D[LPXPXQGHUVKRRWDUHDEHORZ9VVVHH)LJXUH
9QV
0D[LPXPSHDNDPSOLWXGHIRURYHUVKRRWDUHDVHH)LJXUH
TABLE 24: CLOCK, DATA, STROBE, AND MASK PINS
PACKAGE OUTLINE DIMENSIONS
SPECIFICATIONS
Parameter
25
3
UNITS
0D[LPXPSHDNDPSOLWXGHIRURYHUVKRRWDUHDVHH)LJXUH
9
0D[LPXPSHDNDPSOLWXGHDOORZHGIRUXQGHUVKRRWDUHDVHH)LJXUH
9
0D[LPXPRYHUVKRRWDUHDDERYH9DD4VHH)LJXUH
9QV
0D[LPXPXQGHUVKRRWDUHDEHORZ9VV4VHH)LJXUH
9QV
FIGURE 15 & 16: OVERSHOOT/UNDERSHOOT SPECIFICATIONS
Maximum amplitude
Volts (V)
Figure 15: Overshoot
VDD/VDDQ
VSS/VSSQ
Overshoot area
Time (ns)
Time (ns)
Figure 16: Undershoot
VSS/VSSQ
Volts (V)
Maximum amplitude
LOGIC Devices Incorporated
www.logicdevices.com
Undershoot area
High Performance, Integrated Memory Module Product
September 16, 2013 LDS-L9D2xxMxxSBG5 Rev E
L9D232M64SBG5
L9D232M72SBG5
L9D232M80SBG5
L9D264M64SBG5
L9D264M72SBG5
L9D264M80SBG5
2 - 5.0 Gb, DDR2, 32 M [64 M] x 64/72/80 Integrated Memory Module (IMOD)
TABLE 25: AC INPUT TEST CONDITIONS
Parameter/Condition
PACKAGE OUTLINE DIMENSIONS
Symbol
,QSXWVHWXSWLPLQJPHDVXUHPHQWUHIHUHQFHOHYHODGGUHVVEDOOV
MIN
MAX
UNITS
NOTES
9RS
See Note 2
9RH
See Note 5
EDQNDGGUHVVEDOOV&6?5$6?&$6?:(?2'7'0
8'0/'0DQG&.(
,QSXWKROGWLPLQJPHDVXUHPHQWUHIHUHQFHOHYHODGGUHVVEDOOV
EDQNDGGUHVVEDOOV&6?5$6?&$6?:(?2'7'0
8'0/'0DQG&.(
,QSXWWLPLQJPHDVXUHPHQWUHIHUHQFHOHYHOVLQJOHHQGHG8'46[/'46[
9REF'&
,QSXWWLPLQJPHDVXUHPHQWUHIHUHQFHOHYHOGLIIHUHQWLDO&.&.?8'46[
9RD
9DD4[
9DD4[
9,;$&
9
9
8'46[?/'46[/'46[?
127(6
,QSXWZDYHIRUPVHWXSWLPLQJt'6DQGKROGWLPLQJt'+ZKHQVLQJOH
$OOYROWDJHVUHIHUHQFHGWR9VV
,QSXWZDYHIRUPVHWXSWLPLQJt,6ELVUHIHUHQFHGIURPWKHLQSXWVLJQDO
8'46 RU /'46 WKURXJK WKH 9REF OHYHO DSSOLHG WR WKH GHYLFH XQGHU
FURVVLQJDWWKH9IH$&OHYHOIRUDULVLQJVLJQDODQG9IL$&IRUDIDOOLQJ
WHVWDVVKRZQLQ)LJXUH
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VLJQDODSSOLHGWRWKHGHYLFHXQGHUWHVWDVVKRZQLQ)LJXUH
6HH,QSXW6OHZ5DWH'HUDWLQJ
,QSXWZDYHIRUPVHWXSWLPLQJt'6DQGKROGWLPLQJt'+ZKHQGLIIHUHQWLDOGDWDVWUREHLVHQDEOHGLVUHIHUHQFHGIURPWKHFURVVSRLQWRI'46[
'46[?8'46[8'46[?/'46[/'46[?DVVKRZQLQ)LJXUH
7KHVOHZUDWHIRUVLQJOHHQGHGLQSXWVLVPHDVXUHGIURP'&OHYHOWR$&
OHYHO9IL'&WR9IH$&RQWKHULVLQJHGJHDQG9IL$&WR9IH'&RQ
,QSXWZDYHIRUPWLPLQJLVUHIHUHQFHGWRWKHFURVVLQJSRLQWOHYHO9L[RI
WKHIDOOLQJHGJH)RUVLJQDOVUHIHUHQFHGWR9REFWKHYDOLGLQWHUVHFWLRQ
WZRLQSXWVLJQDOV9WUDQG9FSDSSOLHGWRWKHGHYLFHXQGHUWHVWZKHUH
LVZKHUHWKHvWDQJHQWwOLQHLQWHUVHFWV9REFDVVKRZQLQ)LJXUH
9WULVWKHWUXHLQSXWVLJQDODQG9FSLVWKHFRPSOHPHQWDU\LQSXWVLJQDO
DQG
DVVKRZQLQ)LJXUH
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7KHVOHZUDWHIRUGLIIHUHQWLDOO\HQGHGLQSXWVLVPHDVXUHGIURPWZLFHWKH
FURVVLQJDWWKH9IL'&OHYHOIRUDULVLQJVLJQDODQG9IH'&IRUDIDOOLQJ
'&OHYHOWRWZLFHWKH$&OHYHO[9IL'&WR[9IH$&RQWKHIDOOLQJ
VLJQDODSSOLHGWRWKHGHYLFHXQGHUWHVWDVVKRZQLQ)LJXUH
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ULVLQJHGJHDQGZRXOGEHP9WRP9IRU&.IDOOLQJHGJH
LOGIC Devices Incorporated
www.logicdevices.com
High Performance, Integrated Memory Module Product
September 16, 2013 LDS-L9D2xxMxxSBG5 Rev E
L9D232M64SBG5
L9D232M72SBG5
L9D232M80SBG5
L9D264M64SBG5
L9D264M72SBG5
L9D264M80SBG5
2 - 5.0 Gb, DDR2, 32 M [64 M] x 64/72/80 Integrated Memory Module (IMOD)
INPUT SLEW RATE DERATING
t,+ WKH QRPLQDO VOHZ UDWH IRU D ULVLQJ VLJQDO LV GHILQHG DV WKH VOHZ UDWH
)RUDOOLQSXWVLJQDOVWKHWRWDOt,6VHWXSWLPHDQGt,+KROGWLPHUHTXLUHGLV
FDOFXODWHGE\DGGLQJWKHGDWDVKHHW t,6EDVHDQG t,+EDVHYDOXHWRWKH
't,6DQG't,+GHUDWLQJYDOXHUHVSHFWLYHO\6HWXSDQGKROGWLPHVDUHEDVHG
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WKDQWKHHTXLYDOHQWQXPEHURIGLVFUHWHGHYLFHVGXHWRWKHKLJKHUOHYHORI
GLHLQWHJUDWLRQKRZHYHULWPXVWEHDFFRXQWHGIRUZKHQGULYLQJWKHVHSLQV
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XQOHVVPHDVXUHVDUHPDGHWRLQFUHDVHWKHVWUHQJWKRIWKHVLJQDOGULYHUDQG
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TABLE 26: DDR2-400/533 SETUP AND HOLD TIME DERATING VALUES (tIS/tIH)
CMD/ADDR
Slew Rate V/ns
CK, CK\ Differential Slew Rate
2.0V/ns
1.5V/ns
UNITS
1.0V/ns
'tIS
'tIH
'tIS
'tIH
'tIS
'tIH
SV
209
119
239
SV
113
SV
150
105
210
135
SV
125
155
105
SV
21
113
51
SV
0
0
30
30
60
60
SV
-11
19
16
SV
-25
-31
5
-1
29
29
SV
-13
6
6
SV
-53
-23
-23
SV
-110
-125
-95
-65
-65
SV
SV
-292
-255
-262
-232
-232
SV
-350
-320
-315
-315
SV
-525
-500
SV
SV
-1125
-1095
-1065
-1065
SV
LOGIC Devices Incorporated
www.logicdevices.com
High Performance, Integrated Memory Module Product
September 16, 2013 LDS-L9D2xxMxxSBG5 Rev E
L9D232M64SBG5
L9D232M72SBG5
L9D232M80SBG5
L9D264M64SBG5
L9D264M72SBG5
L9D264M80SBG5
2 - 5.0 Gb, DDR2, 32 M [64 M] x 64/72/80 Integrated Memory Module (IMOD)
TABLE 27: DDR2-667/800 SETUP AND HOLD TIME DERATING VALUES (tIS/tIH)
CMD/ADDR
Slew Rate V/ns
CK, CK\ Differential Slew Rate
2.0V/ns
1.5V/ns
UNITS
1.0V/ns
'tIS
'tIH
'tIS
'tIH
'tIS
'tIH
150
210
SV
119
203
SV
133
163
113
193
SV
120
150
105
135
SV
100
160
105
SV
21
51
SV
0
0
30
30
60
60
SV
-5
25
16
55
SV
-13
-31
-1
29
SV
-22
6
SV
-53
36
-23
SV
-60
-125
-30
-95
0
-65
SV
-100
SV
-292
-262
-232
SV
-200
-315
SV
-325
-500
-295
-265
SV
SV
-1000
-1125
-1095
-1065
SV
LOGIC Devices Incorporated
www.logicdevices.com
High Performance, Integrated Memory Module Product
September 16, 2013 LDS-L9D2xxMxxSBG5 Rev E
L9D232M64SBG5
L9D232M72SBG5
L9D232M80SBG5
L9D264M64SBG5
L9D264M72SBG5
L9D264M80SBG5
2 - 5.0 Gb, DDR2, 32 M [64 M] x 64/72/80 Integrated Memory Module (IMOD)
FIGURE 17 - NOMINAL SLEW RATE FOR tIS
CK
CK#
t IH
t IS
VDDQ
t IH
t IS
VIH(AC)min
VREF to AC
region
VIH(DC)min
Nominal
slew rate
VREF(DC)
Nominal
slew rate
VIL(DC)max
VREF to AC
region
VIL(AC)max
VSS
ΔTF
ΔTR
VIH(AC)min - VREF (DC)
Setup slew rate
=
rising signal
ΔTR
VREF(DC) - VIL(AC)max
Setup slew rate
=
falling signal
ΔTF
FIGURE 18 - TANGENT LINE FOR tIS
CK
CK#
t IS
VDDQ
t IH
t IS
t IH
VIH(AC)min
VREF to AC
region
Nominal
line
VIH(DC)min
Tangent
line
VREF(DC)
Tangent
line
VIL(DC)max
Nominal
line
VREF to AC
region
VIL(AC)max
ΔTF
ΔTR
VSS
Setup slew rate
Tangent li ne (VIH[AC]min - VREF[DC])
=
rising signal
ΔTR
LOGIC Devices Incorporated
www.logicdevices.com
High Performance, Integrated Memory Module Product
September 16, 2013 LDS-L9D2xxMxxSBG5 Rev E
L9D232M64SBG5
L9D232M72SBG5
L9D232M80SBG5
L9D264M64SBG5
L9D264M72SBG5
L9D264M80SBG5
2 - 5.0 Gb, DDR2, 32 M [64 M] x 64/72/80 Integrated Memory Module (IMOD)
FIGURE 19 - NOMINAL SLEW RATE FOR tIH
CK
CK#
t IS
t IS
t IH
t IH
VDDQ
VIH(AC)min
VIH(DC)min
DC to V REF
region
Nominal
slew rate
VREF(DC)
Nominal
slew rate
DC to V REF
region
VIL(DC)max
VIL(AC)max
VSS
ΔTR
ΔTF
FIGURE 20 - TANGENT LINE FOR tIH
CK
CK#
t IS
t IS
t IH
t IH
VDDQ
VIH(AC)min
Nominal
line
VIH(DC)min
DC to V REF
region
Tangent
line
VREF(DC)
Tangent
line
Nominal
line
DC to V REF
region
VIL(DC)max
VIL(AC)max
VSS
ΔTR
Hold slew rate
=
rising signal
LOGIC Devices Incorporated
www.logicdevices.com
Tangent line (VREF[DC] - VIL [DC] max)
ΔTR
Hold slew rate
=
falling signal
ΔTF
Tangent line (VIH [DC ]min - VREF[DC] )
ΔTF
High Performance, Integrated Memory Module Product
September 16, 2013 LDS-L9D2xxMxxSBG5 Rev E
L9D232M64SBG5
L9D232M72SBG5
L9D232M80SBG5
L9D264M64SBG5
L9D264M72SBG5
L9D264M80SBG5
2 - 5.0 Gb, DDR2, 32 M [64 M] x 64/72/80 Integrated Memory Module (IMOD)
TABLE 28 - DDR2-400/533 tDS, tDH DERATING VALUES WITH DIFFERENTIAL STROBE
DQ
Slew Rate V/ns
DQSx, DQSx\ Differential Slew Rate
4.0V/ns
3.0V/ns
2.0V/ns
1.8V/ns
1.6V/ns
1.4V/ns
1.2V/ns
1.0V/ns
0.8V/ns
'tDS 'tDH 'tDS 'tDH 'tDS 'tDH 'tDS 'tDH 'tDS 'tDH 'tDS 'tDH 'tDS 'tDH 'tDS 'tDH 'tDS 'tDH
125
125
125
-
-
-
-
-
-
-
-
-
-
-
-
21
21
21
95
33
-
-
-
-
-
-
-
-
-
-
0
0
0
0
0
0
12
12
-
-
-
-
-
-
-
-
-
-
-11
-11
1
-2
13
10
25
22
-
-
-
-
-
-
-
-
-
-
-25
-31
-13
-19
-1
11
5
23
-
-
-
-
-
-
-
-
-
-
-31
-19
-30
5
-6
6
-
-
-
-
-
-
-59
-31
-19
-35
-23
5
-11
-
-
-62
-50
-65
-53
-
-
-
-115
-103
-116
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
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v'&WR9REF'&UHJLRQwWKHUDWHRIDWDQJHQWOLQHWRWKHDFWXDOVLJQDO
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)LJXUH
LOGIC Devices Incorporated
www.logicdevices.com
High Performance, Integrated Memory Module Product
September 16, 2013 LDS-L9D2xxMxxSBG5 Rev E
L9D232M64SBG5
L9D232M72SBG5
L9D232M80SBG5
L9D264M64SBG5
L9D264M72SBG5
L9D264M80SBG5
2 - 5.0 Gb, DDR2, 32 M [64 M] x 64/72/80 Integrated Memory Module (IMOD)
TABLE 29 - DDR2-667/800 tDS, tDH DERATING VALUES WITH DIFFERENTIAL STROBE
DQ
Slew Rate V/ns
DQSx, DQSx\ Differential Slew Rate
4.0V/ns
3.0V/ns
2.0V/ns
1.8V/ns
1.6V/ns
1.4V/ns
1.2V/ns
1.0V/ns
0.8V/ns
'tDS 'tDH 'tDS 'tDH 'tDS 'tDH 'tDS 'tDH 'tDS 'tDH 'tDS 'tDH 'tDS 'tDH 'tDS 'tDH 'tDS 'tDH
100
63
100
63
100
63
112
136
99
111
160
123
135
91
66
103
115
90
102
139
0
0
0
0
0
0
12
12
36
36
60
60
-5
-5
-5
-2
19
10
31
22
55
-13
-31
-13
-31
-13
-31
-1
-19
11
23
5
35
29
59
-22
-22
-22
-10
2
-30
26
-6
6
50
-22
-10
-59
2
-35
26
-23
-11
-60
-125
-60
-125
-60
-125
-113
-36
-101
-12
0
-65
12
-53
-100
-100
-100
-152
-52
-116
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LOGIC Devices Incorporated
www.logicdevices.com
50
High Performance, Integrated Memory Module Product
September 16, 2013 LDS-L9D2xxMxxSBG5 Rev E
L9D232M64SBG5
L9D232M72SBG5
L9D232M80SBG5
L9D264M64SBG5
L9D264M72SBG5
L9D264M80SBG5
2 - 5.0 Gb, DDR2, 32 M [64 M] x 64/72/80 Integrated Memory Module (IMOD)
TABLE 30 - SINGLE-ENDED DQS SLEW RATE DERATING VALUES USING tDSB, tDHB
DQ
Slew Rate V/ns
DQSx Single-Ended Slew Rate Derated (at VREF)
2.0V/ns
1.8V/ns
1.6V/ns
1.4V/ns
1.2V/ns
1.0V/ns
0.8V/ns
0.6V/ns
0.4V/ns
'tDS 'tDH 'tDS 'tDH 'tDS 'tDH 'tDS 'tDH 'tDS 'tDH 'tDS 'tDH 'tDS 'tDH 'tDS 'tDH 'tDS 'tDH
130
53
130
53
130
53
130
53
130
53
155
160
123
135
32
32
32
32
32
112
122
102
139
30
-10
30
-10
30
-10
30
-10
30
-10
-15
55
60
60
25
25
25
25
25
-29
50
-32
55
32
29
59
5
5
5
5
5
20
-69
30
6
50
-93
-93
-93
-93
-93
-102
26
-23
-11
-135
-135
-135
-135
-135
-13
-3
0
-65
12
-53
-63
-203
-53
-206
-116
TABLE 31 - SINGLE-ENDED DQS SLEW RATE FULLY DERATED (DQS, DQ AT VREF) AT DDR2-667
DQ
Slew Rate V/ns
DQSx Single-Ended Slew Rate Derated (at VREF)
2.0V/ns
1.8V/ns
1.6V/ns
1.4V/ns
1.2V/ns
1.0V/ns
0.8V/ns
0.6V/ns
0.4V/ns
'tDS 'tDH 'tDS 'tDH 'tDS 'tDH 'tDS 'tDH 'tDS 'tDH 'tDS 'tDH 'tDS 'tDH 'tDS 'tDH 'tDS 'tDH
330
291
330
291
330
291
330
291
330
290
330
290
330
290
330
290
330
290
330
290
330
290
330
290
290
290
290
290
290
290
290
290
391
290
391
290
391
290
391
290
290
290
290
290
290
290
290
290
522
522
522
522
291
355
365
330
290
355
365
330
290
355
365
290
362
392
290
392
391
290
290
290
522
330
TABLE 32 - SINGLE-ENDED DQS SLEW RATE FULLY DERATED (DQS, DQ AT VREF) AT DDR2-533
DQ
Slew Rate V/ns
DQSx Single-Ended Slew Rate Derated (at VREF)
2.0V/ns
1.8V/ns
1.6V/ns
1.4V/ns
1.2V/ns
1.0V/ns
0.8V/ns
0.6V/ns
0.4V/ns
'tDS 'tDH 'tDS 'tDH 'tDS 'tDH 'tDS 'tDH 'tDS 'tDH 'tDS 'tDH 'tDS 'tDH 'tDS 'tDH 'tDS 'tDH
351
351
351
351
351
336
332
390
329
326
335
332
399
329
325
395
335
332
325
335
332
325
335
332
325
335
331
325
510
510
510
510
510
525
335
535
332
555
325
335
332
325
339
339
339
339
339
662
331
692
LOGIC Devices Incorporated
www.logicdevices.com
51
High Performance, Integrated Memory Module Product
September 16, 2013 LDS-L9D2xxMxxSBG5 Rev E
L9D232M64SBG5
L9D232M72SBG5
L9D232M80SBG5
L9D264M64SBG5
L9D264M72SBG5
L9D264M80SBG5
2 - 5.0 Gb, DDR2, 32 M [64 M] x 64/72/80 Integrated Memory Module (IMOD)
TABLE 33 - SINGLE-ENDED DQS SLEW RATE FULLY DERATED (DQS, DQ AT VREF) AT DDR2-400
DQ
Slew Rate V/ns
DQSx Single-Ended Slew Rate Derated (at VREF)
2.0V/ns
1.8V/ns
1.6V/ns
1.4V/ns
1.2V/ns
1.0V/ns
0.8V/ns
0.6V/ns
0.4V/ns
'tDS 'tDH 'tDS 'tDH 'tDS 'tDH 'tDS 'tDH 'tDS 'tDH 'tDS 'tDH 'tDS 'tDH 'tDS 'tDH 'tDS 'tDH
391
391
391
391
391
390
390
390
390
390
390
390
390
390
390
390
390
390
390
390
390
390
390
390
390
513
390
513
390
513
390
513
390
513
390
560
390
560
390
560
390
560
390
560
390
622
390
622
390
622
390
622
390
622
390
LOGIC Devices Incorporated
www.logicdevices.com
52
595
605
High Performance, Integrated Memory Module Product
September 16, 2013 LDS-L9D2xxMxxSBG5 Rev E
L9D232M64SBG5
L9D232M72SBG5
L9D232M80SBG5
L9D264M64SBG5
L9D264M72SBG5
L9D264M80SBG5
2 - 5.0 Gb, DDR2, 32 M [64 M] x 64/72/80 Integrated Memory Module (IMOD)
FIGURE 21 - NOMINAL SLEW RATE FOR tDS
DQS 1
DQS# 1
t DS
t DH
t DS
t DH
V DDQ
V IH(AC)min
V REF to AC
region
V IH(DC)min
Nominal
slew rate
V REF(DC)
Nominal
slew rate
V IL(DC)max
V REF to AC
region
V IL(AC)max
V SS
ΔTR
ΔTF
V REF(DC) - V IL(AC)max
Setup slew rate
=
falling signal
ΔTF
V IH(AC)min - V REF(DC)
Setup slew rate
=
rising signal
ΔTR
1. DQS, DQS# signals must be monotonic between VIL(DC)max and VIH(DC)min
Note:
.
FIGURE 22 - TANGENT LINE FOR tDS
DQS 1
DQS# 1
t
DS
V DDQ
t
t
DH
DS
t
DH
V IH(AC)min
Nominal
line
V REF to AC
region
V IH(DC)min
Tangent line
V REF(DC)
Tangent line
V IL(DC)max
Nominal line
V REF to AC
region
V IL(AC)max
ΔTR
ΔTF
V SS
Setup slew rate
falling signal
Note:
LOGIC Devices Incorporated
=
Tangent line (V REF[DC] - V IL[AC]max )
Tangent line (V IH[AC]min - V REF[DC] )
Setup slew rate
=
rising signal
ΔTR
ΔTF
1. DQS, DQS# signals must be monotonic between VIL(DC)max and VIH(DC)min.
www.logicdevices.com
53
High Performance, Integrated Memory Module Product
September 16, 2013 LDS-L9D2xxMxxSBG5 Rev E
L9D232M64SBG5
L9D232M72SBG5
L9D232M80SBG5
L9D264M64SBG5
L9D264M72SBG5
L9D264M80SBG5
2 - 5.0 Gb, DDR2, 32 M [64 M] x 64/72/80 Integrated Memory Module (IMOD)
FIGURE 23 - NOMINAL SLEW RATE FOR tDH
DQS 1
DQS# 1
t IS
t IH
t IS
t IH
V DDQ
V IH(AC)min
V IH(DC)min
DC to V REF
region
Nominal
slew rate
V REF(DC)
Nominal
slew rate
DC to V REF
region
V IL(DC)max
V IL(AC)max
V SS
ΔTF
ΔTR
V IH(DC)min - V REF(DC)
Hold slew rate
=
falling signal
ΔTF
V
- V IL(DC)max
Hold slew rate
= REF(DC)
rising signal
ΔTR
Note:
1. DQS, DQS# signals must be monotonic between VIL(DC)max and VIH(DC)min.
FIGURE 24 - TANGENT LINE FOR tDH
DQS1
DQS#1
t IS
t IS
t IH
t IH
VDDQ
VIH(AC)min
Nominal
line
VIH(DC)min
DC to V REF
region
Tangent
line
VREF(DC)
Tangent
line
Nominal
line
DC to V REF
region
VIL(DC)max
VIL(AC)max
VSS
ΔTR
Hold slew rate Tangent line (VREF[DC]- VIL[DC]max )
rising signal =
ΔTR
Note:
LOGIC Devices Incorporated
ΔTF
Hold slew rate Tangent line (VIH[DC]min - VREF[DC])
falling signal =
ΔTF
1. DQS, DQS# signals must be monotonic between VIL(DC)max and VIH(DC)min.
www.logicdevices.com
High Performance, Integrated Memory Module Product
September 16, 2013 LDS-L9D2xxMxxSBG5 Rev E
L9D232M64SBG5
L9D232M72SBG5
L9D232M80SBG5
L9D264M64SBG5
L9D264M72SBG5
L9D264M80SBG5
2 - 5.0 Gb, DDR2, 32 M [64 M] x 64/72/80 Integrated Memory Module (IMOD)
FIGURE 25 - AC INPUT TEST SIGNAL WAVEFORM COMMAND/ADDRESS BALLS
CK#
CK
t IS
b
Logic levels
t IH
t IS
b
b
t IH
b
VDDQ
Vswing (MAX)
VIH(AC)min
VIH(DC)min
VREF(DC)
VIL(DC)min
VIL(AC)min
VSSQ
VREF levels
t ISa
t IHa
t ISa
t IHa
FIGURE 26 - AC INPUT TEST SIGNAL WAVEFORM FOR DATA WITH DQS, DQS# (DIFFERENTIAL)
DQS#
DQS
t DS b
t DS b
t DH b
t DH b
Logic levels
VDDQ
Vswing (MAX)
VIH(AC)min
VIH(DC)min
VREF(DC)
VIL(DC)max
VIL(AC)max
VSSQ
VREF levels
LOGIC Devices Incorporated
www.logicdevices.com
t DS a
t DH a
t DS a
55
t DH a
High Performance, Integrated Memory Module Product
September 16, 2013 LDS-L9D2xxMxxSBG5 Rev E
L9D232M64SBG5
L9D232M72SBG5
L9D232M80SBG5
L9D264M64SBG5
L9D264M72SBG5
L9D264M80SBG5
2 - 5.0 Gb, DDR2, 32 M [64 M] x 64/72/80 Integrated Memory Module (IMOD)
FIGURE 27 - AC INPUT TEST SIGNAL WAVEFORM FOR DATA WITH DQS (SINGLE-ENDED)
VREF
DQS
Logic levels
t DS b
t DH b
t DS b
t DH b
VDDQ
VIH(AC)min
Vswing (MAX)
VIH(DC)min
VREF(DC)
VIL(DC)max
VIL(AC)max
VSSQ
VREF levels
t DSa
t DHa
t DSa
t DHa
FIGURE 28 - AC INPUT TEST SIGNAL WAVEFORM (DIFFERENTIAL)
VDDQ
VTR
Vswing
Crossing point
VIX
VCP
VSSQ
LOGIC Devices Incorporated
www.logicdevices.com
56
High Performance, Integrated Memory Module Product
September 16, 2013 LDS-L9D2xxMxxSBG5 Rev E
L9D232M64SBG5
L9D232M72SBG5
L9D232M80SBG5
L9D264M64SBG5
L9D264M72SBG5
L9D264M80SBG5
2 - 5.0 Gb, DDR2, 32 M [64 M] x 64/72/80 Integrated Memory Module (IMOD)
COMMANDS TRUTH TABLE
TABLE 34: TRUTH TABLE - DDR2 COMMANDS
PACKAGE OUTLINE DIMENSIONS
CKE
Prev
Cycle
Current
Cycle
CS\
RAS\
CAS\
WE\
LOAD MODE
H
H
L
L
L
L
%$
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H
H
L
L
L
H
;
;
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1-3
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H
L
L
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L
H
;
;
;
;
L
H
H
;
;
;
;
;
;
;
1-3
L
H
H
H
Function
BA1-BA0 AN -A11
A10
A9-A10
23&RGH
Notes
(175<
SELF REFRESH
(;,7
H
H
L
L
H
L
%$
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L
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1-3,6
H
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BANK ACTIVATE
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L
H
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NO OPERATION
H
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L
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H
H
;
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1-3
DEVICE DESELECT
H
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;
;
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1-3
POWER-DOWN
H
L
H
;
;
;
;
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1-3,9
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1-3,9
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LOGIC Devices Incorporated
www.logicdevices.com
High Performance, Integrated Memory Module Product
September 16, 2013 LDS-L9D2xxMxxSBG5 Rev E
L9D232M64SBG5
L9D232M72SBG5
L9D232M80SBG5
L9D264M64SBG5
L9D264M72SBG5
L9D264M80SBG5
2 - 5.0 Gb, DDR2, 32 M [64 M] x 64/72/80 Integrated Memory Module (IMOD)
TABLE 35: TRUTH TABLE - CURRENT STATE BANK n - COMMAND TO BANK n
Current State
CS\
RAS\
CAS\
WE\
Command/Action
Notes
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;
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DESELECT123FRQWLQXHSUHYLRXVRSHUDWLRQ
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L
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LOAD MODE
L
H
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H
READ VHOHFW&2/801DQGVWDUW5($'EXUVW
L
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L
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WRITE VHOHFW&2/801DQGVWDUW:5,7(EXUVW
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1-6,9
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LOGIC Devices Incorporated
www.logicdevices.com
High Performance, Integrated Memory Module Product
September 16, 2013 LDS-L9D2xxMxxSBG5 Rev E
L9D232M64SBG5
L9D232M72SBG5
L9D232M80SBG5
L9D264M64SBG5
L9D264M72SBG5
L9D264M80SBG5
2 - 5.0 Gb, DDR2, 32 M [64 M] x 64/72/80 Integrated Memory Module (IMOD)
NOTES CONTINUED
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TABLE 36: TRUTH TABLE - CURRENT STATE BANK n - COMMAND TO BANK m
CS\
RAS\
CAS\
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Command/Action
Notes
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LOGIC Devices Incorporated
www.logicdevices.com
59
High Performance, Integrated Memory Module Product
September 16, 2013 LDS-L9D2xxMxxSBG5 Rev E
L9D232M64SBG5
L9D232M72SBG5
L9D232M80SBG5
L9D264M64SBG5
L9D264M72SBG5
L9D264M80SBG5
2 - 5.0 Gb, DDR2, 32 M [64 M] x 64/72/80 Integrated Memory Module (IMOD)
NOTES
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TABLE 37: MINIMUM DELAY WITH AUTO PRECHARGE ENABLED
From Command
To Command
(Bank n)
(Bank m)
WRITE with AUTO
5($'RU5($'ZLWK$XWR3UHFKDUJH
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1
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LOGIC Devices Incorporated
www.logicdevices.com
Minimum Delay (with Concurrent AUTO PRECHARGE)
60
UNITS
tCK
tCK
High Performance, Integrated Memory Module Product
September 16, 2013 LDS-L9D2xxMxxSBG5 Rev E
L9D232M64SBG5
L9D232M72SBG5
L9D232M80SBG5
L9D264M64SBG5
L9D264M72SBG5
L9D264M80SBG5
2 - 5.0 Gb, DDR2, 32 M [64 M] x 64/72/80 Integrated Memory Module (IMOD)
DESELECT
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61
High Performance, Integrated Memory Module Product
September 16, 2013 LDS-L9D2xxMxxSBG5 Rev E
L9D232M64SBG5
L9D232M72SBG5
L9D232M80SBG5
L9D264M64SBG5
L9D264M72SBG5
L9D264M80SBG5
2 - 5.0 Gb, DDR2, 32 M [64 M] x 64/72/80 Integrated Memory Module (IMOD)
MODE REGISTER (MR)
BURST LENGTH
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FIGURE 29 - MR DEFINITIONS
2
1
BA2 BA1 BA0 An A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Address Bus
16 15 14 n 12 11 10
0
MR
WR
0 PD
Mode Register (Mx)
M12
0
9
8
PD Mode
Fast exit
(normal)
1
Slow exit
(low power)
M11 M10 M9
7
6
5
4
3
2
1
0
DLL TM CAS# Latency BT Burst Length
M2 M1 M0 Burst Length
M7
Mode
0
Normal
0
0
0
Reserved
1
Test
0
0
1
Reserved
0
1
0
4
0
1
1
8
M8 DLL Reset
0
No
1
0
0
Reserved
1
Yes
1
0
1
Reserved
1
1
0
Reserved
1
1
1
Reserved
Write Recovery
0
0
0
Reserved
0
0
1
2
M3
0
1
0
3
0
Sequential
0
1
1
4
1
Interleaved
1
0
0
5
1
0
1
6
1
1
0
7
1
1
1
8
M15 M14
M6 M5 M4
Mode Register Definition
0
0
Mode register (MR)
0
1
Extended mode register (EMR)
1
0
Extended mode register (EMR2)
1
1
Extended mode register (EMR3)
Burst Type
CAS Latency (CL)
0
0
0
Reserved
0
0
1
Reserved
0
1
0
Reserved
0
1
1
3
1
0
0
4
1
0
1
5
1
1
0
6
1
1
1
7
1RWHV0%$LVRQO\DSSOLFDEOHIRUGHQVLWLHV*EUHVHUYHGIRUIXWXUHXVHDQGPXVWEHSURJUDPPHGWR³´
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EHSURJUDPPHGWR³´
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LOGIC Devices Incorporated
www.logicdevices.com
62
High Performance, Integrated Memory Module Product
September 16, 2013 LDS-L9D2xxMxxSBG5 Rev E
L9D232M64SBG5
L9D232M72SBG5
L9D232M80SBG5
L9D264M64SBG5
L9D264M72SBG5
L9D264M80SBG5
2 - 5.0 Gb, DDR2, 32 M [64 M] x 64/72/80 Integrated Memory Module (IMOD)
BURST TYPE
$FFHVVHVZLWKLQDJLYHQEXUVWPD\EHSURJUDPPHGWREHHLWKHUVHTXHQWLDORULQWHUOHDYHG7KH%85677<3(LVVHOHFWHGYLDELW03DVVKRZQLQ)LJXUH7KH
RUGHULQJRIDFFHVVHVZLWKLQDEXUVWLVGHWHUPLQHGE\WKH%8567/(1*7+%85677<3(DQGWKHVWDUWLQJFROXPQDGGUHVVDVVKRZQLQ7DEOH/2*,&uV
DDR2 iMOD
TABLE 38: BURST DEFINITION
Starting Column
Burst Length
Order of Accesses within a Burst
Type = Sequential
Type = Interleaved
Address (A[2,1,0])
00
0,1,2,3
0,1,2,3
01
1,2,3,0
1,0,3,2
10
2,3,0,1
2,3,0,1
11
3,0,1,2
3,2,1,0
000
001
010
011
100
101
110
111
OPERATING MODE
WRITE RECOVERY
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DLL RESET
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LOGIC Devices Incorporated
www.logicdevices.com
63
High Performance, Integrated Memory Module Product
September 16, 2013 LDS-L9D2xxMxxSBG5 Rev E
L9D232M64SBG5
L9D232M72SBG5
L9D232M80SBG5
L9D264M64SBG5
L9D264M72SBG5
L9D264M80SBG5
2 - 5.0 Gb, DDR2, 32 M [64 M] x 64/72/80 Integrated Memory Module (IMOD)
POWER-DOWN MODE
CAS LATENCY (CL)
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WKHGDWDZLOOEHDYDLODEOHQRPLQDOO\FRLQFLGHQWZLWKFORFNHGJHQPWKLV
DVVXPHV$/ FIGURE 30 - CL
T0
T1
T2
T3
T4
T5
T6
READ
NOP
NOP
NOP
NOP
NOP
NOP
CK#
CK
Command
DQS, DQS#
DO
n
DQ
DO
n+1
DO
n+2
DO
n+3
CL = 3 (AL = 0)
T0
T1
T2
T3
T4
T5
T6
READ
NOP
NOP
NOP
NOP
NOP
NOP
CK#
CK
Command
DQS, DQS#
DO
n
DQ
DO
n+1
DO
n+2
DO
n+3
CL = 4 (AL = 0)
Transitioning data
Notes:
LOGIC Devices Incorporated
www.logicdevices.com
Don’t care
1. BL = 4.
2. Posted CAS# additive latency (AL) = 0.
3. Shown with nominal t AC, t DQSCK, and t DQSQ.
High Performance, Integrated Memory Module Product
September 16, 2013 LDS-L9D2xxMxxSBG5 Rev E
L9D232M64SBG5
L9D232M72SBG5
L9D232M80SBG5
L9D264M64SBG5
L9D264M72SBG5
L9D264M80SBG5
2 - 5.0 Gb, DDR2, 32 M [64 M] x 64/72/80 Integrated Memory Module (IMOD)
EXTENDED MODE REGISTER (EMR)
7KH(;7(1'('02'(5(*,67(5FRQWUROVIXQFWLRQVEH\RQGWKRVHDYDLODEOHDQGFRQWUROOHGYLDWKH02'(5(*,67(505WKHVHDGGLWLRQDOIXQFWLRQVDUH
'//HQDEOHGLVDEOH287387'5,9(VWUHQJWK2Q'LH7HUPLQDWLRQ2'73RVWHG$/2II&KLS'ULYHU,PSHGDQFHFDOLEUDWLRQ2&''46?HQDEOHGLVDEOH
DQG2XWSXWGLVDEOHHQDEOH7KHVHIXQFWLRQDUHFRQWUROOHGYLDWKHELWVVKRZQLQ)LJXUH7KH(05LVSURJUDPPHGYLDWKH/0FRPPDQGDQGZLOOUHWDLQWKH
VWRUHGLQIRUPDWLRQXQWLOLWLVSURJUDPPHGDJDLQRUWKHL02'ORVHVSRZHU5HSURJUDPPLQJWKH(05ZLOOQRWDOWHUWKHFRQWHQWVRIWKHPHPRU\DUUD\SURYLGHG
LWLVSHUIRUPHGFRUUHFWO\
7KH(05PXVWEHORDGHGZKHQDOOEDQNVDUHLGOHDQGQREXUVWVDUHLQSURJUHVVDQGWKHFRQWUROOHUPXVWZDLWWKHVSHFLILHGWLPHt05'EHIRUHLQLWLDWLQJDQ\
VXEVHTXHQWRSHUDWLRQV9LRODWLQJHLWKHURIWKHVHUHTXLUHPHQWVFRXOGUHVXOWLQDQXQVSHFLILHGRSHUDWLRQ
FIGURE 31 - EMR DEFINITIONS
BA2 1 BA1 BA0 A n 2 A12
16
0
15 14
MRS
A10 A9 A8
A7 A6 A5 A4 A3 A2
n 12 11 10 9
8 7
6
5
4
3
2
1 0
0 Out RDQS DQS# OCD Program R TT Posted CAS# R TT ODS DLL
E12
Outputs
0
Enabled
1
Disabled
E11 RDQS Enable
0
No
1
Yes
Extended mode
register (Ex)
E0
DLL Enable
0
Enable (normal)
1
Disable (test/debug)
0
0
R TT disabled
0
1
75Ω
1
0
150 Ω
E1
1
1
50Ω
0
Full
1
Reduced
E5 E4 E3
Output Drive Strength
Posted CAS# Additive Latency (AL)
0
Enable
0
0
0
0
1
Disable
0
0
1
1
0
1
0
2
0
1
1
3
1
0
0
4
1
0
1
5
1
1
0
6
1
1
1
Reserved
E9 E8 E7
OCD Operation
4
0
0
0
OCD exit
0
0
1
Reserved
0
1
0
Reserved
1
0
0
Reserved
1
1
1
Enable OCD defaults
3
Mode Register Set
E15 E14
LOGIC Devices Incorporated
Address bus
E6 E2 R TT (Nominal)
E10 DQS# Enable
Notes:
A1 A0
0
0
0
1
Extended mode register (EMR)
1
0
Extended mode register (EMR2)
1
1
Extended mode register (EMR3)
Mode register (MR)
1. E16 (BA2) is only applicable for densities ุ1Gb, reserved for future use, and must be programmed to “0”.
2. Mode bits (En) with corresponding address balls (An ) greater than E12 (A12) are reserved for future use
and must be programmed to “0”.
3. Not all listed AL options are supported in any individual speed grade.
4. As detailed in the Initialization (page 82) section notes, during initialization of the OCD operation,
all three bits must be set to “1” for the OCD default state, then set to “0” before initialization is finished.
www.logicdevices.com
65
High Performance, Integrated Memory Module Product
September 16, 2013 LDS-L9D2xxMxxSBG5 Rev E
L9D232M64SBG5
L9D232M72SBG5
L9D232M80SBG5
L9D264M64SBG5
L9D264M72SBG5
L9D264M80SBG5
2 - 5.0 Gb, DDR2, 32 M [64 M] x 64/72/80 Integrated Memory Module (IMOD)
DLL ENABLED/DISABLED
ON-DIE-TERMINATION (ODT)
7KH'//PD\EH(1$%/('RU',6$%/('E\SURJUDPPLQJELW(0GXULQJ
WKH/0FRPPDQGDVVKRZQLQ)LJXUH7KHVHVSHFLILFDWLRQVDUHDSSOLFDEOHZKHQWKH'//LVHQDEOHGIRUQRUPDORSHUDWLRQ'//(1$%/(LVUHTXLUHG
GXULQJ 32:(583 LQLWLDOL]DWLRQ DQG XSRQ UHWXUQLQJ WR QRUPDO RSHUDWLRQ
DIWHUKDYLQJGLVDEOHGWKH'//IRUWKHSXUSRVHRIGHEXJJLQJRUHYDOXDWLRQ
(QDEOLQJ WKH '// VKRXOG DOZD\V EH IROORZHG E\ UHVHWWLQJ WKH '// XVLQJ
WKH/0FRPPDQG
2'7 HIIHFWLYH UHVLVWDQFH 577()) LV GHILQHG E\ ELWV (2 DQG (6 RI WKH
(05 DV VKRZQ LQ )LJXUH 7KH 2'7 IHDWXUH LV GHVLJQHG WR LPSURYH
VLJQDOLQWHJULW\RIWKHPHPRU\FKDQQHOE\DOORZLQJWKH''5PHPRU\FRQWUROOHUWRLQGHSHQGHQWO\WXUQRQRURII2'7IRUDQ\RUDOOGHYLFHV577HIIHFWLYHUHVLVWDQFHYDOXHVRI::DQG:DUHVHOHFWDEOHDQGDSSO\WR
HDFK'4'46'46?8'468'46?/'46/'46?8'0/'0VLJQDOV
%LWV (6,E2 GHWHUPLQH ZKDW 2'7 UHVLVWDQFH LV HQDEOHG E\ WXUQLQJ RQRII
vVZVZRUVZw
7KH '// LV DXWRPDWLFDOO\ ',6$%/(' ZKHQ HQWHULQJ 6(/) 5()5(6+
RSHUDWLRQ DQG LV DXWRPDWLFDOO\ UHHQDEOHG DQG UHVHW XSRQ H[LW RI 6(/)
5()5(6+RSHUDWLRQV
7KH2'7HIIHFWLYHUHVLVWDQFHYDOXHLVVHOHFWHGE\HQDEOLQJVZLWFKvVZw
ZKLFK HQDEOHV DOO 5 YDOXHV WKDW DUH : HDFK HQDEOLQJ DQ HIIHFWLYH
UHVLVWDQFHRI: (R77>())@ 56LPLODUO\LIvVZwLVHQDEOHGDOO5
YDOXHV WKDW DUH : HDFK HQDEOH DQ HIIHFWLYH 2'7 UHVLVWDQFH RI :
HDFKHQDEOLQJDQHIIHFWLYHUHVLVWDQFHRI: (R77>())@ 56LPLODUO\ LI vVZw LV HQDEOHG DOO 5 YDOXHV WKDW DUH : HDFK HQDEOH DQG
HIIHFWLYH2'7UHVLVWDQFHRI:5HVHUYHGVWDWHVVKRXOGQRWEHXVHGDVDQ
XQNQRZQRSHUDWLRQRULQFRPSDWLELOLW\ZLWKIXWXUHYHUVLRQVPD\UHVXOW
$Q\WLPHWKH'//LV(1$%/('DQGVXEVHTXHQWO\UHVHWFORFNF\FOHV
PXVWRFFXUEHIRUHD5($'FRPPDQGFDQEHLVVXHGWRDOORZWLPHIRUWKH
LQWHUQDO FORFN WR V\QFKURQL]H ZLWK WKH H[WHUQDO FORFN )DLOLQJ WR ZDLW IRU
V\QFKURQL]DWLRQ WR RFFXU PD\ UHVXOW LQ D YLRODWLRQ RI WKH t$& RU t'46&.
SDUDPHWHUV
$Q\WLPH WKH '// LV ',6$%/(' DQG WKH L02' LV RSHUDWHG EHORZ 0+]
DQ\ $872 5()5(6+ FRPPDQG VKRXOG EH IROORZHG E\ D 35(&+$5*(
$//FRPPDQG
7KH2'7FRQWUROEDOOLVXVHGWRGHWHUPLQHZKHQ577())LVWXUQHGRQDQG
RIIDVVXPLQJ2'7KDVEHHQHQDEOHGYLDELWV(DQG(RIWKH(057KH
2'7 IHDWXUH DQG 2'7 LQSXW EDOO DUH RQO\ XVHG GXULQJ $&7,9( $&7,9(
32:(5'2:1 ERWK IDVWH[LW DQG VORZH[LW PRGHV DQG 35(&+$5*(
32:(5'2:1PRGHVRIRSHUDWLRQ
2'7 PXVW EH WXUQHG RII SULRU WR HQWHULQJ 6(/) 5()5(6+ PRGH 'XULQJ
32:(583DQG,1,7,$/,=$7,21RIWKH''5L02'2'7VKRXOGEHGLVDEOHGXQWLOWKH(05FRPPDQGLVLVVXHG7KLVZLOOHQDEOHWKH2'7IHDWXUH
DWZKLFKSRLQWWKH2'7EDOOZLOOGHWHUPLQHWKH577())YDOXH$Q\WLPHWKH
(05HQDEOHVWKH2'7IXQFWLRQ2'7PD\QRWEHGULYHQ+,*+XQWLOHLJKW
FORFNVDIWHUWKH(05KDVEHHQHQDEOHG
DQS\ ENABLE/DISABLE
OFF-CHIP DRIVER (OCD) IMPEDANCE CALIBRATION
7KH2))&+,3'5,9(52&'IXQFWLRQLVDQRSWLRQDO''5-('(&IHDWXUHZKLFKLVQRWVXSSRUWHGE\/2*,&'HYLFHVL02'GHYLFHWKHUHIRUHWKLV
IXQFWLRQPXVWEHVHWDQGPDLQWDLQHGLQWKHGHIDXOWVWDWH(QDEOLQJWKLVIXQFWLRQRXWVLGHRIWKHGHIDXOWVHWWLQJVZLOODOWHUWKH,2GULYHFKDUDFWHULVWLFVDQG
WKHWLPLQJDQGRXWSXW,2VSHFLILFDWLRQVZLOOQRORQJHUEHYDOLG
7KH'46?EDOOLV(1$%/('E\ELW(10 '46?LVWKHFRPSOHPHQWRIWKH
GLIIHUHQWLDOGDWDVWUREHSDLU:KHQ',6$%/(''46?VKRXOGEHOHIWIORDWLQJKRZHYHULWPD\EHWLHGWRJURXQGYLDD: to 10K:UHVLVWRU
OUTPUT DRIVE STRENGTH
POSTED CAS ADDITIVE LATENCY (AL)
7KH287387'5,9(675(1*7+LVGHILQHGE\ELW(1DVVKRZQLQ)LJXUH
7KH 1250$/ '5,9( 675(1*7+ IRU DOO RXWSXWV LV VSHFLILHG WR EH
667/B 3URJUDPPLQJ ELW (1 VHOHFWV QRUPDO IXOO VWUHQJWK '5,9(
675(1*7+ IRU DOO RXWSXWV 6HOHFWLQJ D 5('8&(' '5,9( 675(1*7+
RSWLRQ(1 ZLOOUHGXFHDOORXWSXWVWRDSSUR[LPDWHO\WRSHUFHQWRI
WKH667/'5,9(675(1*7+7KLVRSWLRQLVLQWHQGHGIRUWKHVXSSRUWRI
OLJKWHUORDGDQGRUSRLQWWRSRLQWHQYLURQPHQWV
3267(' &$6 $'',7,9( $/ LV VXSSRUWHG WR PDNH WKH FRPPDQG DQG
GDWDEXVHIILFLHQWIRUVXVWDLQDEOHEDQGZLGWKVLQWKH''5L02'%LWV(3-E5
GHILQH WKH YDOXH RI $/ %LWV (3-E5 DOORZ WKH XVHU WR SURJUDP WKH ''5
L02'ZLWKDQ$/RIRUFORFNV5HVHUYHGVWDWHVVKRXOGQRW
EH XVHG DV DQ XQNQRZQ RSHUDWLRQ RU LQFRPSDWLELOLW\ ZLWK IXWXUH UHYLVLRQV
PD\UHVXOW
,QWKLVRSHUDWLRQWKH''5L02'DOORZVD5($'RU:5,7(FRPPDQGWR
EHLVVXHGSULRUWR t5&'0,1ZLWKWKHUHTXLUHPHQWWKDW$/d t5&'0,1
$ W\SLFDO DSSOLFDWLRQ XVLQJ WKLV IHDWXUH ZRXOG VHW $/ t5&' 0,1 y [
t&.7KH5($'RU:5,7(FRPPDQGLVKHOGIRUWKHWLPHRIWKH$/EHIRUHLW
LVLVVXHGLQWHUQDOO\WRWKH''5L02'GHYLFH5/LVFRQWUROOHGE\WKHVXP
RI$/DQG&/5/ $/&/:5,7(ODWHQF\:/LVHTXDOWR5/PLQXVRQ
FORFN:/ $/&/y[t&.
OUTPUT ENABLE/DISABLE
7KH287387(1$%/(',6$%/(IXQFWLRQLVGHILQHGE\ELW(12DVVKRZQ
LQ)LJXUH:KHQ(1$%/('(12 DOORXWSXWV'4'46'46?IXQFWLRQQRUPDOO\:KHQ',6$%/('(12 DOORXWSXWVDUH',6$%/('WKXV
UHPRYLQJRXWSXWEXIIHUFXUUHQW7KHRXWSXW',6$%/(IHDWXUHLVLQWHQGHGWR
EHXVHGGXULQJ,DDFKDUDFWHUL]DWLRQRI5($'FXUUHQW
LOGIC Devices Incorporated
www.logicdevices.com
66
High Performance, Integrated Memory Module Product
September 16, 2013 LDS-L9D2xxMxxSBG5 Rev E
L9D232M64SBG5
L9D232M72SBG5
L9D232M80SBG5
L9D264M64SBG5
L9D264M72SBG5
L9D264M80SBG5
2 - 5.0 Gb, DDR2, 32 M [64 M] x 64/72/80 Integrated Memory Module (IMOD)
FIGURE 32 - READ LATENCY
T0
T1
T2
T3
T4
T5
T6
T7
T8
ACTIVE n
READ n
NOP
NOP
NOP
NOP
NOP
NOP
NOP
CK#
CK
Command
DQS, DQS#
t RCD (MIN)
DO
n
DQ
AL = 2
CL = 3
DO
n+1
DO
n+2
DO
n+3
RL = 5
Transitioning Data
Notes:
Don’t Care
1. BL = 4
2. Shown with nominal t$&t'46&.DQGtDQSQ.
3. RL = AL + CL = 5.
FIGURE 33 - WRITE LATENCY
T0
T1
ACTIVE n
WRITE n
CK#
T2
T3
T4
T5
T6
T7
NOP
NOP
NOP
NOP
NOP
NOP
CK
Command
t RCD (MIN)
DQS, DQS#
AL = 2
CL - 1 = 2
DI
n
DQ
DI
n+1
DI
n+2
DI
n+3
WL = AL + CL - 1 = 4
Transitioning Data
Notes:
Don’t Care
1. BL = 4
2. CL = 3.
3. WL = AL + CL - 1 = 4
LOGIC Devices Incorporated
www.logicdevices.com
High Performance, Integrated Memory Module Product
September 16, 2013 LDS-L9D2xxMxxSBG5 Rev E
L9D232M64SBG5
L9D232M72SBG5
L9D232M80SBG5
L9D264M64SBG5
L9D264M72SBG5
L9D264M80SBG5
2 - 5.0 Gb, DDR2, 32 M [64 M] x 64/72/80 Integrated Memory Module (IMOD)
EXTENDED MODE REGISTER 2 (EMR2)
7KH (;7(1'(' 02'( 5(*,67(5 (05 FRQWUROV IXQFWLRQV EH\RQG WKRVH FRQWUROOHG E\ WKH 02'( 5(*,67(5 &XUUHQWO\ DOO ELWV LQ WKH (05 DUH
UHVHUYHGH[FHSWIRU(ZKLFKLVXVHGLQFRPPHUFLDORUKLJKWHPSHUDWXUHRSHUDWLRQVDVVKRZQLQ)LJXUH7KH(05LVSURJUDPPHGYLDWKH/0FRPPDQG
DQGZLOOUHWDLQWKHVWRUHGLQIRUPDWLRQXQWLOLWLVSURJUDPPHGDJDLQRUXQWLOWKHL02'LVVXEMHFWHGWRDORVVRISRZHUFRQGLWLRQ5HSURJUDPPLQJWKH(05ZLOOQRW
DOWHUWKHFRQWHQWVRIWKHDUUD\SURYLGHGLWKDVEHHQSHUIRUPHGFRUUHFWO\
Bit E$PXVWEHSURJUDPPHGDVvwWRSURYLGHDIDVWHU5()5(6+5$7(RQ,7(7RU0GHYLFHVLI7CLVRUGRHVH[FHHG&
(05PXVWEHORDGHGZKHQDOOEDQNVDUHLGOHDQGQREXUVWVDUHLQSURJUHVVDQGWKHFRQWUROOHUPXVWZDLWWKHVSHFLILHGWLPHt05'EHIRUHLQLWLDWLQJDQ\VXEVHTXHQWRSHUDWLRQ9LRODWLQJHLWKHURIWKHVHUHTXLUHPHQWVFRXOGUHVXOWLQDQXQVSHFLILHGL02'RSHUDWLRQ
FIGURE 34 - EMR2 DEFINITIONS
BA21 BA1 BA0 A n 2 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2
16
0
E15 E14
15 14 n
MRS
0
12
0
11
0
10
0
9 8 7 6
0 0 SRT 0
Mode Register Set
E7
5
0
4
0
3
0
2
0
A1 A0
1
0
0
Mode register (MR)
0
1X refresh rate (0°C to 85°C)
0
1
Extended mode register (EMR)
1
2X refresh rate (>85°C)
1
0
Extended mode register (EMR2)
1
1
Extended mode register (EMR3)
LOGIC Devices Incorporated
Extended mode
register (Ex)
SRT Enable
0
Notes:
0
0
Address bus
1. E16 (BA2) is only applicable for densities 1Gb, reserved for future use, and must be programmed to “0”.
2. Mode bits (En) with corresponding address balls (An ) greater than E12 (A12) are reserved for future use
and must be programmed to “0”.
www.logicdevices.com
High Performance, Integrated Memory Module Product
September 16, 2013 LDS-L9D2xxMxxSBG5 Rev E
L9D232M64SBG5
L9D232M72SBG5
L9D232M80SBG5
L9D264M64SBG5
L9D264M72SBG5
L9D264M80SBG5
2 - 5.0 Gb, DDR2, 32 M [64 M] x 64/72/80 Integrated Memory Module (IMOD)
EXTENDED MODE REGISTER 3 (EMR3)
7KH (;7(1'(' 02'( 5(*,67(5 (05 FRQWUROV IXQFWLRQV EH\RQG WKRVH FRQWUROOHG E\ WKH 02'( 5(*,67(5 &XUUHQWO\ DOO ELWV RI WKH (05 DUH
UHVHUYHGDVVKRZQLQ)LJXUH7KH(05LVSURJUDPPHGYLDWKH/0FRPPDQGDQGZLOOUHWDLQWKHVWRUHGLQIRUPDWLRQXQWLOLWLVSURJUDPPHGDJDLQRUXQWLOWKH
L02'LVVXEMHFWHGWRDORVVRISRZHUFRQGLWLRQ5HSURJUDPPLQJWKH(05ZLOOQRWDOWHUWKHFRQWHQWVRIWKHPHPRU\DUUD\SURYLGHGLWLVSHUIRUPHGFRUUHFWO\
FIGURE 35 - EMR3 DEFINITIONS
BA21 BA1 BA0 An 2 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2
16
15 14 n
12 11
10
0
MRS
0
0
E15 E14
Notes:
0
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
A1 A0
1
0
0
0
Address bus
Extended mode
register (Ex)
Mode Register Set
0
0
Mode register (MR)
0
1
Extended mode register (EMR)
1
0
Extended mode register (EMR2)
1
1
Extended mode register (EMR3)
1. E16 (BA2) is only applicable for densities 1Gb, reserved for future use, and must be programmed to “0”.
2. Mode bits (En) with corresponding address balls (An ) greater than E12 (A12) are reserved for future use
and must be programmed to “0”.
LOGIC Devices Incorporated
www.logicdevices.com
69
High Performance, Integrated Memory Module Product
September 16, 2013 LDS-L9D2xxMxxSBG5 Rev E
LOGIC Devices Incorporated
VDD
www.logicdevices.com
LVCMOS
T0
t VTD1
15
High-Z
15
DQ
RTT
High-Z
High-Z
15
DQS
16
Address
DM
Command
ODT
CKE low level 2
CK
CK#
VREF
VTT1
VDDQ
VDDL
tCL
Power-up:
VCC and stable
clock (CK, CK#)
T = 200 μs (MIN)3
SSTL_182
low level
tCL
tCK
A10 = 1
PRE
Tb0
T = 400 ns (MIN)4
NOP 3
Ta0
t RPA
EMR(2)
Code
LM 5
Tc0
t MRD
EMR(3)
Code
LM 6
Td0
t MRD
EMR
Code
LM 7
Te0
t MRD
MR with
DLL RESET
t MRD
Code
LM 8
Tf0
A10 = 1
PRE 9
Tg0
t RFC
REF10
Ti0
t MRD
Code
LM 12
Tk0
MR without
EMR with
DLL RESET OCD default
t RFC
Code
LM 11
Tj0
EMR with
OCD exit
t MRD
Code
LM 13
Tl0
Indicates a Break in
Time Scale
200 cycles of CK are required before a READ command can be issued
t RPA
REF10
Th0
Don’t care
Normal
operation
t MRD
Valid
Valid 14
Tm0
L9D232M64SBG5
L9D232M72SBG5
L9D232M80SBG5
L9D264M64SBG5
L9D264M72SBG5
L9D264M80SBG5
2 - 5.0 Gb, DDR2, 32 M [64 M] x 64/72/80 Integrated Memory Module (IMOD)
INITIALIZATION
''5L02'GHYLFHVPXVWEH32:(5('83DQG,1,7,$/,=('LQDSUHGHILQHGPDQQHU2SHUDWLRQDOSURFHGXUHVRWKHUWKDQWKRVHVSHFLILHGPD\UHVXOWLQXQGHILQHGRSHUDWLRQ)LJXUHLOOXVWUDWHVDQGWKHQRWHVRXWOLQHWKHVHTXHQFHUHTXLUHGIRU32:(583DQG,1,7,$/,=$7,21
FIGURE 36 - DDR2 POWER-UP AND INITIALIZATION
High Performance, Integrated Memory Module Product
September 16, 2013 LDS-L9D2xxMxxSBG5 Rev E
L9D232M64SBG5
L9D232M72SBG5
L9D232M80SBG5
L9D264M64SBG5
L9D264M72SBG5
L9D264M80SBG5
2 - 5.0 Gb, DDR2, 32 M [64 M] x 64/72/80 Integrated Memory Module (IMOD)
ACTIVATE
%HIRUHDQ5($'RU:5,7(FRPPDQGVFDQEHLVVXHGWRDEDQNZLWKLQWKH''5L02'DURZLQWKDWEDQNPXVWEHRSHQHGDFWLYDWHGHYHQZKHQDGGLWLYH
ODWHQF\LVXVHG7KLVLVDFFRPSOLVKHGYLDWKH$&7,9$7(FRPPDQGZKLFKVHOHFWVERWKWKHEDQNDQGWKHURZWREHDFWLYDWHG
$IWHUDURZLVRSHQHGZLWKDQ$&7,9$7(FRPPDQGD5($'RU:5,7(FRPPDQGPD\EHLVVXHGWRWKDWURZVXEMHFWWRWKH t5&'VSHFLILFDWLRQ t5&'0,1
VKRXOGEHGHILQHGE\WKHFORFNSHULRGDQGURXQGHGXSWRWKHQH[WZKROHQXPEHUWRGHWHUPLQHWKHHDUOLHVWFORFNHGJHDIWHUWKH$&7,9$7(FRPPDQGRQZKLFK
D5($'RU:5,7(FRPPDQGFDQEHHQWHUHG7KHVDPHSURFHGXUHLVXVHGWRFRQYHUWRWKHUVSHFLILFDWLRQOLPLWVIURPWLPHXQLWVWRFORFNF\FOHV)RUH[DPSOHD
t5&'0,1VSHFLILFDWLRQRIQVZLWKD0+]FORFNt&. QVUHVXOWVLQFORFNVURXQGHGXSWR7KLVLVVKRZQLQ)LJXUH
FIGURE 37 - EXAMPLE: MEETING tRRD (MIN) AND tRCD (MIN)
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
Command
ACT
NOP
NOP
ACT
NOP
NOP
NOP
NOP
NOP
RD/WR
Address
Row
CK#
CK
Row
Bank x
Bank address
Bank y
t RRD
Row
Col
Bank z
Bank y
t RRD
t RCD
Don’t Care
$VXEVHTXHQW$&7,9$7(FRPPDQGWRDGLIIHUHQWURZLQWKHVDPHEDQNFDQRQO\EHLVVXHGDIWHUWKHSUHYLRXVDFWLYHURZKDVEHHQFORVHGSUHFKDUJHG7KH
PLQLPXPWLPHLQWHUYDOEHWZHHQVXFFHVVLYH$&7,9$7(FRPPDQGVWRWKHVDPHEDQNLVGHILQHGE\t5&$VXEVHTXHQW$&7,9$7(FRPPDQGWRDQRWKHUEDQN
FDQEHLVVXHGZKLOHWKHILUVWEDQNLVEHLQJDFFHVVHGZKLFKUHVXOWVLQUHGXFWLRQRIWRWDOURZDFFHVVRYHUKHDG7KHPLQLPXPWLPHLQWHUYDOEHWZHHQVXFFHVVLYH
$&7,9$7(FRPPDQGVWRGLIIHUHQWEDQNVLVGHILQHGE\ t55'''5ZLWKEDQNDUFKLWHFWXUHVKDYHDQDGGLWLRQDOUHTXLUHPHQW t)$:7KLVUHTXLUHVQRPRUH
WKDQIRXU$&7,9$7(FRPPDQGVPD\EHLVVXHGLQDQ\JLYHQt)$:0,1SHULRGDVVKRZQLQ)LJXUH
FIGURE 38 - MULTIBANK ACTIVATE RESTRICTION
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
Command
ACT
READ
ACT
READ
ACT
READ
ACT
READ
NOP
NOP
ACT
Address
Row
Col
Row
Col
Row
Col
Row
Col
Row
Bank a
Bank b
Bank b
Bank c
Bank c
Bank d
Bank d
Bank e
CK#
CK
Bank address
Bank a
tRRD (MIN)
tFAW (MIN)
Don’t Care
Note:
LOGIC Devices Incorporated
1. DDR2-533 (-37E, x4 or x8), t CK = 3.75ns, BL = 4, AL = 3, CL = 4, t RRD (MIN) = 7.5ns,
t FAW (MIN) = 37.5ns.
www.logicdevices.com
High Performance, Integrated Memory Module Product
September 16, 2013 LDS-L9D2xxMxxSBG5 Rev E
L9D232M64SBG5
L9D232M72SBG5
L9D232M80SBG5
L9D264M64SBG5
L9D264M72SBG5
L9D264M80SBG5
2 - 5.0 Gb, DDR2, 32 M [64 M] x 64/72/80 Integrated Memory Module (IMOD)
READ
5($'EXUVWVDUHLQLWLDWHGZLWKD5($'FRPPDQG7KHVWDUWLQJFROXPQDQGEDQNDGGUHVVHVDUHSURYLGHGZLWKWKH5($'FRPPDQGDQGWKH$87235(&+$5*(LVHLWKHUHQDEOHGRUGLVDEOHGIRUWKDW%8567VHTXHQFHRUDFFHVV,I$87235(&+$5*(LVHQDEOHGWKHURZEHLQJDFFHVVHGLVDXWRPDWLFDOO\35(&+$5*('DWWKHFRPSOHWLRQRIWKHEXUVW,I$87235(&+$5*(LVGLVDEOHGWKHURZZLOOEHOHIWRSHQDIWHUWKHFRPSOHWLRQRIWKHEXUVW
'XULQJ5($'EXUVWVWKHYDOLGGDWDRXWHOHPHQWIURPWKHVWDUWLQJFROXPQDGGUHVVZLOOEHDYDLODEOH5($'ODWHQF\5/FORFNVODWHU5/LVGHILQHGDVWKHVXPRI
$/DQG&/5/ $/&/7KHYDOXHRI$/DQG&/DUHSURJUDPPDEOHYLDWKH05DQG(05FRPPDQGVUHVSHFWLYHO\(DFKVXEVHTXHQWGDWDRXWHOHPHQWZLOO
EHYDOLGQRPLQDOO\DWWKHQH[WSRVLWLYHRUQHJDWLYHFORFNHGJHDWWKHQH[WFURVVLQJRI&.[DQG&.[?)LJXUHVKRZVH[DPSOHVRI5/EDVHGRQGLIIHUHQW$/
DQG&/VHWWLQJV
'46['46[?LVGULYHQE\WKH''5L02'DORQJZLWKRXWSXWGDWD7KHLQLWLDO/2:VWDWHRQ'46[DQGWKH+,*+VWDWHRQ'46[?FRLQFLGHQWZLWKWKHODVWGDWD
RXWHOHPHQWDUHNQRZQDVWKH5($'SUHDPEOHt35(7KHORZVWDWHRQ'46[DQGWKH+,*+VWDWHFRLQFLGHQWZLWKWKHODVWGDWDRXWHOHPHQWDUHNQRZDVWKH
5($'SRVWDPEOHt3567
8SRQFRPSOHWLRQRID%8567DVVXPLQJQRRWKHUFRPPDQGVKDYHEHHQLQLWLDWHGWKH'4EXVVZLOOJR+,*+=$GHWDLOHGH[SODQDWLRQRIt'46&.'46[WUDQVLWLRQVNHZWR&/DQGt$&GDWDRXWWUDQVLWLRQVNHZWR&.[LVVKRZQLQ)LJXUH
'DWDIURPDQ\5($'EXUVWPD\EHFRQFDWHQDWHGZLWKGDWDIURPDVXEVHTXHQW5($'FRPPDQGWRSURYLGHDFRQWLQXRXVIORZRIGDWD7KHILUVWGDWDHOHPHQW
IURPWKHQHZEXUVWIROORZVWKHODVWHOHPHQWRIDFRPSOHWHGEXUVW7KHQHZ5($'FRPPDQGVKRXOGEHLVVXHG[F\FOHVDIWHUWKHILUVW5($'FRPPDQGZKHUH[
HTXDOV%/F\FOHVVHH)LJXUH
1RQFRQVHFXWLYH5($'GDWDLVLOOXVWUDWHGLQ)LJXUH)XOOVSHHGUDQGRP5($'DFFHVVHVZLWKLQDSDJHRUSDJHVFDQEHSHUIRUPHG''5L02'GHYLFHV
VXSSRUWWKHXVHRIFRQFXUUHQW$87235(&+$5*(WLPLQJ
''5L02'GHYLFHVGRQRWDOORZLQWHUUXSWLQJRUWUXQFDWLQJRIDQ5($'EXUVWXVLQJ%/ RSHUDWLRQV2QFHWKH%/ 5($'FRPPDQGLVUHJLVWHUHGLWPXVW
EHDOORZHGWRFRPSOHWHWKHHQWLUH5($'EXUVW+RZHYHUD5($'ZLWK$87235(&+$5*(GLVDEOHGXVLQJ9/ RSHUDWLRQWKH5($'PD\EH
LQWHUUXSWHGDQGWUXQFDWHGRQO\E\DQRWKHU5($'EXUVWDVORQJDVWKHLQWHUUXSWLRQRFFXUVRQDELWERXQGDU\DQGWKLVDOORZHGGXHWRWKHQSUHIHWFKDUFKLWHFWXUHRIWKH''5L02'$6VKRZQLQ)LJXUH5($'EXUVW%/ RSHUDWLRQVPD\QRWEHLQWHUUXSWHGRUWUXQFDWHGZLWKDQ\RWKHUFRPPDQGH[FHSWIRUDQRWKHU
5($'
'DWDIURPDQ\5($'EXUVWPXVWEHFRPSOHWHGEHIRUHDVXEVHTXHQW:5,7(EXUVWLVDOORZHG$QH[DPSOHRID5($'EXUVWIROORZHGE\D:5,7(EXUVWLVVKRZQ
LQ)LJXUH
LOGIC Devices Incorporated
www.logicdevices.com
High Performance, Integrated Memory Module Product
September 16, 2013 LDS-L9D2xxMxxSBG5 Rev E
L9D232M64SBG5
L9D232M72SBG5
L9D232M80SBG5
L9D264M64SBG5
L9D264M72SBG5
L9D264M80SBG5
2 - 5.0 Gb, DDR2, 32 M [64 M] x 64/72/80 Integrated Memory Module (IMOD)
FIGURE 39 - READ LATENCY
T0
T1
T2
T3
READ
NOP
NOP
NOP
T3n
T4
T4n
T5
CK#
CK
Command
NOP
NOP
Bank a,
Col n
Address
RL = 3 (AL = 0, CL = 3)
DQS, DQS#
DO
n
DQ
T0
T1
T2
T3
T4
READ
NOP
NOP
NOP
NOP
T4n
T5
T5n
CK#
CK
Command
NOP
Bank a,
Col n
Address
AL = 1
CL = 3
RL = 4 (AL = 1 + CL = 3)
DQS, DQS#
DO
n
DQ
T0
T1
T2
T3
READ
NOP
NOP
NOP
T3n
T4
T4n
T5
CK#
CK
Command
NOP
NOP
Bank a,
Col n
Address
RL = 4 (AL = 0, CL = 4)
DQS, DQS#
DO
n
DQ
Transitioning Data
Notes:
LOGIC Devices Incorporated
Don’t Care
1. DO n = data-out from column n .
2. BL = 4.
3. Three subsequent elements of data-out appear in the programmed order following
DO n.
4. Shown with nominal t AC, t DQSCK, and t DQSQ.
www.logicdevices.com
High Performance, Integrated Memory Module Product
September 16, 2013 LDS-L9D2xxMxxSBG5 Rev E
L9D232M64SBG5
L9D232M72SBG5
L9D232M80SBG5
L9D264M64SBG5
L9D264M72SBG5
L9D264M80SBG5
2 - 5.0 Gb, DDR2, 32 M [64 M] x 64/72/80 Integrated Memory Module (IMOD)
FIGURE 40 - CONSECUTIVE READ BURSTS
T0
T1
T2
T3
T3n
READ
NOP
READ
NOP
T4
T4n
T5n
T5
T6n
T6
CK#
CK
Command
Address
Bank,
Col n
NOP
NOP
NOP
Bank,
Col b
t CCD
RL = 3
DQS, DQS#
DO
n
DQ
T0
T1
T2
READ
NOP
READ
T2n
T3
CK#
DO
b
T3n
T4
T4n
T5
T5n
T6n
T6
CK
Command
Address
Bank,
Col n
NOP
NOP
NOP
NOP
Bank,
Col b
t CCD
RL = 4
DQS, DQS#
DO
n
DQ
Transitioning Data
Notes:
LOGIC Devices Incorporated
DO
b
Don’t Care
1. DO n (or b) = data-out from columnn (or column b).
2. BL = 4.
3. Three subsequent elements of data-out appear in the programmed order following
DO n.
4. Three subsequent elements of data-out appear in the programmed order following
DO b.
5. Shown with nominal t AC, t DQSCK, and t DQSQ.
6. Example applies only when READ commands are issued to same device.
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High Performance, Integrated Memory Module Product
September 16, 2013 LDS-L9D2xxMxxSBG5 Rev E
L9D232M64SBG5
L9D232M72SBG5
L9D232M80SBG5
L9D264M64SBG5
L9D264M72SBG5
L9D264M80SBG5
2 - 5.0 Gb, DDR2, 32 M [64 M] x 64/72/80 Integrated Memory Module (IMOD)
FIGURE 41 - NONCONSECUTIVE READ BURSTS
CK#
CK
Command
Address
T0
T1
T2
READ
NOP
NOP
Bank,
Col n
T3
T3n
READ
T4
T4n
NOP
T5
T6
T6n
NOP
NOP
T7
T7n
NOP
T8
NOP
Bank,
Col b
CL = 3
DQS, DQS#
DO
n
DQ
CK#
CK
Command
Address
T0
T1
T2
READ
NOP
NOP
Bank,
Col n
T3
DO
b
T4n
T4
READ
NOP
T5
NOP
T5n
T6
T7
T7n
NOP
NOP
T8
NOP
Bank,
Col b
CL = 4
DQS, DQS#
DO
n
DQ
DO
b
Transitioning Data
Notes:
LOGIC Devices Incorporated
Don’t Care
1. DO n (or b) = data-out from column n (or column b).
2. BL = 4.
3. Three subsequent elements of data-out appear in the programmed order following
DO n.
4. Three subsequent elements of data-out appear in the programmed order following
DO b.
5. Shown with nominal t AC, t DQSCK, and t DQSQ.
6. Example applies when READ commands are issued to different devices or
nonconsecutive READs.
www.logicdevices.com
High Performance, Integrated Memory Module Product
September 16, 2013 LDS-L9D2xxMxxSBG5 Rev E
L9D232M64SBG5
L9D232M72SBG5
L9D232M80SBG5
L9D264M64SBG5
L9D264M72SBG5
L9D264M80SBG5
2 - 5.0 Gb, DDR2, 32 M [64 M] x 64/72/80 Integrated Memory Module (IMOD)
FIGURE 42 - READ INTERRUPTED BY READ
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
Command
READ1
NOP 2
READ3
NOP 2
Valid
Valid
Valid
Valid
Valid
Valid
Address
Valid 4
CK#
CK
Valid 4
Valid 5
A10
DQS, DQS#
DQ
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
CL = 3 (AL = 0)
t CCD
CL = 3 (AL = 0)
Transitioning Data
Don’t Care
1. BL = 8 required; auto precharge must be disabled (A10 = LOW).
2. NOP or COMMAND INHIBIT commands are valid. PRECHARGE command cannot be issued to banks used for READs at T0 and T2.
3. Interrupting READ command must be issued exactly 2 × t CK from previous READ.
4. READ command can be issued to any valid bank and row address (READ command at T0
and T2 can be either same bank or different bank).
5. Auto precharge can be either enabled (A10 = HIGH) or disabled (A10 = LOW) by the interrupting READ command.
6. Example shown uses AL = 0; CL = 3, BL = 8, shown with nominal t AC, t DQSCK, and t DQSQ.
Notes:
FIGURE 43 - READ-TO-WRITE
CK#
CK
Command
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
ACT n
READ n
NOP
NOP
NOP
WRITE
NOP
NOP
NOP
NOP
NOP
NOP
DQS, DQS#
t RCD = 3
WL = RL - 1 = 4
DO
n
DQ
AL = 2
DO
n +1
DO
n +2
DO
n +3
DI
n
DI
n +1
DI
n +2
DI
n +3
CL = 3
RL = 5
Transitioning Data
Notes:
LOGIC Devices Incorporated
www.logicdevices.com
Don’t Care
1. BL = 4; CL = 3; AL = 2.
2. Shown with nominal t AC, t DQSCK, and t DQSQ.
High Performance, Integrated Memory Module Product
September 16, 2013 LDS-L9D2xxMxxSBG5 Rev E
L9D232M64SBG5
L9D232M72SBG5
L9D232M80SBG5
L9D264M64SBG5
L9D264M72SBG5
L9D264M80SBG5
2 - 5.0 Gb, DDR2, 32 M [64 M] x 64/72/80 Integrated Memory Module (IMOD)
READ WITH PRECHARGE
$5($'EXUVWPD\EHIROORZHGE\D35(&+$5*(FRPPDQGWRWKHVDPHEDQNSURYLGHG$87235(&+$5*(LVQRWDFWLYDWHG7KHPLQLPXP5($'WR35(&+$5*(FRPPDQGVSDFLQJWRWKHVDPHEDQNKDVWZRUHTXLUHPHQWVWKDWPXVWEHVDWLVILHG$/%/FORFNVDQG t573 t573LVWKHPLQLPXPWLPHIURPWKH
ULVLQJFORFNHGJHWKDWLQLWLDWHVWKHODVWELW35()(7&+RID5($'FRPPDQGWRWKH35(&+$5*(FRPPDQG)RU%/ WKLVLVWKHWLPHIURPWKHDFWXDO5($'
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%/y&.0$;t53t&.RU[&.ZKHUH0$;PHDQVWKHODUJHURIWKHWZR
FIGURE 44 - READ-TO-PRECHARGE – BL = 4
CK#
CK
Command
T0
4-bit
prefetch
T1
T2
T3
T4
T5
T6
T7
NOP
NOP
PRE
NOP
NOP
ACT
NOP
READ
AL + BL/2 - 2 CK + MAX ( t RTP/ t CK or 2CK)
Address
Bank a
Bank a
Bank a
Valid
Valid
A10
AL = 1
CL = 3
DQS, DQS#
≥t RTP (MIN)
DQ
DO
DO
DO
DO
≥t RP (MIN)
≥t RAS (MIN)
≥t RC (MIN)
Transitioning Data
Don’t Care
1. RL = 4 (AL = 1, CL = 3); BL = 4.
2. t RTP≥ 2 clocks.
3. Shown with nominal t AC, t DQSCK, and t DQSQ.
Notes:
FIGURE 45 - READ-TO-PRECHARGE – BL = 8
CK#
CK
Command
T0
First 4-bit
prefetch
T1
READ
NOP
T2
Second 4-bit
prefetch
T3
T4
T5
T6
T7
T8
NOP
NOP
NOP
PRE
NOP
NOP
ACT
AL + BL/2 - 2CK + MAX ( t RTP/ t CK or 2CK)
Address
Bank a
A10
AL = 1
Bank a
Bank a
Valid
Valid
CL = 3
DQS, DQS#
DO
DQ
≥t RTP (MIN)
DO
DO
DO
DO
DO
DO
DO
≥t RP (MIN)
≥t RAS (MIN)
≥t RC (MIN)
Transitioning Data
Notes:
LOGIC Devices Incorporated
www.logicdevices.com
Don’t Care
1. RL = 4 (AL = 1, CL = 3); BL = 8.
2. t RTP≥ 2 clocks.
3. Shown with nominal t AC, t DQSCK, and t DQSQ.
High Performance, Integrated Memory Module Product
September 16, 2013 LDS-L9D2xxMxxSBG5 Rev E
L9D232M64SBG5
L9D232M72SBG5
L9D232M80SBG5
L9D264M64SBG5
L9D264M72SBG5
L9D264M80SBG5
2 - 5.0 Gb, DDR2, 32 M [64 M] x 64/72/80 Integrated Memory Module (IMOD)
READ WITH AUTO PRECHARGE
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RSHUDWLRQRQWKHULVLQJHGJHRIFORFNWKDWLV$/%/F\FOHVODWHUWKDQWKH5($'ZLWK$87235(&+$5*(FRPPDQGSURYLGHG t5$60,1DQG t573DUH
VDWLVILHG,It5$60,1LVQRWVDWLVILHGDWWKLVULVLQJFORFNHGJHWKHVWDUWSRLQWRIWKH$87235(&+$5*(RSHUDWLRQZLOOEHGHOD\HGXQWLOt5$60,1LVVDWLVILHG
:KHQWKHLQWHUQDO35(&+$5*(LVSXVKHGRXWE\t573t53VWDUWVDWWKHSRLQWZKHUHWKHLQWHUQDO35(&+$5*(KDSSHQV
:KHQ%/ WKHPLQLPXPWLPHIURP5($'ZLWK$87235(&+$5*(WRWKHQH[W$&7,9$7(FRPPDQGLV$/t573 t53t&.:KHQ%/ WKHPLQLPXP
WLPHIURP5($'ZLWK$87235(&+$5*(WRWKHQH[W$&7,9$7(FRPPDQGLV$/FORFNVt573t53t&.7KHWHUPt573t53t&.LVDOZD\VURXQGHG
XSWRWKHQH[WLQWHJHU$JHQHUDOSXUSRVHHTXDWLRQFDQDOVREHXVHG$/%!y&.t573t53t&.,QDQ\HYHQWWKHLQWHUQDO35(&+$5*(GRHVQRW
VWDUWHDUOLHUWKDQWZRFORFNVDIWHUWKHODVWELWSUHIHWFK
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TABLE 39: READ USING CONCURRENT AUTO PRECHARGE
From Command
To Command
(Bank n)
(Bank m)
READ with AUTO
5($'RU5($'ZLWK$XWR3UHFKDUJH
(BL/2)
:5,7(RU:5,7(ZLWK$XWR3UHFKDUJH
(BL/2) + 2
35(&+$5*(RU$&7,9$7(
1
PRECHARGE
LOGIC Devices Incorporated
www.logicdevices.com
Minimum Delay (with Concurrent AUTO PRECHARGE)
UNITS
tCK
High Performance, Integrated Memory Module Product
September 16, 2013 LDS-L9D2xxMxxSBG5 Rev E
L9D232M64SBG5
L9D232M72SBG5
L9D232M80SBG5
L9D264M64SBG5
L9D264M72SBG5
L9D264M80SBG5
2 - 5.0 Gb, DDR2, 32 M [64 M] x 64/72/80 Integrated Memory Module (IMOD)
FIGURE 46 - BANK READ – WITHOUT AUTO PRECHARGE
CK#
T1
T0
T2
T3
T4
NOP1
READ2
T5
T6
T7
T7n
NOP1
PRE3
NOP1
T8
T8n
T9
CK
t CH
t CK
t CL
CKE
Command
NOP1
NOP1
ACT
NOP1
ACT
t RTP 4
Address
RA
Col n
A10
RA
5
RA
All banks
RA
One bank
Bank address
Bank x
Bank x 6
Bank x
t RCD
Bank x
CL = 3
t RP
t RAS3
t RC
DM
t DQSCK (MIN)
Case 1: t AC (MIN) and t DQSCK (MIN)
7
t RPRE
t RPST
7
DQS, DQS#
t LZ (MIN)
DO
n
DQ8
t LZ (MIN)
Case 2: t AC (MAX) and t DQSCK (MAX)
7
t RPRE
t AC (MIN)
t DQSCK (MAX)
t HZ (MIN)
t RPST
7
DQS, DQS#
t LZ (MAX)
DQ8
DO
n
t LZ (MIN)
t AC (MAX)
Transitioning Data
Notes:
LOGIC Devices Incorporated
t HZ (MAX)
Don’t Care
1. NOP commands are shown for ease of illustration; other commands may be valid at
these times.
2. BL = 4 and AL = 0 in the case shown.
3. The PRECHARGE command can only be applied at T6 if t RAS (MIN) is met.
4. READ-to-PRECHARGE = AL + BL/2 - 2CK + MAX ( t RTP/ t CK or 2CK).
5. Disable auto precharge.
6. “Don’t Care” if A10 is HIGH at T5.
7. I/O balls, when entering or exiting High-Z, are not referenced to a specific voltage level,
but to when the device begins to drive or no longer drives, respectively.
8. DO n = data-out from column n; subsequent elements are applied in the programmed
order.
www.logicdevices.com
High Performance, Integrated Memory Module Product
September 16, 2013 LDS-L9D2xxMxxSBG5 Rev E
L9D232M64SBG5
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L9D264M64SBG5
L9D264M72SBG5
L9D264M80SBG5
2 - 5.0 Gb, DDR2, 32 M [64 M] x 64/72/80 Integrated Memory Module (IMOD)
FIGURE 47 - BANK READ – WITH AUTO PRECHARGE
CK#
T1
T0
T2
T3
T4
T5
T6
T7
T7n
READ2,3
NOP1
NOP1
NOP1
NOP1
T8
T8n
CK
t CK
t CH
t CL
CKE
Command 1
NOP1
NOP1
ACT
ACT
Col n
RA
Address
NOP1
RA
4
A10
Bank address
RA
RA
Bank x
Bank x
Bank x
AL = 1
CL = 3
t RCD
t RTP
t RP
t RAS
t RC
DM
t DQSCK (MIN)
Case 1: t AC (MIN) and t DQSCK (MIN)
5
t RPRE
t RPST
5
DQS, DQS#
t LZ (MIN)
DO
n
DQ6
t LZ (MIN)
Case 2: t AC (MAX) and t DQSCK (MAX)
5
t AC (MIN)
t RPRE
t DQSCK (MAX)
t HZ (MIN)
t RPST
5
DQS, DQS#
t LZ (MAX)
DQ6
DO
n
4-bit
prefetch
t
Internal LZ (MAX)
precharge
t AC (MAX)
Transitioning Data
Notes:
LOGIC Devices Incorporated
t HZ (MAX)
Don’t Care
1. NOP commands are shown for ease of illustration; other commands may be valid at
these times.
2. BL = 4, RL = 4 (AL = 1, CL = 3) in the case shown.
3. The DDR2 SDRAM internally delays auto precharge until both t RAS (MIN) and t RTP (MIN)
have been satisfied.
4. Enable auto precharge.
5. I/O balls, when entering or exiting High-Z, are not referenced to a specific voltage level,
but to when the device begins to drive or no longer drives, respectively.
6. DO n = data-out from column n; subsequent elements are applied in the programmed
order.
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2 - 5.0 Gb, DDR2, 32 M [64 M] x 64/72/80 Integrated Memory Module (IMOD)
t
t
t
FIGURE 48
46--XD
4,ATA
X8 O
DUTPUT
ATA OUTPUT
TIMINGT–IMING
DQSQ,
– tDQSQ,
QH, AND
QH,
DATA
AND V
DALID
ATA W
VALID
INDOW
WINDOW
T1
T2
T2n
T3
T3n
T4
CK#
CK
t HP1
t HP1
t HP1
t HP1
t DQSQ2
t HP1
t HP1
t DQSQ2
t DQSQ2
t DQSQ2
t QH5
t QHS
t QH5
t QHS
t QH5
t QHS
LDSQ#
LDQS3
Lower Byte
DQ (last data valid) 4
DQ4
DQ4
DQ4
DQ4
DQ4
DQ4
DQ (first data no longer valid) 4
t QH5
t QHS
DQ (last data valid) 4
T2
T2n
T3
T3n
DQ (first data no longer valid) 4
T2
T2n
T3
T3n
DQ0–DQ7 and LDQS collectively 6
T2
T2n
T3
T3n
Data valid
window
t DQSQ2
Data valid
window
Data valid
window
Data valid
window
t DQSQ2
t DQSQ2
t DQSQ2
t QH5
t QHS
t QH5
t QHS
t QH5
t QHS
UDQS#
UDQS3
Upper Byte
DQ (last data valid) 7
DQ7
DQ7
DQ7
DQ7
DQ7
DQ7
DQ (first data no longer valid) 7
t QH5
DQ (last data valid) 7
T2
T2n
DQ (first data no longer valid) 7
T2
T2n
DQ8–DQ15 and UDQS collectively 6
T2
T2n
Data valid
window
Notes:
LOGIC Devices Incorporated
Data valid
window
T3
T3
T3
Data valid
window
t QHS
T3n
T3n
T3n
Data valid
window
1. t HP is the lesser of t CL or t CH clock transitions collectively when a bank is active.
2. t DQSQ is derived at each DQS clock edge, is not cumulative over time, begins with DQS
transitions, and ends with the last valid transition of DQ.
3. DQ transitioning after the DQS transitions define the t DQSQ window. LDQS defines the
lower byte, and UDQS defines the upper byte.
4. DQ0, DQ1, DQ2, DQ3, DQ4, DQ5, DQ6, or DQ7.
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L9D264M72SBG5
L9D264M80SBG5
2 - 5.0 Gb, DDR2, 32 M [64 M] x 64/72/80 Integrated Memory Module (IMOD)
t
t
t
t
FIGURE 49
46--XD
4,ATA
X8 O
DUTPUT
ATA OUTPUT
TIMINGT–IMING
AC –AND
DQSQ,
DQSCK
QH, AND DATA VALID WINDOW
T01
T1
T2
T3
T3n
T4
T4n
T5
T5n
T6
T6n
T7
CK#
CK
t DQSCK2 (MAX)
t DQSCK2 (MIN)
t LZ (MIN)
t HZ (MAX)
t RPST
t RPRE
DQS#/DQS or
LDQS#/LDQS/UDQ#/UDQS3
DQ (last data valid)
T3n
T4
T4n
T5n
T6
T6n
DQ (first data valid)
T3
T3
T3n
T4
T4n
T5
T5n
T6
T6n
All DQs collectively 4
T3
T3n
T4
T4n
T5
T5n
T6
T6n
t LZ (MIN)
t AC5 (MIN)
T5
t AC5 (MAX)
t HZ (MAX)
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LOGIC Devices Incorporated
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High Performance, Integrated Memory Module Product
September 16, 2013 LDS-L9D2xxMxxSBG5 Rev E
L9D232M64SBG5
L9D232M72SBG5
L9D232M80SBG5
L9D264M64SBG5
L9D264M72SBG5
L9D264M80SBG5
2 - 5.0 Gb, DDR2, 32 M [64 M] x 64/72/80 Integrated Memory Module (IMOD)
WRITE Continued
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TABLE 40: WRITE USING CONCURRENT AUTO PRECHARGE
From Command
To Command
(Bank n)
(Bank m)
WRITE with AUTO
5($'RU5($'ZLWK$XWR3UHFKDUJH
(CL-1) + (BL/2) + tWTR
:5,7(RU:5,7(ZLWK$XWR3UHFKDUJH
(BL/e)
35(&+$5*(RU$&7,9$7(
1
PRECHARGE
Minimum Delay (with Concurrent AUTO PRECHARGE)
UNITS
tCK
FIGURE 50
46--XW
4,RITE
X8 D
BATA
URST
OUTPUT TIMING – tDQSQ, tQH, AND DATA VALID WINDOW
T0
T1
T2
Command
WRITE
NOP
NOP
Address
Bank a,
Col b
T2n
T3
T3n
T4
CK#
CK
t DQSS (NOM)
NOP
WL ± t DQSS
NOP
5
DQS, DQS#
DI
b
DQ
DM
t DQSS (MIN)
t DQSS 5
WL - t DQSS
DQS, DQS#
DI
b
DQ
DM
t DQSS (MAX)
WL + t DQSS
t DQSS 5
DQS, DQS#
DI
b
DQ
DM
Transitioning Data
Notes:
LOGIC Devices Incorporated
Don’t Care
1. Subsequent rising DQS signals must align to the clock within t DQSS.
2. DI b = data-in for column b.
3. Three subsequent elements of data-in are applied in the programmed order following
DI b.
4. Shown with BL = 4, AL = 0, CL = 3; thus, WL = 2.
5. A10 is LOW with the WRITE command (auto precharge is disabled).
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High Performance, Integrated Memory Module Product
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L9D264M64SBG5
L9D264M72SBG5
L9D264M80SBG5
2 - 5.0 Gb, DDR2, 32 M [64 M] x 64/72/80 Integrated Memory Module (IMOD)
FIGURE 51 - CONSECUTIVE WRITE-TO-WRITE
T0
CK#
T1
T1n
T2
T2n
T3
T3n
T4
T4n
T5
T5n
T6
CK
Command
WRITE
NOP
WRITE
NOP
NOP
NOP
1
1
NOP
t CCD
WL = 2
WL = 2
Bank,
Col b
Address
Bank,
Col n
t DQSS (NOM)
WL ± t DQSS
1
DQS, DQS#
DI
b
DQ
DI
n
DM
Transitioning Data
Notes:
Don’t Care
1. Subsequent rising DQS signals must align to the clock within t DQSS.
2. DI b, etc. = data-in for column b, etc.
3. Three subsequent elements of data-in are applied in the programmed order following
DI b.
4. Three subsequent elements of data-in are applied in the programmed order following
DI n.
5. Shown with BL = 4, AL = 0, CL = 3; thus, WL = 2.
6. Each WRITE command may be to any bank.
FIGURE 52 - NONCONSECUTIVE WRITE-TO-WRITE
T0
CK#
T1
T2
NOP
NOP
T2n
T3
T3n
T4
T4n
T5
T5n
T6
T6n
CK
Command
WRITE
WRITE
WL = 2
Address
Bank,
Col b
t DQSS (NOM)
NOP
NOP
NOP
1
1
WL = 2
Bank,
Col n
WL ± t DQSS
1
DQS, DQS#
DI
n
DI
b
DQ
DM
Transitioning Data
Notes:
LOGIC Devices Incorporated
Don’t Care
1. Subsequent rising DQS signals must align to the clock within t DQSS.
2. DI b (or n), etc. = data-in for column b (or columnn).
3. Three subsequent elements of data-in are applied in the programmed order following
DI b.
4. Three subsequent elements of data-in are applied in the programmed order following
DI n.
5. Shown with BL = 4, AL = 0, CL = 3; thus, WL = 2.
6. Each WRITE command may be to any bank.
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L9D264M72SBG5
L9D264M80SBG5
2 - 5.0 Gb, DDR2, 32 M [64 M] x 64/72/80 Integrated Memory Module (IMOD)
FIGURE 53 - WRITE INTERRUPTED BY WRITE
CK#
CK
Command
Address
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
WRITE 1 a
NOP 2
WRITE 3 b
NOP 2
NOP 2
NOP 2
NOP 2
Valid 4
Valid 4
Valid 4
Valid 5
Valid 5
A10
Valid 6
7
7
7
7
7
DQS, DQS#
DI
a
DQ
DI
a+1
DI
a+2
DI
a+3
DI
b
DI
b+1
DI
b+2
DI
b+3
DI
b+4
DI
b+5
DI
b+6
DI
b+7
WL = 3
2-clock requirement
WL = 3
Transitioning Data
Notes:
LOGIC Devices Incorporated
Don’t Care
1. BL = 8 required and auto precharge must be disabled (A10 = LOW).
2. The NOP or COMMAND INHIBIT commands are valid. The PRECHARGE command cannot
be issued to banks used for WRITEs at T0 and T2.
3. The interrupting WRITE command must be issued exactly 2 × t CK from previous WRITE.
4. The earliest WRITE-to-PRECHARGE timing for WRITE at T0 is WL + BL/2 + t WR where t WR
starts with T7 and not T5 (because BL = 8 from MR and not the truncated length).
5. The WRITE command can be issued to any valid bank and row address (WRITE command
at T0 and T2 can be either same bank or different bank).
6. Auto precharge can be either enabled (A10 = HIGH) or disabled (A10 = LOW) by the
interrupting WRITE command.
7. Subsequent rising DQS signals must align to the clock within t DQSS.
8. Example shown uses AL = 0; CL = 4, BL = 8.
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L9D264M72SBG5
L9D264M80SBG5
2 - 5.0 Gb, DDR2, 32 M [64 M] x 64/72/80 Integrated Memory Module (IMOD)
FIGURE 54 - WRITE-TO-READ
CK#
T0
T1
T2
WRITE
NOP
NOP
T2n
T3
T3n
T4
T5
T6
T7
T8
NOP
READ
NOP
NOP
T9
T9n
CK
Command
NOP
NOP
NOP
t WTR1
Address
Bank a,
Col b
t DQSS (NOM)
Bank a,
Col n
WL ± t DQSS
CL = 3
2
DQS, DQS#
DI
b
DQ
DI
DM
t DQSS (MIN)
WL - t DQSS
CL = 3
2
DQS, DQS#
DI
b
DQ
DI
DM
t DQSS (MAX)
WL + t DQSS
CL = 3
2
DQS, DQS#
DI
b
DQ
DI
DM
Transitioning Data
Notes:
LOGIC Devices Incorporated
Don’t Care
1. t WTR is required for any READ following a WRITE to the same device, but it is not
required between module ranks.
2. Subsequent rising DQS signals must align to the clock within t DQSS.
3. DI b = data-in for column b; DO n = data-out from column n.
4. BL = 4, AL = 0, CL = 3; thus, WL = 2.
5. One subsequent element of data-in is applied in the programmed order following DI b.
6. t WTR is referenced from the first positive CK edge after the last data-in pair.
7. A10 is LOW with the WRITE command (auto precharge is disabled).
8. The number of clock cycles required to meet t WTR is either 2 or t WTR/ t CK, whichever is
greater.
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High Performance, Integrated Memory Module Product
September 16, 2013 LDS-L9D2xxMxxSBG5 Rev E
L9D232M64SBG5
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L9D232M80SBG5
L9D264M64SBG5
L9D264M72SBG5
L9D264M80SBG5
2 - 5.0 Gb, DDR2, 32 M [64 M] x 64/72/80 Integrated Memory Module (IMOD)
FIGURE 55 - WRITE-TO-PRECHARGE
T0
T1
T2
WRITE
NOP
NOP
T2n
T3
T3n
T4
T5
NOP
NOP
T6
T7
NOP
PRE
CK#
CK
Command
NOP
t WR
Address
Bank a,
Col b
t RP
Bank,
(a or all )
t DQSS (NOM)
WL + t DQSS
1
DQS#
DQS
DI
b
DQ
DM
t DQSS (MIN)
WL - t DQSS
1
DQS#
DQS
DI
b
DQ
DM
t DQSS (MAX)
WL + t DQSS
1
DQS#
DQS
DI
b
DQ
DM
Transitioning Data
Notes:
LOGIC Devices Incorporated
Don’t Care
1. Subsequent rising DQS signals must align to the clock within t DQSS.
2. DI b = data-in for column b.
3. Three subsequent elements of data-in are applied in the programmed order following
DI b.
4. BL = 4, CL = 3, AL = 0; thus, WL = 2.
5. t WR is referenced from the first positive CK edge after the last data-in pair.
6. The PRECHARGE and WRITE commands are to the same bank. However, the PRECHARGE
and WRITE commands may be to different banks, in which case t WR is not required and
the PRECHARGE command could be applied earlier.
7. A10 is LOW with the WRITE command (auto precharge is disabled).
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High Performance, Integrated Memory Module Product
September 16, 2013 LDS-L9D2xxMxxSBG5 Rev E
L9D232M64SBG5
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L9D264M64SBG5
L9D264M72SBG5
L9D264M80SBG5
2 - 5.0 Gb, DDR2, 32 M [64 M] x 64/72/80 Integrated Memory Module (IMOD)
FIGURE 56 - BANK WRITE – WITHOUT AUTO PRECHARGE
CK#
T0
T1
CK
T3
T4
T5
WRITE 2
NOP 1
NOP 1
T2
t CK
t CH
T5n
T6
T6n
T7
T8
T9
NOP 1
NOP 1
PRE
t CL
CKE
Command
NOP 1
ACT
NOP 1
Address
RA
Col n
A10
RA
3
NOP 1
All banks
One bank
Bank select
Bank x
Bank x4
Bank x
t RCD
t WR
WL = 2
t RP
t RAS
WL ± t DQSS (NOM)
5
DQS, DQS#
t WPRE
t DQSL t DQSH t WPST
DI
n
DQ6
DM
Transitioning Data
Notes:
LOGIC Devices Incorporated
Don’t Care
1. NOP commands are shown for ease of illustration; other commands may be valid at
these times.
2. BL = 4 and AL = 0 in the case shown.
3. Disable auto precharge.
4. “Don’t Care” if A10 is HIGH at T9.
5. Subsequent rising DQS signals must align to the clock within t DQSS.
6. DI n = data-in for column n; subsequent elements are applied in the programmed order.
7. t DSH is applicable during t DQSS (MIN) and is referenced from CK T5 or T6.
8. t DSS is applicable during t DQSS (MAX) and is referenced from CK T6 or T7.
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High Performance, Integrated Memory Module Product
September 16, 2013 LDS-L9D2xxMxxSBG5 Rev E
L9D232M64SBG5
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L9D232M80SBG5
L9D264M64SBG5
L9D264M72SBG5
L9D264M80SBG5
2 - 5.0 Gb, DDR2, 32 M [64 M] x 64/72/80 Integrated Memory Module (IMOD)
FIGURE 57 - BANK WRITE – WITH AUTO PRECHARGE
CK#
T0
T1
CK
T2
t CK
t CH
T3
T4
T5
WRITE 2
NOP 1
NOP 1
T5n
T6
T6n
T7
T8
T9
NOP 1
NOP 1
NOP 1
tCL
CKE
Command
NOP 1
ACT
Address
RA
A10
RA
NOP 1
NOP 1
Col n
3
Bank select
Bank x
Bank x
t RCD
WR4
WL = 2
t RP
t RAS
WL ± t DQSS (NOM)
5
DQS, DQS#
t WPRE
t DQSL t DQSH t WPST
DI
n
DQ6
DM
Transitioning Data
Notes:
LOGIC Devices Incorporated
Don’t Care
1. NOP commands are shown for ease of illustration; other commands may be valid at
these times.
2. BL = 4 and AL = 0 in the case shown.
3. Enable auto precharge.
4. WR is programmed via MR9–MR11 and is calculated by dividing t WR (in ns) by t CK and
rounding up to the next integer value.
5. Subsequent rising DQS signals must align to the clock within t DQSS.
6. DI n = data-in from column n; subsequent elements are applied in the programmed order.
7. t DSH is applicable during t DQSS (MIN) and is referenced from CK T5 or T6.
8. t DSS is applicable during t DQSS (MAX) and is referenced from CK T6 or T7.
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High Performance, Integrated Memory Module Product
September 16, 2013 LDS-L9D2xxMxxSBG5 Rev E
L9D232M64SBG5
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L9D232M80SBG5
L9D264M64SBG5
L9D264M72SBG5
L9D264M80SBG5
2 - 5.0 Gb, DDR2, 32 M [64 M] x 64/72/80 Integrated Memory Module (IMOD)
FIGURE 58 - WRITE – DM OPERATION
CK#
CK
T0
T1
T2
t CK
T3
t CH
T4
T5
T6
NOP 1
NOP 1
T6n
T7
T7n
T8
T9
T10
T11
t CL
CKE
Command
NOP 1
ACT
NOP 1
WRITE 2
NOP 1
AL = 1
Address
RA
Col n
A10
RA
3
NOP 1
NOP 1
NOP 1
NOP 1
PRE
WL = 2
All banks
One bank
Bank select
Bank x
Bankx4
Bank x
t RCD
t WR5
t RPA
t RAS
WL ± t DQSS (NOM)
6
DQS, DQS#
t WPRE
DQ7
t DQSL t DQSH t WPST
DI
n
DM
Transitioning Data
Notes:
LOGIC Devices Incorporated
Don’t Care
1. NOP commands are shown for ease of illustration; other commands may be valid at
these times.
2. BL = 4, AL = 1, and WL = 2 in the case shown.
3. Disable auto precharge.
4. “Don’t Care” if A10 is HIGH at T11.
5. t WR starts at the end of the data burst regardless of the data mask condition.
6. Subsequent rising DQS signals must align to the clock within t DQSS.
7. DI n = data-in for column n; subsequent elements are applied in the programmed order.
8. t DSH is applicable during t DQSS (MIN) and is referenced from CK T6 or T7.
9. t DSS is applicable during t DQSS (MAX) and is referenced from CK T7 or T8.
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90
High Performance, Integrated Memory Module Product
September 16, 2013 LDS-L9D2xxMxxSBG5 Rev E
L9D232M64SBG5
L9D232M72SBG5
L9D232M80SBG5
L9D264M64SBG5
L9D264M72SBG5
L9D264M80SBG5
2 - 5.0 Gb, DDR2, 32 M [64 M] x 64/72/80 Integrated Memory Module (IMOD)
FIGURE 59 - DATA INPUT TIMING
T0
T1
T1n
T2
T2n
T3
T3n
T4
CK#
CK
t DSH 1 t DSS 2
3
WL - t DQSS (NOM)
t DSH 1 t DSS 2
DQS
DQS#
t DQSL
t WPRE
DQ
t DQSH
t WPST
DI
DM
Transitioning Data
Notes:
1.
2.
3.
4.
5.
6.
Don’t Care
t DSH
(MIN) generally occurs during t DQSS (MIN).
t DSS (MIN) generally occurs during t DQSS (MAX).
Subsequent rising DQS signals must align to the clock within t DQSS.
WRITE command issued at T0.
For x16, LDQS controls the lower byte and UDQS controls the upper byte.
WRITE command with WL = 2 (CL = 3, AL = 0) issued at T0.
PRECHARGE
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DQG:5,7(RSHUDWLRQVHFWLRQV
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WREHSUHFKDUJHGEDQNDGGUHVVLQSXWVGHWHUPLQHWKHEDQNWREHSUHFKDUJHG:KHQDOOEDQNVDUHWREHSUHFKDUJHGWKHEDQNDGGUHVVLQSXWVDUHWUHDWHGDV
v'RQuW&DUHw
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LOGIC Devices Incorporated
www.logicdevices.com
91
High Performance, Integrated Memory Module Product
September 16, 2013 LDS-L9D2xxMxxSBG5 Rev E
L9D232M64SBG5
L9D232M72SBG5
L9D232M80SBG5
L9D264M64SBG5
L9D264M72SBG5
L9D264M80SBG5
2 - 5.0 Gb, DDR2, 32 M [64 M] x 64/72/80 Integrated Memory Module (IMOD)
REFRESH
7KH,QGXVWULDOWHPSHUDWXUH''5L02'GHYLFHVZKHQ7CLVd&UHTXLUHVD5()5(6+F\FOHDWDQDYHUDJHLQWHUYDORI60$;DQGDOOURZVLQDOO
EDQNVPXVWEHUHIUHVKHGDWOHDVWRQFHHYHU\PV7KH5()5(6+EHJLQVZKHQWKH5()5(6+FRPPDQGLVUHJLVWHUHGDQGHQGVt5)&0,1ODWHU7KH
DYHUDJHLQWHUYDOPXVWEHUHGXFHGWR60$;ZKHQ7CLV!&
FIGURE 60 - REFRESH MODE
T0
T3
T4
Ta0
Ta1
Tb0
Tb1
Tb2
NOP1
REF
NOP1
REF2
NOP1
NOP1
ACT
T2
T1
CK#
CK
t CK
t CH
t CL
CKE
Command
NOP1
PRE
NOP1
Address
RA
All banks
A10
RA
One bank
Bank
Bank(s)3
BA
DQS, DQS#4
DQ4
DM 4
t RP
t RFC (MIN)
t RFC 2
Indicates a break in
time scale
Notes:
LOGIC Devices Incorporated
Don’t Care
1. NOP commands are shown for ease of illustration; other valid commands may be possible at these times. CKE must be active during clock positive transitions.
2. The second REFRESH is not required and is only shown as an example of two back-toback REFRESH commands.
3. “Don’t Care” if A10 is HIGH at this point; A10 must be HIGH if more than one bank is
active (must precharge all active banks).
4. DM, DQ, and DQS signals are all “Don’t Care”/High-Z for operations shown.
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High Performance, Integrated Memory Module Product
September 16, 2013 LDS-L9D2xxMxxSBG5 Rev E
L9D232M64SBG5
L9D232M72SBG5
L9D232M80SBG5
L9D264M64SBG5
L9D264M72SBG5
L9D264M80SBG5
2 - 5.0 Gb, DDR2, 32 M [64 M] x 64/72/80 Integrated Memory Module (IMOD)
SELF REFRESH
7KH6(/)5()5(6+FRPPDQGLVLQLWLDWHGZKHQ&.(LVORZ7KHGLIIHUHQWLDOFORFNVKRXOGUHPDLQVWDEOHDQGPHHW t&.(VSHFLILFDWLRQVDWOHDVW[ t&.DIWHU
HQWHULQJ6(/)5()5(6+PRGH7KHSURFHGXUHIRUH[LWLQJ6(/)5()5(6+UHTXLUHVDVHTXHQFHRIFRPPDQGV)LUVWWKHGLIIHUHQWLDOFORFNPXVWEHVWDEOHDQG
meet t&.VSHFLILFDWLRQVDWOHDVW[t&.SULRUWR&.(JRLQJEDFNWR+,*+2QFH&.(LV+,*+t&.(>0,1@KDVEHHQVDWLVILHGZLWKWKUHHFORFNUHJLVWUDWLRQVWKH
''5L02'PXVWKDYH123RU'(6(/(&7FRPPDQGVLVVXHGIRU t;615$VLPSOHDOJRULWKPIRUPHHWLQJERWK5()5(6+DQG'//UHTXLUHPHQWVLVXVHGWR
DSSO\123RU'(6(/(&7FRPPDQGVIRUFORFNF\FOHVEHIRUHDSSO\LQJDQ\RWKHUFRPPDQG
FIGURE 61 - SELF REFRESH
T0
T1
T2
Ta0
Ta1
Tb0
Ta2
Tc0
Td0
CK#
CK1
t CH
t CK1
t CL
t CK1
t ISXR2
t CKE3
t IH
CKE1
Command
NOP
NOP 4
REF
NOP 4
Valid 5
Valid 5
t IH
ODT 6
t AOFD/ t AOFPD 6
Address
Valid
Valid 7
DQS#, DQS
DQ
DM
t XSNR2, 5, 10
t CKE (MIN) 9
t RP 8
t XSRD2, 7
Enter self refresh
mode (synchronous)
Notes:
LOGIC Devices Incorporated
Exit self refresh
mode (asynchronous)
Indicates a break in
time scale
Don’t Care
1. Clock must be stable and meeting t CK specifications at least 1 × t CK after entering self
refresh mode and at least 1 × t CK prior to exiting self refresh mode.
2. Self refresh exit is asynchronous; however, t XSNR and t XSRD timing starts at the first rising clock edge where CKE HIGH satisfies t ISXR.
3. CKE must stay HIGH until t XSRD is met; however, if self refresh is being re-entered, CKE
may go back LOW after t XSNR is satisfied.
4. NOP or DESELECT commands are required prior to exiting self refresh until state Tc0,
which allows any nonREAD command.
5. t XSNR is required before any nonREAD command can be applied.
6. ODT must be disabled and R TT off ( t AOFD and t AOFPD have been satisfied) prior to entering self refresh at state T1.
7. t XSRD (200 cycles of CK) is required before a READ command can be applied at state Td0.
8. Device must be in the all banks idle state prior to entering self refresh mode.
9. After self refresh has been entered, t CKE (MIN) must be satisfied prior to exiting self
refresh.
10. Upon exiting SELF REFRESH, ODT must remain LOW until t XSRD is satisfied.
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High Performance, Integrated Memory Module Product
September 16, 2013 LDS-L9D2xxMxxSBG5 Rev E
L9D232M64SBG5
L9D232M72SBG5
L9D232M80SBG5
L9D264M64SBG5
L9D264M72SBG5
L9D264M80SBG5
2 - 5.0 Gb, DDR2, 32 M [64 M] x 64/72/80 Integrated Memory Module (IMOD)
POWER DOWN MODE
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LOGIC Devices Incorporated
www.logicdevices.com
High Performance, Integrated Memory Module Product
September 16, 2013 LDS-L9D2xxMxxSBG5 Rev E
L9D232M64SBG5
L9D232M72SBG5
L9D232M80SBG5
L9D264M64SBG5
L9D264M72SBG5
L9D264M80SBG5
2 - 5.0 Gb, DDR2, 32 M [64 M] x 64/72/80 Integrated Memory Module (IMOD)
FIGURE 62 - POWER-DOWN
T1
T2
T3
T4
T5
T6
T7
T8
NOP
NOP
Valid
Valid
CK#
CK
Command
t CH
t CK
Valid 1
t CL
NOP
t CKE (MIN) 2
t IH
CKE
t CKE (MIN) 2
t IH
t IS
Address
Valid
Valid
Valid
t XP 3, t XARD 4
t XARDS 5
DQS, DQS#
DQ
DM
Exit
power-down
mode
Enter
power-down
mode 6
Notes:
LOGIC Devices Incorporated
Don’t Care
1. If this command is a PRECHARGE (or if the device is already in the idle state), then the
power-down mode shown is precharge power-down. If this command is an ACTIVATE
(or if at least one row is already active), then the power-down mode shown is active powerdown.
2. t CKE (MIN) of three clocks means CKE must be registered on three consecutive positive
clock edges. CKE must remain at the valid input level the entire time it takes to achieve
the three clocks of registration. Thus, after any CKE transition, CKE may not transition
from its valid level during the time period oft IS + 2 × t CK + t IH. CKE must not transition
during its t IS and t IH window.
3. t XP timing is used for exit precharge power-down and active power-down to any nonREAD command.
4. t XARD timing is used for exit active power-down to READ command if fast exit is selected via MR (bit 12 = 0).
5. t XARDS timing is used for exit active power-down to READ command if slow exit is selected via MR (bit 12 = 1).
6. No column accesses are allowed to be in progress at the time power-down is entered. If
the DLL was not in a locked state when CKE went LOW, the DLL must be reset after
exiting power-down mode for proper READ operation.
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High Performance, Integrated Memory Module Product
September 16, 2013 LDS-L9D2xxMxxSBG5 Rev E
L9D232M64SBG5
L9D232M72SBG5
L9D232M80SBG5
L9D264M64SBG5
L9D264M72SBG5
L9D264M80SBG5
2 - 5.0 Gb, DDR2, 32 M [64 M] x 64/72/80 Integrated Memory Module (IMOD)
TABLE 41: TRUTH TABLE - CKE
CKE
(n)
COMMAND (n)
CS\, RAS\, CAS\, WE\
Action (n)
L
L
;
0DLQWDLQ32:(5'2:1
1-6
L
H
'(6(/(&725123
32:(5'2:1H[LW
Prev. Cycle
Curr. Cycle
Current State
(n-1)
POWER-DOWN
Notes
L
L
;
0DLQWDLQ6(/)5()5(6+
L
H
'(6(/(&725123
SELF-REFRESH exit
BANK(S) ACTIVE
H
L
'(6(/(&725123
$FWLYH32:(5'2:1HQWU\
ALL BANKS ACTIVE
H
L
'(6(/(&725123
35(&+$5*(32:(5'2:1HQWU\
H
L
REFRESH
6(/)5()5(6+HQWU\
H
H
SELF REFRESH
6KRZQLQ7DEOH
127(6
&.(QLVWKHORJLFVWDWHRI&.(DWFORFNHGJHQ&.(QZDVWKHVWDWH
RI&.(DWWKHSUHYLRXVFORFNHGJH
&RPPDQGQLVWKHFRPPDQGUHJLVWHUHGDWFORFNHGJHQDQGDFWLRQQ
FRPPDQGVPD\EHLVVXHGRQO\DIWHUt;65'FORFNVLVVDWLVILHG
9DOLGFRPPDQGVIRU6(/)5()5(6+([LWDUH123DQG'(6(/(&7
7KHVWDWHRI2'7GRHVQRWDIIHFWWKHVWDWHVGHVFULEHGLQWKLVWDEOH7KH
RQO\
32:(5'2:1DQG6(/)5()5(6+FDQQRWEHHQWHUHGZKLOH5($'
32:(5'2:1PRGHVGRQRWSHUIRUPDQ\5()5(6+RSHUDWLRQV7KH
RU:5,7(RSHUDWLRQV/2$'02'(RU35(&+$5*(RSHUDWLRQVDUH
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UHTXLUHPHQWV
v;w PHDQV v'21u7 &$5(w LQFOXGLQJ IORDWLQJ DURXQG 9REF LQ 6(/)
5()5(6+DQG32:(5'2:1+RZHYHU2'7PXVWEHGULYHQ+,*+
RU/2:LQ32:(5'2:1LIWKH2'7IXQFWLRQLVHQDEOHGYLDWKH(05
H[WHQGHGPRGHUHJLVWHU
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LVVXHGRQHYHU\FORFNHGJHRFFXUULQJGXULQJWKH t;615SHULRG5($'
GXUDWLRQRI32:(5'2:1PRGHLVWKHUHIRUHOLPLWHGE\WKH5()5(6+
HGJHQ
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9DOLG FRPPDQGV IRU 32:(5'2:1 (QWU\ DQG ([LW DUH 123 DQG
'(6(/(&72QO\
&XUUHQWVWDWHLVWKHVWDWHRIWKH''56'5$0LPPHGLDWHO\SULRUWRFORFN
LVDUHVXOWRIFRPPDQGQ
tCKE
= 3 x t&.7KLVUHTXLUHVDPLQLPXPRIFORFNF\FOHVRIUHJLVWUD-
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VWDWH
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LOGIC Devices Incorporated
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96
High Performance, Integrated Memory Module Product
September 16, 2013 LDS-L9D2xxMxxSBG5 Rev E
L9D232M64SBG5
L9D232M72SBG5
L9D232M80SBG5
L9D264M64SBG5
L9D264M72SBG5
L9D264M80SBG5
2 - 5.0 Gb, DDR2, 32 M [64 M] x 64/72/80 Integrated Memory Module (IMOD)
FIGURE 63 - READ-TO-POWER-DOWN OR SELF REFRESH ENTRY
CK#
T0
T1
T2
T3
READ
NOP
NOP
NOP
T4
T5
Valid
Valid
T6
T7
CK
Command
NOP 1
t CKE (MIN)
CKE
Address
Valid
A10
DQS, DQS#
DQ
DO
RL = 3
DO
DO
DO
Power-down 2 or
self refresh entry
Transitioning Data
Notes:
Don’t Care
1. In the example shown, READ burst completes at T5; earliest power-down or self refresh
entry is at T6.
2. Power-down or self refresh entry may occur after the READ burst completes.
FIGURE 64 - READ WITH AUTO PRECHARGE-TO-POWER-DOWN OR SELF REFRESH ENTRY
CK#
T0
T1
T2
T3
T4
T5
T6
READ
NOP
NOP
NOP
Valid
Valid
NOP1
T7
CK
Command
t CKE (MIN)
CKE
Address
Valid
A10
DQS, DQS#
DQ
RL = 3
DO
DO
DO
DO
Power-down or
self refresh 2 entry
Transitioning Data
Notes:
LOGIC Devices Incorporated
Don’t Care
1. In the example shown, READ burst completes at T5; earliest power-down or self refresh
entry is at T6.
2. Power-down or self refresh entry may occur after the READ burst completes.
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High Performance, Integrated Memory Module Product
September 16, 2013 LDS-L9D2xxMxxSBG5 Rev E
L9D232M64SBG5
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L9D264M64SBG5
L9D264M72SBG5
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2 - 5.0 Gb, DDR2, 32 M [64 M] x 64/72/80 Integrated Memory Module (IMOD)
FIGURE 65 - WRITE-TO-POWER-DOWN OR SELF REFRESH ENTRY
T0
T1
T2
T3
T4
T5
T6
T7
WRITE
NOP
NOP
NOP
Valid
Valid
Valid
NOP 1
CK#
CK
Command
T8
t CKE (MIN)
CKE
Address
Valid
A10
DQS, DQS#
DQ
DO
DO
DO
DO
t WTR
WL = 3
Power-down or
self refresh entry1
Transitioning Data
Note:
Don’t Care
1. Power-down or self refresh entry may occur after the WRITE burst completes.
FIGURE 66 - WRITE WITH AUTO PRECHARGE-TO-POWER-DOWN OR SELF REFRESH ENTRY
CK#
T0
T1
T2
T3
T4
T5
T6
READ
NOP
NOP
NOP
Valid
Valid
NOP1
T7
CK
Command
t CKE (MIN)
CKE
Address
Valid
A10
DQS, DQS#
DQ
RL = 3
DO
DO
DO
DO
Power-down or
self refresh 2 entry
Transitioning Data
Notes:
LOGIC Devices Incorporated
Don’t Care
1. In the example shown, READ burst completes at T5; earliest power-down or self refresh
entry is at T6.
2. Power-down or self refresh entry may occur after the READ burst completes.
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High Performance, Integrated Memory Module Product
September 16, 2013 LDS-L9D2xxMxxSBG5 Rev E
L9D232M64SBG5
L9D232M72SBG5
L9D232M80SBG5
L9D264M64SBG5
L9D264M72SBG5
L9D264M80SBG5
2 - 5.0 Gb, DDR2, 32 M [64 M] x 64/72/80 Integrated Memory Module (IMOD)
FIGURE 67 - REFRESH COMMAND-TO-POWER-DOWN ENTRY
T0
T1
T2
REFRESH
NOP
T3
CK#
CK
Valid
Command
t CKE (MIN)
CKE
1 x t CK
Don’t Care
Power-down 1
entry
Note:
1. The earliest precharge power-down entry may occur is at T2, which is 1 × t CK after the
REFRESH command. Precharge power-down entry occurs prior to t RFC (MIN) being
satisfied.
FIGURE 68 - ACTIVATE COMMAND-TO-POWER-DOWN ENTRY
T0
T1
T2
Valid
ACT
NOP
T3
CK#
CK
Command
VALID
Address
t CKE (MIN)
CKE
1 t CK
Don’t Care
Power-down 1
entry
Note:
LOGIC Devices Incorporated
1. The earliest active power-down entry may occur is at T2, which is 1 × t CK after the ACTIVATE
command. Active power-down entry occurs prior to t RCD (MIN) being satisfied.
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High Performance, Integrated Memory Module Product
September 16, 2013 LDS-L9D2xxMxxSBG5 Rev E
L9D232M64SBG5
L9D232M72SBG5
L9D232M80SBG5
L9D264M64SBG5
L9D264M72SBG5
L9D264M80SBG5
2 - 5.0 Gb, DDR2, 32 M [64 M] x 64/72/80 Integrated Memory Module (IMOD)
FIGURE 69 - PRECHARGE COMMAND-TO-POWER-DOWN ENTRY
CK#
T0
T1
T2
Valid
PRE
NOP
T3
CK
Command
Address
Valid
All banks
vs
Single bank
A10
t CKE
(MIN)
CKE
Don’t Care
1 x t CK
Power-down 1
entry
Note:
1. The earliest precharge power-down entry may occur is at T2, which is 1 × t CK after the
PRECHARGE command. Precharge power-down entry occurs prior to t RP (MIN) being
satisfied.
LOGIC Devices Incorporated
www.logicdevices.com
100
High Performance, Integrated Memory Module Product
September 16, 2013 LDS-L9D2xxMxxSBG5 Rev E
L9D232M64SBG5
L9D232M72SBG5
L9D232M80SBG5
L9D264M64SBG5
L9D264M72SBG5
L9D264M80SBG5
2 - 5.0 Gb, DDR2, 32 M [64 M] x 64/72/80 Integrated Memory Module (IMOD)
FIGURE 70 - LOAD MODE COMMAND-TO-POWER-DOWN ENTRY
T0
T1
T2
T3
Valid
LM
NOP
NOP
T4
CK#
CK
Command
Valid 1
Address
t CKE (MIN)
CKE
t RP 2
t MRD
Don’t C
Power-down 3
entry
Notes:
LOGIC Devices Incorporated
1. Valid address for LM command includes MR, EMR, EMR(2), and EMR(3) registers.
2. All banks must be in the precharged state and t RP met prior to issuing LM command.
3. The earliest precharge power-down entry is at T3, which is after t MRD is satisfied.
www.logicdevices.com
101
High Performance, Integrated Memory Module Product
September 16, 2013 LDS-L9D2xxMxxSBG5 Rev E
L9D232M64SBG5
L9D232M72SBG5
L9D232M80SBG5
L9D264M64SBG5
L9D264M72SBG5
L9D264M80SBG5
2 - 5.0 Gb, DDR2, 32 M [64 M] x 64/72/80 Integrated Memory Module (IMOD)
PRECHARGE POWER DOWN CLOCK FREQUENCY CHANGE
:KHQWKH''5L02'GHYLFHLVLQ35(&+$5*(32:(5'2:1PRGH2'7PXVWEHWXUQHGRIIDQG&.(PXVWEHDWDORJLF/2:OHYHO$PLQLPXPRIWZR
GLIIHUHQWLDOFORFNF\FOHVPXVWSDVVDIWHU&.(JRHV/2:EHIRUHFORFNIUHTXHQF\PD\FKDQJH7KHGHYLFHLQSXWFORFNIUHTXHQF\LVDOORZHGWRFKDQJHRQO\ZLWKLQ
PLQLPXPDQGPD[LPXPRSHUDWLQJIUHTXHQFLHVVSHFLILHGIRUWKHSDUWLFXODUVSHHGJUDGH'XULQJLQSXWORFNIUHTXHQF\FKDQJH2'7DQG&.(PXVWEHKHOGVWDEOH
/2:OHYHOV:KHQWKHLQSXWFORFNIUHTXHQF\LVFKDQJHGQHZVWDEOHFORFNVPXVWEHSURYLGHGWRWKHGHYLFHEHIRUH35(&+$5*(32:(5'2:1PD\EHH[LWHG
DQG'//PXVWEHUHVHWYLD05DIWHU35(&+$5*(32:(5'2:1H[LW'HSHQGLQJRQWKHQHZFORFNIUHTXHQF\DGGLWLRQDO/0FRPPDQGVPLJKWEHUHTXLUHG
WRDGMXVWWKH&/:5$/DQGVRIRUWK
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UHORFNSHULRGRIF\FOHV2'7PXVWUHPDLQRII$IWHUWKH'///RFNWLPHWKH''5LVUHDG\WRRSHUDWHZLWKDQHZFORFNIUHTXHQF\
FIGURE 71 - INPUT CLOCK FREQUENCY CHANGE DURING PRECHARGE POWER-DOWN MODE
Previous clock frequency
T0
T1
New clock frequency
T2
T3
Ta1
Ta0
Ta2
Ta3
Ta4
Tb0
NOP
Valid
CK#
CK
t CH
t CH
t CL
t CL
t CK
t CK
2 x t CK (MIN) 1
1 x t CK (MIN) 2
t CKE (MIN) 3
t CKE (MIN) 3
CKE
Command
Address
Valid 4
NOP
NOP
NOP
Valid
LM
DLL RESET
Valid
t XP
ODT
DQS, DQS#
DQ
High-Z
High-Z
DM
Enter precharge
power-down mode
Frequency
change
Exit precharge
power-down mode
200 x t CK
Indicates a break in
time scale
Notes:
LOGIC Devices Incorporated
Don’t Care
1. A minimum of 2 × t CK is required after entering precharge power-down prior to changing clock frequencies.
2. When the new clock frequency has changed and is stable, a minimum of 1 × t CK is required prior to exiting precharge power-down.
www.logicdevices.com
102
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September 16, 2013 LDS-L9D2xxMxxSBG5 Rev E
L9D232M64SBG5
L9D232M72SBG5
L9D232M80SBG5
L9D264M64SBG5
L9D264M72SBG5
L9D264M80SBG5
2 - 5.0 Gb, DDR2, 32 M [64 M] x 64/72/80 Integrated Memory Module (IMOD)
RESET
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7KH5(6(7FRQGLWLRQGHILQHGKHUHDVVXPHVDOOVXSSO\YROWDJHVDOOVXSSO\YROWDJHVDQG9REFDUHVWDEOHDQGPHHWDOO'&VSHFLILFDWLRQJXLGHOLQHVSULRUWR
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t'(/$<EHIRUHWXUQLQJRIIWKHFORFNV6WDEOHFORFNVPXVWH[LVWDWWKH&.&.?LQSXWVRIWKH'5$0EHIRUH&.(LVGULYHQ+,*+DWZKLFKWLPHWKHQRUPDOLQLWLDOL]DWLRQVHTXHQFHPXVWRFFXU7KH''5GHYLFHLVQRZUHDG\IRUQRUPDORSHUDWLRQDIWHUWKHLQLWLDOL]DWLRQVHTXHQFH)LJXUHVKRZVWKHSURSHUVHTXHQFHIRU
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LOGIC Devices Incorporated
www.logicdevices.com
103
High Performance, Integrated Memory Module Product
September 16, 2013 LDS-L9D2xxMxxSBG5 Rev E
L9D232M64SBG5
L9D232M72SBG5
L9D232M80SBG5
L9D264M64SBG5
L9D264M72SBG5
L9D264M80SBG5
2 - 5.0 Gb, DDR2, 32 M [64 M] x 64/72/80 Integrated Memory Module (IMOD)
FIGURE 72 - RESET FUNCTION
T0
T1
T3
T2
T4
T5
t CK
Tb0
Ta0
CK#
CK
t CL
t CL
t CKE (MIN)
t DELAY
1
CKE
ODT
Command
NOP 2
READ
READ
NOP 2
NOP 2
NOP 2
PRE
DM 3
Address
Col n
Col n
All banks
A10
Bank address
Bank b
Bank a
DQS 3
DQ 3
High-Z
High-Z
High-Z
DO
DO
4
High-Z
DO
High-Z
RTT
System
RESET
T = 400ns (MIN)
Start of normal
initialization
sequence
Indicates a break in
time scale
Notes:
Unknown
RTT On
Transitioning Data
t RPA
5
Don’t Care
1. VDD, VDDL, VDDQ, VTT, and VREF must be valid at all times.
2. Either NOP or DESELECT command may be applied.
3. DM represents DM for x4/x8 configuration and UDM, LDM for x16 configuration. DQS
represents DQS, DQS#, UDQS, UDQS#, LDQS, LDQS#, RDQS, and RDQS# for the appropriate configuration (x4, x8, x16).
4. In certain cases where a READ cycle is interrupted, CKE going HIGH may result in the
completion of the burst.
5. Initialization timing is shown in Figure 35.
LOGIC Devices Incorporated
www.logicdevices.com
High Performance, Integrated Memory Module Product
September 16, 2013 LDS-L9D2xxMxxSBG5 Rev E
L9D232M64SBG5
L9D232M72SBG5
L9D232M80SBG5
L9D264M64SBG5
L9D264M72SBG5
L9D264M80SBG5
2 - 5.0 Gb, DDR2, 32 M [64 M] x 64/72/80 Integrated Memory Module (IMOD)
ODT TIMING
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RSHQ&.(/2:05> @t$21't$21t$2)'DQGt$2)WLPLQJSDUDPHWHUVDUHDSSOLHGDVVKRZQLQ)LJXUH
'XULQJVORZH[LW32:(5'2:1PRGHDQG35(&+$5*(32:(5'2:1PRGHW$213'DQGW$2)3'WLPLQJSDUDPHWHUVDUHDSSOLHGDVVKRZQLQ)LJXUH
2'7WXUQRIIWLPLQJSULRUWRHQWHULQJDQ\32:(5'2:1PRGHLVGHWHUPLQHGE\WKHSDUDPHWHU t$13'0,1DVVKRZQLQ)LJXUH$WVWDWH72WKH2'7
+,*+VLJQDOVDWLVILHVW$13'0,1SULRUWRHQWHULQJ32:(5'2:1PRGHDW75:KHQ t$13'0,1LVVDWLVILHG t$2)'DQG t$2)WLPLQJSDUDPHWHUVDSSO\
)LJXUHDOVRVKRZVWKHH[DPSOHZKHUHt$13'0,1LV127VDWLVILHGEHFDXVH2'7+,*+GRHVQRWRFFXUXQWLOVWDWH73:KHQt$13'0,1LV127VDWLVILHG
t$213'WLPLQJSDUDPHWHUVDSSO\
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t$213'WLPLQJSDUDPHWHUVDSSO\
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SDUDPHWHUVDSSO\
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t$;3'0,1LV127VDWLVILHGt$213'WLPLQJSDUDPHWHUVDSSO\
FIGURE 73 - ODT TIMING FOR ENTERING AND EXITING POWER-DOWN MODE
Synchronous
Synchronous or
Synchronous
Asynchronous
t
t AXPD (8 t CKs)
ANPD (3 t CKs)
First CKE latched LOW
First CKE latched HIGH
CKE
Any mode except
self refresh mode
Any mode except
Active power-down fast (synchronous)
self refresh mode
Active power-down slow (asynchronous)
Precharge power-down (asynchronous)
Applicable modes
t
AOND/ t AOFD
t
t
AOND/ t AOFD (synchronous)
t
AOND/ t AOFD
AONPD/ t AOFPD (asynchronous)
Applicable timing parameters
LOGIC Devices Incorporated
www.logicdevices.com
105
High Performance, Integrated Memory Module Product
September 16, 2013 LDS-L9D2xxMxxSBG5 Rev E
L9D232M64SBG5
L9D232M72SBG5
L9D232M80SBG5
L9D264M64SBG5
L9D264M72SBG5
L9D264M80SBG5
2 - 5.0 Gb, DDR2, 32 M [64 M] x 64/72/80 Integrated Memory Module (IMOD)
MRS COMMAND TO ODT UPDATE DELAY
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FIGURE 74 - TIMING FOR MRS COMMAND TO ODT UPDATE DELAY
T0
Command
Ta0
Ta1
Ta2
Ta3
Ta4
Ta5
EMRS 1
NOP
NOP
NOP
NOP
NOP
CK#
CK
2
ODT 2
t MOD
t AOFD
t IS
0ns
Internal
RTT setting
Old setting
Undefined
New setting
Indicates a break in
time scale
Notes:
1. The LM command is directed to the mode register, which updates the information in
EMR (A6, A2), that is, RTT (nominal).
2. To prevent any impedance glitch on the channel, the following conditions must be met:
t
AOFD must be met before issuing the LM command; ODT must remain LOW for the
entire duration of the t MOD window until t MOD is met.
LOGIC Devices Incorporated
www.logicdevices.com
106
High Performance, Integrated Memory Module Product
September 16, 2013 LDS-L9D2xxMxxSBG5 Rev E
L9D232M64SBG5
L9D232M72SBG5
L9D232M80SBG5
L9D264M64SBG5
L9D264M72SBG5
L9D264M80SBG5
2 - 5.0 Gb, DDR2, 32 M [64 M] x 64/72/80 Integrated Memory Module (IMOD)
FIGURE 75 - ODT TIMING FOR ACTIVE OR FAST-EXIT POWER-DOWN MODE
CK#
T0
T1
T2
T3
T4
T5
T6
CK
t CK
t CH
t CL
Command
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Address
Valid
Valid
Valid
Valid
Valid
Valid
Valid
CKE
t AOND
ODT
t AOFD
R TT
t AON (MIN)
t AOF (MAX)
t AON (MAX)
t AOF (MIN)
RTT Unknown
LOGIC Devices Incorporated
www.logicdevices.com
RTT On
Don’t Care
High Performance, Integrated Memory Module Product
September 16, 2013 LDS-L9D2xxMxxSBG5 Rev E
L9D232M64SBG5
L9D232M72SBG5
L9D232M80SBG5
L9D264M64SBG5
L9D264M72SBG5
L9D264M80SBG5
2 - 5.0 Gb, DDR2, 32 M [64 M] x 64/72/80 Integrated Memory Module (IMOD)
FIGURE 76 - ODT TIMING FOR SLOW-EXIT OR PRECHARGE POWER-DOWN MODES
CK#
T0
T1
T2
T3
T4
T5
T6
T7
CK
t CK
t CH
t CL
Command
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Address
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
CKE
ODT
t AONPD (MAX)
t AONPD (MIN)
RTT
t AOFPD (MIN)
t AOFPD (MAX)
Transitioning RTT
LOGIC Devices Incorporated
www.logicdevices.com
RTT Unknown
RTT On
Don’t Care
High Performance, Integrated Memory Module Product
September 16, 2013 LDS-L9D2xxMxxSBG5 Rev E
L9D232M64SBG5
L9D232M72SBG5
L9D232M80SBG5
L9D264M64SBG5
L9D264M72SBG5
L9D264M80SBG5
2 - 5.0 Gb, DDR2, 32 M [64 M] x 64/72/80 Integrated Memory Module (IMOD)
FIGURE 77 - ODT TURN-OFF TIMINGS WHEN ENTERING POWER-DOWN MODE
CK#
T0
T1
T2
T3
T4
T5
T6
NOP
NOP
NOP
NOP
NOP
NOP
NOP
CK
Command
t ANPD (MIN)
CKE
t AOFD
ODT
t AOF (MAX)
RTT
t AOF (MIN)
t AOFPD (MAX)
ODT
RTT
t AOFPD (MIN)
Transitioning RTT
LOGIC Devices Incorporated
www.logicdevices.com
RTT Unknown
109
RTT ON
Don’t Care
High Performance, Integrated Memory Module Product
September 16, 2013 LDS-L9D2xxMxxSBG5 Rev E
L9D232M64SBG5
L9D232M72SBG5
L9D232M80SBG5
L9D264M64SBG5
L9D264M72SBG5
L9D264M80SBG5
2 - 5.0 Gb, DDR2, 32 M [64 M] x 64/72/80 Integrated Memory Module (IMOD)
FIGURE 78 - ODT TURN-ON TIMING WHEN ENTERING POWER-DOWN MODE
CK#
T0
T1
T2
T3
T4
T5
T6
NOP
NOP
NOP
NOP
NOP
NOP
NOP
CK
Command
t
ANPD (MIN)
CKE
ODT
t
AOND
t
AON (MAX)
RTT
t
AON (MIN)
ODT
t
AONPD (MAX)
RTT
t
Transitioning R TT
LOGIC Devices Incorporated
www.logicdevices.com
AONPD (MIN)
R TT Unknown
110
R TT On
Don’t Care
High Performance, Integrated Memory Module Product
September 16, 2013 LDS-L9D2xxMxxSBG5 Rev E
L9D232M64SBG5
L9D232M72SBG5
L9D232M80SBG5
L9D264M64SBG5
L9D264M72SBG5
L9D264M80SBG5
2 - 5.0 Gb, DDR2, 32 M [64 M] x 64/72/80 Integrated Memory Module (IMOD)
FIGURE 79 - ODT TURN-OFF TIMING WHEN EXITING POWER-DOWN MODE
CK#
T0
T1
T2
T3
T4
Ta0
Ta1
Ta2
Ta3
Ta4
Ta5
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
CK
Command
t AXPD
(MIN)
CKE
t CKE
(MIN)
t AOFD
ODT
t AOF
(MAX)
RTT
t AOF
t AOFPD
ODT
(MIN)
(MAX)
RTT
t AOFPD
Indicates a break in
time scale
LOGIC Devices Incorporated
www.logicdevices.com
RTT Unknown
111
(MIN)
RTT On
Transitioning RTT
Don’t Care
High Performance, Integrated Memory Module Product
September 16, 2013 LDS-L9D2xxMxxSBG5 Rev E
L9D232M64SBG5
L9D232M72SBG5
L9D232M80SBG5
L9D264M64SBG5
L9D264M72SBG5
L9D264M80SBG5
2 - 5.0 Gb, DDR2, 32 M [64 M] x 64/72/80 Integrated Memory Module (IMOD)
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www.logicdevices.com
113
High Performance, Integrated Memory Module Product
September 16, 2013 LDS-L9D2xxMxxSBG5 Rev E
L9D232M64SBG5
L9D232M72SBG5
L9D232M80SBG5
L9D264M64SBG5
L9D264M72SBG5
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High Performance, Integrated Memory Module Product
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L9D232M64SBG5
L9D232M72SBG5
L9D232M80SBG5
L9D264M64SBG5
L9D264M72SBG5
L9D264M80SBG5
2 - 5.0 Gb, DDR2, 32 M [64 M] x 64/72/80 Integrated Memory Module (IMOD)
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www.logicdevices.com
115
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