L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module Benefits FEATURES Configuration: x/'06%*0HJ[[ 8 banks x/'06%*0HJ[[ 8 banks DDR3 Integrated Module [iMOD]: VDD=VDD4 999 x9FHQWHUWHUPLQDWHGSXVKSXOO ,2 x-('(&VWDQGDUGEDOOSLQRXW x3DFNDJHPP[PP[PP ZEDOOV x0DWUL[EDOOSLWFKPP 6SDFHVDYLQJIRRWSULQW 7KHUPDOO\HQKDQFHG,PSHGDQFH PDWFKHGLQWHJUDWHGSDFNDJLQJ 'LIIHUHQWLDOELGLUHFWLRQDOGDWDVWUREH QELWSUHIHWFKDUFKLWHFWXUH LQWHUQDOEDQNVSHUZRUGZRUGV LQWHJUDWHGLQSDFNDJH 1RPLQDODQGG\QDPLFRQGLHWHUPLQD WLRQ2'7IRUGDWDVWUREHDQGPDVN signals. 3URJUDPPDEOH&$65($'ODWHQF\ &/DQG &$6:5,7(ODWHQF\&:/ and 11 )L[HGEXUVWOHQJWK%/RIDQGEXUVW FKRS%&RI 6HOHFWDEOH%&RU%/RQWKHIO\ 27) 6HOI$XWR5HIUHVKPRGHV 7HPSHUDWXUH&RPSHQVDWHG5HIUHVK 2SHUDWLQJ7HPSHUDWXUH5DQJH DPELHQWWHPS 7A x,QGXVWULDO&WR&VXSSRUWLQJ 6(/)$8725()5(6+ x([WHQGHG&WR&PDQXDO 5()5(6+RQO\ x0LO7HPS&WR&PDQXDO 5()5(6+RQO\ &25(FORFNLQJIUHTXHQFLHV 0+] 'DWD7UDQVIHU5DWHV 0ESV Write leveling 0XOWLSXUSRVHUHJLVWHU 2XWSXW'ULYHU&DOLEUDWLRQ %RDUGDUHDVDYLQJVZLWKVXUIDFH PRXQWIULHQGO\SLWFKPP 5HGXFHGLQWHUFRQQHFWURXWLQJ 5HGXFHGWUDFHOHQJWKVGXHWR WKHKLJKO\LQWHJUDWHGLPSHGDQFH PDWFKHGSDFNDJLQJ 7KHUPDOO\HQKDQFHGSDFNDJLQJ WHFKQRORJ\DOORZVLOLFRQLQWHJUDWLRQ ZLWKRXWSHUIRUPDQFHGHJUDGDWLRQGXH WRSRZHUGLVVLSDWLRQKHDW +LJK7&(RUJDQLFODPLQDWHLQWHU SRVHUIRULPSURYHGJODVVVWDELOLW\ RYHUDZLGHRSHUDWLQJWHPSHUDWXUH 6XLWDELOLW\RIXVHLQ+LJK5HOLDELOLW\ DSSOLFDWLRQVUHTXLULQJ0LOWHPSQRQ KHUPHWLFGHYLFHRSHUDWLRQ 1RWH7KLVLQWHJUDWHGSURGXFWDQGRULWVVSHFLILFDWLRQV DUHVXEMHFWWRFKDQJHZLWKRXWQRWLFH/DWHVWGRFXPHQW VKRXOGEHUHWULHYHGIURP/',SULRUWR\RXUGHVLJQ FRQVLGHUDWLRQ iMOD Part Information ORDER NUMBER SPEED GRADE /'06%*[ ''5 /'06%*[ ''5 /'06%*[ DDR3-1333 /'06%*[ ''5 /'06%*[ ''5 /'06%*[ DDR3-1333 PKG FOOTPRINT PP[PP I/O PITCH PP PKG NO. BG1 'DWDVKHHW,QGH[DYDLODEOHRQSDJH integrated module products LOGIC Devices Incorporated www.logicdevices.com 1 High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module FEATURES FIGURE 1 - DDR3 PART NUMBERS Sample Part Number: L9D3 256M 32S L9D3256M32SBG2I107 BG1 107 I DDR3 iMOD Code Word = 256 MB Speed Grade 15 1.5ns / 1333Mbps 125 1.25ns / 1600Mbps 107 1.07ns / 1800Mbps Wordwidth x32 S = Single Channel PBGA Temperature Code Commercial (0oC to 70oC) C Industrial (-40oC to 85oC) I o o Extended (-40 C to 105 C) E Military (-55oC to 125oC) M Note: Not all options can be combined. Please see our Part Catalog for available offerings. TABLE 1: ADDRESSING Parameter 256-512 Meg x 32 &RQILJXUDWLRQ/'06%* 0[ &RQILJXUDWLRQ/'06%* 0[ 5HIUHVK&RXQW 8K 52:$GGUHVVLQJ/'06%* .$>@ 52:$GGUHVVLQJ/'06%* .$>@ Bank Addressing %$>@ &ROXPQ$GGUHVVLQJ .$>@ LOGIC Devices Incorporated www.logicdevices.com 2 High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module STATE DIAGRAM FIGURE 2 - SIMPLIFIED STATE DIAGRAM CKE L Power applied Power on Reset Procedure MRS, MPR, write leveling Initialization Self refresh SRE ZQCL MRS SRX From any state RESET ZQ Calibration REF ZQCL/ZQCS Idle Refreshing PDE ACT PDX Active PowerDown Preharge PowerDown Activating PDX CKE L CKE L PDE Bank Active WRITE WRITE READ WRITE AP READ AP READ Writing READ Reading WRITE READ AP WRITE AP WRITE AP READ AP PRE, PREA Writing PRE, PREA Preharging PRE, PREA Reading Automatic Sequence Command Sequence ACT = ACTIVATE MPR = Multipurpose register MRS = Mode register set PDE = Power-down entry PDX = Power-down exit PRE = PRECHARGE LOGIC Devices Incorporated www.logicdevices.com PREA=PRECHARGE ALL READ = RD, RDS4, RDS8 READ AP = RDAP, RDAPS4, RDAPS8 REF = REFRESH RESET = START RESET PROCEDURE SRE = Self refresh entry 3 SRX = Self refresh exit WRITE = WR, WRS4, WRS8 WRITE AP = WRAP, WRAPS4, WRAPS8 ZQCL = ZQ LONG CALIBRATION ZQCS = ZQ SHORT CALIBRATION High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module INDUSTRIAL TEMPERATURE FUNCTIONAL DESCRIPTION 7KH ''5 6'5$0 XVHV GRXEOH GDWD UDWH DUFKLWHFWXUH WR DFKLHYH KLJK VSHHGRSHUDWLRQ7KHGRXEOHGDWDUDWH''5DUFKLWHFWXUHLVDQQSUHIHWFK ZLWKDQLQWHUIDFHGHVLJQHGWRWUDQVIHUWZRGDWDZRUGVSHUFORFNF\FOHDWWKH ,2SLQV$VLQJOH5($'RU:5,7(DFFHVVIRUWKH''56'5$0FRQVLVWV RIDVLQJOHQELWZLGHRQHFORFNF\FOHGDWDWUDQVIHUDWWKHLQWHUQDOPHPRU\ FRUHDQGHLJKWFRUUHVSRQGLQJQELWZLGHRQHKDOIFORFNF\FOHGDWDWUDQVIHU DWWKH,2SLQ 7KH LQGXVWULDO WHPSHUDWXUH , GHYLFH UHTXLUHV WKH DPELHQW WHPSHUDWXUH QRWH[FHHG&RU&-('(&VSHFLILFDWLRQVUHTXLUHWKH5()5(6+ UDWHWRGRXEOHZKHQ7AH[FHHGV&WKLVDOVRUHTXLUHVXVHRIWKHKLJK WHPSHUDWXUH6(/)5()5(6+RSWLRQ$GGLWLRQDOO\2'7UHVLVWDQFHDQG WKH ,1387287387 LPSHGDQFH PXVW EH GHUDWHG ZKHQ WKH 7A is <0C RU!C. 7KHGLIIHUHQWLDOVWUREHV/'46[/'46[?8'46[8'46[?DUHWUDQVPLWWHGH[WHUQDOO\DORQJZLWKGDWDIRUXVHLQGDWDFDSWXUHDWWKH''56'5$0 LQSXW UHFHLYHU '46 LV FHQWHUDOLJQHG ZLWK GDWD IRU :5,7(V 7KH 5($' GDWD LV WUDQVPLWWHG E\ WKH ''5 6'5$0 DQG HGJHDOLJQHG WR WKH GDWD strobes. EXTENDED TEMPERATURE 7KH([WHQGHGWHPSHUDWXUH(GHYLFHUHTXLUHVWKHDPELHQWWHPSHUDWXUH QRWH[FHHG&RU&-('(&VSHFLILFDWLRQVUHTXLUHWKHUHIUHVK UDWHWRGRXEOHZKHQ7AH[FHHGV&WKLVDOVRUHTXLUHVXVHRIWKHKLJK WHPSHUDWXUH6(/)5()5(6+RSWLRQ$GGLWLRQDOO\2'7UHVLVWDQFHDQG WKH ,1387287387 LPSHGDQFH PXVW EH GHUDWHG ZKHQ WKH 7A is <0C RU!C. 7KH ''5 6'5$0 RSHUDWHV IURP D GLIIHUHQWLDO FORFN &.[ &.[? 7KH FURVVLQJRI&.JRLQJ+,*+DQG&.?JRLQJ/2:LVUHIHUUHGWRDVWKHSRVLWLYHHGJHRI&ORFN&.&RQWURO&RPPDQGDQG$GGUHVVVLJQDOVDUHUHJLVWHUHGDWHYHU\SRVLWLYHHGJHRI&.,QSXWGDWDLVUHJLVWHUHGRQWKHILUVW ULVLQJ HGJH RI '46 DIWHU WKH :5,7( SUHDPEOH DQG RXWSXW GDWD LV UHIHUHQFHGRQWKHILUVWULVLQJHGJHRI'46DIWHUWKH5($'SUHDPEOH MILITARY, EXTREME OPERATING TEMPERATURE 5($' DQG :5,7( DFFHVVHV WR WKH ''5 6'5$0 DUH EXUVWRULHQWHG $FFHVVHV VWDUW DW D VHOHFWHG ORFDWLRQ DQG FRQWLQXH IRU D SURJUDPPHG QXPEHURIORFDWLRQVLQDSURJUDPPHGVHTXHQFH$FFHVVHVEHJLQZLWKWKH UHJLVWUDWLRQRIDQ$&7,9$7(FRPPDQGZKLFKLVWKHQIROORZHGE\D5($' RU:5,7(FRPPDQG7KHDGGUHVVELWVUHJLVWHUHGFRLQFLGHQWZLWKWKH$&7,9$7(FRPPDQGDUHXVHGWRVHOHFWWKHEDQNDQGWKHVWDUWLQJFROXPQORFDWLRQIRUWKHEXUVWDFFHVV 7KH0LO7HPS0GHYLFHUHTXLUHVWKHDPELHQWWHPSHUDWXUHQRWH[FHHG &RU&-('(&UHTXLUHVWKH5()5(6+UDWHGRXEOHZKHQ7A H[FHHGV&DQG/',UHFRPPHQGVDQDGGLWLRQDOGHUDWLQJDVVSHFLILHG LQ WKLV GRFXPHQW DV WR SURSHUO\ PDLQWDLQ WKH '5$0 FRUH FHOO FKDUJH DW WHPSHUDWXUHVDERYH7A!C. ''56'5$0GHYLFHVXVH5($'DQG:5,7(%/DQG%&$Q$872 35(&+$5*(IXQFWLRQPD\EHHQDEOHGWRSURYLGHDVHOIWLPHG52:35(&+$5*(WKDWLVLQLWLDWHGDWWKHHQGRIWKHEXUVWDFFHVV $VZLWKVWDQGDUG''56'5$0GHYLFHVWKHSLSHOLQHGPXOWLEDQNDUFKLWHFWXUHRIWKH''56'5$0DOORZVIRUFRQFXUUHQWRSHUDWLRQWKHUHE\SURYLGLQJKLJKEDQGZLGWKE\KLGLQJ52:35(&+$5*(DQG$&7,9$7,21WLPH $ 6(/) 5()5(6+ PRGH LV SURYLGHG IRU DOO WHPSHUDWXUH JUDGH RIIHULQJV DORQJZLWK$8726(/)5()5(6+IRU,QGXVWULDOSURGXFWDVZHOODVSRZHU VDYLQJ32:(5'2:1PRGH LOGIC Devices Incorporated www.logicdevices.com 4 High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module FIGURE 3A- L9D3256M32SBG1 FUNCTIONAL BLOCK DIAGRAM CS# RESET# ODT WE# RAS#, CAS# CKE CK, CK# BA0-2 ADDR0-14 ADDR BA DM3 CK, CKE RAS, WE CK# CAS ODT RESET CSA DIE 1 DM2 DQ 7 DQ 0 ZQ1 240Ω ±1% VSSQ ADDR BA CK, CKE RAS, WE CK# CAS DQS3, DQS3# DQ 31 DQ 24 DQS2, DQS2# DQ 23 DQ 16 DQS1, DQS1# ODT RESET CSA DIE 0 DM1 DQ 15 DQ 8 DQ 15 DQ 8 DQS0, DQS0# DQ 7 DQ 0 DM0 ZQ2 240Ω ±1% VSSQ LOGIC Devices Incorporated www.logicdevices.com High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module FIGURE 3B- L9D3512M32SBG1 FUNCTIONAL BLOCK DIAGRAM CS# RESET# ODT WE# RAS#, CAS# CKE CK, CK# BA0-2 ADDR0-15 ADDR BA CK, CKE RAS, WE CK# CAS DM3 ODT RESET CSA DIE 3 DQ 31 DQ 24 DQ 24-31 DQS3, DQS3# VSSQ ADDR BA CK, CKE RAS, WE CK# CAS ODT RESET CSA DIE 2 DM2 DQ 23 DQ 16 DQ 16-23 DQS2, DQS2# VSSQ DM1 DIE 1 DQ 15 DQ 8 DQ 8-15 DQS1, DQS1# VSSQ ADDR BA CK, CKE RAS, WE CK# CAS ODT RESET CSA DIE 0 DM0 DQ 7 DQ 0 DQ 0-7 DQS0, DQS0# VSSQ LOGIC Devices Incorporated www.logicdevices.com High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module BALL /SIGNAL LOCATION (PBGA) FIGURE 4A - L9D3256M32SBG1 PINOUT TOP VIEW LOGIC Devices Incorporated 1 2 3 4 A VDD VSS VSSQ B VDDQ DQ0 C VDDQ D 5 6 7 8 9 10 11 12 DQ1 DQ9 VSSQ VSS VDD A VSSQ DQ3 DQ11 VSSQ DQ8 VDDQ B DQ2 VSSQ DM0 DM1 VSSQ DQ10 VDDQ C VSSQ VDDQ DQS0 DQS0# DQS1# DQS1 VDDQ VSSQ D E VSSQ DQ4 VDDQ DQ5 DQ13 VDDQ DQ12 VSSQ E F VSS DQ6 VDDQ DQ7 DQ15 VDDQ DQ14 VSS F G VDDDL NC CAS# RAS# CK CK# CKE VDD G H RESET# BA2 ODT CS# A10 A14 NC NC H J VREFDQ VSSDL NC WE# A1 NC VSS VREFCA J K BA0 A9 A2 A0 A4 A6 A12 BA1 K L VDD A7 A5 A3 A8 A11 A13 VDD L M VSS DQ24 VDDQ DQ25 DQ17 VDDQ DQ16 VSS M N VSSQ DQ26 VDDQ DQ27 DQ19 VDDQ DQ18 VSSQ N P VSSQ VDDQ DQS3 DQS3# DQS2# DQS2 VDDQ VSSQ P R VDDQ DQ28 VSSQ DM3 DM2 VSSQ DQ20 VDDQ R T VDDQ DQ30 VSSQ DQ29 DQ21 VSSQ DQ22 VDDQ T U VDD VSS VSSQ DQ31 DQ23 VSSQ VSS VDD U 1 2 3 4 9 10 11 12 5 6 7 8 GND (Core) V + (Core Power) UNPOPULATED Address GND (I/O) V + (I/O Power) Data IO VDDDL CNTRL Level REF NC VSSDL www.logicdevices.com 7 High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module BALL /SIGNAL LOCATION (PBGA) FIGURE 4B - L9D3512M32SBG1 PINOUT TOP VIEW 1 2 3 4 A VDD VSS VSSQ B VDDQ DQ0 C VDDQ D 9 10 11 12 DQ1 DQ9 VSSQ VSS VDD A VSSQ DQ3 DQ11 VSSQ DQ8 VDDQ B DQ2 VSSQ DM0 DM1 VSSQ DQ10 VDDQ C VSSQ VDDQ DQS0 DQS0# DQS1# DQS1 VDDQ VSSQ D E VSSQ DQ4 VDDQ DQ5 DQ13 VDDQ DQ12 VSSQ E F VSS DQ6 VDDQ DQ7 DQ15 VDDQ DQ14 VSS F G VDDDLL NC CAS# RAS# CK CK# CKE VDD G H RESET# BA2 ODT CS# A10 A14 A15 NC H J VREFDQ VSSDLL NC WE# A1 NC VSS VREFCA J 6 7 8 K BA0 A9 A2 A0 A4 A6 A12 BA1 K L VDD A7 A5 A3 A8 A11 A13 VDD L M VSS DQ24 VDDQ DQ25 DQ17 VDDQ DQ16 VSS M N VSSQ DQ26 VDDQ DQ27 DQ19 VDDQ DQ18 VSSQ N P VSSQ VDDQ DQS3 DQS3# DQS2# DQS2 VDDQ VSSQ P R VDDQ DQ28 VSSQ DM3 DM2 VSSQ DQ20 VDDQ R T VDDQ DQ30 VSSQ DQ29 DQ21 VSSQ DQ22 VDDQ T U VDD VSS VSSQ DQ31 DQ23 VSSQ VSS VDD U 1 2 3 4 9 10 11 12 GND (Core) LOGIC Devices Incorporated 5 5 6 7 V + (Core Power) 8 UNPOPULATED Address GND (I/O) V + (I/O Power) Data IO VDDDL CNTRL Level REF No Connect VSSDL www.logicdevices.com 8 High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module TABLE 2A - L9D3256M32SBG1 BALL/SIGNAL LOCATION AND DESCRIPTION Ball Assignments .-././ Symbol Type A0, A1, A2, Input Address Inputs: 3URYLGHWKH52:DGGUHVVIRU$&7,9$7(FRPPDQGVDQGWKHFROXPQDGGUHVV .//.+/ A3, A4, A5, ./+ Description DQGDXWRSUHFKDUJHELW$10IRU5($'<:5,7(FRPPDQGVWRVHOHFWRQHORFDWLRQRXWRIWKH A6, A7, A8, PHPRU\DUUD\LQWKHUHVSHFWLYHEDQN$10VDPSOHGGXULQJD35(&+$5*(FRPPDQGGHWHUPLQHV A9, A10/AP, ZKHWKHUWKH35(&+$5*(DSSOLHVWRRQHEDQN$10/2:EDQNVHOHFWHGE\%$>@RUDOOEDQNV A11, A12 / (A10+,*+7KHDGGUHVVLQSXWVDOVRSURYLGHWKHRSFRGHGXULQJD/2$'02'(FRPPDQG BCH, A13, $GGUHVVLQSXWVDUHUHIHUHQFHGWR9UHI&$$12%&ZKHQHQDEOHGLQWKHPRGHUHJLVWHU05$12 A14 LVVDPSOHGGXULQJ5($'DQG:5,7(FRPPDQGVWRGHWHUPLQHZKHWKHUEXUVWFKRS/2: %&4 EXUVWFKRS ..+ BA0, BA1, BA2 Input Bank Address Inputs: %$>@GHILQHWKHEDQNWRZKLFKDQ$&7,9$7(5($':5,7(RU 35(&+$5*(FRPPDQGLVEHLQJDSSOLHG%$>@GHILQHZKLFKPRGHUHJLVWHU050, MR1, MR2, or MR3LVORDGHGGXULQJWKH/2$'02'(FRPPDQG%$>@DUHUHIHUHQFHGWR9UHI&$ G9, G10 CK, CK\ Input Clock: &.[DQG&.[?DUHGLIIHUHQWLDOFORFNLQSXWVRQHGLIIHUHQWLDOSDLUSHU:25'IRXU:25'V FRQWDLQHGLQWKH/'[[*SURGXFW$OOFRQWURODQGDGGUHVVLQSXWVLJQDOVDUHVDPSOHGRQWKH FURVVLQJRIWKHSRVLWLYHHGJHRI&.[DQGWKHQHJDWLYHHGJHRI&.[?2XWSXWGDWDVWUREHV8'46[ 8'46[?DQG/'46[/'46[?LVUHIHUHQFHGWRWKHFURVVLQJRI&.[DQG&.[? G11 CKE Input Clock Enable: &.(HQDEOHVDQGGLVDEOHVLQWHUQDOFLUFXLWU\DQGFORFNVRQWKH6'5$07KH VSHFLILFFLUFXLWU\WKDWLVHQDEOHGGLVDEOHGLVGHSHQGHQWXSRQWKH''56'5$0FRQILJXUDWLRQDQG RSHUDWLQJPRGH7DNLQJ&.(/2:SURYLGHV35(&+$5*(SRZHUGRZQDQG6(/)5()5(6+ RSHUDWLRQVDOOEDQNVLGOHRUDFWLYHSRZHUGRZQURZDFWLYHLQDQ\EDQN&.(LVV\QFKURQRXV IRUSRZHUGRZQHQWU\DQGH[LWDQGIRUVHOIUHIUHVKHQWU\&.(LVDV\QFKURQRXVIRUVHOIUHIUHVK H[LW,QSXWEXIIHUVH[FOXGLQJ&.[&.[?&.(5(6(7DQG2'7DUHGLVDEOHGGXULQJ6(/) 5()5(6+&.(LVUHIHUHQFHGWR9UHI&$ + CS\ Input Chip Select: &6?HQDEOHVUHJLVWHUHG/2:DQGGLVDEOHVWKHFRPPDQGGHFRGHU$OOFRPPDQGV DUHPDVNHGZKHQ&6?LVUHJLVWHUHG+,*+&6?SURYLGHVIRUH[WHUQDOUDQNVHOHFWLRQRQV\VWHPVZLWK PXOWLSOH UDQNV&6?LVFRQVLGHUHGSDUWRIWKHFRPPDQGFRGH&6?LVUHIHUHQFHGWR9UHI&$ C4, C9, R9, R4 DM0, DM1, Input Input Data Mask: /'0[LVWKH/RZHUE\WHRID:25'8'0[LVWKH8SSHUE\WHRID:25'WKH DM2, DM3 /'[[*FRQWDLQVIRXU:25'67KHGDWDPDVNLQSXWPDVNV:5,7(GDWD/RZHUE\WHGDWD PDVNHGZKHQ/'0[LVVDPSOHG+,*+XSSHUE\WHGDWDPDVNHGZKHQ8'0[LVVDPSOHG+,*+ 7KH8'0[DQG/'0[SLQVDUHVWUXFWXUHGDVLQSXWVRQO\WKHSLQVHOHFWULFDOORDGLQJLVGHVLJQHGWR PDWFKWKDWRIWKH'4DQG/'46[?8'46[DQG8'46[?SLQV G4 RAS\ Input ROW Address Strobe/Select: 'HILQHVWKHFRPPDQGEHLQJHQWHUHGDORQJ&$6?:(?DQG&6? 7KLVLQSXWSLQLVUHIHUHQFHGWR9UHI&$ G3 CAS\ Input COLUMN Address Strobe/Select: 'HILQHVWKHFRPPDQGEHLQJHQWHUHGDORQJZLWK5$6?:(? DQG&6?7KLVLQSXWSLQLVUHIHUHQFHGWR9UHI&$ - WE\ Input WRITE Enable Input: 'HILQHVWKHFRPPDQGEHLQJHQWHUHGDORQJZLWK&$6?5$6?DQG&6?7KLV LQSXWSLQLVUHIHUHQFHGWR9UHI&$ LOGIC Devices Incorporated www.logicdevices.com 9 High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module TABLE 2A - L9D3256M32SBG1 BALL/SIGNAL LOCATION AND DESCRIPTION CONTINUED Ball Assignments Symbol Type + ODT Input Description On-Die Termination: 2'7HQDEOHVZKHQUHJLVWHUHG+,*+DQGGLVDEOHVWHUPLQDWLRQUHVLVWDQFHLQWHUQDOWRWKH''56'5$0:KHQHQDEOHGLQQRUPDORSHUDWLRQ2'7LVRQO\DSSOLHG WRHDFKRIWKHIROORZLQJVLJQDOV'4>@/'4;[?8'46[?8'0[DQG/'0[7KH2'7 LQSXWLVLJQRUHGLIGLVDEOHGYLDWKH/2$'02'(UHJLVWHUFRPPDQG2'7LVUHIHUHQFHGWR VrefCA. + RESET\ Input RESET: $QLQSXWFRQWUROSLQDFWLYH/2:UHIHUHQFHGWR9VV7KH5(6(7?LQSXWUHFHLYHULV D&026LQSXWGHILQHGDVDUDLOWRUDLOVLJQDOZLWK'&+,*+t 0.8 x VDD and DC LOW d 0.2 x VDD45(6(7?DVVHUWLRQDQGGHDVVHUWLRQDUHDV\QFKURQRXV D3, D4 DQS0, DQS0# Input Data Strobe, LOW Byte (per WORD): 2XWSXWHGJHDOLJQHGZLWK5($'GDWD,QSXWFHQWHU DOLJQHGZLWK:5,7(GDWD D10, D9 DQS1, DQS1# Input Data Strobe, HIGH Byte (per WORD): 2XWSXWHGJHDOLJQHGZLWK5($'GDWD,QSXWFHQWHU DOLJQHGZLWK:5,7(GDWD %$&%(( DQ0, DQ1, F2, F4 DQ2, DQ3, I/O Data Input/Output: /2:%\WH/2::25':25'3LQUHIHUHQFHGWR9UHI'4 I/O Data Input/Output: +,*+%\WH/2::25':25'3LQUHIHUHQFHGWR9UHI'4 I/O Data Input/Output: /2:%\WH:25'3LQUHIHUHQFHGWR9UHI'4 I/O Data Input/Output: +,*+%\WH:25'3LQUHIHUHQFHGWR9UHI'4 DQ4, DQ5, DQ6, DQ7 %$&%( DQ8, DQ9, ()) DQ10, DQ11, DQ12, DQ13, DQ14, DQ15 M11, M9, N11, N9, R11, DQ16, DQ17, 778 DQ18, DQ19, DQ20, DQ21, DQ22, DQ23 M2, M4, N2, N4, R2, T4, DQ24, DQ25, 78 DQ26, DQ27, DQ28, DQ29, DQ30, DQ31 - VrefCA Supply 9ROWDJH5HIHUHQFH&25(9UHI&$PXVWEHPDLQWDLQHGDWDOOWLPHV - VrefDQ Supply 9ROWDJH5HIHUHQFH,29UHI'4PXVWEHPDLQWDLQHGDWDOOWLPHV LOGIC Devices Incorporated www.logicdevices.com 10 High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module TABLE 2A - L9D3256M32SBG1 BALL/SIGNAL LOCATION AND DESCRIPTION CONTINUED Ball Assignments Symbol A1, A12, G12, L1, L12, VDD Type Description Supply 3RZHU6XSSO\99 88 B1, B12, C1, C12, D2, VDDQ Supply 'DWD,26XSSO\99 '(()) 00113 35577 $$))- Vss Supply Ground 0088 A3, A10, B3, B10, C3, VssQ Supply 'DWD,2*URXQG,VRODWHGIURP&RUHIRULPSURYHGQRLVHLPPXQLW\ &''(( 11335 57788 - VSSDL Ground for DLL G1 VDDDL 6XSSO\IRU'// *++-- NC LOGIC Devices Incorporated www.logicdevices.com 1R&RQQHFW 11 High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module TABLE 2B - L9D3512M32SBG1 BALL/SIGNAL LOCATION AND DESCRIPTION Ball Assignments Symbol Type .-././ A0, A1, A2, Input Address Inputs: 3URYLGHWKH52:DGGUHVVIRU$&7,9$7(FRPPDQGVDQGWKHFROXPQDGGUHVV .//.+/ A3, A4, A5, ./++ Description DQGDXWRSUHFKDUJHELW$10IRU5($'<:5,7(FRPPDQGVWRVHOHFWRQHORFDWLRQRXWRIWKH A6, A7, A8, PHPRU\DUUD\LQWKHUHVSHFWLYHEDQN$10VDPSOHGGXULQJD35(&+$5*(FRPPDQGGHWHUPLQHV A9, A10/AP, ZKHWKHUWKH35(&+$5*(DSSOLHVWRRQHEDQN$10/2:EDQNVHOHFWHGE\%$>@RUDOOEDQNV A11, A12 / BCH, A13, A14, A15 (A10+,*+7KHDGGUHVVLQSXWVDOVRSURYLGHWKHRSFRGHGXULQJD/2$'02'(FRPPDQG $GGUHVVLQSXWVDUHUHIHUHQFHGWR9UHI&$$12%&ZKHQHQDEOHGLQWKHPRGHUHJLVWHU05$12 LVVDPSOHGGXULQJ5($'DQG:5,7(FRPPDQGVWRGHWHUPLQHZKHWKHUEXUVWFKRS/2: %&4 EXUVWFKRS ..+ BA0, BA1, BA2 Input Bank Address Inputs: %$>@GHILQHWKHEDQNWRZKLFKDQ$&7,9$7(5($':5,7(RU 35(&+$5*(FRPPDQGLVEHLQJDSSOLHG%$>@GHILQHZKLFKPRGHUHJLVWHU050, MR1, MR2, or MR3LVORDGHGGXULQJWKH/2$'02'(FRPPDQG%$>@DUHUHIHUHQFHGWR9UHI&$ G9, G10 CK, CK\ Input Clock: &.[DQG&.[?DUHGLIIHUHQWLDOFORFNLQSXWVRQHGLIIHUHQWLDOSDLUSHU:25'IRXU:25'V FRQWDLQHGLQWKH/'[[*SURGXFW$OOFRQWURODQGDGGUHVVLQSXWVLJQDOVDUHVDPSOHGRQWKH FURVVLQJRIWKHSRVLWLYHHGJHRI&.[DQGWKHQHJDWLYHHGJHRI&.[?2XWSXWGDWDVWUREHV8'46[ 8'46[?DQG/'46[/'46[?LVUHIHUHQFHGWRWKHFURVVLQJRI&.[DQG&.[? G11 CKE Input Clock Enable: &.(HQDEOHVDQGGLVDEOHVLQWHUQDOFLUFXLWU\DQGFORFNVRQWKH6'5$07KH VSHFLILFFLUFXLWU\WKDWLVHQDEOHGGLVDEOHGLVGHSHQGHQWXSRQWKH''56'5$0FRQILJXUDWLRQDQG RSHUDWLQJPRGH7DNLQJ&.(/2:SURYLGHV35(&+$5*(SRZHUGRZQDQG6(/)5()5(6+ RSHUDWLRQVDOOEDQNVLGOHRUDFWLYHSRZHUGRZQURZDFWLYHLQDQ\EDQN&.(LVV\QFKURQRXV IRUSRZHUGRZQHQWU\DQGH[LWDQGIRUVHOIUHIUHVKHQWU\&.(LVDV\QFKURQRXVIRUVHOIUHIUHVK H[LW,QSXWEXIIHUVH[FOXGLQJ&.[&.[?&.(5(6(7DQG2'7DUHGLVDEOHGGXULQJ6(/) 5()5(6+&.(LVUHIHUHQFHGWR9UHI&$ + CS\ Input Chip Select: &6?HQDEOHVUHJLVWHUHG/2:DQGGLVDEOHVWKHFRPPDQGGHFRGHU$OOFRPPDQGV DUHPDVNHGZKHQ&6?LVUHJLVWHUHG+,*+&6?SURYLGHVIRUH[WHUQDOUDQNVHOHFWLRQRQV\VWHPVZLWK PXOWLSOH UDQNV&6?LVFRQVLGHUHGSDUWRIWKHFRPPDQGFRGH&6?LVUHIHUHQFHGWR9UHI&$ C4, C9, R9, R4 DM0, DM1, Input Input Data Mask: /'0[LVWKH/RZHUE\WHRID:25'8'0[LVWKH8SSHUE\WHRID:25'WKH DM2, DM3 /'[[*FRQWDLQVIRXU:25'67KHGDWDPDVNLQSXWPDVNV:5,7(GDWD/RZHUE\WHGDWD PDVNHGZKHQ/'0[LVVDPSOHG+,*+XSSHUE\WHGDWDPDVNHGZKHQ8'0[LVVDPSOHG+,*+ 7KH8'0[DQG/'0[SLQVDUHVWUXFWXUHGDVLQSXWVRQO\WKHSLQVHOHFWULFDOORDGLQJLVGHVLJQHGWR PDWFKWKDWRIWKH'4DQG/'46[?8'46[DQG8'46[?SLQV G4 RAS\ Input ROW Address Strobe/Select: 'HILQHVWKHFRPPDQGEHLQJHQWHUHGDORQJ&$6?:(?DQG&6? 7KLVLQSXWSLQLVUHIHUHQFHGWR9UHI&$ G3 CAS\ Input COLUMN Address Strobe/Select: 'HILQHVWKHFRPPDQGEHLQJHQWHUHGDORQJZLWK5$6?:(? DQG&6?7KLVLQSXWSLQLVUHIHUHQFHGWR9UHI&$ - WE\ Input WRITE Enable Input: 'HILQHVWKHFRPPDQGEHLQJHQWHUHGDORQJZLWK&$6?5$6?DQG&6?7KLV LQSXWSLQLVUHIHUHQFHGWR9UHI&$ LOGIC Devices Incorporated www.logicdevices.com 12 High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module TABLE 2B - L9D3512M32SBG1 BALL/SIGNAL LOCATION AND DESCRIPTION CONTINUED Ball Assignments Symbol Type + ODT Input Description On-Die Termination: 2'7HQDEOHVZKHQUHJLVWHUHG+,*+DQGGLVDEOHVWHUPLQDWLRQUHVLVWDQFHLQWHUQDOWRWKH''56'5$0:KHQHQDEOHGLQQRUPDORSHUDWLRQ2'7LVRQO\DSSOLHG WRHDFKRIWKHIROORZLQJVLJQDOV'4>@/'4;[?8'46[?8'0[DQG/'0[7KH2'7 LQSXWLVLJQRUHGLIGLVDEOHGYLDWKH/2$'02'(UHJLVWHUFRPPDQG2'7LVUHIHUHQFHGWR VrefCA. + RESET\ Input RESET: $QLQSXWFRQWUROSLQDFWLYH/2:UHIHUHQFHGWR9VV7KH5(6(7?LQSXWUHFHLYHULV D&026LQSXWGHILQHGDVDUDLOWRUDLOVLJQDOZLWK'&+,*+t 0.8 x VDD and DC LOW d 0.2 x VDD45(6(7?DVVHUWLRQDQGGHDVVHUWLRQDUHDV\QFKURQRXV D3, D4 DQS0, DQS0# Input Data Strobe, LOW Byte (per WORD): 2XWSXWHGJHDOLJQHGZLWK5($'GDWD,QSXWFHQWHU DOLJQHGZLWK:5,7(GDWD D10, D9 DQS1, DQS1# Input Data Strobe, HIGH Byte (per WORD): 2XWSXWHGJHDOLJQHGZLWK5($'GDWD,QSXWFHQWHU DOLJQHGZLWK:5,7(GDWD %$&%(( DQ0, DQ1, F2, F4 DQ2, DQ3, I/O Data Input/Output: /2:%\WH/2::25':25'3LQUHIHUHQFHGWR9UHI'4 I/O Data Input/Output: +,*+%\WH/2::25':25'3LQUHIHUHQFHGWR9UHI'4 I/O Data Input/Output: /2:%\WH:25'3LQUHIHUHQFHGWR9UHI'4 I/O Data Input/Output: +,*+%\WH:25'3LQUHIHUHQFHGWR9UHI'4 DQ4, DQ5, DQ6, DQ7 %$&%( DQ8, DQ9, ()) DQ10, DQ11, DQ12, DQ13, DQ14, DQ15 M11, M9, N11, N9, R11, DQ16, DQ17, 778 DQ18, DQ19, DQ20, DQ21, DQ22, DQ23 M2, M4, N2, N4, R2, T4, DQ24, DQ25, 78 DQ26, DQ27, DQ28, DQ29, DQ30, DQ31 - VrefCA Supply 9ROWDJH5HIHUHQFH&25(9UHI&$PXVWEHPDLQWDLQHGDWDOOWLPHV - VrefDQ Supply 9ROWDJH5HIHUHQFH,29UHI'4PXVWEHPDLQWDLQHGDWDOOWLPHV LOGIC Devices Incorporated www.logicdevices.com 13 High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module TABLE 2A - L9D3256M32SBG1 BALL/SIGNAL LOCATION AND DESCRIPTION CONTINUED Ball Assignments Symbol A1, A12, G12, L1, L12, VDD Type Description Supply 3RZHU6XSSO\99 88 B1, B12, C1, C12, D2, VDDQ Supply 'DWD,26XSSO\99 '(()) 00113 35577 $$))- Vss Supply Ground 0088 A3, A10, B3, B10, C3, VssQ Supply 'DWD,2*URXQG,VRODWHGIURP&RUHIRULPSURYHGQRLVHLPPXQLW\ &''(( 11335 57788 - VSSDL Ground for DLL G1 VDDDL 6XSSO\IRU'// *+-- NC LOGIC Devices Incorporated www.logicdevices.com 1R&RQQHFW 14 High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module FIGURE 5 - MECHANICAL DRAWING [120 Ø PP A B C D ( F G + 12.8 NOM K L M N 3 R T 8 /'06%* 0.8 NOM 0.8 NOM /'06%* 8.8 NOM 1RWHV$OOGLPHQVLRQVLQPP %HIRUHVROGHULQJWKHEDOOLVPP$IWHUVROGHULQJLWIODWWHQVVOLJKWO\WRPP LOGIC Devices Incorporated www.logicdevices.com High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module TABLE 3: ABSOLUTE MAXIMUM RATINGS Symbol MIN MAX UNITS NOTES VDD VDD6XSSO\9ROWDJHUHODWLYHWR9ss Parameter -0.4 1.78 V 1 VDDQ VDD6XSSO\9ROWDJHUHODWLYHWR9ssQ -0.4 1.78 V 1 VIN, V287 9ROWDJHRQDQ\SLQUHODWLYHWR9ss -0.4 1.78 V 1 II ,QSXWOHDNDJHFXUUHQW -4 4 μA I95() V5()VXSSO\OHDNDJHFXUUHQW -2 2 μA 2 TAIndustrial 2SHUDWLQJ$PELHQW7HPSHUDWXUH -40 °C 3,4 TA([WHQGHG 2SHUDWLQJ$PELHQW7HPSHUDWXUH -40 °C 3,4 TA0LOWHPS 2SHUDWLQJ$PELHQW&DVH7HPSHUDWXUH °C 3,4 TSTG 6WRUDJH7HPSHUDWXUH °C 3,4 127(6 1. VDD and VDD4PXVWEHZLWKLQP9RIHDFKRWKHUDWDOOWLPHVDQG95()PXVWQRWEHJUHDWHUWKDQ[9DD4:KHQ9DD and VDD4DUHOHVVWKDQ0995()PD\EHdP9 7KHPLQLPXPOLPLWUHTXLUHPHQWLVIRUWHVWLQJSXUSRVHV7KHOHDNDJHFXUUHQWRQWKH95()SLQVKRXOGEHPLQLPDO 0D[RSHUDWLQJDPELHQWWHPSHUDWXUHTALVPHDVXUHGLQWKHFHQWHURIWKHSDFNDJH 'HYLFH)XQFWLRQDOLW\LVQRWJXDUDQWHHGLIWKH'5$0GHYLFHH[FHHGVWKH0D[LPXP7AGXULQJRSHUDWLRQ TABLE 4: INPUT/OUTPUT CAPACITANCE Capacitance Parameter PACKAGE OUTLINE DIMENSIONS Symbol MIN &.DQG&.? CCK 0.8 S) 6LQJOHHQG,2'4'0 C10 1.4 4.4 8.8 S) 2 'LIIHUHQWLDO,2'46'46? C10 1.4 4.4 8.8 S) 3 C,B6KDUHG 0.8 S) ,QSXWV5$6?&$6?:(?&6?&.(5(6(7?$''5%$ MAX (256M) MAX (512M) UNITS NOTES 127(6 1. VDD 9P999DDQ = VDD, V5() = VssI 0+]TA °C, V287 (DC [9DDQ, V287SHDNWRSHDN 9 '0LQSXWLVJURXSHGZLWK,2SLQVUHIOHFWLQJWKHVLJQDOLVJURXSHGZLWK'4DQGWKHUHIRUHPDWFKHGLQORDGLQJ 3. CCCQSLVIRU'46YV'46? 4. CDIO &,2'4[&,2>'46@&,2>'46?@ ([FOXGHV&.&.? &DI_CNTL &,&17/[&&.>&.@&&.>&.?@&17/ 2'7&6?DQG&.( 7. CDI_CMD_ADDR &,&0'B$''5[&&.>&.@&&.>&.?@&0' 5$6?&$6?DQG:(?$''5 >Q@ LOGIC Devices Incorporated www.logicdevices.com High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module TABLE 5: TIMING PARAMETERS FOR IDD MEASUREMENTS - CLOCK UNITS IDD Parameter DDR3-1333 DDR3-1600 DDR3-1866 -15 -12 -11 9-9-9 11-11-11 13-13-13 t&.0,1,DD 1.071 ns CL IDD 10 11 13 CK t5&'0,1,DD 10 11 13 CK W5&0,1,DD 34 39 CK t5$60,1,DD 24 28 32 CK 10 11 13 CK 30 32 33 CK t530,1,DD tFAW [ tRRD IDD [ tRFC LOGIC Devices Incorporated CK 174 208 243 CK www.logicdevices.com 17 High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B LOGIC Devices Incorporated ODT WE\ CAS\ RAS\ Sub-Loop CKE www.logicdevices.com 1 2 3 4 5 6 7 BA [2:0] Cycle Number 0 A [15:11] PRE A [10] 0 1 1 1 1 A [9:7] ACT D D D\ D\ 0 PRE A [6:3] 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 Repeat cycles 1 through 4 until n RAS - 1, truncate if needed 0 1 0 0 0 0 0 0 0 Repeat cycles 1 through 4 until n RC - 1, truncate if needed 0 1 1 0 0 0 0 0 F 0 0 0 0 0 0 0 0 F 0 0 0 0 0 0 0 0 F 1 1 1 0 0 0 0 0 F 1 1 1 0 0 0 0 0 F Repeat cycles n RC +1 through n RC +4 until n RC - 1 + n RAS - 1, truncate if needed 0 1 0 0 0 0 0 0 F Repeat cycles n RC +1 through n RC +4 until 2 x RC - 1, truncate if needed Repeat sub-loop 0, use BA [2:0] = 1 Repeat sub-loop 0, use BA [2:0] = 2 Repeat sub-loop 0, use BA [2:0] = 3 Repeat sub-loop 0, use BA [2:0] = 4 Repeat sub-loop 0, use BA [2:0] = 5 Repeat sub-loop 0, use BA [2:0] = 6 Repeat sub-loop 0, use BA [2:0] = 7 CK, CK\ 18 0 0 0 0 0 0 0 0 0 0 0 0 A [2:0] 0 0 0 1 1 - - - - Data 0 0 1 1 1 1 Command ACT D D D\ D\ CS\ 0 1 2 3 4 n RAS n RC n RC + 1 n RC + 2 n RC + 3 n RC + 4 n RC + n RAS 2 x nRC 4 x n RC 6 x n RC 8 x n RC 10 x n RC 12 x n RC 14 x n RC L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module TABLE 6: IDD0 MEASUREMENT LOOP Static HIGH Toggling High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B Cycle Number Sub-Loop CKE CK, CK\ LOGIC Devices Incorporated www.logicdevices.com 19 2 x n RC 2 x n RC 2 x n RC 2 x n RC 2 x n RC 2 x n RC 2 x n RC Command 1 2 3 4 5 6 7 CS\ 0 1 1 1 1 0 0 ACT D D D\ D\ RD PRE 0 RAS\ PRE 0 1 0 0 0 1 1 0 CAS\ 0 WE\ 1 ODT 0 BA [2:0] RD A [15:11] 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 Repeat cycles 1 through 4 until nRCD - 1, truncate if needed 0 1 0 0 0 0 0 0 Repeat cycles 1 through 4 until nRAS - 1, truncate if needed 1 0 0 0 0 0 0 0 Repeat cycles 1 through 4 until nRC - 1, truncate if needed 1 1 0 0 0 0 0 F 0 0 0 0 0 0 0 F 0 0 0 0 0 0 0 F 1 1 0 0 0 0 0 F 1 1 0 0 0 0 0 F Repeat cycles nRC + 1 through nRC + 4 until nRC + nRCD - 1, truncate if needed 0 1 0 0 0 0 0 F Repeat cycles nRC + 1 through nRC + 4 until nRC + nRAS - 1, truncate if needed 1 0 0 0 0 0 0 F Repeat cycle nRC + 1 through nRC + 4 until 2 x nRC - 1, truncate if needed Repeat sub-loop 0, use BA [2:0] = 1 Repeat sub-loop 0, use BA [2:0] = 2 Repeat sub-loop 0, use BA [2:0] = 3 Repeat sub-loop 0, use BA [2:0] = 4 Repeat sub-loop 0, use BA [2:0] = 5 Repeat sub-loop 0, use BA [2:0] = 6 Repeat sub-loop 0, use BA [2:0] = 7 A [10] 1 0 0 1 1 A [9:7] 0 0 0 1 1 A [6:3] 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A [2:0] ACT D D D\ D\ - 00110011 - - 00000000 - Data 0 1 2 3 4 n RCD n RAS n RC n RC +1 nRC +2 n RC +3 n RC +4 n RC + nRCD n RC + nRAS L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module TABLE 7: IDD1 MEASUREMENT LOOP Static HIGH Toggling High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module TABLE 8: IDD MEASUREMENT CONDITIONS FOR POWER-DOWN CURRENTS IDD2P0 IDD2P1 IDD2Q Precharge Power- Precharge PowerPrecharge Quiet Down Current Down Current Standby Current (Slow Exit) (Fast Exit) Name 7LPLQJ3DWWHUQ &.( ([WHUQDO&ORFN IDD3P Active PowerDown Current QD QD QD QD LOW LOW +,*+ LOW Toggling Toggling Toggling Toggling tCK t&.0,1,DD t&.0,1,DD t&.0,1,DD t&.0,1,DD tRC Q?D Q?D Q?D Q?D tRAS Q?D Q?D Q?D Q?D tRCD Q?D Q?D Q?D Q?D tRRD Q?D Q?D Q?D Q?D tRC Q?D Q?D Q?D Q?D CL Q?D Q?D Q?D Q?D AL Q?D Q?D Q?D Q?D &6? +,*+ +,*+ +,*+ +,*+ &RPPDQG,QSXWV LOW LOW LOW LOW 52:&2/801$GGU LOW LOW LOW LOW Bank Address LOW LOW LOW LOW DM LOW LOW LOW LOW 'DWD,2 Mid-level Mid-level Mid-level Mid-level 2XWSXW%XIIHU'4'46 (QDEOHG (QDEOHG (QDEOHG (QDEOHG (QDEOHG2)) (QDEOHG2)) (QDEOHG2)) (QDEOHG2)) 8 8 8 8 ODT %XUVW/HQJWK None None None None ,'/(%DQNV All All All All 6SHFLDO1RWHV Q?D Q?D Q?D Q?D $&7,9(%DQNV LOGIC Devices Incorporated www.logicdevices.com 20 High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module A [15:11] BA [2:0] ODT WE\ CAS\ RAS\ CKE CK, CK\ www.logicdevices.com 0 0 0 0 0 0 F F 0 1 2 3 4 5 6 7 D D D\ D\ Cycle Number Sub-Loop LOGIC Devices Incorporated 0 0 0 0 Command 0 1 2 3 4-7 8-11 12-15 16-19 20-23 24-27 28-31 CS\ 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Repeat sub-loop 0, use BA [2:0] = 1 Repeat sub-loop 0, use BA [2:0] = 2 Repeat sub-loop 0, use BA [2:0] = 3 Repeat sub-loop 0, use BA [2:0] = 4 Repeat sub-loop 0, use BA [2:0] = 5 Repeat sub-loop 0, use BA [2:0] = 6 Repeat sub-loop 0, use BA [2:0] = 7 A [10] 0 0 1 1 A [9:7] 0 0 1 1 A [6:3] 0 0 1 1 A [2:0] 1 1 1 1 Data - TABLE 9: IDD2N / IDD3N MEASUREMENT LOOP Static HIGH Toggling 21 High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B LOGIC Devices Incorporated www.logicdevices.com D D D\ D\ A [15:11] BA [2:0] ODT WE\ CAS\ RAS\ CS\ Sub-Loop CKE 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 Repeat sub-loop 0, use BA [2:0] = 1; ODT = 0 Repeat sub-loop 0, use BA [2:0] = 2; ODT = 1 Repeat sub-loop 0, use BA [2:0] = 3; ODT = 1 Repeat sub-loop 0, use BA [2:0] = 4; ODT = 0 Repeat sub-loop 0, use BA [2:0] = 5; ODT = 0 Repeat sub-loop 0, use BA [2:0] = 6; ODT = 1 Repeat sub-loop 0, use BA [2:0] = 7; ODT = 1 A [10] 0 0 1 1 0 0 0 0 A [9:7] 0 0 1 1 0 0 F F A [6:3] 1 1 1 1 0 0 0 0 A [2:0] 1 2 3 4 5 6 7 Command Cycle Number 0 1 2 3 4-7 8-11 12-15 16-19 20-23 24-27 28-31 - Data 0 L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module TABLE 10: IDD2NT MEASUREMENT LOOP Static HIGH CK, CK\ Toggling 22 High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B LOGIC Devices Incorporated www.logicdevices.com BA [2:0] ODT WE\ CAS\ RAS\ CS\ Sub-Loop CKE CK, CK\ 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Repeat sub-loop 0, use BA [2:0] = 1 Repeat sub-loop 0, use BA [2:0] = 2 Repeat sub-loop 0, use BA [2:0] = 3 Repeat sub-loop 0, use BA [2:0] = 4 Repeat sub-loop 0, use BA [2:0] = 5 Repeat sub-loop 0, use BA [2:0] = 6 Repeat sub-loop 0, use BA [2:0] = 7 A [15:11] 1 0 1 1 1 0 1 1 A [10] 0 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 A [9:7] 1 0 1 1 1 0 1 1 0 0 0 0 F F F F A [6:3] 0 1 1 1 0 1 1 1 0 0 0 0 0 0 0 0 A [2:0] 1 2 3 4 5 6 7 RD D D\ D\ RD D D\ D\ 00000000 00110011 - Data 0 Command Cycle Number 0 1 2 3 4 5 6 7 8-15 16-23 24-31 32-39 40-47 48-55 56-63 L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module TABLE 11: IDD4R MEASUREMENT LOOP Static HIGH Toggling 23 High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B LOGIC Devices Incorporated www.logicdevices.com BA [2:0] ODT WE\ CAS\ RAS\ CS\ Sub-Loop CKE CK, CK\ 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 Repeat sub-loop 0, use BA [2:0] = 1 Repeat sub-loop 0, use BA [2:0] = 2 Repeat sub-loop 0, use BA [2:0] = 3 Repeat sub-loop 0, use BA [2:0] = 4 Repeat sub-loop 0, use BA [2:0] = 5 Repeat sub-loop 0, use BA [2:0] = 6 Repeat sub-loop 0, use BA [2:0] = 7 A [15:11] 0 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 A [10] 0 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 A [9:7] 1 0 1 1 1 0 1 1 0 0 0 0 F F F F A [6:3] 0 1 1 1 0 1 1 1 0 0 0 0 0 0 0 0 A [2:0] 1 2 3 4 5 6 7 WR D D\ D\ WR D D\ D\ 00000000 00110011 - Data 0 Command Cycle Number 0 1 2 3 4 5 6 7 8-15 16-23 24-31 32-39 40-47 48-55 56-63 L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module TABLE 12: IDD4W MEASUREMENT LOOP Stac HIGH Toggling 24 High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B LOGIC Devices Incorporated www.logicdevices.com REF D D D\ D\ Cycle Number 0 1 2 3 4 5-8 9-12 13-16 17-20 21-24 25-28 29-32 33-n RFC-1 Sub-Loop CKE CK, CK\ 1b 1c 1d 1e 1f 1g 1h 2 1a Command 0 A [9:7] A [10] A [15:11] BA [2:0] ODT WE\ CAS\ Repeat sub-loop 1a, use BA [2:0] = 1 Repeat sub-loop 1a, use BA [2:0] = 2 Repeat sub-loop 1a, use BA [2:0] = 3 Repeat sub-loop 1a, use BA [2:0] = 4 Repeat sub-loop 1a, use BA [2:0] = 5 Repeat sub-loop 1a, use BA [2:0] = 6 Repeat sub-loop 1a, use BA [2:0] = 7 Repeat sub-loop 1a through 1h until n RFC - 1, truncate if needed L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module TABLE 13: IDD5B MEASUREMENT LOOP Data A [2:0] A [6:3] RAS\ CS\ Static HIGH Toggling High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module PACKAGE OUTLINE DIMENSIONS TABLE 14: IDD MEASUREMENT LOOP Industrial Range TA &WR& ([WHQGHGRU0LO7HPSHUDWXUH5DQJH TA &WR&RU&WR& IDD6: Self Refresh Current IDD6E/M: Self Refresh Current IDD8: Reset &.( LOW LOW Mid-level ([WHUQDO&ORFN 2II&.DQG&.? /2: 2II&.DQG&.? /2: Mid-level tCK Q?D Q?D Q?D IDD Test tRC Q?D Q?D Q?D tRAS Q?D Q?D Q?D tRCD Q?D Q?D Q?D tRRD Q?D Q?D Q?D tRC Q?D Q?D Q?D CL Q?D Q?D Q?D AL Q?D Q?D Q?D &6? Mid-level Mid-level Mid-level &RPPDQG,QSXWV Mid-level Mid-level Mid-level 52:&2/081DGGUHVVHV Mid-level Mid-level Mid-level BANK addresses Mid-level Mid-level Mid-level 'DWD,2 Mid-level Mid-level Mid-level 2XWSXWEXIIHU'4'46 (QDEOHG (QDEOHG Mid-level ODT (QDEOHG0LGOHYHO (QDEOHG0LGOHYHO Mid-level %XUVW/HQJWK Q?D Q?D Q?D $FWLYH%$1.6 Q?D Q?D None ,'/(%$1.6 Q?D Q?D All SRT 'LVDEOHGQRUPDO (QDEOHGH[WHQGHG Q?D ASR Disabled Disabled Q?D LOGIC Devices Incorporated www.logicdevices.com High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B LOGIC Devices Incorporated Sub-Loop CKE www.logicdevices.com CK, CK\ 27 19 15 16 17 18 14 12 13 11 10 9 5 6 7 8 Cycle Number 0 0 1 ACT RDA D D 1 1 0 0 1 ACT RDA D D 1 D RAS\ 1 0 0 0 1 0 0 1 0 0 0 CAS\ D WE\ 0 1 0 ODT 4 0 0 1 ACT RDA D BA [2:0] 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 Repeat cycle 2 until n RRD - 1 1 1 0 1 0 0 0 0 1 0 1 0 1 0 0 0 0 1 0 0 0 Repeat cycle n RRD + 2 until 2 x n RRD - 1 Repeat sub-loop 0, use BA[2:0] = 2 Repeat sub-loop 0, use BA[2:0] = 3 0 0 0 3 0 0 0 Repeat cycle 4 x n RRD until n FAW - 1, if needed Repeat sub-loop 0, use BA[2:0] = 4 Repeat sub-loop 1, use BA[2:0] = 5 Repeat sub-loop 0, use BA[2:0] = 6 Repeat sub-loop 1, use BA[2:0] = 7 0 0 0 7 0 0 0 Repeat cycle n FAW + 4 x n RRD until 2 x n FAW - 1, if needed 1 1 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 Repeat cycle 2 x n FAW + 2 until 2 x n FAW + n RRD - 1 1 1 0 1 0 0 0 0 1 0 1 0 1 0 0 0 0 1 0 0 0 Repeat cycle 2 x n FAW + n RRD + 2 until 2 x n FAW + 2 x n RRD - 1 Repeat sub-loop 10, use BA[2:0] = 2 Repeat sub-loop 11, use BA[2:0] = 3 0 0 0 3 0 0 0 Repeat cycle 2 x n FAW + 4 x n RRD until 3 x n FAW - 1, if needed Repeat sub-loop 10, use BA[2:0] = 4 Repeat sub-loop 11, use BA[2:0] = 5 Repeat sub-loop 10, use BA[2:0] = 6 Repeat sub-loop 11, use BA[2:0] = 7 0 0 0 7 0 0 0 Repeat cycle 3 x n FAW + 4 x n RRD until 4 x n FAW - 1, if needed A [15:11] 1 1 0 A [10] 1 0 0 A [9:7] 0 1 0 0 0 0 0 0 F F F F F F F F 0 0 0 A [6:3] 2 3 0 0 1 Command ACT RDA D 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 A [2:0] 1 CS\ 0 1 2 3 n RRD n RRD + 1 n RRD + 2 n RRD + 3 2 x n RRD 3x n RRD 4 x n RRD 4 x n RRD + 1 n FAW n FAW + n RRD n FAW + 2xn RRD n FAW + 3xn RRD n FAW + 4xn RRD n FAW + 4xn RRD+1 2 x n FAW 2 x n FAW + 1 2 x n FAW + 2 2 x n FAW + 3 2 x n FAW + n RRD 2 x n FAW + n RRD+1 2 x n FAW + n RRD+2 2 x n FAW + n RRD+3 2 x nFAW + 2x n RRD 2 x n FAW + 3x n RRD 2 x n FAW + 4x n RRD 2 x n FAW+4x n RRD+1 3 x nFAW 3 x nFAW + nRRD 3 x nFAW + 2x nRRD 3 x nFAW + 3x nRRD 3 x nFAW + 4x nRRD 3 x nFAW + 4x nRRD +1 - 00000000 - 00110011 - - - 00110011 - 00000000 - Data 0 L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module TABLE 15: IDD7 MEASUREMENT LOOP Static HIGH Toggling High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module TABLE 16A: IDD MAXIMUM LIMITS (256M) Speed Bin IDD DDR3-1333 DDR3-1600 DDR3-1866 UNITS IDD0 IDD1 IDD3 IDD3 IDD2Q IDD2N IDD3 IDD3N IDD4R IDD4W IDD% IDD IDD7 IDD8 220 40 88 100 480 400 420 44 IDD3P$ IDD3P$ IDD3P$ 180 230 40 74 94 110 440 44 IDD3P$ IDD3P$ IDD3P$ 200 240 40 84 104 120 44 IDD3P$ IDD3P$ IDD3P$ P$ P$ P$ P$ P$ P$ P$ P$ P$ P$ P$ P$ P$ P$ P$ P$ IND (;7 0,/7(03 127(6TA = 0°C to d°&657DQG$65DUHGLVDEOHGHQDEOLQJ$65FRXOGLQFUHDVH,DD[E\XSWRDQDGGLWLRQDOP$ TABLE 16B: IDD MAXIMUM LIMITS (512M) Speed Bin IDD DDR3-1333 DDR3-1600 DDR3-1866 UNITS IDD0 IDD1 IDD3 IDD3 IDD2Q IDD2N IDD3 IDD3N IDD4R IDD4W IDD% IDD IDD7 IDD8 320 440 80 128 200 232 292 800 840 88 1040 IDD3P$ IDD3P$ IDD3P$ 80 148 188 220 308 1020 900 880 88 1140 IDD3P$ IDD3P$ IDD3P$ 400 480 80 208 240 272 328 1200 1200 920 88 1280 IDD3P$ IDD3P$ IDD3P$ P$ P$ P$ P$ P$ P$ P$ P$ P$ P$ P$ P$ P$ P$ P$ P$ IND (;7 0,/7(03 127(6TA = 0°C to d°&657DQG$65DUHGLVDEOHGHQDEOLQJ$65FRXOGLQFUHDVH,DD[E\XSWRDQDGGLWLRQDOP$ LOGIC Devices Incorporated www.logicdevices.com 28 High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module TABLE 17: DC ELECTRICAL CHARACTERISTICS AND OPERATINGPC ONDITIONS ACKAGE OUTLINE DIMENSIONS $OO9ROWDJHVDUHUHIHUHQFHGWR9VV Parameter/Condition Supply Voltage I/O Supply Voltage Input Leakage Current: Symbol MIN TYP MAX UNITS NOTES VDD V 1,2 VDDQ V 1,2 II -4 - 4 μA I95() -4 - 4 μA $Q\LQSXW9dVINdVDD, V5()SLQ9dVINd1.1V $OORWKHUSLQVQRWXQGHUWHVW 9 VREF Supply Leakage Current: 3,4 V5()'4 = VDDRU95()&$ = VDD $OORWKHUSLQVQRWXQGHUWHVW 9 127(6 1. VDD and VDD4PXVWWUDFNRQHDQRWKHU9DD4PXVWEHOHVVWKDQRUHTXDO 3. V5()VHH7DEOH 4. 7KH PLQLPXP OLPLW UHTXLUHPHQW LV IRU WHVWLQJ SXUSRVHV 7KH OHDNDJH to VDD, Vss = VssQ. 2. VDD and VDD4PD\LQFOXGH$&QRLVHRIP9N+]WR0+]LQ FXUUHQWRQWKH95()SLQVKRXOGEHPLQLPDO DGGLWLRQWRWKH'&+]WRN+]VSHFLILFDWLRQV9DD and VDD4PXVW EHDWWKHVDPHOHYHOIRUYDOLG$&WLPLQJSDUDPHWHUV TABLE 18: DC ELECTRICAL CHARACTERISTICS AND INPUT CONDITIONS PACKAGE OUTLINE DIMENSIONS $OO9ROWDJHVDUHUHIHUHQFHGWR9VV Parameter/Condition VIN low; DC/commands/address busses VIN high; DC/commands/address busses Symbol MIN TYP VIL Vss QD V,+ See Table 17 MAX UNITS See Table 17 V QD VDD V NOTES Input reference voltage command/address bus V5()&$'& 0.49 x VDD [9DD [9DD V 1,2 I/O reference voltage DQ bus V5()'4'& 0.49 x VDD [9DD [9DD V 2,3 I/O reference voltage DQ bus in SELF REFRESH V5()'465 Vss [9DD VDD V 4 VTT - [9DDQ - V Command/address termination voltage V\VWHPOHYHOQRW GLUHFW'5$0LQSXW 127(6 1. V5()&$'&LVH[SHFWHGWREHDSSUR[LPDWHO\[9DDDQGWRWUDFNYDUL- PRQ PRGH RQ 95()'4 PD\ QRW H[FHHG [ 9DD DURXQG WKH DWLRQVLQWKH'&OHYHO([WHUQDOO\JHQHUDWHGSHDNQRLVHQRQFRPPRQ 95()'4'&YDOXH3HDNWRSHDN$&QRLVHRQ95()'4VKRXOGQRW PRGHRQ95()&$PD\QRWH[FHHG[9DDDURXQGWKH95()&$'& H[FHHGRI95()'4'& YDOXH3HDNWRSHDN$&QRLVHRQ95()&$VKRXOGQRWH[FHHGRI V5()&$'& 4. V5()'4'& PD\ WUDQVLWLRQ WR 95()'465 DQG EDFN WR 95()'4'& ZKHQ LQ 6(/) ]5()5(6+ ZLWKLQ UHVWULFWLRQV RXWOLQHG LQ WKH 6(/) 2. '&YDOXHVDUHGHWHUPLQHGWREHOHVVWKDQ0+]LQIUHTXHQF\'5$0 5()5(6+VHFWLRQ PXVW PHHW VSHFLILFDWLRQV LI WKH '5$0 LQGXFHV DGGLWLRQDO $& QRLVH JUHDWHUWKDQ0+]LQIUHTXHQF\ VTT LV QRW DSSOLHG GLUHFWO\ WR WKH GHYLFH 9TT LV D V\VWHP VXSSO\ IRU VLJQDOWHUPLQDWLRQUHVLVWRUV0,1DQG0$;YDOXHVDUHV\VWHPGHSHQ- 3. V5()'4'& LV H[SHFWHG WR EH DSSUR[LPDWHO\ [ 9DD DQG WR WUDFN dent. YDULDWLRQVLQWKH'&OHYHO([WHUQDOO\JHQHUDWHGSHDNQRLVHQRQFRP- LOGIC Devices Incorporated www.logicdevices.com 29 High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module TABLE 19: INPUT SWITCHING CONDITIONS PACKAGE OUTLINE DIMENSIONS Symbol DDR3-1333 DDR3-1600 V,+$&0,1 Input high AC voltage: Logic 1 V,+$&0,1 Input high DC voltage: Logic 1 V,+'&0,1 Input high DC voltage: Logic 0 Input high AC voltage: Logic 0 Input high AC voltage: Logic 0 Parameter/Condition DDR3-1866 UNITS &RPPDQGDQG$GGUHVV Input high AC voltage: Logic 1 - P9 - P9 P9 V,/'&0$; -100 -100 P9 V,/$&0$; - P9 V,/$&0$; - P9 DQ and DM Input high AC voltage: Logic 1 V,+$&0,1 - - P9 Input high AC voltage: Logic 1 V,+$&0,1 - P9 Input high DC voltage: Logic 1 V,+'&0,1 P9 Input high DC voltage: Logic 0 V,/'&0$; -100 -100 P9 Input high AC voltage: Logic 0 V,/$&0$; - P9 Input high AC voltage: Logic 0 V,/$&0$; - - P9 127(6 1. $OOYROWDJHVDUHUHIHUHQFHGWR95(), V5() is V5()&$IRUFRQWUROFRP- 3. PDQGDQGDGGUHVV$OOVOHZUDWHVDQGVHWXSKROGWLPHVDUHVSHFLILHGDW ,QSXWKROGWLPLQJSDUDPHWHUVt,+DQG t'+DUHUHIHUHQFHGDW9IL'& V,+'&QRW95()$& WKH'5$0EDOO95() is V5()'4IRU'4DQG'0LQSXWV 4. 2. ,QSXWVHWXSWLPLQJSDUDPHWHUVtIS and t'6DUHUHIHUHQFHGDW9IL$& 6LQJOHHQGHG LQSXW VOHZ UDWH 9QV PD[LPXP LQSXW YROWDJH VZLQJ XQGHUWHVWLVP9SHDNWRSHDN V,+$&QRW95()'& LOGIC Devices Incorporated www.logicdevices.com 30 High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module OPERATING CONDITIONS FIGURE 6 - INPUT SIGNAL VIL and VIH levels with ringback 1.90V VDDQ + 0.4V narrow pulse width 1.50V VDDQ Minimum VIL and VIH levels VIH (AC) 0.925V 0.925V VIH (AC) VIH (DC) VIH (DC) 0.850V 0.850V 0.780V 0.765V 0.750V 0.735V 0.720V 0.780V 0.765V 0.750V 0.735V 0.720V VREF + AC noise VREF + DC error VREF + DC error VREF + AC noise 0.650V VIL (DQ) 0.575V VIL (AC) 0.650V VIL (DC) 0.575V VIL (AC) VSS 0.0V VSS 0.4V narrow pulse width -0.40V Notes: LOGIC Devices Incorporated www.logicdevices.com 1. Numbers in diagrams reflect nominal values. 31 High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module AC OVERSHOOT/UNDERSHOOT SPECIFICATION TABLE 20: CONTROL AND ADDRESS PINS PACKAGE OUTLINE DIMENSIONS Parameter DDR3-1333 DDR3-1600 DDR3-1866 0.4V 0.4V 0.4V 0.4V 0.4V 0.4V Maximum overshoot area above Vcc VHH)LJXUH 0.4Vns 0.33Vns 0.28Vns Maximum undershoot area below Vss VHH)LJXUH 0.4Vns 0.33Vns 0.28Vns Maximum peak amplitude allowed for overshoot area VHH)LJXUH Maximum peak amplitude allowed for undershoot area VHH)LJXUH TABLE 21: CLOCK, DATA, STROBE, AND MASK PINS PACKAGE OUTLINE DIMENSIONS Parameter DDR3-1333 Maximum peak amplitude allowed for overshoot area DDR3-1600 DDR3-1866 0.4V 0.4V 0.4V 0.4V 0.4V 0.4V 9QV 0.13Vns 0.11Vns 9QV 0.13Vns 0.11Vns VHH)LJXUH Maximum peak amplitude allowed for undershoot area VHH)LJXUH Maximum overshoot area above Vcc/ VccQ VHH)LJXUH Maximum undershoot area below Vss/ VssQ VHH)LJXUH FIGURE 7 & 8: OVERSHOOT/UNDERSHOOT SPECIFICATIONS Maximum amplitude Volts (V) Figure 7: Overshoot Overshoot area VDD/VDDQ Time (ns) Time (ns) Figure 8: Undershoot VSS/VSSQ Volts (V) Maximum amplitude LOGIC Devices Incorporated www.logicdevices.com 32 Undershoot area High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module TABLE 22: DIFFERENTIAL INPUT OPERATING CONDITIONS (CKXP, ACKAGE CKX\, DQS X, AND DQSX\) OUTLINE DIMENSIONS Parameter/Condition Symbol MIN MAX UNITS NOTES Differential input voltage, logic high - slew V,+',))$&VOHZ QD P9 4 Differential input voltage, logic low - slew VIL ',))$&VOHZ QD -200 P9 4 Differential input voltage, logic high V,+',))$& 2x(V,+$&95() VDD9DDQ P9 Differential input voltage, logic low VIL ',))$& Vss9ssQ 2x(V5()-VIL$& P9 V,; V5()'& V5()'& P9 7 V,; V5()'& V5()'& P9 7,8 V6+( VDD49,+$& VDDQ P9 VDD9,+AC VDD VssQ VDD49IL$& P9 Vss VDD-VIL$& Differential input crossing voltage relative to VDD/2 for DQS, DQS\, CK, CK\ Differential input crossing voltage relative to VDD/2 for CK, CK\ Single-ended high level for strobes Single-ended high level for CK, CK\ Single-ended low level for strobes V6(/ Single-ended low level for CK, CK\ 127(6 1. &ORFN LV UHIHUHQFHG WR 9DD' DQG 9VV 'DWD VWUREH LV UHIHUHQFHG WR VDDQ and VssQ. 0,1OLPLWLVUHODWLYHWRVLQJOHHQGHGVLJQDOVWKHXQGHUVKRRWVSHFLILFDWLRQVDUHDSSOLFDEOH 2. 5HIHUHQFHLV95()&$'&IRUFORFNDQGIRU95()'4'&IRUVWUREH 7. 7KHW\SLFDOYDOXHRI9,;$&LVH[SHFWHGWREHDERXW[9DDRIWKH 3. 'LIIHUHQWLDOLQSXWVOHZUDWH 9PV 4. 'HILQHVVOHZUDWHUHIHUHQFHSRLQWVUHODWLYHWRLQSXWFURVVLQJYROWDJHV 0$; OLPLW LV UHODWLYH WR VLQJOHHQGHG VLJQDOV WKH RYHUVKRRW VSHFLILFD- V,;H[WHQGHGUDQJHLVRQO\DOORZHGZKHQWKHIROORZLQJFRQGLWLRQVDUH WLRQVDUHDSSOLFDEOH PHW7KHVLQJOHHQGHGLQSXWVLJQDOVDUHPRQRWRQLFKDYHWKHVLQJOH WUDQVPLWWLQJGHYLFHDQG9,;$&LVH[SHFWHGWRWUDFNYDULDWLRQVLQ9DD. V,;$& LQGLFDWHV WKH YROWDJH DW ZKLFK GLIIHUHQWLDO LQSXW VLJQDOV PXVW FURVV 8. 7KH9,;H[WHQGHGUDQJHP9LVDOORZHGRQO\IRUWKHFORFNDQGWKLV ended swing V6(/, V6(+ of at least VDDP9DQGWKHGLIIHUHQWLDO VOHZUDWHRI&.&.?LVJUHDWHUWKDQ9QV LOGIC Devices Incorporated www.logicdevices.com 33 High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module OVERSHOOT/UNDERSHOOT SPECIFICATIONS FIGURE 9 - VIX FOR DIFFERENTIAL SIGNALS VDD, VDDQ VDD, VDDQ CK#, DQS# CK#, DQS# VIX X VIX VDD/2, VDDQ/2 X VDD/2, VDDQ/2 X VIX VIX X CK, DQS CK, DQS VSS, VSSQ VSS, VSSQ FIGURE 10 - SINGLE-ENDED REQUIREMENTS FOR DIFFERENTIAL SIGNALS V DD or VDD Q VSEH (MIN) V DD /2 or VDD Q/2 VSEH CK or DQS VSEL (MAX) VSEL VSS or VSS Q LOGIC Devices Incorporated www.logicdevices.com 34 High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module OVERSHOOT/UNDERSHOOT SPECIFICATIONS FIGURE 11 - DEFINITION OF DIFFERENTIAL AC-SWING AND tDVAC t DVAC V IHDIFF ( A C) MIN V IHDIFF (MIN) V IHDIFF ( DC) MIN CK - CK# DQ S - DQS # 0.0 V ILDIFF ( DC) MAX V ILDIFF (MAX) V ILDIFF ( A C) MAX t DVAC half cycle TABLE 23: DIFFERENTIAL INPUT OPERATING CONDITIONS (tDVAC) FOR CK X, CKD X\, DQSX, AND DQSX\ PACKAGE OUTLINE IMENSIONS Below VIL$& tDVAC (ps) at [VIHDIFF(AC) to VILDiff(AC)] LOGIC Devices Incorporated Slew Rate (V/ns) 350mV 300mV -4.0 4.0 170 3.0 2.0 38 1.9 34 1.6 29 1.4 22 1.2 13 1.0 0 <1.0 0 www.logicdevices.com High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module SLEW RATE DEFINITIONS FOR SINGLE-ENDED INPUT SIGNALS +ROGt,+DQGt'+QRPLQDOVOHZUDWHIRUDULVLQJVLJQDOLVGHILQHGDVWKHVOHZ UDWHEHWZHHQWKHODVWFURVVLQJRI9IL'&0$;DQGWKHILUVWFURVVLQJRI95(). +ROGt,+DQGt'+QRPLQDOVOHZUDWHIRUDIDOOLQJVLJQDOLVGHILQHGDVWKHVOHZ UDWHEHWZHHQWKHODVWFURVVLQJRI9,+'&0,1DQGWKHILUVWFURVVLQJRI95(). 6HWXS tIS and t'6 QRPLQDO VOHZ UDWH IRU D ULVLQJ VLJQDO LV GHILQHG DV WKH VOHZUDWHEHWZHHQWKHODVWFURVVLQJRI95()DQGWKHILUVWFURVVLQJ9,+$& 0,1 6HWXS tIS and t'6 QRPLQDO VOHZ UDWH IRU D IDOOLQJ VLJQDO LV GHILQHG DVWKHVOHZUDWHEHWZHHQWKHODVWFURVVLQJRI95()DQWKHILUVWFURVVLQJRI VIL$&0$; TABLE 24: SINGLE-ENDED INPUT SLEW RATE Measured Input Slew Rate (Linear Signals) Input PACKAGE OUTLINE DIMENSIONS Edge From To Rising V5() V,+$&0,1 Falling V5() VIL$&0$; Rising VIL'&0D[ V5() Setup Calculation V,+$&0,195() V5()VIL$&0$; 'TFS V5()VIL'&0$; '7)+ Hold Falling V,+'&0,1 V5() V,+'&0,195() '756+ LOGIC Devices Incorporated www.logicdevices.com High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module SLEW RATE DEFINITIONS FOR SINGLE-ENDED INPUT SIGNALS FIGURE 12 - NOMINAL SLEW RATE DEFINITION FOR SINGLE-ENDED INPUT SIGNALS ΔTRS Setup Single-ended input voltage (DQ, CMD, ADDR) VIH(AC) MIN VIH(DC) MIN VREFDQ or VREFCA VIL(DC) MAX VIL(AC) MAX ΔTFS ΔTRH Hold Single-ended input voltage (DQ, CMD, ADDR) VIH(AC) MIN VIH(DC) MIN VREFDQ or VREFCA VIL(DC) MAX VIL(AC) MAX ΔTFH LOGIC Devices Incorporated www.logicdevices.com 37 High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module SLEW RATE DEFINITIONS FOR DIFFERENTIAL INPUT SIGNALS ,QSXWVOHZUDWHIRUGLIIHUHQWLDOVLJQDOV&.[&.[?8'46[8'46[?/'46[DQG/'46[?DUHGHILQHGDQGPHDVXUHGDVVKRZQLQ7DEOH7KHQRPLQDOVOHZ UDWHIRUDULVLQJVLJQDOLVGHILQHGDVWKHVOHZUDWHEHWZHHQ9IL',))0$;DQG9,+',))0,17KHQRPLQDOVOHZUDWHIRUDIDOOLQJVLJQDOLVGHILQHGDVWKHVOHZ rate between V,+',))0,1DQG9IL',))0$; TABLE 25: DIFFERENTIAL INPUT SLEW RATE DEFINITION Measured Input Slew Rate (Linear Signals) Input Edge PACKAGE OUTLINE DIMENSIONS From Rising V5() To Calculation V,+',))0,1- VIL',))0$; V,+$&0,1 '75',)) CK and DQS Reference V,+',))0,1 VIL',))0$; Falling V5() VIL($&0$; '7)',)) FIGURE 13 - NOMINAL DIFFERENTIAL INPUT SLEW RATE DEFINITION FOR DQS, DQS# AND CK, CK# Differential input voltage (DQS, DQS#; CK, CK#) ΔTR DIFF VIH(DIFF) MIN 0 VIL(DIFF) MAX ΔTFDIFF LOGIC Devices Incorporated www.logicdevices.com 38 High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module ODT CHARACTERISTICS FIGURE 14 - ODT LEVELS AND I-V CHARACTERISTICS Chip in termination mode 2'7uV HIIHFWLYH UHVLVWDQFH 5TT LV GHILQHG E\ 05> DQG @ 2'7 LV DSSOLHGWRWKH'4[8'0[/'0[8'46[8'46[?/'46[DQG/'46[? EDOOV7KH2'7WDUJHWYDOXHVDUHOLVWHGLQ7DEOH ODT VDD Q IPU IOUT = IPD - IPU To other circuitry such as RCV, . . . RTTPU DQ IOUT R TTPD VOUT IPD VSSQ TABLE 26: ON-DIE TERMINATION DC ELECTRICAL CHARACTERISTICS Parameter/Condition Symbol RTTHIIHFWLYHLPSHGDQFH RTTB()) 'HYLDWLRQRI90ZLWKUHVSHFWWR9DD4 'VM MIN TYP MAX UNITS NOTES 1, 2, 3, 4 1, 2, 4 See Table 27 127(6 1. 7ROHUDQFH OLPLWV DUH DSSOLFDEOH DIWHU D SURSHU =4 FDOLEUDWLRQ KDV EHHQ 3. 0HDVXUHYROWDJH90DWWKHWHVWHGSLQZLWKQRORDG SHUIRUPHGDWDVWDEOHWHPSHUDWXUHDQGYROWDJH9DDQ=VDD9VV49VV 5HIHUWRv2'76HQVLWLYLW\wRQSDJHLIHLWKHUWKHWHPSHUDWXUHRUYROWDJH 'VM = FKDQJHVDIWHUFDOLEUDWLRQ 2. 2 x VM -1 x 100 VDDQ 0HDVXUHPHQWGHILQLWLRQIRU5TT$SSO\9,+$&WRDSLQXQGHUWHVWDQG PHDVXUHWKHFXUUHQW,>9,+$&@WKHQDSSO\9IL$&WRSLQXQGHUWHVWDQG 4. )RU H[WHQGHG 0,/WHPS GHYLFHV WKH PLQLPXP YDOXHV DUH GHUDWHG E\ ZKHQWKHGHYLFHLVEHWZHHQ&DQG&TA PHDVXUHFXUUHQW,>9IL$&@ VIL$&9IL$& RTT = LOGIC Devices Incorporated ,>9,+$&,9IL$&@ www.logicdevices.com 39 High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module TABLE 27: RTT EFFECTIVE IMPEDANCES MR1 [9,6,2] RTT PACKAGE OUTLINE DIMENSIONS Resistor RTT1203'240 0, 1, 0 120: RTT12038240 120: RTT3'120 0, 0, 1 : RTT38240 : RTT403'80 0, 1, 1 40: RTT403880 40: RTT303' 1, 0, 1 30: RTT3038 30: RTT203'40 1, 0, 0 20: RTT203840 20: LOGIC Devices Incorporated www.logicdevices.com VOUT MIN TYP MAX UNITS 0.2 x VDDQ 1.0 1.1 5=4 [9DDQ 0.9 1.0 1.1 5=4 0.8 x VDDQ 0.9 1.0 1.4 5=4 0.2 x VDDQ 0.9 1.0 1.4 5=4 [9DDQ 0.9 1.0 1.1 5=4 0.8 x VDDQ 0.9 1.0 1.1 5=4 VIL$&WR9,+$& 0.9 1.0 5=4 0.2 x VDDQ 1.0 1.1 5=4 [9DDQ 0.9 1.0 1.1 5=4 0.8 x VDDQ 0.9 1.0 1.4 5=4 0.2 x VDDQ 0.9 1.0 1.4 5=4 [9DDQ 0.9 1.0 1.1 5=4 0.8 x VDDQ 0.9 1.0 1.1 5=4 VIL$&WR9,+$& 0.9 1.0 5=4 0.2 x VDDQ 1.0 1.1 5=4 [9DDQ 0.9 1.0 1.1 5=4 0.8 x VDDQ 0.9 1.0 1.4 5=4 0.2 x VDDQ 0.9 1.0 1.4 5=4 [9DDQ 0.9 1.0 1.1 5=4 0.8 x VDDQ 0.9 1.0 1.1 5=4 VIL$&WR9,+$& 0.9 1.0 5=4 0.2 x VDDQ 1.0 1.1 5=4 [9DDQ 0.9 1.0 1.1 5=4 0.8 x VDDQ 0.9 1.0 1.4 5=4 0.2 x VDDQ 0.9 1.0 1.4 5=4 [9DDQ 0.9 1.0 1.1 5=4 0.8 x VDDQ 0.9 1.0 1.1 5=4 VIL$&WR9,+$& 0.9 1.0 5=4 0.2 x VDDQ 1.0 1.1 5=4 [9DDQ 0.9 1.0 1.1 5=4 0.8 x VDDQ 0.9 1.0 1.4 5=4 0.2 x VDDQ 0.9 1.0 1.4 5=4 [9DDQ 0.9 1.0 1.1 5=4 0.8 x VDDQ 0.9 1.0 1.1 5=4 VIL$&WR9,+$& 0.9 1.0 5=4 40 High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module ODT SENSITIVITY ,IHLWKHUWKHWHPSHUDWXUHRUYROWDJHFKDQJHVDIWHU,2FDOLEUDWLRQWKHWROHUDQFHOLPLWVOLVWHGLQ7DEOHFDQEHH[SHFWHGWRZLGHQDFFRUGLQJWR7DEOHVDQG TABLE 28: ODT SENSITIVITY DEFINITION Symbol RTT MIN 0.9 - dRTTdT x dRTTdV x [DV] MAX UNITS 5=4 G5TTG7[>'7@G5TTdV x [DV] TABLE 29 - ODT TEMPERATURE & VOLTAGE SENSITIVITY Change MIN MAX UNITS dRTTdT 0 0 dRTTdV 0 0 FIGURE 15 - ODT TIMING REFERENCE LOAD ODT TIMING DEFINITIONS 2'7ORDGLQJGLIIHUVIURPWKDWXVHGLQ$&WLPLQJPHDVXUHPHQWV7ZRSDUDPHWHUVGHILQHZKHQ2'7WXUQVRQRURIIV\QFKURQRXVO\WZRGHILQHZKHQ2'7 WXUQVRQRURII$V\QFKURQRXVO\DQGDQRWKHUGHILQHVZKHQ2'7WXUQVRQRU RIIG\QDPLFDOO\7DEOHRXWOLQHVDQGSURYLGHVGHILQLWLRQDQGPHDVXUHPHQW UHIHUHQFHVHWWLQJVIRUHDFKSDUDPHWHU DUT CK, CK# 2'7 WXUQRQ WLPH EHJLQV ZKHQ WKH RXWSXW OHDYHV +,*+= DQG 2'7 UHVLVWDQFHEHJLQVWRWXUQRQ2'7WXUQRIIWLPHEHJLQVZKHQWKHRXWSXWOHDYHV /2:=DQG2'7UHVLVWDQFHEHJLQVWRWXUQRII VREF DQ, DM DQS, DQS# ZQ VDDQ/2 RTT = 25Ω VTT = VSSQ Timing reference point RZQ = 240Ω VSSQ LOGIC Devices Incorporated www.logicdevices.com 41 High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module ODT TIMING DEFINITIONS TABLE 30: ODT TIMING DEFINITIONS Symbol PACKAGE OUTLINE DIMENSIONS End Point Definition Figure 5LVLQJHGJHRI&.&.?GHILQHGE\WKHHQGSRLQWRI2'7/RQ Begin Point Definition ([WUDSRODWHGSRLQWDW9VV4 )LJXUHRQSDJH tAOF 5LVLQJHGJHRI&.&.?GHILQHGE\WKHHQGSRLQWRI2'7/RII ([WUDSRODWHGSRLQWDW95TT_NORM )LJXUHRQSDJH tAONPD 5LVLQJHGJHRI&.&.?ZLWK2'7ILUVWEHLQJUHJLVWHUHG+,*+ ([WUDSRODWHGSRLQWDW9VV4 )LJXUHRQSDJH 5LVLQJHGJHRI&.&.?ZLWK2'7ILUVWEHLQJUHJLVWHUHG/2: ([WUDSRODWHGSRLQWDW95TT_NOM )LJXUHRQSDJH 5LVLQJHGJHRI&.&.?GHILQHGE\WKHHQGSRLQWRI2'7/&1: ([WUDSRODWHGSRLQWVDW95TT_WR and VRTT_NOM )LJXUHRQSDJH tAON tAOFPD tADC ODTLCWN4, or ODTLCWN8 TABLE 31: REFERENCE SETTINGS FOR ODT TIMING MEASUREMENTS PACKAGE OUTLINE DIMENSIONS Measured Parameter RTT_NORM Setting tAON tAOF tAONPD tAOFPD tADC VSW1 VSW2 5=4: RTT_WR_Setting QD P9 P9 5=4: QD P9 P9 5=4: QD P9 P9 5=4: QD P9 P9 5=4: QD P9 P9 5=4: QD P9 P9 5=4: QD P9 P9 5=4: QD P9 P9 5=4: 5=4: P9 P9 FIGURE 16 - tAON AND tAOF DEFINITIONS t AON t AOF Begin point: Rising edge of CK - CK# defined by the end point of ODTL off Begin point: Rising edge of CK - CK# defined by the end point of ODTL on CK CK VDDQ/2 CK# CK# t AON t AOF End point: Extrapolated point at VRTT_NOM TSW 2 VRTT_NOM TSW 1 TSW 1 TSW 1 VSW 2 DQ, DM DQS, DQS# VSS Q VSW 2 VSW 1 VSW 1 VSS Q End point: Extrapolated point at VSS Q LOGIC Devices Incorporated www.logicdevices.com 42 High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module ODT CHARACTERISTICS FIGURE 17 - tAONPD AND tAOFPD DEFINITION t AONPD t AOFPD Begin point: Rising edge of CK - CK# with ODT first registered HIGH Begin point: Rising edge of CK - CK# with ODT first registered LOW CK CK VDD Q/2 CK# CK# t AONPD t AOFPD End point: Extrapolated point at VRTT_NOM VRTT_NOM TSW 2 TSW 2 TSW 1 TSW 1 VSW 2 VSW 2 DQ, DM DQS, DQS# VSW 1 VSW1 VSS Q VSS Q End point: Extrapolated point at VSS Q FIGURE 18 - tADC DEFINITION Begin point: Rising edge of CK - CK# defined by the end point of ODTLCNW Begin point: Rising edge of CK - CK# defined by the end point of ODTLCNW4 or ODTLCNW8 CK VDDQ/2 CK# t ADC VRTT_NOM DQ, DM DQS, DQS# End point: Extrapolated point at VRTT_NOM t ADC VRTT_NOM TSW 21 TSW 11 VSW 2 TSW 22 TSW 12 VSW 1 VRTT_WR End point: Extrapolated point at VRTT_WR VSS Q LOGIC Devices Incorporated www.logicdevices.com 43 High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module OUTPUT DRIVER IMPEDANCE FIGURE 19 - OUTPUT DRIVER 34 OHM OUTPUT DRIVER IMPEDANCE 7KH:GULYHU05>@ LVWKHGHIDXOWGULYHU8QOHVVRWKHUZLVHVWDWHG DOOWLPLQJVDQGVSHFLILFDWLRQVOLVWHGKHUHLQDSSO\WRWKH:GULYHURQO\,WV LPSHGDQFH 5ON LV GHILQHG E\ WKH YDOXH RI WKH H[WHUQDO UHIHUHQFH UHVLVWRU 5=4DVIROORZV5ON 5=4ZLWKQRPLQDO5=4 :DQGLVDFWXDOO\:7KH:RXWSXWGULYHULPSHGDQFHFKDUDFWHULVWLFVDUHOLVWHG in Table 32. Chip in drive mode Output driver VDDQ IPU To other circuitry such as RCV, . . . RONPU DQ IOUT RONPD IPD VOUT VSSQ TABLE 32: 34: DRIVER IMPEDANCE CHARACTERISTICS MR1[5,1] 0, 1 RON PACKAGE OUTLINE DIMENSIONS RESISTOR VOUT MIN TYP MAX UNITS 9DDQ 1.0 1.1 5=4 1 RON34PD 9DDQ 0.9 1.0 1.1 5=4 1 9DDQ 0.9 1.0 1.4 5=4 1 9DDQ 0.9 1.0 1.4 5=4 1 9DDQ 0.9 1.0 1.1 5=4 1 9DDQ 1.0 1.1 5=4 1 9DDQ -10 QD 10 1, 2 34.3: RON34PU Pull-Up/Pull-Down mismatch (MMPUPD) NOTES 127(6 1. 7ROHUDQFHOLPLWVDUHDSSOLFDEOHDIWHUSURSHU=4FDOLEUDWLRQKDVEHHQSHUIRUPHGDWDVWDEOHWHPSHUDWXUHDQGYROWDJH9DDQ = VDD9VV4 9VV5HIHUWR v2KPGULYHVHQVLWLYLW\wLIHLWKHUWKHWHPSHUDWXUHRUWKHYROWDJHFKDQJHVDIWHUFDOLEUDWLRQ 2. 0HDVXUHPHQWGHILQLWLRQIRUPLVPDWFKEHWZHHQSXOOXSDQGSXOOGRZQ00383'0HDUXUHERWK52138 and R213'DW[9DDQ: MM38' = R2138 - R213' RONNOM LOGIC Devices Incorporated www.logicdevices.com 44 High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module 34 OHM OUTPUT DRIVER IMPEDANCE 34 OHM DRIVER 7KH:GULYHUuVFXUUHQWUDQJHKDVEHHQFDOFXODWHGDQGVXPPDUL]HGLQ7DEOHIRU9DD 97DEOHIRU9DD 9DQG7DEOHIRU9DD 9 7KHLQGLYLGXDOSXOOXSDQGSXOOGRZQUHVLVWRUV5213'DQG52138DUHGHILQHGDVIROORZVZLWKWKH,PSHGDQFH&DOFXODWLRQVOLVWHGLQ7DEOH xRON3' 9287>,287@52138LVWXUQHGRII xRON38 9DDQ-V287>,287@5213'LVWXUQHGRII TABLE 33: 34: DRIVER PULL-UP AND PULL-DOWN IMPEDANCE CALCULATIONS PACKAGE OUTLINE DIMENSIONS MR1[5,1] RON RON MIN RZQ = 240:±1% RZQ = (240:±1%)/7 RESISTOR RON34PD 0, 1 34.3: RON34PU TYP MAX UNITS 240 242.4 : 33.9 34.3 : VOUT MIN TYP MAX 9DDQ 2.04 34.3 38.1 UNITS : 9DDQ 34.3 38.1 : 9DDQ 34.3 : 9DDQ 34.3 : 9DDQ 34.3 38.1 : 9DDQ 20.4 34.3 38.1 : TABLE 34: 34: DRIVER IOH/IOL CHARACTERISTICS: VDD = VPDD Q = 1.35V ACKAGE OUTLINE DIMENSIONS MR1[5,1] RON RESISTOR RON34PD 0, 1 34.3: RON34PU VOUT MIN TYP MAX UNITS IOL @ 0.2 x VDDQ 14.7 8.8 7.9 P$ IOL#[9DDQ 21.9 19.7 P$ IOL @ 0.8 x VDDQ 39.3 24.8 P$ IOL @ 0.2 x VDDQ 39.3 24.8 P$ IOL#[9DDQ 21.9 19.7 P$ IOL @ 0.8 x VDDQ 14.7 8.8 7.9 P$ TABLE 35: 34: DRIVER IOH/IOL CHARACTERISTICS: VDD=VDD Q=1.4175V PACKAGE OUTLINE DIMENSIONS MR1[5,1] RON RESISTOR RON34PD 0, 1 34.3: RON34PU LOGIC Devices Incorporated www.logicdevices.com VOUT MIN TYP IOL @ 0.2 x VDDQ 9.2 8.3 P$ IOL#[9DDQ 23 20.7 P$ IOL @ 0.8 x VDDQ 41.2 P$ IOL @ 0.2 x VDDQ 41.2 P$ IOL#[9DDQ 23 20.7 P$ IOL @ 0.8 x VDDQ 9.2 8.3 P$ MAX UNITS High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module 34 OHM OUTPUT DRIVER IMPEDANCE TABLE 36: 34: DRIVER IOH/IOL CHARACTERISTICS: VDD=VDD Q=1.2825V PACKAGE OUTLINE DIMENSIONS MR1[5,1] RON RESISTOR RON34PD 0, 1 34.3: RON34PU VOUT MIN TYP MAX UNITS IOL @ 0.2 x VDDQ 14 8.3 P$ IOL#[9DDQ 23.3 20.8 18.7 P$ IOL @ 0.8 x VDDQ 37.3 33.3 P$ IOL @ 0.2 x VDDQ 37.3 33.3 P$ IOL#[9DDQ 23.3 20.8 18.7 P$ IOL @ 0.8 x VDDQ 14 8.3 P$ 34: OUTPUT DRIVER SENSITIVITY ,IHLWKHUWKHWHPSHUDWXUHRUYROWDJHFKDQJHVDIWHU=4FDOLEUDWLRQWKHWROHUDQFHOLPLWVOLVWHGLQ7DEOHFDQEHH[SHFWHGWRZLGHQDFFRUGLQJWR7DEOHDQG TABLE 37: 34: OUTPUT DRIVER SENSITIVITY DEFINITION Symbol MIN MAX UNITS RON @ 0.8 x VDDQ 0.9 - dRONG7+[>'7@G5ONG9+[>'V] 1.1 - dRONG7+[>'7@G5ONG9+[>'V] 5=4 RON @ 0.5 x VDDQ 0.9 - dRONdTM x ['7@G5ONdVM x ['V] 1.1 - dRONdTM x ['7@G5ONdVM x ['V] 5=4 RON @ 0.2 x VDDQ 0.9 - dRONdTL x ['7@G5ONdVL x ['V] 1.1 - dRONdTL x ['7@G5ONdVL x ['V] 5=4 TABLE 38: 34: OUTPUT DRIVER VOLTAGE AND TEMPERATURE SENSITIVITY Change MIN MAX UNITS dRONdTM 0 & dRONdVM 0 0.13 P9 dRONdTL 0 & dRONdVL 0 0.13 P9 dRONdTH 0 & dRONdVH 0 0.13 P9 LOGIC Devices Incorporated www.logicdevices.com High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module ALTERNATIVE 40 OHM DRIVER TABLE 39 - 40: DRIVER IMPEDANCE CHARACTERISTICS MR1[5,1] 0, 1 RON PACKAGE OUTLINE DIMENSIONS RESISTOR VOUT MIN TYP MAX UNITS NOTES 9DDQ 1.0 1.1 5=4 1 RON40PD 9DDQ 0.9 1.0 1.1 5=4 1 9DDQ 0.9 1.0 1.4 5=4 1 9DDQ 0.9 1.0 1.4 5=4 1 9DDQ 0.9 1.0 1.1 5=4 1 9DDQ 1.0 1.1 5=4 1 9DDQ -10 QD 10 1, 2 40.0: RON40PU Pull-Up/Pull-Down mismatch (MMPUPD) 127(6 1. 7ROHUDQFHOLPLWVDVVXPH5=4RI:DQGDUHDSSOLFDEOHDIWHUSURSHU=4FDOLEUDWLRQKDVEHHQSHUIRUPHGDWDVWDEOHWHPSHUDWXUHDQGYROWDJH (VDDQ = VDD9VV4 9VV5HIHUWRv2KPGULYHVHQVLWLYLW\wLIHLWKHUWKHWHPSHUDWXUHRUWKHYROWDJHFKDQJHVDIWHUFDOLEUDWLRQ 2. 0HDVXUHPHQWGHILQLWLRQIRUPLVPDWFKEHWZHHQSXOOXSDQGSXOOGRZQ00383'0HDUXUHERWK5ON38DQG5ON3'DW[9DDQ: MM383' = R2138 - R213' x 100 RONNOM 40: OUTPUT DRIVER SENSITIVITY ,IHLWKHUWKHWHPSHUDWXUHRUYROWDJHFKDQJHVDIWHU,2FDOLEUDWLRQWKHWROHUDQFHOLPLWVOLVWHGLQ7DEOHFDQEHH[SHFWHGWRZLGHQDFFRUGLQJWR7DEOHDQG TABLE 40: 40: OUTPUT DRIVER SENSITIVITY DEFINITION Symbol MIN MAX UNITS RON @ 0.8 x VDDQ 0.9 - dRONG7+[>'7@G5ONG9+[>'V] 1.1 - dRONG7+[>'7@G5ONG9+[>'V] 5=4 RON @ 0.5 x VDDQ 0.9 - dRONdTM x ['7@G5ONdVM x ['V] 1.1 - dRONdTM x ['7@G5ONdVM x ['V] 5=4 RON @ 0.2 x VDDQ 0.9 - dRONdTL x ['7@G5ONdVL x ['V] 1.1 - dRONdTL x ['7@G5ONdVL x ['V] 5=4 LOGIC Devices Incorporated www.logicdevices.com 47 High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module ALTERNATIVE 40 OHM DRIVER TABLE 41: 40: OUTPUT DRIVER VOLTAGE AND TEMPERATURE SENSITIVITY Change MIN MAX dRONdTM 0 UNITS & dRONdVM 0 P9 dRONdTL 0 & dRONdVL 0 P9 dRONdTH 0 & dRONdVH 0 P9 OUTPUT CHARACTERISTICS AND OPERATING CONDITIONS 7KH6'5$0XVHVERWKVLQJOHHQGHGDQGGLIIHUHQWLDORXWSXWGULYHUV7KHVLQJOHHQGHGRXWSXWGULYHULVVXPPDUL]HGLQ7DEOHZKLOHWKHGLIIHUHQWLDORXWSXW GULYHULVVXPPDUL]HGLQ7DEOH TABLE 42: SINGLE-ENDED OUTPUT DRIVER CHARACTERISTICS PACKAGE OUTLINE DIMENSIONS Parameter/Condition Output leakage current:'4DUHGLVDEOHG Symbol MIN UNITS NOTES I2= MAX uA 1 6546( 9QV 1, 2, 3, 4 0V d V287d VDD42'7LVGLVDEOHG2'7LV+,*+ Output slew rate:6LQJOHHQGHGIRUULVLQJDQGIDOOLQJ HGJHVPHDVXUHEHWZHHQ9OL$& 95() - 0.1 x VDDQ and V2+$& 95()[9DDQ Single-ended DC high-level output voltage V2+'& 0.8 x VDDQ V Single-ended DC mid-point level output voltage VOM'& [9DDQ V Single-ended DC low-point level output voltage VOL'& 0.2 x VDDQ V Single-ended DC high-point level output voltage V2+$& 977[9DDQ V Single-ended DC low-point level output voltage VOL$& VTT - 0.1 x VDDQ V Delta RON between pull-up and pull-down for DQ/DQS MM383' 1, 7 Test load for AC timing and output slew rates -10 10 3 2XWSXWWR9TT (VDD4YLD: resistor 127(6 1. 5=4RI:ZLWK5=4HQDEOHGGHIDXOW:GULYHUDQGLVDSSOL- FDEOH DIWHU SURSHU =4 FDOLEUDWLRQ KDV EHHQ SHUIRUPHG DW D VWDEOH WHP- 6HH7DEOHRQSDJHIRURXWSXWVOHZUDWH SHUDWXUHDQGYROWDJH9DDQ = VDD9VV4 9VV 7. 6HH7DEOHRQSDJHIRUDGGLWLRQDOLQIRUPDWLRQ 2. VTT = VDD4 8. 6HH )LJXUH RQ SDJH IRU DQ H[DPSOH RI D VLQJOHHQGHG RXWSXW 3. 6HH)LJXUHRQSDJHIRUWKHWHVWORDGFRQILJXUDWLRQ 4. 6HH7DEOHRQSDJH,9FXUYHOLQHDULW\'RQRWXVH$&7HVWORDG signal. 7KH9QVPD[LPXPLVDSSOLFDEOHIRUDVLQJOH'4VLJQDOZKHQLWLVVZLWFKLQJIURPHLWKHU+,*+WR/2:RU/2:WR+,*+ZKLOHWKHUHPDLQLQJ'4 VLJQDOVLQWKHVDPHE\WHODQHDUHFRPELQDWLRQVWKHPD[LPXPOLPLWRI9 QVPD[LPXPLVUHGXFHGWR9QV LOGIC Devices Incorporated www.logicdevices.com 48 High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module TABLE 43: DIFFERENTIAL OUTPUT DRIVER CHARACTERISTICS PACKAGE OUTLINE DIMENSIONS Parameter/Condition Output leakage current:'4DUHGLVDEOHG Symbol MIN MAX UNITS NOTES I2= uA 1 SRQDIFF 12 9QV 1 V2;$& V5() V5() P9 1, 2, 3 0V d V287d VDD42'7LV+,*+ Output slew rate:'LIIHUHQWLDOIRUULVLQJDQGIDOOLQJHGJHV PHDVXUHEHWZHHQ9OL',))$& [9DDQ and V2+ $& [9DDQ Output differential cross-point voltage Differential high-level output voltage V2+',))$& [9DDQ V 1, 4 Differential low-level output voltage VOL',))$& - 0.2 x VDDQ V 1, 4 Delta RON between pull-up and pull-down for DQ/DQS MM383' -10 10 2XWSXWWR9TT (VDD4YLD: resistor Test load for AC timing and output slew rates 3 127(6 1. 5=4RI:ZLWK5=4HQDEOHGGHIDXOW:GULYHUDQGLVDSSOL- 4. 6HH7DEOHRQSDJHIRUWKHRXWSXWVOHZUDWH FDEOH DIWHU SURSHU =4 FDOLEUDWLRQ KDV EHHQ SHUIRUPHG DW D VWDEOH WHP- 6HH7DEOHRQSDJHIRUDGGLWLRQDOLQIRUPDWLRQ SHUDWXUHDQGYROWDJH9DDQ = VDD9VV4 9VV 6HH)LJXUHRQSDJHIRUDQH[DPSOHRIDGLIIHUHQWLDORXWSXWVLJQDO 2. V5() = VDD4 3. 6HH)LJXUHRQSDJHIRUWKHWHVWORDGFRQILJXUDWLRQ FIGURE 20 - DQ OUTPUT SIGNAL MAX output VOH(AC) VOL(AC) MIN output LOGIC Devices Incorporated www.logicdevices.com 49 High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module OUTPUT CHARACTERISTICS AND OPERATING CONDITIONS FIGURE 21 - DIFFERENTIAL OUTPUT SIGNAL MAX output VOH(DIFF) X VOX(AC) MAX X X VOX(AC) MIN X VOL(DIFF) MIN output REFERENCE OUTPUT LOAD )LJXUHUHSUHVHQWVWKHHIIHFWLYHUHIHUHQFHORDGRI:XVHGLQGHILQLQJWKHUHOHYDQWGHYLFH$&WLPLQJSDUDPHWHUVH[FHSW2'7UHIHUHQFHWLPLQJDVZHOODVWKH RXWSXWVOHZUDWHPHDVXUHPHQWV,WLVQRWLQWHQGHGWREHDSUHFLVHUHSUHVHQWDWLRQRIDSDUWLFXODUV\VWHPHQYLURQPHQWRUDGHSLFWLRQRIWKHDFWXDOORDGSUHVHQWHG E\DQ\VSHFLILF,QGXVWU\WHVWV\VWHPDSSDUDWXV6\VWHPGHVLJQHUVVKRXOGXVH,%,6RURWKHUVLPXODWLRQWRROVWRFRUUHODWHWKHWLPLQJUHIHUHQFHORDGSUHVHQWHGRU H[KLELWHGRQWKHV\VWHPRUV\VWHPHQYLURQPHQW FIGURE 22 - REFERENCE OUTPUT LOAD FOR AC TIMING AND OUTPUT SLEW RATE DUT VREF DQ DQS DQS# VDDQ/2 RTT = 25Ω VTT = VDDQ/2 Timing Reference Point ZQ RZQ = 240Ω VSS LOGIC Devices Incorporated www.logicdevices.com High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module SLEW RATE DEFINITIONS FOR SINGLE-ENDED OUTPUT SIGNALS 7KHVLQJOHHQGHGRXWSXWGULYHULVVXPPDUL]HGLQ7DEOH:LWKWKHUHIHUHQFHORDGIRUWLPLQJPHDVXUHPHQWVWKHRXWSXWVOHZUDWHIRUIDOOLQJDQGULVLQJHGJHV LVGHILQHGDQGPHDVXUHGEHWZHHQ9OL$&DQG92+$&IRUVLQJOHHQGHGVLJQDOVDVLQGLFDWHGLQ7DEOHDQG)LJXUH TABLE 44: SINGLE-ENDED OUTPUT SLEW RATE Measured Output Slew Rate (Linear Signals) Output PACKAGE OUTLINE DIMENSIONS Edge From To Rising VOL$& V2+$& Falling V2+$& VOL$& Calculation V2+$&9OL $& '756( DQ V2+$&9OL$& '7)6( FIGURE 23 - NOMINAL SLEW RATE DEFINITION FOR SINGLE-ENDED OUTPUT SIGNALS ΔTRSE VOH(AC) VTT VOL(AC) ΔTFSE LOGIC Devices Incorporated www.logicdevices.com High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module SLEW RATE DEFINITIONS FOR DIFFERENTIAL OUTPUT SIGNALS 7KHGLIIHUHQWLDORXWSXWGULYHULVVXPPDUL]HGLQ7DEOH:LWKWKHUHIHUHQFHORDGIRUWLPLQJPHDVXUHPHQWVWKHRXWSXWVOHZUDWHIRUIDOOLQJDQGULVLQJHGJHVLV GHILQHGDQGPHDVXUHGEHWZHHQ9OL$&DQG92+$&IRUGLIIHUHQWLDOVLJQDOVDVVKRZQLQ7DEOHDQG)LJXUH TABLE 45: DIFFERENTIAL OUTPUT SLEW RATE DEFINITION Measured Output Slew Rate (Linear Signals) Output PACKAGE OUTLINE DIMENSIONS Edge From To Rising VOL',))$& V2+',))$& Falling V2+',))$& VOL',))$& Calculation V2+',))$&9OL ',))$& 'TRDIFF DQS, DQS\ V2+',))$&9OL',))$& 'TFDIFF FIGURE 24 - NOMINAL DIFFERENTIAL OUTPUT SLEW RATE DEFINITION FOR DQS, DQS# VOH(DIFF) AC 0 VOL(DIFF) AC ΔTFDIFF LOGIC Devices Incorporated www.logicdevices.com High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module TABLE 46: SPEED BINS PACKAGE OUTLINE DIMENSIONS ''5''5''5 >&:/ @>&:/ @>&:/ @ Parameter Symbol MIN MAX MIN MAX MIN tRCD - - 13.91 - ns 35(&+$5*(FRPPDQGSHULRG t53 - - 13.91 - ns $&7,9$7(WR$&7,9$7(RU5()5(6+FRPPDQGSHULRG tRC - - 48.91 - ns tRAS 9 x t5(), 9 x t5(), 34 9 x t5(), ns 1 &:/ t&.$9* 3 3.3 3 3.3 3 3 ns 2 &:/ t&.$9* ns 3 ns 3 ns 2 $&7,9$7(WRLQWHUQDO5($'RU:5,7(GHOD\WLPH $&7,9$7(WR35(&+$5*(FRPPDQGSHULRG &/ &/ CL=8 CL=10 MAX UNITS NOTES CWL=7 t&.$9* &:/ t&.$9* &:/ t&.$9* ns 3 CWL=7 t&.$9* ns 3 &:/ t&.$9* &:/ t&.$9* CWL=7 3.3 3.3 3.3 ns 3 ns 2,3 t&.$9* ns 3 &:/ t&.$9* ns 3 &:/ t&.$9* CWL=7 t&.$9* ns 3 ns 2,3 CK 6XSSRUWHG&/6HWWLQJV 6XSSRUWHG&:/6HWWLQJV CK 127(6 1. t5(),GHSHQGVRQt23(5 2. 7KH &/ DQG &:/ VHWWLQJ UHVXOW LQ t&. UHTXLUHPHQWV :KHQ PDNLQJ D VHOHFWLRQRI t&.ERWK&/DQG&:/UHTXLUHPHQWVHWWLQJVQHHGWREHIXO- 3. 5HVHUYHGILOOHGEORFNVVHWWLQJVDUHQRWDOORZHG filled. LOGIC Devices Incorporated www.logicdevices.com High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B LOGIC Devices Incorporated www.logicdevices.com t t CK (AVG) CKDLL_DIS Cumulave error across 3 Cycles 4 Cycles 5 Cycles 6 Cycles 7 Cycles 8 Cycles 9 Cycles 10 Cycles 11 Cycles 12 Cycles 2 Cycles n = 13, 14 … 49, 50 Cycles DLL LOCKED DLL LOCKING ERR3PERR t ERRnPER ERR4PERR t ERR5PERR t ERR6PERR t ERR7PERR t ERR8PERR t ERR9PERR t ERR10PERR t ERR11PERR t ERR12PERR t t t JITCC JITCC, LCK t ERR2PERR t -140 -155 -168 -177 -186 -193 -200 -205 -210 -215 -118 0.43 t Clock absolute LOW pulse width Cycle-to-Cycle JITTER 0.43 CH (ABS) CL (ABS) 0.53 0.53 80 70 0.47 0.47 -70 -60 0.53 0.53 70 60 0.47 0.47 -60 -50 See SPEED BIN TABLE (#49) for tCK range allowed 0.53 0.53 60 50 -12 (DDR3-1600) -11 (DDR3-1866) [CWL=1.25; 11-11-11] [CWL=1.07; 13-13-13] MIN MAX MIN MAX 8 7800 8 7800 8 3900 8 3900 8 2900 - 118 -103 0.43 0.43 140 120 103 - - -88 0.43 0.43 120 100 140 -122 122 -105 155 -136 136 -117 168 -147 147 -126 177 -155 155 -133 186 -163 163 -139 193 -169 169 -145 200 -175 175 -150 205 -180 180 -154 210 -184 184 -158 215 -188 188 -161 tERRnPER MIN = (1+0.68ln[n]) x tJITPER MIN tERRnPER MAX = (1+0.68ln[n]) x tJITPER MAX 160 140 - - 105 117 126 133 139 145 150 154 158 161 88 - - MIN=tCK (AVG) MIN+tJITPER MIN; MAX=tCK (AVG)MAX+tJITPER MAX 0.47 0.47 -80 -70 Clock absolute HIGH pusle width CH (AVG) t CL (AVG) t JITPER t JITPER, LCK t CLK (ABS) t Symbol t Parameter TC = 0˚C to <85˚C Clock period average: DLL TC = 85˚C to 105˚C disable mode TC = >105˚C to ≤125˚C Clock period average: DLL enable mode HIGH pulse width average LOW pulse width average DLL LOCKED Clock period JITTER DLL LOCKING Clock absolute period -15 (DDR3-1333) [CWL=1.5; 9-9-9] MIN MAX 8 7800 8 3900 8 2900 ps ps ps ps ps ps ps ps ps ps ps 17 17 17 17 17 17 17 17 17 17 17 16 16 17 15 tCK (AVG) ps ps ps 14 10,11 12 12 13 13 Notes 9,42 9,42 9,42 tCK (AVG) ns CK CK ps ps ps ns Units L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module TABLE 47 (SHEET 1 OF 6) - ELECTRICAL CHARACTERISTICS AND AC OPERATING CONDITIONS High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B LOGIC Devices Incorporated www.logicdevices.com DQS, DQS\ DIFFERENTIAL READ postamble DQS, DQS\ DIFFERENTIAL Output HIGH me DQS, DQS\ DIFFERENTIAL Output LOW me DQS, DQS\ LOW-Z me (RL-1) DQS, DQS\ HIGH-Z me (RL+BL/2) DQS, DQS\ DIFFERENTIAL READ preamble DQS, DQS\ RISING to/from RISING CK, CK\ when DLL is disabled DQS, DQS\ RISING to/from RISING CK, CK\ DQS,DQS\ RISING to CK, CK\ RISING DQS, DQS\ DIFFERENTIAL Input Low pulse width DQS, DQS\ DIFFERENTIAL Input HIGH pulse width DQS, DQS\ FALLING Setup to CK, CK\ RISING DQS, DQS\ FALLING Hold from CK, CK\ RISING DQS, DQS\ DIFFERENTIAL WRITE preamble DQS, DQS\ DIFFERENTIAL WRITE postamble t QH 0.38 t RPST DQSK DLL_DIS t QSH t QSL t LZ (DQS) t HZ (DQS) t RPRE t 0.3 0.4 0.4 -500 0.9 1 -500 LZ (DQ) HZ (DQ) DQ Strobe Input Timing t -0.25 DQSS t 0.45 DQSL t 0.45 DQSH t 0.2 DSS t 0.2 DSH t 0.9 WPRE t 0.3 WPST DQ Strobe Output Timing t -255 DQSCK t DQ LOW-Z me from CK, CK\ DQ HIGH-A me from CK, CK\ Base (specificaon) VREF @ 1V/ns Base (specificaon) VREF @ 1V/ns Base (specificaon) VREF @ 1V/ns t DQ Output HOLD me from DQS, DQS\ DQS, DQS\ to DQ SKEW, per access Data HOLD me from DQS, DQS\ Minimum Data Pulse Width Data SETUP me to DQS, DQS\ Data SETUP me to DQS, DQS\ Parameter Note 27 250 250 Note 24 10 255 0.25 0.55 0.55 - 250 250 - -15 (DDR3-1333) [CWL=1.5; 9-9-9] Symbol MIN MAX DQ Input Timing t DS AC175 30 t DS AC150 180 65 t DH AC100 165 t 400 DIPW DQ Ouput Timing t 125 DQSQ 0.3 0.4 0.4 -450 0.9 1 -225 -0.27 0.45 0.45 0.18 0.18 0.9 0.3 - -450 0.38 - 10 160 45 145 360 Note 27 225 225 Note 24 10 225 0.27 0.55 0.55 - 225 225 - 100 - 0.3 0.4 0.4 -390 0.9 1 -195 -0.27 0.45 0.45 0.18 0.18 0.9 0.3 - -390 0.38 - 135 20 120 320 Note 27 195 195 Note 24 10 195 0.27 0.55 0.55 - 195 195 - 85 - -12 (DDR3-1600) -11 (DDR3-1866) [CWL=1.25; 11-11-11] [CWL=1.07; 13-13-13] MIN MAX MIN MAX CK CK CK ps ps CK ns ps CK CK CK CK CK CK CK ps ps tCK (AVG) ps ps ps ps ps ps ps ps Units 23,27 21 21 22,23 22,23 23,24 26 23 25 25 25 22,23 22,23 21 18,19 19,20 18,19 19,20 18,19 19,20 41 Notes L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module TABLE 47 (SHEET 2 OF 6) - ELECTRICAL CHARACTERISTICS AND AC OPERATING CONDITIONS High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B LOGIC Devices Incorporated www.logicdevices.com 2KB page size 1KB page size MULTIPURPOSE REGISTER READ burst end to mode register set for mulpurpose register exit MODE REGISTER SET command cycle me MODE REGISTER SET command update delay t DAL MPRR MOD MRD t t t RTP CCD MIN = 1CK; MAX = n/a MIN = 4CK; MAX = n/a MIN = greater of 12CK or 15ns; MAX = n/a MIN = WR + tRP/tCK (AVG); MAX = n/a MIN = greater of 4CK or 7.5ns; MAX = n/a MIN = 4CK; MAX = n/a t MIN = greater of 4CK or 7.5ns; MAX = n/a MIN = 15ns; MAX = n/a WTR WR t t t Auto precharge WRITE recovery + PRECHARGE me Delay from start of internal WRITE transacon to internal READ command READ-to-PRECHARE me CAS\-to-CAS\ command delay WRITE recovery me Four ACTIVATE windows for 1KB page size Four ACTIVATE windows for 2KB page size ACTIVATE-to-ACTIVATE minimum command period DLL Locking me Base (specificaon) CTRL, CMD, ADDR setup to CK, VREF @ 1V/ns CK\ Base (specificaon) CTRL, CMD, ADDR setup to CK, VREF @ 1V/ns CK\ Base (specificaon) CTRL, CMD, ADDR hold to CK, VREF @ 1V/ns CK\ Minimum CTRL, CMD, ADDR pulse width ACTIVATE to Internal READ or WRITE delay PRECHARGE command period ACTIVATE-to-PRECHARGE command period ACTIVATE-to-ACTIVATE command period Parameter -15 (DDR3-1333) -12 (DDR3-1600) -11 (DDR3-1866) [CWL=1.5; 9-9-9] [CWL=1.25; 11-11-11] [CWL=1.07; 13-13-13] Symbol MIN MAX MIN MAX MIN MAX Command and Address Timing t 512 512 512 DLLK 65 65 45 t IS AC175 240 220 200 150 190 170 t IS AC150 275 340 320 100 140 120 t IH DC100 200 240 220 t 535 620 560 IPW t See "Speed Bin Table (#49) for tRCD RCD t See "Speed Bin Table (#49) for tRP RP t See "Speed Bin Table (#49) for tRAS RAS t See "Speed Bin Table (#49) for tRC RCD MIN=greater of 4CK MIN=greater of 4CK MIN=greater of 4CK or 5ns or 6ns or 6ns t RRD MIN=greater of 4CK MIN=greater of 4CK or 7.5ns or 6ns 25 30 30 t FAW 35 45 40 - CK CK CK CK CK CK CK CK 31,34 31,32,33 31 31 31 CK ns ns 31 28 29,30 20,30 29,30 20,30 29,30 20,30 41 31 31 31,32 31 Notes CK CK ps ps ps ps ps ps ps ns ns ns ns Units L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module TABLE 47 (SHEET 3 OF 6) - ELECTRICAL CHARACTERISTICS AND AC OPERATING CONDITIONS High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B LOGIC Devices Incorporated www.logicdevices.com TC ≤ 85˚C TC >85˚C ≤ 105˚C TC >105˚C ≤ 125˚C TC ≤ 85˚C TC >85˚C ≤ 105˚C TC >105˚C ≤ 125˚C Valid clocks before SELF REFRESH exit, POWER-DOWN exit, or RESET exit Valid clocks aer SELF REFRESH entry or POWER-DOWN entry MINIMUM CKE LOW pulse width for SELF REFRESH entry to SELF REFRESH exit ming EXIT SELF REFRESH TO commands requiring a locked DLL Exit SELF REFRESH TO commands not requiring a locked DLL Maximum REFRESH period/interval Maximum REFRESH period REFRESH-to-ACTIVATE or REFRESH command period RESET\ LOW to power supplies stable RESET\ LOW to I/O and RTT HIGH-Z Begin power supply ramp to power supplies stable Exit RESET from CKE HIGH to a valid command Normal operaon POWER-UP and RESET operaon ZQCS command: Short Calibraon Time ZQCL command: Long Calibraon me Parameter ZQINIT 512 512 512 t VDDPR REFI - CKSRE CKESR XSDLL XS CKSRX t t t t t SELF REFRESH Timing t t RPS IOZ REFRESH Timing t RFC - 1Gb t RFC - 2Gb t RFC - 4Gb t MIN = greater of 5CK or 10ns; MAX = n/a MIN = greater of 5CK or 10ns; MAX = n/a MIN = tCKE (MIN) + CK; MAX = n/a MIN = tDLLK (MIN); MAX = n/a CK CK CK CK CK ns ns ns ms ms ms μs μs μs MIN = 110; MAX = 70,200 MIN = 160; MAX = 70,200 MIN = 260; MAX = 70,200 64 (1X) 32 (2X) 24 7.8 3.9 2.9 MIN = greater of 5CK or tRFC + 10ns; MAX = n/a ms ns ms CK CK CK CK Units MIN = 0; MAX = 200 MIN = n/a; MAX = 20 MIN = n/a; MAX = 200 - - -12 (DDR3-1600) -11 (DDR3-1866) [CWL=1.25; 11-11-11] [CWL=1.07; 13-13-13] MIN MAX MIN MAX 256 256 256 ZQOPER t 64 64 64 ZQCS Inializaon and RESET Timing t MIN = greater of 5CK or tRFC + 10ns; MAX = n/a XPR t t -15 (DDR3-1333) [CWL=1.5; 9-9-9] Symbol MIN MAX Calibraon Timing 28 36 36 36 36 36 36 35 Notes L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module TABLE 47 (SHEET 4 OF 6) - ELECTRICAL CHARACTERISTICS AND AC OPERATING CONDITIONS High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B LOGIC Devices Incorporated www.logicdevices.com t BL8 (OTF, MRS) BC4OTF BC4MRS WRPDEN WRPDEN RDPDEN WRAPDEN t t t XP XPDLL t t WRAPDEN POWER-DOWN Exit Timing t BC4MRS BL8 (OTF, MRS) BC4OTF DLL on, any valid command, or DLL off to commands not requiring DLL locked PRECHARGE POWER-DOWN with DLL off to command requiring DLL locked WRITE with AUTO PRECHARGE command to POWER-DOWN entry WRITE Command to POWERDOWN entry READ/READ with AUTO PRECHARGE commant to POWER-DOWN entry PRPDEN REFPDEN MRSPDEN REFRESH command to POWER-DOWN entry MRS command to POWER-DOWN entry t t ACTPDEN PRECHARGE/PRECHARGE ALL command to POWER-DOWN entry t WL - 1CK ANPD + tXPDLL MIN = 2 MIN = 2 MIN = 2 MIN = Greater of 10CK or 24ns; MAX = n/a MIN = Greater of 3CK or 6.0ns; MAX = n/a MIN = WL + 2 + WR + 1 MIN = WL + 4 + WR + 1 t MIN = WL + 2 + WR/ CK (AVG) t MIN = WL + 4 + tWR/tCK (AVG) MIN = RL + 4 + 1 MIN = tMOD (MIN) MIN = 1 MIN = 1 MIN = 1 t Greater of tANPD or tRFC - REFRESH command to CKE LOW me POWER-DOWN Entry MINIMUM Timing t ACTIVATE command to POWER-DOWN entry PDX POWER-DOWN exit period: ODT either synchronous or asynchronous ANPD PDE t POWER-DOWN entry period: ODT eher synchronous or asynchronous Begin POWER-DOWN period prior to CKE registered HIGH Command pass disable delay POWER-DOWN entry to POWER-DOWN exit ming CKE MIN pulse width Parameter -15 (DDR3-1333) -12 (DDR3-1600) -11 (DDR3-1866) [CWL=1.5; 9-9-9] [CWL=1.25; 11-11-11] [CWL=1.07; 13-13-13] Symbol MIN MAX MIN MAX MIN MAX POWER-DOWN Timing Greater of 3CK or Greater of 3CK or Greater of 3CK or t CKE (MIN) 5.625ns 5ns 5ns t MIN = 1; MAX = n/a CPDED t MIN = tCKE (MIN); MAX = 60ms PD CK CK CK CK CK CK CK CK CK CK CK CK CK CK CK CK CK Units 28 37 Notes L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module TABLE 47 (SHEET 5 OF 6) - ELECTRICAL CHARACTERISTICS AND AC OPERATING CONDITIONS High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B LOGIC Devices Incorporated www.logicdevices.com AON AOF First DQS, DQS\ RISING edge DQS; DQS\ delay WRITE Leveling SETUP from rising CK, CK\ crossing to rising DQS, DQS\ crossing WRITE Leveling HOLD from rising DQS, DQS\ crossing to rising CK, CK\ crossing WRITE Leveling output delay WRITE Leveling output error RTT_NOM-to=RTT_WR change skew RTT_WR-to-RTT_NOM change skew - BC4 RTT_WR-to-RTT_NOM change skew - BC8 RTT dynamic change skew ODT HIGH me without WRITE command or with WRITE command and BC8 ODT HIGH me without WRITE command or with WRITE command and BC4 t WLH WLS WLO WLOE t t t 0 0 195 195 9 2 - - - 0 0 163 163 40 25 7.5 2 - - - WL - 2CK 4CK + ODTL OFF 6CK + ODTL OFF 0.3 0.7 MIN = 4; MAX = n/a ODTH4 Dynamic ODT Timing ODTLCNW ODTLCNW4 ODTLCNW8 t 0.3 ADC WRITE Leveling Timing t 40 WLMRD t 25 WLDQSEN MIN = 6; MAX = n/a ODTH8 0.7 MIN = 2; MAX = 8.5 AOFPD t 225 0.7 Asynchronous RTT TURN-OFF delay (POWER-DOWN with DLL OFF) -225 0.3 MIN = 2; MAX = 8.5 250 0.7 AONPD -250 0.3 t t t Symbol ODT Timing ODTL on ODTL off 0 0 140 140 40 25 0.3 -195 0.3 7.5 2 - - - 0.7 195 0.7 -12 (DDR3-1600) -11 (DDR3-1866) [CWL=1.25; 11-11-11] [CWL=1.07; 13-13-13] MIN MAX MIN MAX Asynchronous RTT TURN-ON delay (POWER-DOWN with DLL OFF) RTT synchronous TURN-ON delay RTT synchronous TURN-OFF delay RTT TURN-ON from ODTL ON reference RTT TURN-OFF from ODTL OFF reference Parameter -15 (DDR3-1333) [CWL=1.5; 9-9-9] MIN MAX ns ns ps ps CK CK CK CK CK CK CK CK ns ns CK CK ps CK Units 39 40 38 38 40 23,38 39,40 Notes L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module TABLE 47 (SHEET 6 OF 6) - ELECTRICAL CHARACTERISTICS AND AC OPERATING CONDITIONS High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module NOTES 1. 3DUDPHWHUVDUHDSSOLFDEOHZLWK&d TA d&DQG9DD9DD4 99 2. $OOYROWDJHVDUHUHIHUHQFHGWR9VV 3. 2XWSXWWLPLQJVDUHRQO\YDOLGIRU5ONRXWSXWEXIIHUVHOHFWLRQ 4. 8QLW t&. $9* UHSUHVHQWV WKH DFWXDO t&. $9* RI WKH LQSXW FORFN XQGHURSHUDWLRQ8QLW&.UHSUHVHQWVRQHFORFNF\FOHRIWKHLQSXWFORFN FRXQWLQJWKHDFWXDOFORFNHGJHV 7. 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VIH(AC) = VREF(DC) + 175mV, VIL(AC) = VREF(DC) - 175mV CMD/ADDR Slew Rate V/ns CK, CK\ Differential Slew Rate 4.0V/ns 3.0V/ns 2.0V/ns 1.8V/ns 1.6V/ns 1.4V/ns 1.2V/ns 1.0V/ns 'tIS 'tIH 'tIS 'tIH 'tIS 'tIH 'tIS 'tIH 'tIS 'tIH 'tIS 'tIH 'tIS 'tIH 'tIS 'tIH 2.0 88 88 88 112 74 120 84 128 100 34 34 34 42 83 91 99 84 1.0 0 0 0 0 0 0 8 8 8 24 24 32 34 40 0.9 -2 -4 -2 -4 -2 -4 4 12 22 20 30 30 38 0.8 -10 -10 -10 2 -2 2 18 14 24 34 40 0.7 -11 -11 -11 -3 -8 -3 0 13 8 21 18 29 34 -17 -17 -17 -9 -18 -9 -10 7 -2 8 23 24 -40 -40 -40 -27 -32 -27 -24 -11 -2 10 0.4 -44 -38 -30 -22 -10 LOGIC Devices Incorporated www.logicdevices.com High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module TABLE 50: DERATING VALUES FOR tIS/tIH – AC150/DC100-BASED Shaded cells indicate slew-rate combinations not supported 'tIS, 'tIH Derating (ps) - AC/DC-Based, AC150 Threshold; VIH(AC) = VREF(DC) + 150mV, VIL(AC) = VREF(DC) - 150mV CMD/ADDR Slew Rate V/ns CK, CK\ Differential Slew Rate 4.0V/ns 3.0V/ns 2.0V/ns 1.8V/ns 1.6V/ns 1.4V/ns 1.2V/ns 1.0V/ns 'tIS 'tIH 'tIS 'tIH 'tIS 'tIH 'tIS 'tIH 'tIS 'tIH 'tIS 'tIH 'tIS 'tIH 'tIS 'tIH 2.0 83 91 99 74 107 84 100 34 34 34 42 74 82 90 84 1.0 0 0 0 0 0 0 8 8 24 24 32 34 40 0.9 0 -4 0 -4 0 -4 8 4 12 24 20 32 30 40 0.8 0 -10 0 -10 0 -10 8 -2 24 14 32 24 40 40 0.7 0 0 0 8 -8 0 24 8 32 18 40 34 -1 -1 -1 7 -18 -10 23 -2 31 8 39 24 -10 -40 -10 -40 -10 -40 -2 -32 -24 14 22 30 10 0.4 -17 -9 -44 -1 7 -10 TABLE 51: MINIMUM REQUIRED TIME tVAC ABOVE VIH(AC) FOR A VALID TRANSITION Below VIL(AC) Slew Rate (V/ns) tVAC at 175mV(ps) tVAC at 150mV(ps) tVAC at 135mV(ps) tVAC at 125mV(ps) >2.0 200 2.0 170 190 180 1.0 38 140 170 0.9 34 130 0.8 29 120 0.7 22 110 QD 13 QD 0 QD QD 0 QD QD LOGIC Devices Incorporated www.logicdevices.com High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module FIGURE 25 - NOMINAL SLEW RATE AND tVAC FOR tIS (COMMAND AND ADDRESS – CLOCK) t IS t IH t IS t IH CK CK# DQS# DQS VDDQ t VAC VIH(AC) MIN VREF to AC region VIH(DC) MIN Nominal slew rate VREF(DC) Nominal slew rate VIL(DC) MAX VREF to AC region VIL(DC) MAX t VAC VSS ∆TF Setup slew rate falling signal ∆TR VREF(DC) - VIL(AC) MAX Setup slew rate risin g signal = ∆TF Notes: LOGIC Devices Incorporated VIH(AC) MIN - V REF(DC) = ∆TR 1. Both the clock and the strobe are drawn on different time scales. www.logicdevices.com High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module FIGURE 26 - NOMINAL SLEW RATE FOR tIH (COMMAND AND ADDRESS – CLOCK) t IS t IH t IS t IH CK CK# DQS# DQS VDDQ VIH(AC) MIN VIH(DC) MIN Nominal slew rate DC to V REF region VREF(DC) Nominal slew rate DC to V REF region VIL(DC) MAX VIL(AC) MAX VSS ∆TF ∆TR Hol d slew rate = rising signal VREF(DC) - VIL(DC) MAX Hol d slew rate falling signal = ∆TR Notes: LOGIC Devices Incorporated www.logicdevices.com VIH(DC) MIN - V REF(DC) ∆TF 1. Both the clock and the strobe are drawn on different time scales. High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module FIGURE 27 - TANGENT LINE FOR tIS (COMMAND AND ADDRESS – CLOCK) t IS t IH t IS t IH CK CK# DQS# DQS VDDQ t VAC Nominal line VIH(AC) MIN VREF to AC region VIH(DC) MIN Tangent line VREF(DC) Tangent line VIL(DC) MAX VREF to AC region VIL(AC) MAX Nominal line t VAC ∆TR VSS Setup slew rate rising signal = ∆TF Notes: LOGIC Devices Incorporated Tangent line (V IH [ DC] MIN - VREF[ DC ]) ∆TR Tangent line (VREF [ DC] - V IL[ AC] MAX) Setup slew rate falling signal = ∆TF 1. Both the clock and the strobe are drawn on different time scales. www.logicdevices.com High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module FIGURE 28 - TANGENT LINE FOR tIH (COMMAND AND ADDRESS – CLOCK) t IS t IH t IS t IH CK CK# DQS # DQS VDDQ VIH(AC) MIN Nominal line VIH(DC) MIN DC to V REF region Tangent line VREF(DC) DC to V REF region Tangent line Nominal line VIL( DC) MAX VIL( AC) MAX VSS ∆TR ∆TR Hol d slew rate rising signal = Tangent line (V REF [ DC] - V IL[ DC] MAX) Hol d slew rate falling signal = Tangent line (V IH [ DC] MIN - VREF[ DC]) ∆TR ∆TF Notes: LOGIC Devices Incorporated 1. Both the clock and the strobe are drawn on different time scales. www.logicdevices.com High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module DATA SETUP, HOLD AND DERATING 7KHWRWDO t'6VHWXSWLPHDQGt'+KROGWLPHUHTXLUHGLVFDOFXODWHGE\DGGLQJWKHGDWDVKHHWt'6EDVHDQGt'+EDVHYDOXHVVHH7DEOHWRWKH'tDS and 't'+GHUDWLQJYDOXHVVHH7DEOHUHVSHFWLYHO\ $OWKRXJKWKHWRWDOVHWXSWLPHIRUVORZVOHZUDWHVPLJKWEHQHJDWLYHDYDOLGLQSXWVLJQDOLVVWLOOUHTXLUHGWRFRPSOHWHWKHWUDQVLWLRQDQGWRUHDFK9,+9IL$&)RU VOHZUDWHVZKLFKIDOOEHWZHHQWKHYDOXHVOLVWHGLQ7DEOHWKHGHUDWLQJYDOXHVPD\EHREWDLQHGE\OLQHDULQWHUSRODWLRQ 6HWXSt'6QRPLQDOVOHZUDWHIRUDULVLQJVLJQDOLVGHILQHGDVWKHVOHZUDWHEHWZHHQWKHODVWFURVVLQJRI95()'&DQGWKHILUVWFURVVLQJRI9,+$&0,16HWXS (t'6QRPLQDOVOHZUDWHIRUDIDOOLQJVLJQDOLVGHILQHGDVWKHVOHZUDWHEHWZHHQWKHODVWFURVVLQJRI95()'&DQGWKHILUVWFURVVLQJRI9IL$&0$;,IWKHDFWXDO VLJQDOLVDOZD\VHDUOLHUWKDQWKHQRPLQDOVOHZUDWHOLQHEHWZHHQWKHVKDGHGv95()'&WR$&UHJLRQwXVHWKHQRPLQDOVOHZUDWHGHUDWLQJYDOXHVHH)LJXUH ,IWKHDFWXDOVLJQDOLVODWHUWKDQWKHQRPLQDOVOHZUDWHOLQHDQ\ZKHUHEHWZHHQWKHVKDGHGv95()'&WR$&UHJLRQwWKHVOHZUDWHRIDWDQJHQWOLQHWRWKHDFWXDO VLJQDOIURPWKH$&OHYHOWRWKH'&OHYHOLVXVHGIRUWKHGHUDWLQJYDOXHVHH)LJXUH +ROGt'+QRPLQDOVOHZUDWHIRUDULVLQJVLJQDOLVGHILQHGDVWKHVOHZUDWHEHWZHHQWKHODVWFURVVLQJRI9IL'&0$;DQGWKHILUVWFURVVLQJRI95()'&+ROG (t'+QRPLQDOVOHZUDWHIRUDIDOOLQJVLJQDOLVGHILQHGDVWKHVOHZUDWHEHWZHHQWKHODVWFURVVLQJRI9,+'&0,1DQGWKHILUVWFURVVLQJRI95()'&,IWKHDFWXDO VLJQDOLVDOZD\VODWHUWKDQWKHQRPLQDOVOHZUDWHOLQHEHWZHHQWKHVKDGHGv'&WR95()'&UHJLRQwXVHWKHQRPLQDOVOHZUDWHIRUGHUDWLQJYDOXHVHH)LJXUH ,IWKHDFWXDOVLJQDOLVHDUOLHUWKDQWKHQRPLQDOVOHZUDWHOLQHDQ\ZKHUHEHWZHHQWKHVKDGHGv'&WR95()'&UHJLRQwWKHVOHZUDWHRIDWDQJHQWOLQHWRWKH DFWXDOVLJQDOIURPWKHv'&WR95()'&UHJLRQwLVXVHGIRUWKHGHUDWLQJYDOXHVHH)LJXUH TABLE 52: DATA SETUP AND HOLD VALUES AT 1V/NS (DQSX, DQSX\ AT 2V/NS) - AC/DC BASED DDR3-1333 DDR3-1600 tDS(base)AC175 Symbol - - DDR3-1866 - UNITS SV REFERENCE V,+$&9IL$& tDS(base)AC175 - - - SV V,+$&9IL$& tDS(base)DC150 30 10 10 SV V,+$&9IL$& tDS(base)DC150 SV V,+$&9IL$& TABLE 53: DERATING VALUE FOR tDS/tDH – AC175/DC100 - BASED Shaded cells indicate slew-rate combinations not supported ǻtDS, ǻtDH Derating (ps) – AC175/D100-Based DQ Slew Rate V/ns DQS, DQS# Differential Slew Rate 4.0V/ns 3.0V/ns 2.0V/ns 1.8V/ns 1.6V/ns 1.4V/ns 1.2V/ns 1.0V/ns 'tDS 'tDH 'tDS 'tDH 'tDS 'tDH 'tDS 'tDH 'tDS 'tDH 'tDS 'tDH 'tDS 'tDH 'tDS 'tDH 2.0 88 88 88 34 34 34 42 1.0 0 0 0 0 0 0 8 8 -2 -4 -2 -4 4 14 12 22 20 -10 2 -2 10 18 14 24 -3 -8 0 13 8 21 18 29 34 -1 -10 7 -2 8 23 24 -11 0.9 0.8 0.7 0.4 LOGIC Devices Incorporated www.logicdevices.com -2 10 -30 -22 -10 High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module TABLE 54: DERATING VALUE FOR tDS/tDH – AC150/DC100 - BASED Shaded cells indicate slew-rate combinations not supported ǻtDS, ǻtDH Derating (ps) – AC150/DC100-Based DQ Slew Rate V/ns DQS, DQS# Differential Slew Rate 4.0V/ns 3.0V/ns 2.0V/ns 1.8V/ns 1.6V/ns 1.4V/ns 1.2V/ns 1.0V/ns 'tDS 'tDH 'tDS 'tDH 'tDS 'tDH 'tDS 'tDH 'tDS 'tDH 'tDS 'tDH 'tDS 'tDH 'tDS 'tDH 2.0 34 34 34 42 1.0 0 0 0 0 0 0 8 8 0 -4 0 -4 8 4 12 24 20 0 -10 8 -2 24 14 32 24 8 -8 0 24 8 32 18 40 34 -10 23 -2 31 8 39 24 14 22 30 10 7 -10 0.9 0.8 0.7 0.4 TABLE 55: REQUIRED TIME tVAC ABOVE VIH(AC) (BELOW VIL[AC]) FOR A VALID TRANSITION tVAC Slew Rate (V/ns) at 175mV(ps) [MIN] tVAC at 150mV(ps) [MIN] >2.0 2.0 170 1.0 38 0.9 34 0.8 29 0.7 22 13 0 0 LOGIC Devices Incorporated www.logicdevices.com High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module FIGURE 29 - NOMINAL SLEW RATE AND tVAC FOR tDS (DQ – STROBE) CK CK# DQS# DQS t DS t DH t DS t DH VDDQ t VAC VIH(AC) MIN VREF to AC region VIH(DC) MIN Nominal slew rate VREF(DC) Nominal slew rate VIL(DC) MAX VREF to AC region VIL(AC) MAX t VAC VSS ∆TF Setup slew rate = rising signal Notes: LOGIC Devices Incorporated ∆TR VREF(DC) - VIL(AC) MAX ∆TF Setup slew rate = rising signal VIH(AC) MIN - VREF (DC) ∆TR 1. Both the clock and the strobe are drawn on different time scales. www.logicdevices.com 70 High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module FIGURE 30 - NOMINAL SLEW RATE FOR tDH (DQ – STROBE) CK CK# DQS# DQS t DS t DH t DS t DH VDDQ VIH(AC) MIN VIH(DC) MIN Nominal slew rate DC to V REF region VREF(DC) Nominal slew rate DC to V REF region VIL(DC) MAX VIL(AC) MAX VSS ∆TF ∆TR Hold slew rate = rising signal Notes: LOGIC Devices Incorporated VREF(DC) - VIL(DC) MAX ∆TR Hold slew rate = falling signal VIH(DC) MIN - V REF(DC) ∆TF 1. Both the clock and the strobe are drawn on different time scales. www.logicdevices.com 71 High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module FIGURE 31 - NOMINAL SLEW RATE AND tVAC FOR tDS (DQ – STROBE) CK CK# DQS# DQS t DS t DH t DS t DH VDDQ Nominal line t VAC VIH(AC) MIN VREF to AC region VIH(DC) MIN Tangent line VREF(DC) Tangent line VIL(DC) MAX VREF to AC region VIL(AC) MAX Nominal line t VAC ∆TR VSS Setup slew rate rising signal = Tangent line (V IH[ AC ] MIN - V REF [ DC]) ∆TR ∆TF Setup slew rate falling signal = Tangent line (V REF[ DC] - V IL[ AC] MAX) ∆TF Notes: LOGIC Devices Incorporated 1. Both the clock and the strobe are drawn on different time scales. www.logicdevices.com 72 High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module FIGURE 32 - NOMINAL SLEW RATE FOR tDH (DQ – STROBE) CK CK# DQS# DQS t DS t DH t DS t DH VDDQ VIH(AC) MIN Nominal line VIH(DC) MIN DC to VREF region Tangent line VREF(DC) DC to VREF region Tangent line Nominal line VIL(DC) MAX VIL(AC) MAX VSS ∆TR Notes: LOGIC Devices Incorporated ∆TF Tangent line (V REF[ DC] - V IL[ DC] MAX) Hol d slew rate falling signal = Hol d slew rate falling signal = ∆TR Tangent line (V IH [ DC] MIN - VREF[ DC]) ∆TF 1. Both the clock and the strobe are drawn on different time scales. www.logicdevices.com 73 High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module COMMANDS TRUTH TABLE TABLE 56: TRUTH TABLE - COMMAND PACKAGE OUTLINE DIMENSIONS CKE Function Symbol Prev Cycle Next Cycle CS\ RAS\ CAS\ WE\ BA[2:0] An A12 A10 A[11,0:0] Notes Mode Register Set MRS + + L L L L BA REFRESH 5() + + L L L + V V V V V SELF REFRESH entry 65( + L L L L + V V V V V SELF REFRESH exit 65; L + + L V + V + V + V V V V V 35( + + L L L L VBA V V L V 35($ + + L L L L V V V + V ACT + + L L L + BA WR + + L + + L BA 5)8 V L CA 8 BC4OTF WRS4 + + L + + L BA 5)8 L L CA 8 BL8OTF WRS8 + + L + + L BA 5)8 + L CA 8 BL8MRS BC4MRS :5$3 + + L + + L BA 5)8 V + CA 8 BC4OTF :5$36 + + L + + L BA 5)8 L + CA 8 BL8OTF :5$36 + + L + + L BA 5)8 + + CA 8 BL8MRS BC4MRS RD + + L + + + BA 5)8 V L CA 8 BC4OTF RDS4 + + L + + + BA 5)8 L L CA 8 BL8OTF RDS8 + + L + + + BA 5)8 + L CA 8 Single-Bank PRECHARGE PRECHARGE all banks Bank ACTIVATE BL8MRS BC4MRS WRITE WRITE with AUTO PRECHARGE READ READ with AUTO PRECHARGE CA 5'$3 + + L + + + BA 5)8 V + CA 8 BC4OTF 5'$36 + + L + + + BA 5)8 L + CA 8 BL8OTF BL8MRS BC4MRS 5'$36 + + L + + + BA 5)8 + + CA 8 NO OPERATION 123 + + L + + + V V V V V 9 Device DESELECTED '(6 + + + ; ; ; ; ; ; ; ; 3'( + + V + V + V + V 10 POWER-DOWN entry + V + V V V V V V V V V V V 12 3'; L + L + L + ZQ CALIBRATION LONG =4&/ + + L + + L ; ; ; + ; ZQ CALIBRATION SHORT =4&6 + + L + + L ; ; ; L ; POWER-DOWN exit L 127(6 1. &RPPDQGVDUHGHILQHGE\VWDWHVRI&6?5$6?&$6?:(?DQG&.(DW 8. WKHULVLQJHGJHRIWKHFORFN7KH06%RI%$5$DQG&$DUHGHYLFH GHQVLW\DQGFRQILJXUDWLRQGHSHQGHQW 2. %XUVW 5($'V RU :5,7(V FDQQRW EH WHUPLQDWHG RU LQWHUUXSWHG 056 IL[HGDQG27)%/%&DUHGHILQHGLQ05 9. 7KHSXUSRVHRIWKH123FRPPDQGLVWRSUHYHQWWKH6'5$0IURPUHJLVWHULQJDQ\XQZDQWHGFRPPDQGV$123ZLOOQRWWHUPLQDWHDQGRSHUD- 5(6(7?LV/2:HQDEOHGDQGXVHGRQO\IRUDV\QFKURQRXV5(6(77KXV WLRQWKDWLVLQH[HFXWLRQ 5(6(7?PXVWEHKHOG+,*+GXULQJDQ\QRUPDORSHUDWLRQ 3. 7KHVWDWHRI2'7GRHVQRWDIIHFWWKHVWDWHVGHVFULEHGLQWKLVWDEOH 10. 7KH'(6DQG123FRPPDQGVSHUIRUPVLPLODUO\ 4. 2SHUDWLRQVDSSO\WRWKHEDQNGHILQHGE\WKHEDQNDGGUHVV)RU056%$ 11. 7KH 32:(5'2:1 PRGH GRHV QRW SHUIRUP DQ\ 5()5(6+ RSHUDtions. VHOHFWVRQHRIIRXUPRGHUHJLVWHUV 12. =4 &$/,%5$7,21 /21* LV XVHG IRU HLWKHU =4,17 ILUVW =4&/ FRP- v9wPHDQVv+wRUv/wDGHILQHGORJLFOHYHODQGv;wPHDQVv'RQuW&DUHw 6HH7DEOHIRUDGGLWLRQDOLQIRUPDWLRQRQ&.(WUDQVLWLRQ PDQGGXULQJLQLWLDOL]DWLRQRU=423(5=4&/FRPPDQGDIWHULQLWLDOL]D- 7. 6(/)5()5(6+H[LWLVDV\QFKURQRXV WLRQ LOGIC Devices Incorporated www.logicdevices.com 74 High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module TABLE 57: TRUTH TABLE - CKE CKE Current State 3 (n-1) (n) Previous Cycle 4 Present Cycle 4 (RAS\, CAS\, WE\, CS\) Command 5 Action 5 Notes L L v'RQuW&DUHw 0DLQWDLQ32:(5'2:1 1,2 L + '(6RU123 32:(5'2:1H[LW 1,2 POWER-DOWN SELF REFRESH L L v'RQuW&DUHw 0DLQWDLQ6(/)5()5(6+ 1,2 Bank(s) ACTIVE + + '(6RU123 6(/)5()5(6+H[LW 1,2 READING + L '(6RU123 $FWLYH32:(5'2:1HQWU\ 1,2 WRITING + L '(6RU123 32:(5'2:1HQWU\ 1,2 PRECHARGING + L '(6RU123 32:(5'2:1HQWU\ 1,2 REFRESHING + L '(6RU123 35(&+$5*(32:(5'2:1HQWU\ 1,2 All Banks IDLE + L '(6RU123 35(&+$5*(32:(5'2:1HQWU\ + L 5()5(6+ 6(/)5()5(6+ 127(6 1. $OOVWDWHVDQGVHTXHQFHVQRWVKRZQDUHLOOHJDORUUHVHUYHGXQOHVVH[SOLF- 4. LWO\GHVFULEHGHOVHZKHUHLQWKLVGRFXPHQW 2. VWDWHRI&.(DWWKHSUHYLRXVFORFNHGJH t&.(0,1PHDQV&.(PXVWEHUHJLVWHUHGDWPXOWLSOHFRQVHFXWLYHSRVL- &200$1'LVWKHFRPPDQGUHJLVWHUHGDWWKHFORFNHGJHPXVWEHD WLYHFORFNHGJHV&.(PXVWUHPDLQDWWKHYDOLGLQSXWOHYHOWKHHQWLUHWLPH OHJDO FRPPDQG DV GHILQHG LQ 7DEOH $FWLRQ LV D UHVXOW RI &20- LWWDNHVWRDFKLHYHWKHUHTXLUHGQXPEHURIUHJLVWUDWLRQFORFNV7KXVDIWHU 0$1'2'7GRHVQRWDIIHFWWKHVWDWHVGHVFULEHGLQWKLVWDEOHDQGLV DQ\&.(WUDQVLWLRQ&.(PD\QRWWUDQVLWLRQIURPLWVYDOLGOHYHOGXULQJWKH WLPHSHULRGRIt,6t&.(0,1t,+ 3. &.(QLVWKHORJLFVWDWHRI&.(DWFORFNHGJHQ&.(QZDVWKH not listed. ,GOHVWDWH DOOEDQNVDUHFORVHGQRGDWDEXUVWVDUHLQSURJUHVV&.(LV &XUUHQWVWDWH 7KHVWDWHRIWKH6'5$0LPPHGLDWHO\SULRUWRFORFNHGJH +,*+DQGDOOWLPLQJVIURPSUHYLRXVRSHUDWLRQVDUHVDWLVILHG$OO6(/) n. 5()5(6+H[LWDQG32:(5'2:1H[LWSDUDPHWHUVDUHDOVRVDWLVILHG NO OPERATION (NOP) DESELECT (DES) 7KH'(6FRPPDQG&6?+,*+SUHYHQWVQHZFRPPDQGVIURPEHLQJH[HFXWHGE\WKH6'5$02SHUDWLRQVDOUHDG\LQSURJUHVVDUHQRWDIIHFWHG 7KH123FRPPDQG&6?/2:SUHYHQWVXQZDQWHGFRPPDQGVIURPEHLQJ UHJLVWHUHG GXULQJ LGOH RU ZDLW VWDWHV 2SHUDWLRQV DOUHDG\ LQ SURJUHVV DUH QRWDIIHFWHG ZQ CALIBRATION ZQ Calibration LONG (ZQCL) 7KH=4&/FRPPDQGLVXVHGWRSHUIRUPWKHLQLWLDOFDOLEUDWLRQGXULQJDSRZHUXSLQLWLDOL]DWLRQDQGUHVHWVHTXHQFH7KLVFRPPDQGPD\EHLVVXHGDWDQ\WLPHE\ WKHFRQWUROOHUGHSHQGLQJRQWKHV\VWHPHQYLURQPHQW7KH=4&/FRPPDQGWULJJHUVWKHFDOLEUDWLRQHQJLQHLQVLGHWKH6'5$0$IWHUFDOLEUDWLRQLVDFKLHYHGWKH FDOLEUDWHGYDOXHVDUHWUDQVIHUUHGIURPWKHFDOLEUDWLRQHQJLQHWRWKH6'5$0,2ZKLFKDUHUHIOHFWHGDVXSGDWHG5ON and ODT values. 7KH6'5$0LVDOORZHGDWLPLQJZLQGRZGHILQHGE\HLWKHU t=4,1,7RU t=423(5WRSHUIRUPWKHIXOOFDOLEUDWLRQDQGWUDQVIHURIYDOXHV:KHQ=4&/LVLVVXHG GXULQJWKHLQLWLDOL]DWLRQVHTXHQFHWKHWLPLQJSDUDPHWHUW=4,1,7PXVWEHVDWLVILHG:KHQLQLWLDOL]DWLRQLVFRPSOHWHVXEVHTXHQW=4&/FRPPDQGVUHTXLUHWKH WLPLQJSDUDPHWHUt=423(5WREHVDWLVILHG ZQ Calibration SHORT (ZQCS) 7KH=4&6FRPPDQGLVXVHGWRSHUIRUPSHULRGLFFDOLEUDWLRQVWRDFFRXQWIRUVPDOOYROWDJHDQGWHPSHUDWXUHYDULDWLRQV7KHVKRUWHUWLPLQJZLQGRZLVSURYLGHG WRSHUIRUPWKHUHGXFHGFDOLEUDWLRQDQGWUDQVIHURIYDOXHVDVGHILQHGE\WLPLQJSDUDPHWHUt=4&6$=4&6FRPPDQGFDQHIIHFWLYHO\FRUUHFWDPLQLPXPRI RON and RTTLPSHGDQFHHUURUVZLWKLQFORFNF\FOHVDVVXPLQJWKHPD[LPXPVHQVLWLYLWLHVVSHFLILHGLQ7DEOHDQG7DEOH LOGIC Devices Incorporated www.logicdevices.com High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module ACTIVATE READ 7KH $&7,9$7( FRPPDQG LV XVHG WR RSHQ RU $&7,9$7( D URZ LQ D SDUWLFXODU EDQN IRU D VXEVHTXHQW DFFHVV 7KH YDOXH RQ WKH %$ >@ LQSXWVVHOHFWVWKHEDQNDQGWKHDGGUHVVSURYLGHGRQLQSXWV$>Q@VHOHFWV WKHURZ7KLVURZUHPDLQVRSHQRU$&7,9(IRUDFFHVVHVXQWLOD35(&+$5*(FRPPDQGLVLVVXHGWRWKDWEDQN 7KH5($'FRPPDQGLVXVHGWRLQLWLDWHDEXUVW5($'DFFHVVWRDQ$&7,9( URZ 7KH DGGUHVV SURYLGHG RQ LQSXWV $>@ VHOHFWV WKH VWDUWLQJ FROXPQ DGGUHVVGHSHQGLQJRQWKHEXUVWOHQJWKDQGEXUVWW\SHVHOHFWHGVHHWDEOH 7KHYDOXHRQLQSXW$GHWHUPLQHVZKHWKHURUQRWDXWRSUHFKDUJHLV XVHG,IDXWRSUHFKDUJHLVVHOHFWHGWKHURZEHLQJDFFHVVHGZLOOEH35(&+$5*('DWWKHHQGRIWKH5($'EXUVW,I$87235(&+$5*(LVQRW VHOHFWHGWKHURZZLOOUHPDLQRSHQIRUVXEVHTXHQWDFFHVVHV7KHYDOXHRQ LQSXW$LIHQDEOHGLQWKH02'(5(*,67(5ZKHQWKH5($'FRPPDQG LVLVVXHGGHWHUPLQHVZKHWKHU%&FKRSRU%/LVXVHG$IWHUD5($' FRPPDQGLVLVVXHGWKH5($'EXUVWPD\QRWEHLQWHUUXSWHG$VXPPDU\ RI5($'FRPPDQGVLVVKRZQLQ7DEOH $35(&+$5*(FRPPDQGPXVWEHLVVXHGEHIRUHRSHQLQJDGLIIHUHQWURZ LQWKHVDPHEDQN TABLE 58: READ COMMAND SUMMARY CKE Function READ READ with AUTO PRECHARGE Symbol Prev Cycle Next Cycle CS\ RAS\ CAS\ WE\ + L + L + BA 5)8 + L + L + BA RDS8 + L + L + BA BL8MRS BC4MRS 5'$3 + L + L + BC4OTF 5'$36 + L + L + BL8OTF 5'$36 + L + L + BL8MRS BC4MRS RD BC4OTF RDS4 BL8OTF BA[2:0] An A12 A10 A[11,0:0] Notes V L CA 5)8 L L CA 5)8 + L CA BA 5)8 V + CA BA 5)8 L + CA BA 5)8 + + CA WRITE 7KH:5,7(FRPPDQGLVXVHGWRLQLWLDWHDEXUVW:5,7(DFFHVVWRDQ$&7,9(URZ7KHYDOXHRQWKH%$>@LQSXWVVHOHFWVWKHEDQN7KHYDOXHRQLQSXW$ GHWHUPLQHVZKHWKHURUQRW$87235(&+$5*(LVXVHG7KHYDOXHRQLQSXW$LIHQDEOHGLQWKH02'(5(*,67(5>05@ZKHQWKH:5,7(FRPPDQGLV LVVXHGGHWHUPLQHVZKHWKHU%&FKRSRU%/LVXVHG7KH:5,7(FRPPDQGVXPPDU\LVVKRZQLQ7DEOH TABLE 59: WRITE COMMAND SUMMARY CKE Function Symbol BL8MRS BC4MRS WRITE WRITE with AUTO PRECHARGE WR Prev Cycle Next Cycle CS\ RAS\ CAS\ WE\ BA[2:0] An A12 A10 A[11,0:0] Notes + L + L L BA 5)8 V L CA + BC4OTF WRS4 + L L L BA 5)8 L L CA BL8OTF WRS8 + L + L L BA 5)8 + L CA + BL8MRS BC4MRS :5$3 + L L L BA 5)8 V + CA BC4OTF :5$36 + L + L L BA 5)8 L + CA + L + L L BA 5)8 + + CA BL8OTF LOGIC Devices Incorporated :5$36 www.logicdevices.com High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module PRECHARGE REFRESH 7KH35(&+$5*(FRPPDQGLVXVHGWR'($&7,9$7(WKHRSHQURZLQD SDUWLFXODUEDQNRULQDOOEDQNV7KHEDQNVDUHDYDLODEOHIRUDVXEVHTXHQW URZDFFHVVDWDVSHFLILHGWLPHt53DIWHUWKH35(&+$5*(FRPPDQGLV LVVXHGH[FHSWLQWKHFDVHRIFRQFXUUHQW$87235(&+$5*($5($'RU :5,7(FRPPDQGWRDGLIIHUHQWEDQNLVDOORZHGGXULQJFRQFXUUHQW$872 35(&+$5*(DVORQJDVLWGRHVQRWLQWHUUXSWWKHGDWDWUDQVIHULQWKHFXUUHQWEDQNDQGGRHVQRWYLRODWHDQ\RWKHUWLPLQJSDUDPHWHUV,QSXW$ GHWHUPLQHVZKHWKHURQHRUDOOEDQNVDUHSUHFKDUJHG,QWKHFDVHZKHUH RQO\RQHEDQNLVUHFKDUJHG,QSXWV%$>@VHOHFWWKHEDQNRWKHUZLVH %$>@DUHWUHDWHGDVv'RQuW&DUHw$IWHUDEDQNLV35(&+$5*('LWLV LQWKHLGOHVWDWHDQGPXVWEHDFWLYDWHGSULRUWRDQ\5($'RU:5,7(FRPPDQGVEHLQJLVVXHGWRWKDWEDQN$35(&+$5*(FRPPDQGLVWUHDWHG DVD123LIWKHUHLVQRRSHQURZLQWKDWEDQNLGOHVWDWHRULIWKHSUHYLRXVO\RSHQURZLVDOUHDG\LQWKHSURFHVVRISUHFKDUJLQJ+RZHYHUWKH 35(&+$5*(SHULRGLVGHWHUPLQHGE\WKHODVW35(&+$5*(FRPPDQG LVVXHGWRWKHEDQN 5()5(6+LVXVHGGXULQJQRUPDORSHUDWLRQRIWKH6'5$0DQGLVDQDORJRXV WR&$6?EHIRUH5$6?&%5UHIUHVKRU$8725()5(6+7KLVFRPPDQG LVQRQSHUVLVWHQWVRLWPXVWEHLVVXHGHDFKWLPHD5()5(6+LVUHTXLUHG 7KH DGGUHVVLQJ LV JHQHUDWHG E\ WKH LQWHUQDO 5()5(6+ FRPPDQG 7KH 6'5$0UHTXLUHV5()5(6+F\FOHVDWDQDYHUDJHLQWHUYDORIVPD[LPXPZKHQ7Ad&RUV0$;ZKHQ7Ad&7KH5()5(6+SHULRG EHJLQVZKHQWKH5()5(6+FRPPDQGLVUHJLVWHUHGDQGHQGV t5)&0,1 later. 7RDOORZIRULPSURYHGHIILFLHQF\LQVFKHGXOLQJDQGVZLWFKLQJEHWZHHQWDVNV VRPHIOH[LELOLW\LQWKHDEVROXWH5()5(6+LQWHUYDOLVSURYLGHG$PD[LPXP RIHLJKW5()5(6+FRPPDQGVFDQEHSRVWHGWRDQ\JLYHQ6'5$0PHDQLQJWKDWWKHPD[LPXPDEVROXWHLQWHUYDOEHWZHHQDQ\5()5(6+FRPPDQG DQG WKH QH[W 5()5(6+ FRPPDQG LV QLQH WLPHV WKH PD[LPXP DYHUDJH LQWHUYDO UHIUHVK UDWH 6(/) 5()5(6+ PD\ EH HQWHUHG ZLWK XS WR HLJKW 5()5(6+FRPPDQGVEHLQJSRVWHG$IWHUH[LWLQJ6(/)5()5(6+ZKHQ HQWHUHGZLWKSRVWHG5()5(6+FRPPDQGVDGGLWLRQDOSRVWLQJRI5()5(6+ FRPPDQGV LV DOORZHG WR WKH H[WHQW WKH PD[LPXP QXPEHU RI FXPXODWLYH SRVWHG5()5(6+FRPPDQGVERWKSUHDQGSRVW6(/)5()5(6+GRHV QRWH[FHHGHLJKW5()5(6+FRPPDQGV FIGURE 33 - REFRESH MODE T0 T2 T1 T3 T4 Ta0 Ta1 Tb0 Tb1 Valid 1 Valid 1 NOP1 NOP1 Tb2 CK# CK t CK t CH t CL Valid 1 CKE Command NOP 1 PRE NOP 1 NOP 1 REF NOP 1 REF 2 ACT Address RA All banks A10 RA One bank Bank(s) 3 BA[2:0] BA DQS, DQS# 4 DQ4 DM 4 t RP t RFC (MIN) t RFC 2 Indicates A Break in Time Scale Notes: LOGIC Devices Incorporated Don’t Care 1. NOP commands are shown for ease of illustration; other valid commands may be possible at these times. CKE must be active during the PRECHARGE, ACTIVATE, and REFRESH commands, but may be inactive at other times (see “Power-Down Mode” on page 153). www.logicdevices.com 77 High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module SELF REFRESH 7KH6(/)5()5(6+FRPPDQGLVXVHGWRUHWDLQGDWDLQWKH6'5$0HYHQLIWKHUHVWRIWKHV\VWHPLVSRZHUHGGRZQ:KHQLQWKH6(/)5()5(6+PRGHWKH 6'5$0UHWDLQVGDWDZLWKRXWH[WHUQDOFORFNLQJ7KH6(/)5()5(6+PRGHLVDOVRDFRQYHQLHQWPHWKRGXVHGWRHQDEOHGLVDEOHWKH'//DVZHOODVWRFKDQJH WKHFORFNIUHTXHQF\ZLWKLQWKHDOORZHGV\QFKURQRXVRSHUDWLQJUDQJH$OOSRZHUVXSSO\LQSXWVLQFOXGLQJ95()&$ and V5()'4PXVWEHPDLQWDLQHGDWYDOLGOHYHOV XSRQHQWU\H[LWDQGGXULQJ6(/)5()5(6+PRGHRSHUDWLRQ$OOSRZHUVXSSO\LQSXWVLQFOXGLQJ95()&$and V5()'4PXVWEHPDLQWDLQHGDWYDOLGOHYHOVXSRQ HQWU\H[LWDQGGXULQJ6(/)5()5(6+PRGHXQGHUFHUWDLQFRQGLWLRQV x9VV95()'4< VDDLVPDLQWDLQHG x95()'4LVYDOLGDQGVWDEOHSULRUWR&.(JRLQJEDFN+,*+ x7KHILUVW:5,7(RSHUDWLRQPD\QRWRFFXUHDUOLHUWKDQFORFNVDIWHU95()'4 is valid x$OORWKHU6(/)5()5(6+PRGHH[LWWLPHUHTXLUHPHQWVDUHPHW DLL DISABLE MODE ,IWKH'//LVGLVDEOHGE\WKH02'(5(*,67(505>@FDQEHVZLWFKHGGXULQJLQLWLDOL]DWLRQRUODWHUWKH6'5$0LVWDUJHWHGEXWQRWJXDUDQWHHGWRRSHUDWH VLPLODUO\WRWKH1250$/PRGHZLWKDIHZQRWDEOHH[FHSWLRQV x x x 7KH6'5$0VXSSRUWVRQO\RQHYDOXHRI&$6ODWHQF\&/ DQGRQHYDOXHRI&$6:5,7(ODWHQF\&:/ '//',6$%/(PRGHDIIHFWVWKH5($'GDWDFORFNWRGDWDVWUREHUHODWLRQVKLSt'46&.EXWQRWWKH5($'GDWDWRGDWDVWUREHUHODWLRQVKLS (tDQSQ, t4+6SHFLDODWWHQWLRQLVQHHGHGWROLQHWKH5($'GDWDXSZLWKWKHFRQWUROOHUWLPHGRPDLQZKHQWKH'//LVGLVDEOHG ,Q1250$/RSHUDWLRQ'//RQ t'46&.VWDUWVIURPWKHULVLQJFORFNHGJH$/&/F\FOHVDIWHUWKH5($'FRPPDQG,Q'//',6$%/( PRGH t'46&.VWDUWV$/ &/yF\FOHVDIWHUWKH5($'FRPPDQG$GGLWLRQDOO\ZLWKWKH'//GLVDEOHGWKHYDOXHRI t'46&.FRXOGEH ODUJHUWKDQtCK. 7KH2'7IHDWXUHLVQRWVXSSRUWHGGXULQJ'//',6$%/(PRGHLQFOXGLQJG\QDPLF2'77KH2'7UHVLVWRUVPXVWEHGLVDEOHGE\FRQWLQXRXVO\UHJLVWHULQJWKH 2'7EDOO/2:E\SURJUDPPLQJ5TTB125005>@DQG5TTB:505>@WRvwZKLOHLQ'//',6$%/(PRGH 6SHFLILFVWHSVPXVWEHIROORZHGWRVZLWFKEHWZHHQWKH'//HQDEOHDQG'//',6$%/(PRGHVGXHWRDJDSLQWKHDOORZHGFORFNUDWHVEHWZHHQWKHWZRPRGHV (t&.>$9*@0$;DQG t&.>'//',6$%/(@0,1UHVSHFWLYHO\7KHRQO\WLPHWKHFORFNLVDOORZHGWRFURVVWKLVFORFNUDWHJDSLVGXULQJ6(/)5()5(6+PRGH 7KXVWKHUHTXLUHGSURFHGXUHIRUVZLWFKLQJIURPWKH'//(1$%/(WR'//',6$%/(PRGHLVWRFKDQJHIUHTXHQF\FXULQJVHOIUHIUHVKVHH)LJXUH 1. 2. 3. 4. 6WDUWLQJIURPWKH,'/(VWDWHDOOEDQNVDUH35(&+$5*('DOOWLPLQJVDUHIXOILOOHG2'7LVWXUQHGRIIDQG5TT_NOM and RTT_WR are +,*+=VHW05>@WRvwWR',6$%/(WKH'// (QWHU6(/)5()5(6+PRGHDIWHUt02'KDVEHHQVDWLVILHG After t&.65(LVVDWLVILHGFKDQJHWKHIUHTXHQF\WRWKHGHVLUHGFORFNUDWH 6(/)5()5(6+PD\EHH[LWHGZKHQWKHFORFNLVVWDEOHGZLWKWKHQHZIUHTXHQF\IRUt&.65; 7KH6'5$0ZLOOEHUHDG\IRULWVQH[WFRPPDQGLQWKH'//',6$%/(PRGHDIWHUWKHJUHDWHURItMRD or t02'KDVEHHQVDWLVILHG$=4&/ FRPPDQGVKRXOGEHLVVXHGZLWKDSSURSULDWHWLPLQJPHWDVZHOO LOGIC Devices Incorporated www.logicdevices.com 78 High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module FIGURE 34 - DLL ENABLE MODE TO DLL DISABLE MODE T0 T1 Ta0 Ta1 Tb0 Tc0 Td0 Td1 Te0 Te1 Tf0 CK# CK Vali d 1 CKE Command MRS2 6 NOP SRE 3 t MOD SRX 4 NOP t CKSRE t CKSRX 8 7 NOP MRS5 NOP Vali d 1 t MOD t XS t CKESR ODT 9 Vali d 1 Indicates a Break in Time Scale 127(6 1. $Q\YDOLGFRPPDQG 2. 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After t&.65(LVVDWLVILHGFKDQJHWKHIUHTXHQF\WRWKHQHZFORFNUDWH 6HOIUHIUHVKPD\EHH[LWHGZKHQWKHFORFNLVVWDEOHZLWKWKHQHZIUHTXHQF\IRUt&.65;$IWHUt;6LVVDWLVILHGXSGDWHWKHPRGHUHJLVWHUV ZLWKWKHDSSURSULDWHYDOXHV$WDPLQLPXPVHW05>@WRvwWRHQDEOHWKH'//:DLWt05'WKHQVHW05>@WRvwWRHQDEOH'//5(6(7 $IWHUDQRWKHUt05'GHOD\LVVDWLVILHGWKHQXSGDWHWKHUHPDLQLQJPRGHUHJLVWHUVZLWKWKHDSSURSULDWHYDOXHV 7KH'5$0ZLOOEHUHDG\IRULWVQH[WFRPPDQGLQWKH'//HQDEOHPRGHDIWHUWKHJUHDWHURItMRD or t02'KDVEHHQVDWLVILHG+RZHYHU EHIRUHDSSO\LQJDQ\FRPPDQGRUIXQFWLRQUHTXLULQJDORFNHG'//DGHOD\RIt'//.DIWHU'//5(6(7PXVWEHVDWLVILHG$=4&/FRPPDQG VKRXOGEHLVVXHGZLWKWKHDSSURSULDWHWLPLQJVPHWDVZHOO LOGIC Devices Incorporated www.logicdevices.com 79 High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module FIGURE 35- DLL DISABLE MODE TO DLL ENABLE MODE T0 Ta0 Ta1 Tb0 Tc0 Tc1 Td0 Te0 Tf0 Tg0 Th0 CK# CK CKE Vali d t DLLK Command SRE1 NOP SRX2 NOP t CKSRE 7 t CKSRX 9 8 MRS3 t XS MRS4 t MRD MRS5 Vali d 6 t MRD ODTL off + 1 × t CK t CKESR ODT10 Indicates a Break in Time Scale Don ’t Care 127(6 1. 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Wait t05'WKHQVHW05>@WRvwWREHJLQ'//5(6(7 Wait t05'XSGDWHUHJLVWHUV&/&:/DQGZULWHUHFRYHU\PD\EHQHFHVVDU\ Wait t02'DQ\YDOLGFRPPDQG 7. 6WDUWLQJZLWKWKHLGOHVWDWH 8. &KDQJHIUHTXHQF\ 9. &ORFNPXVWEHVWDEOHDWOHDVWt&.65; 10. 6WDWLF/2:LQFDVH5TT_NOM or RTTB:5LVHQDEOHGRWKHUZLVHVWDWLF/2:RU+,*+ 7KHFORFNIUHTXHQF\UDQJHIRUWKH'//GLVDEOHPRGHLVVSHFLILHGE\WKHSDUDPHWHU t&.'//B',6'XHWRODWHQF\FRXQWHUDQGWLPLQJUHVWULFWLRQVRQO\&/ DQG&:/ DUHVXSSRUWHG '//GLVDEOHPRGHZLOODIIHFWWKHUHDGGDWDFORFNWRGDWDVWUREHUHODWLRQVKLSt'46&.EXWQRWWKHGDWDVWUREHWRGDWDUHODWLRQVKLStDQSQ, t4+6SHFLDODWWHQWLRQLVQHHGHGWRWKHFRQWUROOHUWLPHGRPDLQ &RPSDUHGWRWKH'//RQPRGHZKHUH t'46&.VWDUWVIURPWKHULVLQJFORFNHGJH$/&/F\FOHVDIWHUWKH5($'FRPPDQGWKH'//GLVDEOHPRGH tDQSCK VWDUWV$/&/F\FOHVDIWHUWKH5($'FRPPDQGVHH)LJXUHRQSDJH :5,7(RSHUDWLRQVIXQFWLRQVLPLODUO\EHWZHHQWKH'//HQDEOHDQG'//GLVDEOHPRGHVKRZHYHU2'7IXQFWLRQDOLW\LVQRWDOORZHGZLWK'//GLVDEOHPRGH LOGIC Devices Incorporated www.logicdevices.com 80 High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module FIGURE 36 - DLL DISABLE tDQSCK TIMING T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 READ NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP CK# CK Command Add ress Vali d RL = AL + C L = 6 (C L = 6, AL = 0) CL = 6 DQS, DQS# DLL on DI b DQ BL8 DLL on DI b+1 DI b+2 DI b+3 DI b+4 DI b+5 DI b+6 DI b+7 RL (DLLdisable) = AL + (C L - 1) = 5 t DQSCK (DLL_DIS) MIN DQS, DQS# DLL off DI b DQ BL8 DLL disable DI b+1 DI b+2 DI b+3 DI b+4 DI b+5 DI b+6 DI b+7 DI b+3 DI b+4 DI b+5 DI b+6 t DQSCK (DLL_ DIS) MAX DQS, DQS# DLL off DI b DQ BL8 DLL disable DI b+1 DI b+2 Transitioning Data DI b+7 Don ’t Care INPUT CLOCK FREQUENCY CHANGE :KHQWKH''56'5$0LVLQLWLDOL]HGLWUHTXLUHVWKHFORFNWREHVWDEOHGXULQJPRVW1250$/VWDWHVRIRSHUDWLRQ7KLVPHDQVWKDWDIWHUWKHFORFNIUHTXHQF\ KDVEHHQVHWWRWKHVWDEOHVWDWHWKHFORFNSHULRGLVQRWDOORZHGWRGHYLDWHH[FHSWZKDWLVDOORZHGIRUE\WKHFORFNMLWWHUDQGVSUHDGVSHFWUXPFORFNLQJ66& VSHFLILFDWLRQV 7KHLQSXWFORFNIUHTXHQF\FDQEHFKDQJHGIURPRQHVWDEOHFORFNUDWHWRDQRWKHUXQGHUWZRFRQGLWLRQV6(/)5()5(6+PRGHDQG35(&+$5*(SRZHUGRZQ PRGH2XWVLGHRIWKHVHWZRPRGHVLWLVLOOHJDOWRFKDQJHWKHFORFNIUHTXHQF\)RUWKH6(/)5()5(6+PRGHFRQGLWLRQZKHQWKH''56'5$0KDVEHHQ VXFFHVVIXOO\SODFHGLQWR6(/)5()5(6+PRGHDQG t&.65(KDVEHHQVDWLVILHGWKHVWDWHRIWKHFORFNEHFRPHVDv'RQuW&DUHw:KHQWKHFORFNEHFRPHVD v'RQuW&DUHwFKDQJLQJWKHFORFNIUHTXHQF\LVSHUPLVVLEOHSURYLGHGWKHQHZFORFNIUHTXHQF\LVVWDEOHSULRUWRt&.65;:KHQHQWHULQJDQGH[LWLQJVHOIUHIUHVK PRGHIRUWKHVROHSXUSRVHRIFKDQJLQJWKHFORFNIUHTXHQF\WKH6(/)5()5(6+HQWU\DQGH[LWVSHFLILFDWLRQVPXVWVWLOOEHPHW 7KH35(&+$5*(SRZHUGRZQPRGHFRQGLWLRQLVZKHQWKH''56'5$0LVLQ35(&+$5*(SRZHUGRZQPRGHHLWKHUIDVWH[LWPRGHRUVORZH[LWPRGH (LWKHU2'7PXVWEHDWDORJLF/2:RU5TT_NOM and RTTB:5PXVWEHGLVDEOHGYLD05DQG057KLVHQVXUHV5TT_NOM and RTT_WR are in an off state SULRUWRHQWHULQJ35(&+$5*(SRZHUGRZQPRGHZKLOHPDLQWDLQLQJ&.(DWDORJLF/2:$PLQLPXPRIt&.65(PXVWRFFXUDIWHU&.(JRHV/2:EHIRUHWKH FORFNIUHTXHQF\FDQFKDQJH7KH''56'5$0LQSXWFORFNIUHTXHQF\LVDOORZHGWRFKDQJHRQO\ZLWKLQWKHPLQLPXPDQGPD[LPXPRSHUDWLQJIUHTXHQF\VSHFLILHGIRUWKHSDUWLFXODUVSHHGWHPSHUDWXUHJUDGHtCK [AVG] MIN to t&.>$9*@0$;GHYLFH'XULQJWKHLQSXWFORFNIUHTXHQF\FKDQJH&.(PXVWEHKHOGDWD VWDEOH/2:OHYHO:KHQWKHLQSXWFORFNIUHTXHQF\LVFKDQJHGDVWDEOHFORFNPXVWEHSURYLGHGWRWKH6'5$0t&.65;EHIRUH35(&+$5*(SRZHUGRZQPD\ EHH[LWHG$IWHU35(&+$5*(SRZHUGRZQLVH[LWHGDQGt;3KDVEHHQVDWLVILHGWKH'//PXVWEHUHVHWYLDWKH056'HSHQGLQJRQWKHQHZFORFNIUHTXHQF\ DGGLWLRQDO056FRPPDQGVPD\QHHGWREHLVVXHG'XULQJWKH'//ORFNWLPH5TT_NOM and RTTB:5PXVWUHPDLQLQDQRIIVWDWH$IWHUWKH'//ORFNWLPH WKH6'5$0LVUHDG\WRRSHUDWHZLWKDQHZFORFNIUHTXHQF\SHULRG7KLVSURFHVVLVGHSLFWHGLQ)LJXUH LOGIC Devices Incorporated www.logicdevices.com 81 High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module FIGURE 37- CHANGE FREQUENCY DURING PRECHARGE POWER-DOWN Previous clock frequency T0 T1 T2 New clock fre quency Ta0 Tb0 Tc1 Tc0 Td0 Td1 Te0 Te1 CK# CK t CH t CL t CH t CK t CK t CKSRE t IS t IH t CH b t CK b t CL b t CH b b b t CL t CK b b t CKSRX t CKE t IH CKE t IS t CPDED Command t CL b NOP NOP NOP NOP NOP Address MRS NOP Valid DLL RESET t AOFPD/ t AOF t XP Valid t IH t IS ODT DQS, DQS# High-Z High-Z DQ DM t DLLK Enter precharge power-down mode Frequency change Exit precharge power-down mode Indicates a Break in Time Scale Don’t Care 127(6 1. $SSOLFDEOHIRUERWKVORZH[LWDQGIDVWH[LWSUHFKDUJHSRZHUGRZQPRGHV 2. t$2)3' DQG t$2) PXVW EH VDWLVILHG DQG RXWSXWV +LJK= SULRU WR 7 VHH v2Q'LH 7HUPLQDWLRQ 2'7wRQSDJHIRUH[DFWUHTXLUHPHQWV 3. ,IWKH5TTB120IHDWXUHZDVHQDEOHGLQWKHPRGHUHJLVWHUSULRUWRHQWHULQJSUHFKDUJHSRZHUGRZQ PRGH WKH 2'7 VLJQDO PXVW EH FRQWLQXRXVO\ UHJLVWHUHG /2: HQVXULQJ 5TT is in an off state. If WKH5TTB120IHDWXUHZDVGLVDEOHGLQWKHPRGHUHJLVWHUSULRUWRHQWHULQJSUHFKDUJHSRZHUGRZQ PRGH5TTZLOOUHPDLQLQWKHRIIVWDWH7KH2'7VLJQDOFDQEHUHJLVWHUHGHLWKHU/2:RU+,*+LQ WKLVFDVH LOGIC Devices Incorporated www.logicdevices.com 82 High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module WRITE LEVELING )RUEHWWHUVLJQDOLQWHJULW\''56'5$0PHPRU\VXEV\VWHPGHVLJQVKDYHDGRSWHGXVHRIIO\E\WRSRORJ\IRUWKHFRPPDQGVDGGUHVVHVFRQWUROVLJQDOVDQG FORFNV:5,7(OHYHOLQJLVDVFKHPHIRUWKHPHPRU\FRQWUROOHUWRGHVNHZWKH'46[VWUREH'46['46[?WR&.UHODWLRQVKLSDWWKH6'5$0ZLWKDVLPSOH IHHGEDFNIHDWXUHSURYLGHGLWE\WKH''56'5$0LWVHOI:5,7(OHYHOLQJLVJHQHUDOO\XVHGDVSDUWRIWKHLQLWLDOL]DWLRQSURFHVVLIUHTXLUHG)RU1250$/ 6'5$0RSHUDWLRQWKLVIHDWXUHPXVWEHGLVDEOHG7KLVLVWKHRQO\6'5$0RSHUDWLRQZKHUHWKH'46IXQFWLRQVDVDQLQSXWWRFDSWXUHWKHLQFRPLQJFORFNDQG WKH'4VIXQFWLRQDVRXWSXWVWRUHSRUWWKHVWDWRIWKHFORFN1RWHWKDWQRQVWDQGDUG2'7VFKHPHVDUHUHTXLUHG 7KHPHPRU\FRQWUROOHUXVLQJWKH:5,7(OHYHOLQJSURFHGXUHPXVWKDYHDGMXVWDEOHGHOD\VHWWLQJRQLWV'46VWUREHWRDOLJQWKHULVLQJHGJHRI'46WRWKHFORFN DWWKH6'5$0SLQV7KLVLVDFFRPSOLVKHGZKHQWKH6'5$0DV\QFKURQRXVO\IHHGVEDFNWKH&.VWDWXVYLDWKH'4EXVDQGVDPSOHVZLWKWKHULVLQJHGJHRI '467KHFRQWUROOHUUHSHDWHGO\GHOD\VWKH'46VWUREHXQWLOD&.WUDQVLWLRQIURPvwWRvwLVGHWHFWHG7KH'46GHOD\HVWDEOLVKHGWKURXJKWKLVSURFHGXUH KHOSVHQVXUHtDQSS, tDSS, and t'6+VSHFLILFDWLRQVLQV\VWHPVWKDWXVHIO\E\WRSRORJ\E\GHVNHZLQJWKHWUDFHOHQJWKPLVPDWFK$FRQFHSWXDOWLPLQJRIWKLV SURFHGXUHLVVKRZQLQ)LJXUH FIGURE 38- WRITE LEVELING CONCEPT T0 T1 T2 T3 T4 T5 T6 T7 CK# CK Source Differential DQS Tn T0 T1 T2 T3 T4 T5 T6 T4 T5 CK# CK Destination Differential DQS 0 DQ Destination Tn T0 T1 0 T2 T3 T6 CK# CK Push DQS to capture 0–1 transition Differential DQS 1 DQ 1 Don’t Care LOGIC Devices Incorporated www.logicdevices.com 83 High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module WRITE LEVELING :KHQ:5,7(OHYHOLQJLVHQDEOHGWKHULVLQJHGJHRI'46VDPSOHV&.DQGWKHULPH'4RXWSXWVWKHVDPSOHG&.uVVWDWXV7KHSULPH'4IRUHDFKRIWKH ZRUGVFRQWDLQHGLQWKHL02'LV'4IRUWKHORZE\WH'4IRUWKHKLJKE\WH,WRXWSXWVWKHVWDWXVRI&.VDPSOHGE\/'46[DQG8'46[$OORWKHU'4V '4>@'4>@IRUWKHORZZRUG'4>@'4>@IRUWKHQH[WZRUG'4>@'4>@IRUWKHQH[WDQG'4>@'4>@IRUWKH+,*+ZRUG FRQWLQXHWRGULYH/2:7ZRSULPH'4RQHDFKRIWKHZRUGVFRQWDLQHGLQWKH/',L02'DOORZHDFKE\WHODQHWREHOHYHOHGLQGHSHQGHQWO\ WRITE LEVELING PROCEDURE $PHPRU\FRQWUROOHULQLWLDWHVWKH6'5$0:5,7(/HYHOLQJPRGHE\VHWWLQJWKH05>@WRDvwDVVXPLQJWKHRWKHUSURJUDPPDEOHIHDWXUHV050505 DQG05DUHILUVWVHWDQGWKH'//LVIXOO\UHVHWDQGORFNHG7KH'4EDOOVHQWHUWKH:5,7(/HYHOLQJPRGHJRLQJIURPDv+,*+=wVWDWHWRDQXQGHILQHGGULYLQJVWDWHVRWKH'4EXVVKRXOGQRWEHGULYHQ'XULQJ:5,7(/HYHOLQJPRGHRQO\WKH123DQG'(6FRPPDQGVDUHDOORZHG7KHPHPRU\FRQWUROOHUVKRXOG DWWHPSWWROHYHORQO\RQHUDQNDWDWLPHWKXVWKHRXWSXWVRIRWKHUUDQNVVKRXOGEHGLVDEOHGE\VHWWLQJ05>@WRDvw7KHPHPRU\FRQWUROOHUPD\DVVHUW ODT after a t02'GHOD\DVWKH6'5$0ZLOOEHUHDG\WRSURFHVVWKH2'7/RQGHOD\:/t&.SURYLGHGLWGRHVQRWYLRODWHWKHDIRUHPHQWLRQHG t02'GHOD\ UHTXLUHPHQW 7KHPHPRU\FRQWUROOHUPD\GULYH/'46[8'46[/2:DQG/'46[?8'46[?+,*+DIWHUt:/'46(1KDVEHHQVDWLVILHG7KHFRQWUROOHUPD\EHJLQWRWRJJOH /'46[8'46[DIWHUt:/05'RQH/>8@'46VWRJJOHLV'46VWUDQVLWLRQLQJIURPD/2:VWDWHWRD+,*+VWDWHZLWK/>8@'46[?WUDQVLWLRQLQJIURPD+,*+VWDWH WRD/2:VWDWHWKHQERWKWUDQVLWLRQEDFNWRWKHLURULJLQDOVWDWHV$WDPLQLPXP2'7/RQDQGt$21PXVWEHVDWLVILHGDWOHDVWRQHFORFNSULRUWR'46WRJJOLQJ After t:/05'DQG'46/2:SUHDPEOHt:35(KDYHEHHQVDWLVILHGWKHPHPRU\FRQWUROOHUPD\SURYLGHHLWKHUDVLQJOH'46[WRJJOHRUPXOWLSOH'46[WRJJOHV WRVDPSOH&.IRUDJLYHQ'46[WR&.VNHZ(DFK'46WRJJOHPXVWQRWYLRODWHt'46/0,1DQGt'46+0,1VSHFLILFDWLRQVt'46/0$;DQGt'46+0$; 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The DQ result, “= 1,” between Ta0 and Tc0, is a result of the DQS, DQS# signals capturing CK HIGH just after the T0 state. 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SEQUENCE T (MAX) = 200ms VDD VDDQ VTT See power-up c onditions in the initialization sequence text, set up 1 VREF Power-up ramp t VTD Sta ble and vali d clo ck T0 T1 t CK Tc0 Tb0 Ta0 Td0 CK# CK t CKSRX t CL t CL t IOz = 20ns RESET# t IS T (MIN) = 10ns Valid CKE Valid ODT t IS Command NOP MRS MRS MRS MRS ZQCL Add ress Code Code Code Code A10 Code Code Code Code BA0 = L BA1 = H BA2 = L BA0 = H BA1 = H BA2 = L BA0 = H BA1 = L BA2 = L BA0 = L BA1 = L BA2 = L Valid DM BA[2:0] Valid Valid A10 = H Valid DQS DQ RTT T = 200μs (MIN) T = 500μs (MIN) MR2 All voltage supplies valid and stable t MRD t MRD t MRD t XPR MR3 MR1 with DLL ena ble t MOD MR0 with DLL reset t ZQ INIT ZQ cali bration t DLLK DRAM ready for external commands Normal operation Indicates a Break in Time Scale LOGIC Devices Incorporated www.logicdevices.com 88 Don ’t Care High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module MODE REGISTERS 0RGHUHJLVWHUV0505DUHXVHGWRGHILQHYDULRXVPRGHVRISURJUDPPDEOHRSHUDWLRQRIWKH''56'5$0L02'$PRGHUHJLVWHULVSURJUDPPHGYLD WKH02'(5(*,67(56(7056FRPPDQGGXULQJLQLWLDOL]DWLRQDQGLWUHWDLQVWKHVWRUHGLQIRUPDWLRQH[FHSWIRU05>@ZKLFKLVVHOIFOHDULQJXQWLOLWLVHLWKHU UHSURJUDPPHG5(6(7?JRHV/2:RUXQWLOWKHGHYLFHORVHVSRZHU &RQWHQWVRIDPRGHUHJLVWHUFDQEHDOWHUHGE\UHH[HFXWLQJWKH056FRPPDQG,IWKHXVHUFKRRVHVWRPRGLI\RQO\DVXEVHWRIWKHPRGHUHJLVWHUuVYDULDEOHV DOOYDULDEOHVPXVWEHSURJUDPPHGZKHQWKH056FRPPDQGLVLVVXHG5HSURJUDPPLQJWKHPRGHUHJLVWHUZLOOQRWDOWHUWKHFRQWHQWVRIWKHPHPRU\DUUD\ SURYLGHGLWLVSHUIRUPHGFRUUHFWO\ 7KH056FRPPDQGFDQRQO\EHLVVXHGRUUHLVVXHGZKHQDOOEDQNVDUHLGOHDQGLQWKH35(&+$5*('VWDWHt53LVVDWLVILHGDQGQRGDWDEXUVWVDUHLQSURJUHVV$IWHUDQ056FRPPDQGKDVEHHQLVVXHGWZRSDUDPHWHUVPXVWEHVDWLVILHGtMRD and tMOD. 7KHFRQWUROOHUPXVWZDLWt05'EHIRUHLQLWLDWLQJDQ\VXEVHTXHQW056FRPPDQGVVHH)LJXUH FIGURE 42- MRS-TO-MRS COMMAND TIMING (tMRD) T0 T1 T2 Ta0 Ta1 Ta2 MRS1 NOP NOP NOP NOP MRS2 CK# CK Command t MRD Add ress Valid Valid CKE 3 Indicates a Break in Time Scale Don ’t Care 127(6 1. 3ULRUWRLVVXLQJWKH056FRPPDQGDOOEDQNVPXVWEHLGOHDQGSUHFKDUJHGt530,1PXVWEHVDWLVILHG DQGQRGDWDEXUVWVFDQEHLQSURJUHVVWKHOHYHOLQJSURFHGXUH 2. t05'VSHFLILHVWKH056WR056FRPPDQGPLQLPXPF\FOHWLPH 3. &.( PXVW EH UHJLVWHUHG +,*+ IURP WKH 056 FRPPDQG XQWLO t0563'(1 0,1 VHH v3RZHU'RZQ 0RGHwRQSDJH 4. )RUD&$6ODWHQF\FKDQJHt;3'//WLPLQJPXVWEHPHWEHIRUHDQ\QRQ056FRPPDQG 7KHFRQWUROOHUPXVWDOVRZDLW t02'EHIRUHLQLWLDWLQJDQ\QRQ056FRPPDQGVH[FOXGLQJ123DQG'(6DVVKRZQLQ)LJXUHRQSDJH7KH'5$0 UHTXLUHVt02'LQRUGHUWRXSGDWHWKHUHTXHVWHGIHDWXUHVZLWKWKHH[FHSWLRQRI'//5(6(7ZKLFKUHTXLUHVDGGLWLRQDOWLPH8QWLOt02'KDVEHHQVDWLVILHGWKH XSGDWHGIHDWXUHVDUHWREHDVVXPHGXQDYDLODEOH LOGIC Devices Incorporated www.logicdevices.com 89 High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module FIGURE 43- MRS-TO-NONMRS COMMAND TIMING (tMOD) T1 T2 t WLS t WLH CK# CK Command MRS1 NOP2 NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP t MOD ODT t WLDQSEN t DQSL3 t DQSH3 t DQSL3 t DQSH3 Differential DQS4 t WLMRD t WLO t WLO Prime DQ 5 t WLO t WLOE Early remaining DQ t WLO Late remaining DQ Indicates a Break in Time Scale Undefined Driving Mode Don’t Care 127(6 1. 3ULRUWRLVVXLQJWKH056FRPPDQGDOOEDQNVPXVWEHLGOHWKH\PXVWEHSUHFKDUJHGt53PXVWEH VDWLVILHGDQGQRGDWDEXUVWVFDQEHLQSURJUHVV 2. 3ULRUWR7DZKHQt02'0,1LVEHLQJVDWLVILHGQRFRPPDQGVH[FHSW123'(6PD\EHLVVXHG 3. ,I577ZDVSUHYLRXVO\HQDEOHG2'7PXVWEHUHJLVWHUHG/2:DW7VRWKDW2'7/LVVDWLVILHGSULRU WR7D2'7PXVWDOVREHUHJLVWHUHG/2:DWHDFKULVLQJ&.HGJHIURP7XQWLO t02'0,1LV satisfied at Ta2. 4. &.( PXVW EH UHJLVWHUHG +,*+ IURP WKH 056 FRPPDQG XQWLO t0563'(1 0,1 DW ZKLFK WLPH SRZHUGRZQPD\RFFXUVHHv3RZHU'RZQ0RGHwRQSDJH MODE REGISTER 0 (MR0) 7KHEDVHUHJLVWHU05LVXVHGWRGHILQHYDULRXV''5L02'PRGHVRIRSHUDWLRQ7KHVHGHILQLWLRQVLQFOXGHWKHVHOHFWLRQRIDEXUVWOHQJWKEXUVWW\SH&$6 ODWHQF\RSHUDWLQJPRGH'//5(6(7:5,7(UHFRYHU\DQG35(&+$5*(SRZHUGRZQPRGHDVVKRZQLQ)LJXUH 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Burst Length Read/Write &+23 Starting Column Address (A[2,1,0]) 5($' :5,7( 8 5($' :5,7( 000 001 Burst Type (Decimal) Type = Sequential Type = Interleaved ==== 1,2 ==== ==== 1,2 010 ==== ==== 1,2 011 ==== ==== 1,2 100 ==== ==== 1,2 101 ==== ==== 1,2 110 ==== ==== 1,2 111 ==== ==== 1,2 0VV ;;;; ;;;; 1,3,4 1VV ;;;; ;;;; 1,3,4 000 1 001 1 010 1 011 1 100 1 101 1 110 1 111 1 1,3 VVV 127(6 1. ,QWHUQDO5($'DQG:5,7(RSHUDWLRQVVWDUWDWWKHVDPHSRLQWLQWLPHIRU %&DVWKH\GRIRU%/ DLL RESET 2. = 'DWDDQG6WUREHRXWSXWGULYHUVLQWULVWDWH 3. ; w'RQuW&DUHw WRITE RECOVERY '//5(6(7LVGHILQHGE\05>@VHH)LJXUH3URJUDPPLQJ05>@ WRvwDFWLYDWHVWKH'//5(6(7IXQFWLRQ05>@LVVHOIFOHDULQJPHDQLQJ LW UHWXUQV WR D YDOXH RI vw DIWHU WKH '// 5(6(7 IXQFWLRQ KDV EHHQ initiated. :5,7(5(&29(5<WLPHLVGHILQHGE\05>@VHH)LJXUH:5,7( 5(&29(5< YDOXHV RI RU PD\ EH XVHG E\ SURJUDPPLQJ 05>@7KHXVHULVUHTXLUHGWRSURJUDPWKHFRUUHFWYDOXHRI:5,7( 5(&29(5<DQGLVFDOFXODWHGE\GLYLGLQJt:5QVE\t&.QVDQGURXQGLQJ XS D QRQLQWHJHU YDOXH WR WKH QH[W LQWHJHU :5 F\FOHV URXQGXS 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FORFN F\FOHV EHIRUH D 5($' FRPPDQGFDQEHLVVXHG7KLVLVWRDOORZWLPHIRUWKHLQWHUQDOFORFNWREH V\QFKURQL]HGZLWKWKHH[WHUQDOFORFN)DLOLQJWRZDLWIRUV\QFKURQL]DWLRQ WRRFFXUPD\UHVXOWLQLQYDOLGRXWSXWWLPLQJVSHFLILFDWLRQVVXFKDVtDQSCK WLPLQJV LOGIC Devices Incorporated Notes ==== www.logicdevices.com 92 High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module CAS Latency (CL) PRECHARGE POWER-DOWN (PRECHARGE PD) 7KH35(&+$5*(3'ELWDSSOLHVRQO\ZKHQ35(&+$5*(SRZHUGRZQ PRGHLVEHLQJXVHG:KHQ05>@LVVHWWRvwWKH'//LVRIIGXULQJ 35(&+$5*(SRZHUGRZQSURYLGLQJDORZHUVWDQGE\FXUUHQWPRGHKRZever, t;3'// PXVW EH VDWLVILHG ZKHQ H[LWLQJ :KHQ 05>@ LV VHW WR vwWKH'//FRQWLQXHVWRUXQGXULQJ35(&+$5*(SRZHUGRZQPRGHWR HQDEOH D IDVWHU H[LW RI 35(&+$5*( SRZHUGRZQ PRGH KRZHYHU t;3 PXVWEHVDWLVILHGZKHQH[LWLQJVHH3RZHU'RZQPRGHRQ3DJH 7KH&/LVGHILQHGE\05>@DVVKRZQLQ)LJXUH&$6ODWHQF\LVWKH GHOD\DVPHDVXUHGLQFORFNF\FOHVEHWZHHQWKHLQWHUQDO5($'FRPPDQG DQGWKHDYDLODELOLW\RIWKHILUVWELWRIYDOLGRXWSXWGDWD7KH&/FDQEHVHW WRRU''56'5$0L02'VGRQRWVXSSRUWKDOIFORFNODWHQFLHV ([DPSOHVRI&/ DQG&/ DUHVKRZQLQ)LJXUHEHORZ,IDQLQWHUQDO 5($'FRPPDQGLVUHJLVWHUHGDWFORFNHGJHQDQGWKH&$6ODWHQF\LVP FORFNVWKHGDWDZLOOEHDYDLODEOHQRPLQDOO\FRLQFLGHQWZLWKFORFNHGJHQP 7DEOHLQGLFDWHVWKH&/VVXSSRUWHGDWDYDLODEOHRSHUDWLQJIUHTXHQFLHV FIGURE 45- READ LATENCY T0 T1 T2 T3 T4 T5 T6 T7 T8 READ NOP NOP NOP NOP NOP NOP NOP NOP CK# CK Command AL = 0, CL = 6 DQS, DQS# DI n DQ DI n+1 DI n+2 DI n+3 DI n+4 T0 T1 T2 T3 T4 T5 T6 T7 T8 READ NOP NOP NOP NOP NOP NOP NOP NOP CK# CK Command AL = 0, CL = 8 DQS, DQS# DI n DQ Transitioning Data Don’t Care 127(6 1. )RULOOXVWUDWLRQSXUSRVHVRQO\&/ DQG&/ DUHVKRZQ2WKHU&/YDOXHVDUH SRVVLEOH 2. LOGIC Devices Incorporated 6KRZQZLWKQRPLQDOt'46&.DQGQRPLQDOtDSDQ. www.logicdevices.com 93 High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module MODE REGISTER 1 (MR1) 7KH 02'( 5(*,67(5 05 FRQWUROV DGGLWLRQDO IXQFWLRQV DQG IHDWXUHV QRW DYDLODEOH LQ WKH RWKHU PRGH UHJLVWHUV 4 2)) 287387 ',6$%/( '// (1$%/('//',6$%/(5TTB120YDOXH2'7:5,7(/(9(/,1*3267('&$6$'',7,9(ODWHQF\DQG287387'5,9(675(1*7+7KHVHIXQFWLRQV DUHFRQWUROOHGYLDWKHELWVVKRZQLQ)LJXUHEHORZ7KH05UHJLVWHULVSURJUDPPHGYLDWKH05FRPPDQGDQGUHWDLQVWKHVWRUHGLQIRUPDWLRQXQWLOLWLV UHSURJUDPPHGXQWLO5(6(7?JRHV/2:WUXHRUXQWLOWKHGHYLFHORVHVSRZHU5HSURJUDPPLQJWKH05UHJLVWHUZLOOQRWDOWHUWKHFRQWHQWVRIWKHPHPRU\ DUUD\SURYLGHGWKHRSHUDWLRQLVSHUIRUPHGFRUUHFWO\ 7KH05UHJLVWHUPXVWEHORDGHGZKHQDOOEDQNVDUHLGOHDQGQREXUVWVDUHLQSURJUHVV7KHFRQWUROOHUPXVWVDWLVI\WKHVSHFLILHGWLPLQJSDUDPHWHUVtMRD and t02'EHIRUHLQLWLDWLQJDVXEVHTXHQWRSHUDWLRQ FIGURE 46- MODE REGISTER 1 (MR1) DEFINITION 127(6 1. 2. 05>@DUHUHVHUYHGIRUIXWXUHXVHDQGPXVWEHSURJUDPPHGWRvw 'XULQJZULWHOHYHOLQJLI05>@DQG05>@DUHvwWKHQDOO5TT_NOM values are available for use. 3. 'XULQJZULWHOHYHOLQJLI05>@LVDvwEXW05>@LVDvwWKHQRQO\5TT_NOM write values are available for use. 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DUHWULVWDWHG7KHRXWSXW',6$%/(IHDWXUHLVLQWHQGHGWREHXVHGGXULQJ IDD FKDUDFWHUL]DWLRQ RI WKH 5($' FXUUHQW DQG GXULQJ t'466 PDUJLQLQJ :5,7(/(9(/,1*RQO\ LOGIC Devices Incorporated www.logicdevices.com High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module POSTED CAS ADDITIVE LATENCY (AL) $/LVVXSSRUWHGWRPDNHWKHFRPPDQGDQGGDWDEXVHIILFLHQWIRUVXVWDLQDEOHEDQGZLGWKVLQ''565$0V05>@GHILQHWKHYDOXHRI$/VHH)LJXUH 05>@HQDEOHVWKHXVHUWRSURJUDPWKH''56'5$0ZLWKDQ$/ &/RU&/ :LWKWKLVIHDWXUHWKH''56'5$0HQDEOHVD5($'RU:5,7(FRPPDQGWREHLVVXHGDIWHUWKH$&7,9$7(FRPPDQGIRUWKDWEDQNSULRUWRt5&'0,17KH RQO\UHVWULFWLRQLV$&7,9$7(WR5($'RU:5,7($/t t5&'0,1PXVWEHVDWLVILHG$VVXPLQJt5&'0,1 &/DW\SLFDODSSOLFDWLRQXVLQJWKLVIHDWXUHVHWV AL=CL – 1tCK = tRCD(MIN-1t&.7KH5($'RU:5,7(FRPPDQGLVKHOGIRUWKHWLPHRIWKH$/EHIRUHLWLVUHOHDVHGLQWHUQDOO\WRWKH''56'5$0L02' GHYLFH5($'ODWHQF\5/LVFRQWUROOHGE\WKHVXPRIWKH$/DQG&$6ODWHQF\&/5/ $/&/:5,7(ODWHQF\:/LVWKHVXPRI&$6:5,7(ODWHQF\DQG $/:/ $/&:/VHHv02'(5(*,67(505w([DPSOHVRI5($'DQG:5,7(ODWHQFLHVDUHVKRZQLQ)LJXUHDQG)LJXUH FIGURE 47- READ LATENCY (AL = 5, CL = 6) BC4 T0 T1 ACTIVE n READ n T2 T6 T11 T12 T13 T14 NOP NOP NOP NOP NOP NOP CK# CK Command t RCD (MIN) DQS, DQS# AL = 5 CL = 6 DO n DQ DO n+1 DO n+2 DO n+3 RL = AL + CL = 11 Indicates a Break in Time Scale LOGIC Devices Incorporated www.logicdevices.com Transitioning Data Don’t Care High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module MODE REGISTER 2 (MR2) 7KH02'(5(*,67(505FRQWUROVDGGLWLRQDOIXQFWLRQVDQGIHDWXUHVQRWDYDLODEOHLQWKHRWKHUPRGHUHJLVWHUV7KHVHDGGLWLRQDOIXQFWLRQVDUH&$6 :5,7(ODWHQF\&:/$8726(/)5()5(6+$656(/)5()5(6+7(03(5$785(657DQG'<1$0,&2'75TTB:57KHVHIXQFWLRQVDUHFRQWUROOHGYLDWKHELWVVKRZQLQ)LJXUH7KH05LVSURJUDPPHGYLDWKH056FRPPDQGDQGZLOOUHWDLQWKHVWRUHGLQIRUPDWLRQXQWLOLWLVSURJUDPPHGDJDLQRU XQWLOWKHGHYLFHORVHVSRZHU5HSURJUDPPLQJWKH05UHJLVWHUZLOOQRWDOWHUWKHFRQWHQWVRIWKHPHPRU\DUUD\SURYLGHGWKDWWKHRSHUDWLRQKDVEHHQSHUIRUPHG FRUUHFWO\7KH05UHJLVWHUPXVWEHORDGHGZKHQDOOEDQNVDUHLGOHDQGQRGDWDEXUVWVDUHLQSURJUHVVDQGWKHPHPRU\FRQWUROOHUPXVWZDLWIRUWKHVSHFLILHG WLPHtMRD and t02'EHIRUHLQLWLDWLQJDVXEVHTXHQWRSHUDWLRQ 7KHWHPSHUDWXUHFRPSHQVDWHGVHOIUHIUHVK7&65IHDWXUHVXEVWDQWLDOO\UHGXFHVWKHVHOIUHIUHVKFXUUHQW,''7&65WDNHVDIIHFWZKHQ7CLVOHVVWKDQoC DQGWKHDXWRVHOIUHIUHVK$65IXQFWLRQLVHQDEOHG$65LVUHTXLUHGWRXVHWKH7&65IHDWXUHDQGLVHQDEOHGPDQXDOO\YLDPRGHUHJLVWHU05>@6HH 0RGH5HJLVWHU05'HILQLWLRQEHORZ (QDEOLQJ$65DOVRDXWRPDWLFDOO\FKDQJHVWKH'5$0VHOIUHIUHVKUDWHIURP[WR[ZKHQWKHFDVHWHPSHUDWXUHH[FHHGVo&7KLVDOORZVWKHXVHUWRRSHUDWH WKH'5$0EH\RQGWKHVWDQGDUGo&OLPLWXSWRWKHRSWLRQDOH[WHQGHGWHPSHUDWXUHUDQJHRIo&ZKLOHLQVHOIUHIUHVKPRGH :KHQ$65LVGLVDEOHGDQG7C is 0o&WRo&WKHVHOIUHIUHVKPRGHuVUHIUHVKUDWHLVDVVXPHGWREHDWWKHQRUPDOUDWHVRPHWLPHVUHIHUUHGWRDV[UHIUHVKUDWH Also, if ASR is disabled and TCLVo&WRo&WKHXVHUPXVWVHOHFWWKH657H[WHQGHGWHPSHUDWXUHVHOIUHIUHVKUDWHVRPHWLPHVUHIHUUHGWRDV[UHIUHVKUDWH 657LVVHOHFWHGYLDPRGHUHJLVWHU05>@UHJLVWHU6HH0RGH5HJLVWHU05'HILQLWLRQEHORZ 63'VHWWLQJVVKRXOGDOZD\VVXSSRUWKELQDU\LQ%\WH 0RGHUHJLVWHU05FRQWUROVDGGLWLRQDOIXQFWLRQVDQGIHDWXUHVQRWDYDLODEOHLQWKHRWKHUPRGHUHJLVWHUV7KHDXWRVHOIUHIUHVK$65IXQFWLRQLVRISDUWLFXODU LQWHUHVWIRUWKH''5/566'5$0EHFDXVHWKH0LFURQ''5/566'5$0JRHVLQWR7&65PRGHZKHQ$65KDVEHHQHQDEOHG7KLVIXQFWLRQLVFRQWUROOHG YLDWKHELWVVKRZQLQWKHILJXUHEHORZ FIGURE 48- MODE REGISTER 2 (MR2) DEFINITION BA2 BA 1 BA 0 A13 A12 A11 A10 A9 A8 A7 A 6 A5 A4 A3 A2 A1 A0 Address bus 16 15 14 13 12 11 10 9 8 7 6 0 01 01 01 RTT_WR 01 SRT ASR Mode Register 2 (MR2) 5 01 1 M15 M14 Mode Register M5 M4 M3 2 1 0 01 01 01 CAS Write Latency (CWL) 5 CK (t CK ≥ 2.5ns) 0 Mode register set 0 (MR0) 0 Normal (0° C to 85° C) 0 0 0 0 1 Mode register set 1 (MR1) 1 Extended (0°C to 95° C) 0 0 1 1 0 Mode register set 2 (MR2) 0 1 0 6 CK (2.5ns > t CK ≥ 1.875ns) 7 CK (1.875ns > t CK ≥ 1.5ns) 1 1 Mode register set 3 (MR3) 0 1 1 8 CK (1.5ns > t CK ≥ 1.25ns) 1 0 0 1 0 9 CK (1.25ns >tCK ≥ 1.07ns) 1 10 CK (1.071ns >tCK ≥ 0.938ns) 1 1 0 Reserved 1 1 1 Reserved 0 LOGIC Devices Incorporated 3 0 M10 M9 Notes: M7 Self Refresh Temperature 4 CWL 0 Dynamic ODT ( R TT_WR ) RTT_WR disabled 0 1 1 0 RZQ/2 1 1 Reserved RZQ/4 M6 0 Auto Self Refresh (Optional) Disabled: Manual 1 Enabled: Automatic 1. MR2[16, 13:11, 8, and 2:0] are reserved for future use and must all be programmed to “0.” www.logicdevices.com 97 High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module CAS WRITE LATENCY (CWL) &:/LVGHILQHGE\05>@DQGLVWKHGHOD\LQFORFNF\FOHVIURPWKHUHOHDVLQJRIWKHLQWHUQDO:5,7(WRWKHODWFKLQJRIWKHILUVWGDWDLQ&:/PXVWEHFRUUHFWO\ VHWWRWKHFRUUHVSRQGLQJRSHUDWLQJFORFNIUHTXHQF\VHH)LJXUH7KHRYHUDOO:5,7(/$7(1&<:/LVHTXDOWR&:/$/VHH)LJXUH FIGURE 49- CAS WRITE LATENCY BC4 T0 T1 ACTIVE n WRITE n T2 T6 T11 T12 T13 T14 NOP NOP NOP NOP NOP NOP CK# CK Command t RCD (MIN) DQS, DQS# AL = 5 CWL = 6 DI n DQ DI n+1 DI n+2 DI n+3 WL = AL + CWL = 11 Indicates A Break in Time Scale Transitioning Data Don’t Care RSWLRQDOH[WHQGHGWHPSHUDWXUHUDQJHRI&ZKLOHLQ6(/)5()5(6+ PRGH7KHVWDQGDUG6(/)5()5(6+FXUUHQWWHVWVSHFLILHVWHVWFRQGLWLRQV WRQRUPDODPELHQWWHPSHUDWXUH&RQO\PHDQLQJLI657LVHQDEOHGWKH VWDQGDUG6(/)5()5(6+FXUUHQWVSHFLILFDWLRQVGRQRWDSSO\ AUTO SELF REFRESH (ASR) 0RGHUHJLVWHU05>@LVXVHGWR',6$%/((1$%/(WKH$65IXQFWLRQ :KHQ$65LV',6$%/('WKH6(/)5()5(6+PRGHuV5()5(6+UDWH LVDVVXPHGWREHDWWKHQRUPDO&OLPLWFRPPRQO\UHIHUUHGWRDVWKH ;5()5(6+UDWH,QWKH',6$%/('PRGH$65UHTXLUHVWKHXVHUWR HQVXUHWKH6'5$0QHYHUH[FHHGVD7ARI&ZKLOHLQ6(/)5()5(6+ XQOHVVWKHXVHUHQDEOHVWKH657IHDWXUHOLVWHGEHORZVXSSRUWLQJDQHOHYDWHGWHPSXSWR&ZKLOHLQ6(/)5()5(6+ SRT vs. ASR ,IWKHQRUPDODPELHQWWHPSHUDWXUHOLPLWRI&LVQRWH[FHHGHGWKHQQHLWKHU 657 QRU $65 LV UHTXLUHG DQG ERWK FDQ EH ',6$%/(' WKURXJKRXW RSHUDWLRQ,IWKHH[WHQGHGWHPSHUDWXUHRSWLRQLVXVHGWKHXVHULVUHTXLUHG WR SURYLGH D ; UHIUHVK UDWH GXULQJ PDQXDO UHIUHVK IRU ([WHQGHG WHPS GHYLFHVRU;UHIUHVKUDWHIRU0LOWHPSGHYLFHV657DQG$65VKRXOGEH HQDEOHGIRUDXWRPDWLF5()5(6+VHUYLFHVRQDOOGHYLFHVXVHGLQWHPSHUDWXUHHQYLURQPHQWVd& 7KH VWDQGDUG 6(/) 5()5(6+ FXUUHQW WHVW VSHFLILHV WHVW FRQGLWLRQV WR QRUPDODPELHQWWHPSHUDWXUH&RQO\PHDQLQJLI$65LVHQDEOHGWKH VWDQGDUG6(/)5()5(6+FXUUHQWVSHFLILFDWLRQGRHVQRWDSSO\VHHWKH v(;7(1'('7(03(5$785(86$*(wGHVFULSWLRQODWHULQWKLV'6 657IRUFHVWKH6'5$0WRVZLWFKWKHLQWHUQDO6(/)5()5(6+UDWHIURP ;WR;6(/)5()5(6+LVSHUIRUPHGDW;UHJDUGOHVVRITA. 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'\QDPLF2'7LVRQO\DSSOLFDEOHGXULQJ:5,7(F\FOHV,I2'75TTB120LVGLVDEOHGG\QDPLF2'75TTB:5LVVWLOOSHUPLWWHG5TT_NOM and RTTB:5FDQ EHXVHGLQGHSHQGHQWRIRQHDQRWKHU'\QDPLF2'7LVQRWDYDLODEOHGXULQJ:5,7(/(9(/,1*PRGHUHJDUGOHVVRIWKHVWDWHRI2'75TTB120)RUGHWDLOV RQ2'7RSHUDWLRQUHIHUWRWKHv2Q'LH7HUPLQDWLRQ2'7wVHFWLRQ MODE REGISTER (MR3) 7KHPRGHUHJLVWHU05FRQWUROVDGGLWLRQDOIXQFWLRQVDQGIHDWXUHVQRWDYDLODEOHYLD0505RU05&XUUHQWO\GHILQHGDVWKH08/7,385326(5(*,67(50357KLVIXQFWLRQLVFRQWUROOHGYLDWKHELWVVKRZQLQ)LJXUH7KH05LVSURJUDPPHGYLDWKH/2$'02'(FRPPDQGDQGUHWDLQVWKHVWRUHGLQIRUPDWLRQXQWLOLWLVSURJUDPPHGDJDLQRUXQWLOWKHGHYLFHORVHVSRZHU5HSURJUDPPLQJWKH05UHJLVWHUZLOOQRWDOWHUWKHFRQWHQWVRIWKHPHPRU\DUUD\SURYLGHG WKHSURJUDPPLQJRIWKH05KDVEHHQSHUIRUPHGFRUUHFWO\7KH05UHJLVWHUPXVWEHORDGHGZKHQDOOEDQNVDUHLGOHDQGQRGDWDEXUVWVDUHLQSURJUHVVDQG WKHPHPRU\FRQWUROOHUPXVWZDLWWKHVSHFLILHGWLPHtMRD and t02'EHIRUHLQLWLDWLQJDVXEVHTXHQWRSHUDWLRQ FIGURE 50 - MODE REGISTER 3 (MR3) DEFINITION 127(6 LOGIC Devices Incorporated 1. 05>DQG@DUHUHVHUYHGIRUIXWXUHXVHDQGPXVWDOOEHSURJUDPPHGWRvw 2. :KHQ035FRQWUROLVVHWIRUQRUPDO'5$0RSHUDWLRQ05>@ZLOOEHLJQRUHG 3. ,QWHQGHGWREHXVHGIRU5($'V\QFKURQL]DWLRQ www.logicdevices.com 99 High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module MULTIPURPOSE REGISTER (MPR) 7KH08/7,385326(5(*,67(5IXQFWLRQLVXVHGWRRXWSXWDSUHGHILQHGV\VWHPWLPLQJFDOLEUDWLRQELWVHTXHQFH%LWLVWKHPDVWHUELWWKDWHQDEOHVRUGLVDEOHV DFFHVVWRWKH035UHJLVWHUDQGELWVDQGGHWHUPLQHZKLFKPRGHWKH035LVSODFHGLQ7KHEDVLFFRQFHSWRIWKHPXOWLSXUSRVHUHJLVWHULVVKRZQLQ)LJXUH ,I05>@LVDvwWKHQWKH035DFFHVVLVGLVDEOHGDQGWKH6'5$0RSHUDWHVLQQRUPDOPRGH+RZHYHULI05>@LVDvwWKHQ6'5$0QRORQJHURXWSXWV QRUPDOUHDGGDWDEXWRXWSXWV035GDWDDVGHILQHGE\05>@,I05>@LVHTXDOWRvwWKHQDSUHGHILQHGUHDGSDWWHUQIRUV\VWHPFDOLEUDWLRQLVVHOHFWHG 7RHQDEOHWKH035WKH056FRPPDQGLVLVVXHGWR05DQG05>@ VHH7DEOH3ULRUWRLVVXLQJWKH056FRPPDQGDOOEDQNVPXVWEHLQWKHLGOHVWDWH DOOEDQNVDUHSUHFKDUJHGDQGt53LVPHW:KHQWKH035LVHQDEOHGDQ\VXEVHTXHQW5($'RU5'$3FRPPDQGVDUHUHGLUHFWHGWRWKHPXOWLSXUSRVHUHJLVWHU 7KHUHVXOWLQJRSHUDWLRQZKHQHLWKHUD5($'RUD5'$3FRPPDQGLVLVVXHGLVGHILQHGE\05>@ZKHQ035LVHQDEOHGVHH7DEOH:KHQWKH035LV HQDEOHGRQO\5($'RU5'$3FRPPDQGVDUHDOORZHGXQWLODVXEVHTXHQW056FRPPDQGLVLVVXHGZLWKWKH035GLVDEOHG05>@ 32:(5'2:16(/) 5()5(6+DQGDQ\RWKHU1215($'RU5'$3FRPPDQGLVQRWDOORZHG7KH5(6(7IXQFWLRQLVVXSSRUWHGGXULQJ035HQDEOHPRGH FIGURE 51 - MULTIPURPOSE REGISTER (MPR) BLOCK DIAGRAM Memory core MR3[2] = 0 (MPR off) Multipurpose register pre defined data for READs MR3[2] = 1 (MPR on) DQ, DM, DQ S, DQS# 127(6 1. $SUHGHILQHGGDWDSDWWHUQFDQEHUHDGRXWRIWKH035ZLWKDQH[WHUQDO5($'FRPPDQG 2. 05>@GHILQHVZKHWKHUWKHGDWDIORZFRPHVIURPWKHPHPRU\FRUHRUWKH035:KHQWKHGDWD IORZ LV GHILQHG WKH 035 FRQWHQWV FDQ EH UHDG RXW FRQWLQXRXVO\ ZLWK D UHJXODU 5($' RU 5'$3 FRPPDQG LOGIC Devices Incorporated www.logicdevices.com 100 High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module TABLE 61: BURST ORDER MR3[2] MPR 0 MR3[1:0] MPR READ Function v'RQuW&DUHw Function 1RUPDO2SHUDWLRQQR035WUDQVDFWLRQ$OOVXEVHTXHQW5($'VFRPHIURP WKH6'5$0PHPRU\DUUD\$OOVXEVHTXHQW:5,7(VJRWRWKH6'5$0 PHPRU\DUUD\ 1 $>@6HH7DEOH (QDEOH035PRGHVXEVHTXHQW5($'5'$3FRPPDQGVGHILQHGE\ELWV and 2. MPR FUNCTIONAL DESCRIPTION 7KH035-('(&GHILQLWLRQDOORZVIRUHLWKHUDSULPH'4IRUORZHUE\WHDQG'4IRUWKHXSSHUE\WHRIHDFKRIWKHZRUGVFRQWDLQHGLQWKH/',L02'WRRXWSXW WKH035GDWDZLWKWKHUHPDLQLQJ'4VGULYHQ/2:RUIRUDOO'4VWRRXWSXWWKH035GDWD7KH035UHDGRXWVXSSRUWVIL[HG5($'EXUVWDQG5($'EXUVWFKRS 056DQG27)YLD$%&ZLWKUHJXODU5($'ODWHQFLHVDQG$&WLPLQJVDSSOLFDEOH7KLVSURYLGLQJWKH'//LVORFNHGDVUHTXLUHG 035DGGUHVVLQJIRUDYDOLG0355($'LVDVIROORZV x$>@PXVWEHVHWWRvwDVWKHEXUVWRUGHULVIL[HGSHUQLEEOH x$VHOHFWVWKHEXUVWRUGHU x%/$LVVHWWRvwDQGWKHEXUVWRUGHULVIL[HGWR x)RUEXUVWFKRSFDVHVWKHEXUVWRUGHULVVZLWFKHGRQWKHQLEEOHEDVHDQG xA2=0: burst order =0,1,2,3 x$ EXUVWRUGHU x%XUVWRUGHUELWWKHILUVWELWLVDVVLJQHGWR/6%DQGEXUVWRUGHUELWWKHODVWELWLVDVVLJQHGWR06% x$>@DUHDv'RQuW&DUHw x$LVDv'RQuW&DUHw x$LVDv'RQuW&DUHw x$6HOHFWVEXUVWFKRSPRGHRQWKHIO\LIHQDEOHGZLWKLQ05 x$LVDv'RQuW&DUHw x%$>@DUHDv'RQuW&DUHw LOGIC Devices Incorporated www.logicdevices.com 101 High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module MPR REGISTER ADDRESS DEFINITIONS and BURSTING ORDER 7KH035FXUUHQWO\VXSSRUWVDVLQJOHGDWDIRUPDW7KLVGDWDIRUPDWLVDSUHGHILQHG5($'SDWWHUQIRUV\VWHPFDOLEUDWLRQ7KHSUHGHILQHGSDWWHUQLVDOZD\VD UHSHDWLQJELWSDWWHUQ ([DPSOHVRIWKHGLIIHUHQWW\SHRISUHGHILQHG5($'SDWWHUQEXUVWVDUHVKRZQLQ)LJXUHVDQG TABLE 62: BURST ORDER MR3[2] MR3[1:0] Function Burst Length 00 5($'SUHGHILQHGSDWWHUQIRU BL8 1 Read A[2:0] 000 Burst Order and Data Pattern %XUVW2UGHU 3UHGHILQHGSDWWHUQ V\VWHPFDOLEUDWLRQ BC4 000 Burst Order: 0,1,2,3 3UHGHILQHGSDWWHUQ BC4 100 %XUVW2UGHU 3UHGHILQHGSDWWHUQ 1 1 1 LOGIC Devices Incorporated 01 5)8 10 5)8 11 5)8 www.logicdevices.com QD QD QD QD QD QD QD QD QD QD QD QD QD QD QD QD QD QD QD QD QD QD QD QD QD QD QD 102 High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B LOGIC Devices Incorporated www.logicdevices.com 103 DQ Notes: 0 A [ 15:13] DQS, DQS# 0 A12/BC# 0 A10/AP 0 00 A[9:3] A 11 1 A2 1 0 MRS A[1:0] t RP Ta0 3 PREA T0 Bank add ress Command CK# CK NOP NOP Tc5 NOP Tc6 t MPRR MRS Tc7 0 0 Vali d 1 Val i d 0 0 00 Val i d Vali d Vali d 0 NOP Tc4 02 NOP Tc3 Vali d NOP Tc2 02 RL NOP Tc1 3 NOP Tc0 Vali d READ1 Tb1 1. READ with BL8 either by MRS or OTF. 2. Memory controller must drive 0 on A[2:0]. t MOD Tb0 Indicates a Break in Time Scale t MOD NOP Tc8 NOP Tc9 Don ’t Care Valid Tc10 L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module Figure 52 - MPR System Read Calibration with BL8: Fixed Burst Order Single Readout High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B LOGIC Devices Incorporated www.logicdevices.com 104 DQ Notes: 0 A[15:13] DQS, DQS# 0 A12/BC# 0 A10/AP 0 00 A[9:3] A11 1 A2 1 0 MRS A[1:0] t RP Ta 3 PREA T0 Bank add ress Command CK# CK RL NOP Tc6 NOP Tc7 t MPRR NOP Tc9 Indicates a Break in Time Scale NOP Tc8 0 00 0 Vali d 3 MRS Tc10 Vali d RL Vali d 0 0 NOP Tc5 Vali d 1 NO Tc4 Vali d NOP Tc3 0 NOP Tc2 Vali d Vali d NOP Tc1 Vali d Vali d Vali d 12 02 Vali d 02 02 READ1 Vali d t CCD Vali d READ1 Tc0 1. READ with BL8 either by MRS or OTF. 2. Memory controller must drive 0 on A[2:0]. t MOD Tb Vali d Don ’t Care t MOD Td L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module Figure 53 - MPR System Read Calibration with BL8: Fixed Burst Order, Back-to-Back Readout High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B LOGIC Devices Incorporated www.logicdevices.com DQ DQS, DQS# Notes: 1. 2. 3. 4. Vali d 1 0 0 Vali d 1 Val i d 0 A 11 A12/BC# A[15:13] Vali d Val i d 0 1 RL Vali d NOP Tc1 NOP Tc2 RL NOP Tc3 READ with BC4 either by MRS or OTF. Memory controller must drive 0 on A[1:0]. A2 = 0 selects lower 4 nibble bits 0 . . . 3. A2 = 1 selects upper 4 nibble bits 4 . . . 7. Vali d Vali d Vali d A 10/A P Val i d 00 14 03 A [ 9:3] 02 1 Vali d READ1 02 t CCD Vali d READ1 0 t MOD Tc0 A2 MRS Tb A[1:0] t RF Ta 3 PREA T0 Bank add ress Command CK# CK NOP Tc4 NOP Tc5 NOP Tc6 NOP Tc7 t MPRR 0 0 0 0 00 0 Vali d 3 MRS Tc8 t MOD NOP Tc10 Indicates a Break in Time Scale NOP Tc9 Don ’t Care Valid Td L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module Figure 54 - MPR System Read Calibration with BC4: Lower Nibble, Then Upper Nibble High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B LOGIC Devices Incorporated www.logicdevices.com DQ DQS, DQS# A [ 15:13] 0 0 A12/BC# 0 A 10/A P 0 00 A [ 9:3] A 11 1 A2 1 0 MRS A[1:0] t RF Ta 3 PREA T0 Bank add ress Command CK# CK t MOD RL Vali d Vali d 1 Vali d 1 Val i d Vali d Vali d Val i d Val i d Vali d 04 13 Val i d 02 02 READ1 Vali d t CCD Tc0 Vali d READ1 Tb Notes: NOP Tc1 1. 2. 3. 4. RL NOP Tc3 NOP Tc4 NOP Tc5 NOP Tc6 READ with BC4 either by MRS or OTF. Memory controller must drive 0 on A[1:0]. A2 = 1 selects upper 4 nibble bits 4 . . . 7. A2 = 0 selects lower 4 nibble bits 0 . . . 3. NOP Tc2 t MPRR NOP Tc7 0 0 0 0 00 0 t MOD NOP Tc9 Indicates a Break in Time Scale Vali d 3 MR S Tc8 NOP Tc10 Don ’t Care Valid Td L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module Figure 55 - MPR System Read Calibration with BC4: Upper Nibble, Then Lower Nibble High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module MPR READ PREDEFINED PATTERN 7KHSUHGHWHUPLQHG5($'FDOLEUDWLRQSDWWHUQLVDIL[HGSDWWHUQRI7KHIROORZLQJLVDQH[DPSOHRIXVLQJWKH5($'RXWSUHGHWHUPLQHG5($' FDOLEUDWLRQSDWWHUQ7KHH[DPSOHLVWRSHUIRUPPXOWLSOH5($'6IURPWKH08/7,385326(5(*,67(5035LQRUGHUWRGRV\VWHPOHYHO5($'WLPLQJFDOLEUDWLRQEDVHGRQWKHSUHGHWHUPLQHGDQGVWDQGDUGL]HGSDWWHUQ 7KHIROORZLQJSURWRFRORXWOLQHVWKHVWHSVXVHGWRSHUIRUPWKH5($'FDOLEUDWLRQ x3UHFKDUJHDOOEDQNV xAfter t53LVVDWLVILHGVHW05605>@ DQG05>@ 7KLVUHGLUHFWVDOOVXEVHTXHQW5($'VDQG/RDGVWKHSUHGHILQHGSDWWHUQLQWR WKH035$VVRRQDVtMRD and t02'DUHVDWLVILHGWKH035LVDYDLODEOH x'DWD:5,7(RSHUDWLRQVDUHQRWDOORZHGXQWLOWKH035UHWXUQVWRWKHQRUPDO6'5$0VWDWH x,VVXHD5($'ZLWKEXUVWRUGHULQIRUPDWLRQDOORWKHUDGGUHVVSLQVDUHv'RQuW&DUHw x$>@ GDWDEXUVWRUGHULVIL[HGVWDUWLQJDWQLEEOH x$ IRU%/EXUVWRUGHULVIL[HGDV x$ XVH%/ x$IWHU5/ $/&/WKH6'5$0EXUVWVRXWWKHSUHGHILQHG5($'FDOLEUDWLRQSDWWHUQ x7KHPHPRU\FRQWUROOHUUHSHDWVWKHFDOLEUDWLRQ5($'VXQWLO5($'GDWDFDSWXUHDWWKHPHPRU\FRQWUROOHULVRSWLPL]HG x$IWHUWKHODVW0355($'EXUVWDQGDIWHU t0355KDVEHHQVDWLVILHGLVVXH05605>@ DQG05>@ v'RQuW&DUHwWRWKHQRUPDO 6'5$0VWDWH$OOVXEVHTXHQW5($'DQG:5,7(DFFHVVHVZLOOEHUHJXODU5($'6DQG:5,7(6IURPWRWKH6'5$0DUUD\ x:KHQ tMRD and t02'DUHVDWLVILHGIURPWKHODVW056WKHUHJXODU6'5$0FRPPDQGVVXFKDV$&7,9$7(D0HPRU\EDQNIRUUHJXODU 5($'RU:5,7(DFFHVVDUHSHUPLWWHG MODE REGISTER SET (MRS) 7KHPRGHUHJLVWHUVDUHORDGHGYLDLQSXWV%$>@$>@%$>@GHWHUPLQHVZKLFKPRGHUHJLVWHULVSURJUDPPHG xBA2 = 0, BA1 = 0, BA0 = 0 for MR0 xBA2 = 0, BA1 = 0, BA0 = 1 for MR1 xBA2 = 0, BA1 = 1, BA0 = 0 for MR2 xBA2 = 0, BA1 = 1, BA0 = 1 for MR3 7KH056FRPPDQGFDQRQO\EHLVVXHGRUUHLVVXHGZKHQDOOEDQNVDUHLGOHDQGLQWKHSUHFKDUJHGVWDWHt53LVVDWLVILHGDQGQRGDWDEXUVWVDUHLQ SURJUHVV7KHFRQWUROOHUPXVWZDLWWKHVSHFLILHGWLPHt05'EHIRUHLQLWLDWLQJDVXEVHTXHQWRSHUDWLRQVXFKDVDQ$&7,9$7(FRPPDQG7KHUHLVDOVR DUHVWULFWLRQDIWHULVVXLQJDQ056FRPPDQGZLWKUHJDUGWRZKHQWKHXSGDWHGIXQFWLRQVEHFRPHDYDLODEOH7KLVSDUDPHWHULVVSHFLILHGE\t02'%RWK tMRD and t02'SDUDPHWHUVDUHVKRZQLQ)LJXUHDQG9LRODWLQJHLWKHURIWKHVHUHTXLUHPHQWVZLOOUHVXOWLQXQVSHFLILHGRSHUDWLRQ ZQ CALIBRATION 7KH=4&$/,%5$7,21FRPPDQGLVXVHGWRFDOLEUDWHWKH6'5$0RXWSXWGULYHUV521DQG2'7YDOXHV5TTRYHUSURFHVVYROWDJHDQGWHPSHUDWXUHSURYLGHGDGHGLFDWHG:H[WHUQDOUHVLVWRULVFRQQHFWHGIURPWKH6'5$0uV=4EDOOWR9VV4 ''56'5$0VQHHGDORQJHUWLPHWRFDOLEUDWH5ONDQG2'7DWSRZHUXS,1,7,$/,=$7,21DQG6(/)5()5(6+H[LWDQGDUHODWLYHO\VKRUWHUWLPHWRSHUIRUP SHULRGLFFDOLEUDWLRQV''56'5$0GHILQHVWZR=4&$/,%5$7,21FRPPDQGV=4&$/,%5$7,21/21*=4&/DQG=4&$/,%5$7,216+257=4&6 $QH[DPSOHRI=4&$/,%5$7,21WLPLQJLVVKRZQLQ)LJXUH $OOEDQNVPXVWEH35(&+$5*('DQGt53PXVWEHPHWEHIRUH=4&/RU=4&6FRPPDQGVFDQEHLVVXHGWRWKH6'5$01RRWKHUDFWLYLWLHVRWKHUWKDQDQRWKHU =4&/RU=4&6FRPPDQGPD\EHLVVXHGWRWKH6'5$0FDQEHSHUIRUPHGRQWKH6'5$0DUUD\E\WKHFRQWUROOHUIRUWKHGXUDWLRQRI t=4,1,7RU t=423(5 7KHTXLHWWLPHRQWKH6'5$0DUUD\KHOSVDFFXUDWHO\FDOLEUDWH5ONDQG2'7$IWHU6'5$0FDOLEUDWLRQLVDFKLHYHGWKH6'5$0VKRXOGGLVDEOHWKH=4EDOOuV FXUUHQWFRQVXPSWLRQSDWKWRUHGXFHRYHUDOOSRZHUXVDJH =4&$/,%5$7,21FRPPDQGVFDQEHLVVXHGLQSDUDOOHOWR'//5(6(7DQGORFNLQJWLPH8SRQ6(/)5()5(6+H[LWDQH[SOLFLW=4&/LVUHTXLUHGLI=4&$/,BRATION is desired. ,QGXDOUDQNV\VWHPGHVLJQVWKDWVKDUHWKH=4UHVLVWRUEHWZHHQGHYLFHVWKHFRQWUROOHUPXVWQRWDOORZRYHUODSRIt=4,17t=423(5RUt=4&6EHWZHHQUDQNV LOGIC Devices Incorporated www.logicdevices.com 107 High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module FIGURE 56 - ZQ CALIBRATION TIMING (ZQCL AND ZQCS) T0 T1 Ta0 Ta1 Ta2 Ta3 Tb0 Tb1 Tc0 Tc1 Tc2 ZQCL NOP NOP NOP Valid Vali d ZQCS NOP NOP NOP Valid Address Vali d Vali d Vali d A10 Vali d Vali d Vali d CK# CK Command CKE 1 Vali d Vali d 1 Vali d ODT 2 Vali d Vali d 2 Vali d DQ 3 A ctivities 3 High-Z Activities High-Z t ZQ INIT or t ZQ OPER t ZQCS Indicates a Break in Time Scale Don ’t Care 127(6 1. &.(PXVWEHFRQWLQXRXVO\UHJLVWHUHG+,*+GXULQJWKHFDOLEUDWLRQSURFHGXUH 2. 2'7PXVWEHGLVDEOHGYLDWKH2'7VLJQDORUWKH056GXULQJWKHFDOLEUDWLRQSURFHGXUH 3. $OOGHYLFHVFRQQHFWHGWRWKH'4EXVVKRXOGEH+LJK=GXULQJFDOLEUDWLRQ ACTIVATE %HIRUHDQ\5($'RU:5,7(FRPPDQGVFDQEHLVVXHGWRDEDQNZLWKLQWKH6'5$0D52:LQWKDWEDQNPXVWEHRSHQHG$&7,9$7('7KLVLVDFFRPSOLVKHG YLDWKH$&7,9$7(FRPPDQGZKLFKVHOHFWVERWKWKH%$1.DQGWKH52:WREH$&7,9$7(' $IWHUD52:LVRSHQHGZLWKDQ$&7,9$7(FRPPDQGD5($'RU:5,7(FRPPDQGPD\EHLVVXHGWRWKDW52:VXEMHFWWRWKHt5&'VSHFLILFDWLRQ+RZHYHULI WKHDGGLWLYHODWHQF\LVSURJUDPPHGFRUUHFWO\D5($'RU:5,7(FRPPDQGPD\EHLVVXHGSULRUWRt5&'0,1,QWKLVRSHUDWLRQWKH6'5$0HQDEOHVD5($' RU:5,7(FRPPDQGWREHLVVXHGDIWHUWKH$&7,9$7(FRPPDQGIRUWKDWEDQNEXWSULRUWRt5&'0,1VHHv3267('&$6$'',7,9(/$7(1&<$/tRCD 0,1VKRXOGEHGLYLGHGE\WKHFORFNSHULRGDQGURXQGHGXSWRWKHQH[WZKROHQXPEHUWRGHWHUPLQHWKHHDUOLHVWFORFNHGJHDIWHUWKH$&7,9$7(FRPPDQGRQ ZKLFKWKH5($'RU:5,7(FRPPDQGFDQEHHQWHUHG7KHVDPHSURFHGXUHLVXVHGWRFRQYHUWRWKHUVSHFLILFDWLRQOLPLWVIURPWLPHXQLWVWRFORFNF\FOHV :KHQDWOHDVWRQHEDQNLVRSHQDQ\5($'WR5($'FRPPDQGGHOD\RU:5,7(WR:5,7(FRPPDQGGHOD\LVUHVWULFWHGWRt&&'0,1 $ VXEVHTXHQW $&7,9$7( FRPPDQG WR D GLIIHUHQW 52: LQ WKH VDPH %$1. FDQ RQO\ EH LVVXHG DIWHU WKH SUHYLRXV $&7,9( 52: KDV EHHQ FORVHG 35(&+$5*('7KHPLQLPXPWLPHLQWHUYDOEHWZHHQVXFFHVVLYH$&7,9$7(FRPPDQGVWRWKHVDPH%$1.LVGHILQHGE\tRC. $VXEVHTXHQW$&7,9$7(FRPPDQGWRDQRWKHU%$1.FDQEHLVVXHGZKLOHWKHILUVW%$1.LVEHLQJDFFHVVHGZKLFKUHVXOWVLQDUHGXFWLRQRIWRWDO52:$&&(66 RYHUKHDG7KHPLQLPXPWLPHLQWHUYDOEHWZHHQVXFFHVVLYH$&7,9$7(FRPPDQGVPD\EHLVVXHGLQDJLYHQt)$:0,1SHULRGDQGWKHt55'0,1UHVWULFWLRQ VWLOODSSOLHV7KHt)$:0,1SDUDPHWHUDSSOLHVUHJDUGOHVVRIWKHQXPEHURI%$1.6DOUHDG\RSHQHGRUFORVHG LOGIC Devices Incorporated www.logicdevices.com 108 High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module FIGURE 57 - EXAMPLE: MEETING tRRD (MIN) AND tRCD (MIN) T0 T1 T2 T3 T4 T5 T8 T9 T10 T11 Command ACT NOP NOP ACT NOP NOP NOP NOP NOP RD/WR Add ress Row BA[2:0] Bank x CK# CK Row Col Bank y Bank y t RRD t RCD Indicates a Break in Time Scale Don ’t Care FIGURE 58 - EXAMPLE: tFAW CK# T0 T1 T4 T5 T8 T9 T10 T11 T19 T20 ACT NOP ACT NOP A CT NOP ACT NOP NOP A CT CK Command Add ress BA[2:0] Row Bank a Row Row Row Row Bank b Bank c Bank d Bank ye t RRD t FAW Indicates a Break in Time Scale LOGIC Devices Incorporated www.logicdevices.com 109 Don ’t Care High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module READ 5($'EXUVWVDUHLQLWLDWHGZLWKD5($'FRPPDQG7KHVWDUWLQJ&2/801DQG%$1.DGGUHVVHVDUHSURYLGHGZLWKWKH5($'FRPPDQGDQG $87235(&+$5*(LVHLWKHUHQDEOHGRUGLVDEOHGIRUWKDWEXUVWDFFHVV,I$87235(&+$5*(LVHQDEOHGWKH52:EHLQJDFFHVVHGLVDXWRPDWLFDOO\35(&+$5*('DW WKHFRPSOHWLRQRIWKHEXUVWVHTXHQFH,I$87235(&+$5*(LVGLVDEOHGWKH52:ZLOOEHOHIWRSHQDIWHUWKHFRPSOHWLRQRIWKHEXUVW 'XULQJ5($'EXUVWVWKHYDOLGGDWDRXWHOHPHQWIURPWKHVWDUWLQJFROXPQDGGUHVVLVDYDLODEOHDW5($'/$7(1&<5/FORFNVODWHU5/LVGHILQHGDVWKHVXP RI3267('&$6$'',7,9(/$7(1&<$/DQG&$6/$7(1&<&/5/ $/&/7KHYDOXHRI$/DQG&/LVSURJUDPPDEOHLQWKHPRGHUHJLVWHUYLDWKH 056FRPPDQG(DFKVXEVHTXHQWGDWDRXWHOHPHQWZLOOEHYDOLGQRPLQDOO\DWWKHQH[WSRVLWLYHRUQHJDWLYHFORFNHGJHWKDWLVDWWKHQH[WFURVVLQJRI&.DQG &.?)LJXUHVKRZVDQH[DPSOHRI5/EDVHGRQD&/VHWWLQJRIDVZHOODV$/ FIGURE 59 - READ LATENCY T0 T7 T8 T9 T10 T11 T12 T12 Command READ NOP NOP NOP NOP NOP NOP NOP Add ress Bank a, Col n CK# CK CL = 8, AL = 0 DQS, DQS# DO n DQ Indicates a Break in Time Scale Notes: Don ’t Care 1. DO n = data-out from column n. 2. Subsequent elements of data-out appear in the programmed order following DO . n. />8@'46[/>8@'46[?LVGULYHQE\WKH6'5$0DORQJZLWKWKHRXWSXWGDWD 7KHLQLWLDO/2:VWDWHRQ/>8@'46[DQG+,*+VWDWHRQ/>8@'46[?LVNQRZQ DVWKH5($'SUHDPEOHt535(7KH/2:VWDWHRQ'46[DQGWKH+,*+ VWDWHRQ/>8@'46[?FRLQFLGHQWZLWKWKHODVWGDWDRXWHOHPHQWLVNQRZQDV WKH5($'SRVWDPEOHt53678SRQFRPSOHWLRQRIDEXUVWDVVXPLQJQR RWKHUFRPPDQGVKDYHEHHQLQLWLDWHGWKH'4ZLOOJR+,*+=$GHWDLOHG H[SODQDWLRQRI t'464YDOLGGDWDRXWVNHZ t4+GDWDRXWZLQGRZKROG DQGWKHYDOLGGDWDZLQGRZDUHGHSLFWHGLQ)LJXUH$GHWDLOHGH[SODQDtion of t'46&.'46WUDQVLWLRQVNHZWR&.LVDOVRGHSLFWHGLQ)LJXUH $5($'EXUVWPD\EHIROORZHGE\D35(&+$5*(FRPPDQGWRWKHVDPH EDQN SURYLGHG $872 35(&+$5*( LV QRW $&7,9$7(' 7KH PLQLPXP 5($'WR35(&+$5*(FRPPDQGVSDFLQJWRWKHVDPHEDQNLVIRXUFORFNV DQGPXVWDOVRVDWLVI\DPLQLPXPDQDORJWLPHIURPWKH5($'FRPPDQG 7KLVWLPHLVFDOOHG t5735($'WR35(&+$5*( t573VWDUWV$/F\FOHV ODWHUWKDQWKH5($'FRPPDQG([DPSOHVIRU%/DUHVKRZQLQ)LJXUH DQG%&LQ)LJXUH)ROORZLQJWKH35(&+$5*(FRPPDQGDVXEVHTXHQWFRPPDQGWRWKHVDPHEDQNFDQQRWEHLVVXHGXQWLOt53LVPHW7KH 35(&+$5*(FRPPDQGIROORZHGE\DQRWKHU35(&+$5*(FRPPDQGWR WKHVDPHEDQNLVDOORZHG+RZHYHUWKHSUHFKDUJHSHULRGZLOOEHGHWHUPLQHGE\WKHODVW35(&+$5*(FRPPDQGLVVXHGWRWKHEDQN 'DWDIURPDQ\5($'EXUVWPD\EHFRQFDWHQDWHGZLWKGDWDIURPDVXEVHTXHQW5($'FRPPDQGWRSURYLGHDFRQWLQXRXVIORZRIGDWD7KHILUVWGDWD HOHPHQWIURPWKHQHZEXUVWIROORZVWKHODVWHOHPHQWRIDFRPSOHWHGEXUVW 7KH QHZ 5($' FRPPDQG VKRXOG EH LVVXHG t&&' F\FOHV DIWHU WKH ILUVW 5($'FRPPDQG7KLVLVVKRZQIRU%/LQ)LJXUH,I%&LVHQDEOHG t&&'PXVWVWLOOEHPHWZKLFKZLOOFDXVHDJDSLQWKHGDWDRXWSXWDVVKRZQ LQ)LJXUH1RQFRQVHFXWLYH5($'GDWDLVUHIOHFWHGLQ)LJXUH''5 6'5$0VGRQRWDOORZLQWHUUXSWLQJRUWUXQFDWLQJDQ\5($'EXUVW ,I$LV+,*+ZKHQD5($'FRPPDQGLVLVVXHGWKH5($'ZLWK$872 35(&+$5*( IXQFWLRQ LV HQJDJHG 7KH 6'5$0 VWDUWV DQ $872 35(&+$5*(RSHUDWLRQRQWKHULVLQJHGJHZKLFKLV$/t573F\FOHVDIWHUWKH 5($' FRPPDQG ''5 6'5$0V VXSSRUW D t5$6 ORFNRXW IHDWXUH VHH )LJXUH,I t5$60,1LVQRWVDWLVILHGDWWKHHGJHWKHVWDUWLQJSRLQWRI WKH$87235(&+$5*(RSHUDWLRQZLOOEHGHOD\HGXQWLOt5$60,1LVVDWLVILHG,QFDVHWKHLQWHUQDO35(&+$5*(RSHUDWLRQLVSXVKHGRXWE\t573 t53VWDUWVDWWKHSRLQWDWZKLFKWKHLQWHUQDO35(&+$5*(KDSSHQV7KH WLPH IURP 5($' ZLWK $872 35(&+$5*( WR WKH QH[W $&7,9$7( FRPPDQGWKHVDPHEDQNLV$/t573t53ZKHUHvwPHDQVURXQGHGXS WRWKHQH[WLQWHJHU,QDQ\HYHQWLQWHUQDO5(&+$5*(GRHVQRWVWDUWHDUOLHU WKDQIRXUFORFNVDIWHUWKHODVWQELWSUHIHWFK 'DWDIURPDQ\5($'EXUVWPXVWEHFRPSOHWHGEHIRUHDVXEVHTXHQW:5,7( EXUVWLVDOORZHG$QH[DPSOHRID5($'EXUVWIROORZHGE\D:5,7(EXUVW IRU %/ LV VKRZQ LQ )LJXUH 7R HQVXUH WKH 5($' GDWD LV FRPSOHWHG EHIRUHWKH:5,7(GDWDLVRQWKHEXVWKHPLQLPXP5($'WR:5,7(WLPLQJ LV5/t&&'y:/tCK. LOGIC Devices Incorporated Transitioning Data www.logicdevices.com 110 High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B LOGIC Devices Incorporated www.logicdevices.com Bank, Col n Add ress 2 DQ3 DQS, DQS# REA D T0 Command 1 CK CK# Notes: NOP T1 1. 2. 3. 4. 111 RL = 5 NOP T3 Bank, Col b REA D T4 t RPRE NOP T5 DO n DO n+1 NOP T6 DO n+3 RL = 5 DO n+2 DO n+4 NOP T7 DO n+5 DO n+6 NOP T8 DO n+7 NOP T9 DO b DO b+1 DO b+2 NOP T10 DO b+3 DO b+4 NO P T11 DO b+5 NOP T12 DO b+7 Transitioning Data DO b+6 t RPST NOP T13 Don ’t Care NOP T14 NOP commands are shown for ease of illustration; other commands may be valid at these times. The BL8 setting is activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during READ command at T0 and T4. DO n (or b) = data-out from column n (or column b). BL8, RL = 5 (CL = 5, AL = 0). t CCD NOP T2 L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module Figure 60 - Consecutive READ Bursts (BL8) High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B LOGIC Devices Incorporated www.logicdevices.com Bank, Col n Address 2 DQ3 DQS, DQS# READ T0 Comman d 1 CK CK# Notes: NOP T1 1. 2. 3. 4. 112 RL = 5 NOP T3 Bank, Col b READ T4 t RPRE NOP T5 DO n DO n+1 NOP T6 RL = 5 DO n+2 DO n+3 t RPST NOP T7 NOP T8 t RPRE NOP T9 DO b DO b+1 NOP T10 DO b+2 DO b+3 t RPST NOP T11 NOP T13 Transitioning Data NOP T12 Don ’t Care NOP T14 NOP commands are shown for ease of illustration; other commands may be valid at these times. The BC4 setting is activated by either MR0[1:0] = 10 or MR0[1:0] = 01 and A12 = 0 during READ command at T0 and T4. DO n (or b) = data-out from column n (or column b). BC4, RL = 5 (CL = 5, AL = 0). t CCD NOP T2 L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module Figure 61 - Consecutive READ Bursts (BC4) High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B LOGIC Devices Incorporated www.logicdevices.com DQ DQS, DQS# READ Bank a, Col n Add ress T0 Command CK CK# Notes: NOP T1 1. 2. 3. 4. NOP T2 CL = 8 NOP T4 Bank a, Col b READ T5 NOP T6 NOP T7 DO n NOP T8 CL = 8 NOP T9 NOP T10 NOP T11 NOP T12 NOP T13 DO b AL = 0, RL = 8. DO n (or b) = data-out from column n (or column b). Seven subsequent elements of data-out appear in the programmed order following DO n. Seven subsequent elements of data-out appear in the programmed order following DO b. NOP T3 NOP T14 NOP T15 Transitioning Data NOP T16 Don ’t Care NOP T17 L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module Figure 62 - Nonconsecutive READ Bursts 113 High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B LOGIC Devices Incorporated www.logicdevices.com Bank, Col n Add ress 2 114 DQ3 DQS, DQS# READ T0 Command 1 CK CK# NOP T2 NOP T3 NOP T4 NOP T5 Notes: DO n DO n+1 DO n+2 Bank, Col b WRITE T6 DO n+3 DO n+4 NOP T7 DO n+5 NOP T9 DO n+7 t RPST WL = 5 DO n+6 NOP T8 NOP T10 t WPRE DI n NOP T11 DI n+1 DI n+2 NOP T12 DI n+3 DI n+5 DI n+6 NOP T14 Transitioning Data DI n+4 t BL = 4 clocks NOP T13 Don ’t Care DI n+7 t WPST t WTR t WR NOP T15 1. NOP commands are shown for ease of illustration; other commands may be valid at these times. 2. The BL8 setting is activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during the READ command at T0, and the WRITE command at T6. RL = 5 t RPRE READ-to-WRITE command delay = RL + t CCD + 2t CK - WL NOP T1 L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module Figure 63 - READ (BL8) to WRITE (BL8) High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B LOGIC Devices Incorporated www.logicdevices.com DQ3 DQS, DQS# Add ress2 Command 1 CK CK# NOP T1 NOP T2 NOP T3 WRITE T4 Bank, Col n Notes: 1. 2. 3. 4. DO n NOP T5 DO n +1 NOP T7 DO n+ 3 t RPST WL = 5 DO n +2 NOP T6 NOP T8 t WPRE DI n NOP T9 DI n +1 DI n +2 NOP T10 DI n +3 t WPST t BL = 4 clo cks NOP T11 NOP T12 T14 t WR t WTR NOP Transitioning Data NOP T13 NOP T15 Don ’t Care NOP commands are shown for ease of illustration; other commands may be valid at these times. The BC4 OTF setting is activated by MR0[1:0] and A12 = 0 during READ command at T0 and WRITE command at T4. DO n = data-out from column n; DI n = data-in from column b. BC4, RL = 5 (AL - 0, CL = 5), WL = 5 (AL = 0, CWL = 5). RL = 5 t RPRE Bank, Col b READ-to-WRITE command delay = RL + t CC D/2 + 2 t CK - WL READ T0 L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module Figure 64 - READ (BC4) to WRITE (BC4) OTF High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B LOGIC Devices Incorporated www.logicdevices.com Bank, Col n Add ress 2 DQ3 DQS, DQS# READ T0 Command 1 CK CK# NOP T2 NOP T3 NOP T4 NOP T5 Notes: DO n DO n+1 DO n+2 Bank, Col b WRITE T6 DO n+3 DO n+4 NOP T7 DO n+5 NOP T9 DO n+7 t RPST WL = 5 DO n+6 NOP T8 NOP T10 t WPRE DI n NOP T11 DI n+1 DI n+2 NOP T12 DI n+3 DI n+5 DI n+6 NOP T14 Transitioning Data DI n+4 t BL = 4 clocks NOP T13 Don ’t Care DI n+7 t WPST t WTR t WR NOP T15 1. NOP commands are shown for ease of illustration; other commands may be valid at these times. 2. The BL8 setting is activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during the READ command at T0, and the WRITE command at T6. 3. DO n = data-out from column, DI b = data-in for column b. 4. BL8, RL = 5 (AL = 0, CL = 5), WL = 5 (AL = 0, CWL = 5). RL = 5 t RPRE READ-to-WRITE command delay = RL + t CCD + 2t CK - WL NOP T1 L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module Figure 65 - READ to PRECHARGE (BL8) High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module ACT PRE Don ’t Care DO n+3 DO n+2 NOP 117 DQ Add ress DQS, DQS# READ Bank a, Col n Command NOP T2 T1 T0 www.logicdevices.com CK C K# LOGIC Devices Incorporated t RAS t RTP T3 NOP T4 NOP T5 Bank a, (or all) T6 NOP T7 NOP T8 NOP DO n DO n+1 t RP T9 NOP T10 NOP NOP T11 T12 NOP Bank a, Row b T13 T14 NOP T15 NOP T16 NOP Transitioning Data NOP T17 Figure 66 - READ to PRECHARGE (BC4) High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module LOGIC Devices Incorporated www.logicdevices.com RL = AL + CL = 11 CL = 6 AL = 5 DQ DQS, DQS# CK Command BC4 CK# T0 ACTIVE n T1 READ n t RCD (MIN) T2 NOP T6 NOP T11 NOP T12 NOP Indicates a Break in Time Scale DO n DO n+1 T13 NOP DO n+2 Transitioning Data DO n+3 T14 NOP Don’t Care Figure 67 - READ to PRECHARGE (AL = 5, CL = 6) 118 High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module LOGIC Devices Incorporated www.logicdevices.com Don ’t Care t RP Indicates A Break in Time Scale DO n+2 t RAS (MIN) CL = 6 t RTP (MIN) AL = 4 DQ Add ress DQS, DQS# READ Bank a, Col n Command CK CK# T0 T1 NOP T2 NOP T3 NOP T4 NOP T5 NOP T6 NOP T7 NOP T8 NOP T9 NOP T10 NOP DO n DO n+1 NOP T11 DO n+3 T12 NOP T13 NOP Transitioning Data Bank a, Row b NOP Ta0 ACT Figure 68 - READ with Auto Precharge (AL = 4, CL = 6) 119 High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module READ $'46[WR'4RXWSXWWLPLQJLVVKRZQLQ)LJXUH7KH'4WUDQVLWLRQVEHWZHHQYDOLGGDWDRXWSXWVPXVWEHZLWKLQt'464RIWKHFURVVLQJSRLQWRI/>8@'46[ />8@'46[?'46PXVWDOVRPDLQWDLQDPLQLPXP+,*+DQG/2:WLPHRIt46+DQGt46/3ULRUWRWKH5($'SUHDPEOHWKH'4EDOOVZLOOHLWKHUEHIORDWLQJRU WHUPLQDWHGGHSHQGLQJRQWKHVWDWXVRIWKH2'7VLJQDO )LJXUHVKRZVWKHVWUREHWRFORFNWLPLQJGXULQJD5($'7KHFURVVLQJSRLQW'46['46[?PXVWWUDQVLWLRQZLWKt'46&.RIWKHFORFNFURVVLQJSRLQW7KH GDWDRXWKDVQRWLPLQJUHODWLRQVKLSWRFORFNRQO\WR'46DVVKRZQLQ)LJXUH )LJXUHDOVRVKRZVWKH5($'SUHDPEOHDQGSRVWDPEOH1RUPDOO\ERWK'46[DQG'46[?DUH+,*+=WRVDYHSRZHU9DD43ULRUWRGDWDRXWSXWIURPWKH 6'5$0'46[LVGULYHQ/2:DQG'46[?GULYHQ+,*+IRUt535(7KLVLVNQRZQDVWKH5($'SUHDPEOH 7KH5($'SRVWDPEOHt5367LVRQHKDOIFORFNIURPWKHODVW/>8@'46[/>8@'46[?WUDQVLWLRQ'XULQJWKH5($'SRVWDPEOH/>8@'46[LVGULYHQ/2:DQG/>8@ '46[?GULYHQ+,*+:KHQFRPSOHWHWKH'4ZLOOHLWKHUEHGLVDEOHGRUZLOOFRQWLQXHWHUPLQDWLQJGHSHQGLQJRQWKHVWDWHRIWKH2'7VLJQDO)LJXUHGHPRQVWUDWHVKRZWRPHDVXUHt5367 LOGIC Devices Incorporated www.logicdevices.com 120 High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B LOGIC Devices Incorporated www.logicdevices.com 121 Notes: All DQ collectively DQ3 (first data no lon ger valid) DQ3 (last data valid) 1. 2. 3. 4. 5. 6. 7. Bank, Col n Add ress 2 DQS, DQS# READ T0 Command 1 CK CK# NOP T2 RL = AL + CL NOP T3 t RPRE t DQSQ (MAX) t LZ (DQ) MIN NOP T4 Data valid DO n DO n t QH DO n NOP T5 t DQSQ (MAX) NOP T7 NOP T8 t RPST NOP T9 DO n+1 DO n+2 Data valid DO n+3 DO n+4 DO n+5 DO n+7 Transitioning Data DO n+6 t QH DO DO DO DO DO DO DO n+1 n+2 n+3 n+4 n+5 n+6 n+7 DO DO DO DO DO DO DO n+3 n+1 n+2 n+4 n+5 n+6 n+7 NOP T6 Don ’t Care t HZ (DQ) MAX NOP T10 NOP commands are shown for ease of illustration; other commands may be valid at these times. The BL8 setting is activated by either MR0[1, 0] = 0, 0 or MR0[0, 1] = 0, 1 and A12 = 1 during READ command at T0. DO n = data-out from column n. BL8, RL = 5 (AL = 0, CL = 5). Output timings are referenced to VCCQ/2 and DLL on and locked. t DQSQ defines the skew between DQS, DQS# to data and does not define DQS, DQS# to clock. Early data transitions may not always happen at the same DQ. Data transitions of a DQ can vary (either early or late) within a burst. NOP T1 L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module Figure 69 - Data Output Timing – tDQSQ and Data Valid Window High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module OUTPUT TIMING t+=DQG t/=WUDQVLWLRQVRFFXULQWKHVDPHDFFHVVWLPHDVYDOLGGDWDWUDQVLWLRQV7KHVHSDUDPHWHUVDUHUHIHUHQFHGWRDVSHFLILFYROWDJHOHYHOZKLFKVSHFLILHV ZKHQWKHGHYLFHRXWSXWLVQRORQJHUGULYLQJt+='46DQGt+='4RUEHJLQVGULYLQJt/='46t/='4)LJXUHVKRZVDPHWKRGWRFDOFXODWHWKHSRLQW ZKHQWKHGHYLFHLVQRWORQJHUGULYLQJ t+='46DQG t+='4RUEHJLQVGULYLQJ t/='46 t/='4E\PHDVXULQJWKHVLJQDODWWZRGLIIHUHQWYROWDJHV7KH DFWXDOYROWDJHPHDVXUHPHQWSRLQWVDUHQRWFULWLFDODVORQJDVWKHFDOFXODWLRQLVFRQVLVWHQW7KHSDUDPHWHUVt/='46t/='4t+='46DQGt+='4DUH defined as single-ended. LOGIC Devices Incorporated www.logicdevices.com 122 High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B LOGIC Devices Incorporated www.logicdevices.com DQS, DQS# late strobe DQS, DQS# early strobe CK# CK t LZ (DQS)MIN 123 t RPRE t RPRE Bit 0 Bit 0 t QSH Bit 2 Bit 1 t QSL t QSL t QSL Bit 2 t QSH Bit 3 Bit 4 Bit 5 t QSL Bit 4 Bit 5 Bit 6 Bit 7 t RPST Bit 6 Bit 7 t RPST t HZ (DQS) MAX T5 t HZ (DQS) MIN t DQSCK(MAX) T4 t DQSCK(MIN) t DQSCK(MAX) T3 t DQSCK(MIN) t DQSCK(MAX) Bit 3 t QSH T2 t DQSCK(MIN) t DQSCK(MAX) Bit 1 t QSH T1 t DQSCK(MIN) t LZ (DQS)MAX T0 RL measured to this point T6 L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module Figure 70 - Data Strobe Timing – READs High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module Figure 71 - Method for Calculating tLZ and tHZ VOH - xmV VTT + 2xmV VOH - 2xmV VTT + xmV t LZ (DQS), t LZ (DQ) t HZ (DQS), t HZ (DQ) T2 T1 VOL + 2xmV VTT - xmV VOL + xmV VTT - 2xmV LOGIC Devices Incorporated T2 t LZ (DQS),t LZ (DQ) begin point = 2 × T1 - T2 t HZ (DQS),t HZ (DQ) end point = 2 × T1 - T2 Notes: T1 1. Within a burst, the rising strobe edge is not necessarily fixed at t DQSCK (MIN) or t DQSCK (MAX). Instead, the rising strobe edge can vary between t DQSCK (MIN) and t DQSCK (MAX). 2. The DQS high pulse width is defined by t QSH, and the DQS low pulse width is defined by t QSL. Likewise, t LZ (DQS) MIN and t HZ (DQS) MIN are not tied to t DQSCK (MIN) (early strobe case) and t LZ (DQS) MAX and t HZ (DQS) MAX are not tied to t DQSCK (MAX) (late strobe case); however, they tend to track one another. 3. The minimum pulse width of the READ preamble is defined by t RPRE (MIN). The minimum pulse width of the READ postamble is defined by t RPST (MIN). www.logicdevices.com 124 High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module FIGURE 72 - tRPRE TIMING CK VTT CK# tA tB DQS VTT Single-ended signal, provided as background information tC tD VTT DQS# Single-ended signal, provided as background information T1 t RPRE begins DQS - DQS# t RPRE 0V T2 t RPRE ends Resultin g differential signal relevant for t RPRE specification FIGURE 73 - tRPST TIMING CK VTT CK# tA DQS Single-ended signal, provided as background information VTT tB tC tD DQS# VTT Single-ended signal, provided as background information t RPST DQS - DQS# Resultin g differential signal relevant for t RPST specification LOGIC Devices Incorporated www.logicdevices.com 0V T1 t RPST begins T2 t RPST ends High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module FIGURE 74 - tWPRE TIMING CK VTT CK# T1 t WPRE begins DQS - DQS# 0V t WPRE T2 t WPRE ends Resulting differential signal relevant for t WPRE specification FIGURE 75 - tWPST TIMING CK VTT CK# t WPST DQS - DQS# Resulting differential signal relevant for t WPST specification LOGIC Devices Incorporated www.logicdevices.com 0V T1 t WPST begins T2 t WPST ends High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module WRITE :5,7(EXUVWVDUHLQLWLDWHGZLWKD:5,7(FRPPDQG7KHVWDUWLQJ&2/801DQG%$1.DGGUHVVHVDUHSURYLGHGZLWKWKH:5,7(FRPPDQGDQG$87235(&+$5*(LVVHOHFWHGWKH52:EHLQJDFFHVVHGZLOOEH35(&+$5*('DWWKHHQGRI:5,7(EXUVW,I$87235(&+$5*(LVQRWVHOHFWHGWKH52:ZLOOUHPDLQ RSHQIRUVXEVHTXHQWDFFHVVHV$IWHUD:5,7(FRPPDQGKDVEHHQLVVXHGWKH:5,7(EXUVWPD\QRWEHLQWHUUXSWHG)RUWKHJHQHULF:5,7(FRPPDQGVXVHG LQ)LJXUHWKRXJK)LJXUH$87235(&+$5*(LVGLVDEOHG 'XULQJ:5,7(EXUVWVWKHILUVWYDOLGGDWDLQHOHPHQWLVUHJLVWHUHGRQDULVLQJHGJHRI'46[IROORZLQJWKH:5,7(/$7(1&<:/FORFNVODWHUDQGVXEVHTXHQW GDWDHOHPHQWVZLOOEHUHJLVWHUHGRQVXFFHVVLYHHGJHVRI'46[:5,7(/$7(1&<:/LVGHILQHGDVWKHVXPRI3267('&$6$'',7,9(/$7(1&<$/DQG &$6:5,7(/$7(1&<&:/:/ $/&:/7KHYDOXHVRI$/DQG&:/DUHSURJUDPPHGLQWKH05DQG05UHJLVWHUVUHVSHFWLYHO\3ULRUWRWKHILUVW YDOLG'46[HGJHDIXOOF\FOHLVQHHGHGLQFOXGLQJDGXPP\FURVVRYHURI'46['46[?DQGVSHFLILHGDVWKH:5,7(SUHDPEOHVKRZQLQ)LJXUH7KHKDOI F\FOHRQ'46[IROORZLQJWKHODVWGDWDLQHOHPHQWLVNQRZQDVWKH:5,7(SRVWDPEOH 7KHWLPHEHWZHHQWKH:5,7(FRPPDQGDQGWKHILUVWYDOLGHGJHRI'46[LV:/FORFNVt'466)LJXUHWKURXJK)LJXUHVKRZWKHQRPLQDOFDVHZKHUH QVKRZHYHU)LJXUHLQFOXGHVt'4660,1DQGt'4660$;FDVHV t'466 'DWDPD\EHPDVNHGIURPFRPSOHWLQJD:5,7(XVLQJGDWDPDVN7KHPDVNRFFXUVRQWKH'0EDOODOLJQHGWRWKH:5,7(GDWD,I'0LV/2:WKH:5,7( FRPSOHWHVQRUPDOO\,I'0LV+,*+WKDWELWRIGDWDLVPDVNHG 8SRQFRPSOHWLRQRIDEXUVWDVVXPLQJQRRWKHUFRPPDQGVKDYHEHHQLQLWLDWHGWKH'4ZLOOUHPDLQ+,*+=DQGDQ\DGGLWLRQDOLQSXWGDWDZLOOEHLJQRUHG 'DWDIRUDQ\:5,7(EXUVWPD\EHFRQFDWHQDWHGZLWKDVXEVHTXHQW:5,7(FRPPDQGWRSURYLGHDFRQWLQXRXVIORZRILQSXWGDWD7KHQHZ:5,7(FRPPDQG FDQEHt&&'FORFNVIROORZLQJWKHSUHYLRXV:5,7(FRPPDQG7KHILUVWGDWDHOHPHQWIURPWKHQHZEXUVWLVDSSOLHGDIWHUWKHODVWHOHPHQWRIDFRPSOHWHGEXUVW )LJXUHVDQGVKRZFRQFDWHQDWHGEXUVWV$QH[DPSOHRIQRQFRQVHFXWLYH:5,7(6LVVKRZQLQ)LJXUH 'DWDIRUDQ\:5,7(EXUVWPD\EHIROORZHGE\DVXEVHTXHQW5($'FRPPDQGDIWHUt:75KDVEHHQPHWVHH)LJXUHVDQG 'DWDIRUDQ\:5,7(EXUVWPD\EHIROORZHGE\DVXEVHTXHQW35(&+$5*(FRPPDQGSURYLGLQJt:5KDVEHHQPHWDVVKRZQLQ)LJXUHDQG)LJXUH %RWKtWTR and t:5VWDUWLQJWLPHPD\YDU\GHSHQGLQJRQWKHPRGHUHJLVWHUVHWWLQJVIL[HG%&%/YV27) LOGIC Devices Incorporated www.logicdevices.com 127 High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module FIGURE 76 - WRITE BURST T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 WRITE NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP CK# CK Command 1 WL = AL + CWL Address 2 Bank, Col n t DQSS t DSH t DSH t DSH t DSH t WPRE t DQSS(MIN) t WPST DQS, DQS# t DQSH t DQSL t DQSH DI n DQ3 t DQSL t DQSH DI n+1 DI n+2 t DQSL t DQSH DI n+3 t DSH DI n+4 t DQSL t DQSH DI n+5 t DSH DI n+6 t DQSL DI n+7 t DSH t DSH t WPRE t DQSS(NOM) t WPST DQS, DQS# t DQSH t DQSL t DQSH t DSS DI n DQ3 t DQSL t DQSH t DQSL t DQSH t DQSL t DQSH t DQSL t DSS t DSS t DSS t DSS DI n+1 DI n+2 DI n+3 DI n+4 DI n+5 DI n+6 DI n+7 t DQSS t WPRE t DQSS(MAX) t WPST DQS, DQS# t DQSH t DQSL t DQSH t DSS DI n DQ3 t DQSL t DQSH t DSS DI n+1 t DQSL t DQSH t DSS DI n+2 DI n+3 t DQSL t DQSH t DSS DI n+4 DI n+5 t DQSL t DSS DI n+6 DI n+7 Transitioning Data Notes: LOGIC Devices Incorporated Don ’t Care 1. NOP commands are shown for ease of illustration; other commands may be valid at these times. 2. The BL8 setting is activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during the WRITE command at T0. 3. DI n = data-in for column n. 4. BL8, WL = 5 (AL = 0, CWL = 5). 5. t DQSS must be met at each rising clock edge. 6. t WPST is usually depicted as ending at the crossing of DQS, DQS#; however, t WPST actually ends when DQS no longer drives LOW and DQS# no longer drives HIGH. www.logicdevices.com 128 High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module FIGURE 77 - CONSECUTIVE WRITE (BL8) TO WRITE (BL8) T0 T1 WRITE NOP T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 NOP NOP WRITE NOP NOP NOP NOP NOP NOP NOP t BL = 4 clocks NOP NOP T14 C K# CK Command 1 t CCD NOP t WR t WTR Add ress 2 Valid Valid t WPST t WPRE DQS, DQS# DI n DQ3 DI n+1 DI n+2 DI n+3 DI n+4 DI n+5 DI n+6 DI n+7 DI b DI b+1 DI b+2 DI b+3 DI b+4 DI b+5 DI b+6 DI b+7 WL = 5 WL = 5 Transitioning Data Notes: Don ’t Care 1. NOP commands are shown for ease of illustration; other commands may be valid at these times. 2. The BL8 setting is activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during the WRITE commands at T0 and T4. 3. DI n (or b) = data-in for column n (or column b). 4. BL8, WL = 5 (AL = 0, CWL = 5). FIGURE 78 - CONSECUTIVE WRITE (BC4) TO WRITE (BC4) VIA MRS OR OTF T0 T1 WRITE NOP T2 T3 T4 T5 T6 T7 T8 T9 T10 NOP NOP WRITE NOP NOP NOP NOP NOP NOP T11 T12 T13 NOP NOP NOP T14 C K# CK Command 1 t CCD t BL = 4 clo cks NOP t WR t WTR Address2 Vali d Vali d t WPRE t WPST t WPRE t WPST DQS, DQS# DI n DQ3 DI n+1 DI n+2 DI n+3 DI b DI b+1 DI b+2 DI b+3 WL = 5 WL = 5 Transitioning Data Notes: LOGIC Devices Incorporated 1. 2. 3. 4. Don ’t Care NOP commands are shown for ease of illustration; other commands may be valid at these times. BC4, WL = 5 (AL = 0, CWL = 5). DI n (or b) = data-in for column n (or column b). The BC4 setting is activated by MR0[1:0] = 01 and A12 = 0 during the WRITE command at T0 and T4. www.logicdevices.com 129 High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module FIGURE 79 - NONCONSECUTIVE WRITE TO WRITE T0 T1 T2 T3 T4 WRITE NOP NOP NOP NOP T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 NOP NOP NOP NOP NOP NOP NOP NOP C K# CK C ommand Add ress NOP WRITE Vali d NOP NOP NOP Vali d WL = C WL + AL = 7 WL = C WL + AL = 7 DQS, DQS# DI n DQ DI n+1 DI n+2 DI n+3 DI n+4 DI n+5 DI n+6 DI n+7 DI b DI b+1 DI b+2 DI b+3 DI b+4 DI b+5 DI b+6 DI b+7 DM Transitioning Data Notes: 1. 2. 3. 4. Don't Care DI n (or b) = data-in for column n (or column b). Seven subsequent elements of data-in are applied in the programmed order following DO n. Each WRITE command may be to any bank. Shown for WL = 7 (CWL = 7, AL = 0). FIGURE 80 - WRITE (BL8) TO READ (BL8) T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 WRITE NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP T11 Ta0 NOP READ CK# CK Command 1 t WTR 2 Add ress3 Vali d Vali d t WPRE t WPST DQS, DQS# DI n DQ4 DI n+1 DI n+2 DI n+3 DI n+4 DI n+5 DI n+6 DI n+7 WL = 5 Indicates a Break in Time Scale Notes: LOGIC Devices Incorporated Transitioning Data Don ’t Care 1. NOP commands are shown for ease of illustration; other commands may be valid at these times. 2. t WTR controls the WRITE-to-READ delay to the same device and starts with the first rising clock edge after the last write data shown at T9. 3. The BL8 setting is activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and MR0[12] = 1 during the WRITE command at T0. The READ command at Ta0 can be either BC4 or BL8, depending on MR0[1:0] and the A12 status at Ta0. 4. DI n = data-in for column n. 5. RL = 5 (AL = 0, CL = 5), WL = 5 (AL = 0, CWL = 5). www.logicdevices.com 130 High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B LOGIC Devices Incorporated www.logicdevices.com Vali d Add ress3 DQ 4 DQS, DQS# WRITE T0 Command 1 CK CK# Notes: 131 NOP T2 WL = 5 NOP T3 NOP T4 t WPRE DI n NOP T5 DI n+1 DI n+2 NOP T6 DI n+3 T8 NOP Indicates a Break in Time Scale t WPST NOP T7 NOP Transitioning Data t WTR 2 T9 Don ’t Care Vali d READ Ta0 1. NOP commands are shown for ease of illustrati on; other commands may be valid at these times. 2. t WTR controls the WRITE-to-READ delay to the same device and starts with the first rising clock edge after the last write data shown at T7. 3. The fixed BC4 setting is activated by MR0[1:0] = 10 during the WRITE command at T0 and the READ command at Ta0. 4. DI n = data-in for column n. 5. BC4 (fixed), WL = 5 (AL = 0, CWL = 5), RL = 5 (AL = 0, CL = 5). NOP T1 L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module FIGURE 81 - WRITE TO READ (BC4 MODE REGISTER SETTING) High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B LOGIC Devices Incorporated www.logicdevices.com Vali d Add ress 3 DQ 4 DQS, DQS# WRITE T0 C ommand 1 CK CK# Notes: NOP T1 132 WL = 5 NOP T3 NOP T4 t WPRE DI n NOP T5 DI n+1 DI n+2 NOP T6 DI n+3 t WPST t BL = 4 clo cks NOP T7 NOP T8 NOP T9 Indicates a Break in Time Scale t WTR 2 NOP T10 Transitioning Data NOP T11 RL = 5 Don ’t Care Vali d READ Tn NOP commands are shown for ease of illustration; other commands may be valid at these times. t WTR controls the WRITE-to -READ delay to the same device and starts after t BL. The BC4 OTF setting is activated by MR0[1:0] = 01 and A 12 = 0 during the WRITE command at T0 and the READ command at Tn. 4. DI n = data-in for column n. 5. BC4, RL = 5 (AL = 0, CL = 5), WL = 5 (AL = 0, CWL = 5). 1. 2. 3. NOP T2 L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module FIGURE 82 - WRITE (BC4 OTF) TO READ (BC4 OTF) High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module FIGURE 83 - WRITE (BL8) TO PRECHARGE CK# T0 T1 T2 T3 T4 T5 T6 T7 WRITE NOP NOP NOP NOP NOP NOP NOP T8 T9 T10 T11 T12 Ta0 Ta1 NOP NOP NOP NOP NOP NOP PRE CK Command Add ress Vali d Vali d t WR WL = AL + CWL DQS, DQS# DI n DQ BL8 DI n+1 DI n+2 DI n+3 DI n+4 DI n+5 DI n+6 DI n+7 Indicates a Break in Time Scale Notes: Transitioning Data Don ’t Care 1. DI n = data-in from column n. 2. Seven subsequent elements of data-in are applie d in the programmed order following DO n. 3. Shown for WL = 7 (AL = 0, CWL = 7). FIGURE 84 - WRITE (BC4 MODE REGISTER SETTING) TO PRECHARGE CK# T0 T1 T2 T3 T4 T5 T6 T7 WRITE NOP NOP NOP NOP NOP NOP NOP T8 T9 T10 T11 T12 Ta0 Ta1 NOP NOP NOP NOP NOP NOP PRE CK Comman d Add ress Vali d Vali d t WR WL = AL + CWL DQS, DQS# DI n DQ BC4 DI n+ 1 DI n+ 2 DI n+ 3 Indicates a Break in Time Scale Notes: LOGIC Devices Incorporated Transitioning Data Don ’t Care 1. NOP commands are shown for ease of illustration; other commands may be valid at these times. 2. The write recovery time ( t WR) is referenced from the first rising clock edge after the last write data is shown at T7. t WR specifies the last burst WRITE cycle until the PRECHARGE command can be issued to the same bank. 3. The fixed BC4 setting is activated by MR0[ 1:0] = 10 during the WRITE command at T0. 4. DI n = data-in for column n. 5. BC4 (fixed), WL = 5, RL = 5. www.logicdevices.com 133 High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module FIGURE 85 - WRITE (BC4 OTF) TO PRECHARGE T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 WRITE NOP NOP NOP NOP NOP NOP NOP NOP NOP Tn CK# CK Command 1 PRE t WR2 Bank, Col n Add ress 3 Valid t WPST t WPRE DQS, DQS # DI n DQ4 DI n+1 DI n+2 DI n+3 WL = 5 Indicates a Break In Time Scale Notes: Transitioning Data Don ’t Care 1. NOP commands are shown for ease of illustration; other commands may be valid at these times. 2. The write recovery time ( t WR) is referenced from the rising clock edge at T9. t WR specifies the last burst WRITE cycle until the PRECHARGE command can be issued to the same bank. 3. The BC4 setting is activated by MR0[1:0] = 01 and A12 = 0 during the WRITE command at T0. 4. DI n = data-in for column n. 5. BC4 (OTF), WL = 5, RL = 5. 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FIGURE 86 - DATA INPUT TIMING DQ S, DQS# t WPRE t DQSH t WPST t DQSL DI b DQ DM t DS t DH Transitioning Data LOGIC Devices Incorporated www.logicdevices.com 134 Don ’t Care High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module PRECHARGE ,QSXW$GHWHUPLQHVZKHWKHURQHEDQNRUDOOEDQNVDUHWREH35(&+$5*('DQGLQWKHFDVHZKHUHRQO\RQHEDQNLVWREHSUHFKDUJHGLQSXWV%$>@VHOHFW WKHDUUD\%$1. :KHQDOOEDQNVDUHWREH35(&+$5*('LQSXWV%$>@DUHWUHDWHGDVv'RQuW&DUHw$IWHUDEDQNLV35(&+$5*('LWLVLQWKH,'/(6WDWHDQGPXVWEH $&7,9$7('SULRUWRDQ\5($'RU:5,7(FRPPDQGVEHLQJLVVXHG SELF REFRESH 7KH6(/)5()5(6+FRPPDQGLVLQLWLDWHGOLNHD5()5(6+FRPPDQGH[FHSW&.(LV/2:7KH'//LVDXWRPDWLFDOO\GLVDEOHGXSRQHQWHULQJ6(/)5()5(6+ DQGLVDXWRPDWLFDOO\HQDEOHGDQGUHVHWXSRQH[LWLQJ6(/)5()5(6+$OOSRZHUVXSSO\LQSXWVLQFOXGLQJ95()&$ and V5()'4PXVWEHPDLQWDLQHGDWYDOLG OHYHOVXSRQHQWU\H[LWDQGGXULQJ6(/)5()5(6+PRGHRSHUDWLRQ95()'4PD\IORDWRUQRWGULYH9DD4ZKLOHLQWKH6(/)5()5(6+PRGHXQGHUFHUWDLQ FRQGLWLRQV xVss<V5()'4<VDDLVPDLQWDLQHG xV5()'4LVYDOLGDQGVWDEOHSULRUWR&.(JRLQJEDFN+,*+ x7KHILUVW:5,7(RSHUDWLRQPD\QRWRFFXUHDUOLHUWKDQFORFNVDIWHU95()'4 is valid x$OORWKHU6(/)5()5(6+PRGHH[LWWLPLQJUHTXLUHPHQWVDUHPHW 7KH6'5$0PXVWEHLGOHZLWKDOO%$1.6LQWKH35(&+$5*(VWDWHt53LVVDWLVILHGDQGQREXUVWVDUHLQSURJUHVVEHIRUHD6(/)5()5(6+HQWU\FRPPDQG FDQEHLVVXHG2'7PXVWDOVREHWXUQHGRIIEHIRUH6(/)5()5(6+HQWU\E\UHJLVWHULQJWKH2'7EDOO/2:SULRUWRWKH6(/)5()5(6+HQWU\FRPPDQGVHH v2Q'LH7HUPLQDWLRQ2'7IRUWLPLQJUHTXLUHPHQWV,I5TT_NOM and RTTB:5DUHGLVDEOHGLQWKHPRGHUHJLVWHUV2'7FDQEHDv'RQuW&DUHw$IWHUWKH6(/) 5()5(6+HQWU\FRPPDQGLVUHJLVWHUHG&.(PXVWEHKHOG/2:WRNHHSWKH6'5$0LQ6(/)5()5(6+PRGH $IWHUWKH6'5$0KDVHQWHUHG6(/)5()5(6+PRGHDOOH[WHUQDOFRQWUROVLJQDOVH[FHSW&.(DQG5(6(7?EHFRPHv'RQuW&DUHw7KH6'5$0LQLWLDWHVD PLQLPXPRIRQH5()5(6+FRPPDQGLQWHUQDOO\ZLWKLQWKHt&.(SHULRGZKHQLWHQWHUV6(/)5()5(6+PRGH 7KHUHTXLUHPHQWVIRUHQWHULQJDQGH[LWLQJ6(/)5()5(6+PRGHGHSHQGRQWKHVWDWHRIWKHFORFNGXULQJ6(/)5()5(6+PRGH)LUVWDQGIRUHPRVWWKHFORFN PXVWEHVWDEOHPHHWLQJt&.VSHFLILFDWLRQVZKHQ6(/)5()5(6+PRGHLVHQWHUHG,IWKHFORFNUHPDLQVVWDEOHDQGWKHIUHTXHQF\LQQRWDOWHUHGZKLOHLQ6(/) 5()5(6+PRGHWKHQWKH6'5$0LVDOORZHGWRH[LW6(/)5()5(6+DIWHUt&.(65LVVDWLVILHG&.(LVDOORZHGWRWUDQVLWLRQ+,*+ t&.(65ODWHUWKDQZKHQ &.(ZDVUHJLVWHUHG/2:6LQFHWKHFORFNUHPDLQVVWDEOHLQ6(/)5()5(6+PRGHQRIUHTXHQF\FKDQJHt&.65(DQGt&.65;DUHQRWUHTXLUHG+RZHYHU LIWKHFORFNLVDOWHUHGGXULQJ6(/)5()5(6+PRGHWKHQt&.65(DQGt&.65;PXVWEHVDWLVILHG:KHQHQWHULQJ6(/)5()5(6+t&.65(PXVWEHVDWLVILHG SULRUWRDOWHULQJWKHFORFNuVIUHTXHQF\3ULRUWRH[LWLQJ6(/)5()5(6+t&.65;PXVWEHVDWLVILHGSULRUWRUHJLVWHULQJ&.(+,*+ :KHQ&.(LV+,*+GXULQJ6(/)5()5(6+H[LW123RU'(6PXVWEHLVVXHGIRUt;6WLPHt;6LVUHTXLUHGIRUWKHFRPSOHWLRQRIDQ\LQWHUQDO5()5(6+WKDW LVDOUHDG\LQSURJUHVVDQGPXVWEHVDWLVILHGEHIRUHDYDOLGFRPPDQGQRWUHTXLULQJDORFNHG'//FDQEHLVVXHGWRWKHGHYLFHt;6LVDOVRWKHHDUOLHVWWLPHWKDWD 6(/)5()5(6+UHHQWU\PD\RFFXUVHH)LJXUH%HIRUHDFRPPDQGUHTXLULQJDORFNHG'//FDQEHDSSOLHGD=4&/FRPPDQGPXVWEHLVVXHGt=423(5 WLPLQJPXVWEHPHWDQGt;6'//PXVWEHVDWLVILHG2'7PXVWEHRIIGXULQJt;6'// LOGIC Devices Incorporated www.logicdevices.com High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module FIGURE 87 - SELF REFRESH ENTRY/EXIT TIMING T0 T1 T2 Ta0 Tb0 Tc 0 Tc1 Td0 Te0 Tf0 Vali d Vali d CK# CK t CKSRX1 t CKSRE1 t IS t IH t CPDED t IS CKE t CKESR (MIN)1 t IS ODT2 Vali d ODTL RESET# 2 Command SRE(REF)3 NOP NOP 4 SRX (NOP) NOP 5 Add ress Vali d 6 Vali d 7 Vali d Vali d t XS 6 , 9 t RP 8 t XSDLL7, 9 Enter self refresh mode (synchronous) Exit self refresh mode (asynchronous) Indicates a Break in Time Scale Notes: LOGIC Devices Incorporated Don ’t Care 1. The clock must be valid and stable meeting t CK specifications at least t CKSRE after entering self refresh mode, and at least t CKSRX prior to exiting self refresh mode, if the clock is stopped or altered between states Ta0 and Tb0. If the clock remains valid and unchanged from entry and during self refresh mode, then t CKSRE and t CKSRX do not apply; however, t CKESR must be satisfied prior to exiting at SRX. 2. ODT must be disabled and R TT off prior to entering self re fresh at state T1. If both R TT_NOM and RTT_WR are disabled in the mode registers, ODT can be a “Don’t Care.” 3. Self refresh entry (SRE) is synchronous via a REFRESH command with CKE LOW. 4. A NOP or DES command is required at T2 after the SRE command is issued prior to the inputs becoming “Don’t Care.” 5. NOP or DES commands are required prior to exiting self refresh mode until state Te0. 6. t XS is required before any commands not requiring a locked DLL. 7. t XSDLL is required before any commands requiring a locked DLL. 8. The device must be in the all banks idle state prior to entering self refresh mode. For example, all banks must be precharged, t RP must be met, and no data bursts can be in progress. 9. Self refresh exit is asynchronous; however, t XS and t XSDLL timings start at the first rising clock edge where CKE HIGH satisfies t ISXR at Tc1.t CKSRX timing is also measured so that t ISXR is satisfied at Tc1. www.logicdevices.com High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module EXTENDED TEMPERATURE USAGE /2*,&'HYLFHV,QFL02'''56'5$0PRGXOHVXSSRUWVWKHRSWLRQDOH[WHQGHGWHPSHUDWXUHUDQJHXSWRd&ZKLOHVXSSRUWLQJ6(/)5()5(6+$872 5()5(6+DQGVXSSRUW7AWHPSHUDWXUHV!&d&ZLWK0$18$/5()5(6+RQO\:KHQXVLQJ6(/)5()5(6+$8725()5(6+DQGWKHDPELHQW WHPSHUDWXUHLV!&657DQG$65RSWLRQVPXVWEHXVHG 7KHH[WHQGHGUDQJHWHPSHUDWXUHUDQJH6'5$0PXVWEH5()5(6+('H[WHUQDOO\DW;DQ\WLPHWKHDPELHQWWHPSHUDWXUHLV!&7KHH[WHUQDO5()5(6+,1*UHTXLUHPHQWLVDFFRPSOLVKHGE\UHGXFLQJWKH5()5(6+3(5,2'IURPPVWRPV6(/)5()5(6+PRGHUHTXLUHVWKHXVHRI$65RU657WRVXSSRUW WKHH[WHQGHGWHPSHUDWXUH TABLE 63: SELF REFRESH TEMPERATURE AND AUTO SELF REFRESH DESCRIPTION Field MR2 Bits 6HOI5HIUHVK7HPSHUDWXUH657 7 SRT Description ,I$65LVGLVDEOHG05>@ 657PXVWEHSURJUDPPHGWRLQGLFDWHt23(5GXULQJ6(/)5()5(6+ 05>@ 1RUPDORSHUDWLQJWHPSHUDWXUHUDQJHC to d& 05>@ ([WHQGHGRSHUDWLQJWHPSHUDWXUHUDQJH!C to d& ,I$65LVHQDEOHG05>@ 657PXVWEHVHWWRHYHQLIWKHH[WHQGHGWHPSHUDWXUHUDQJHLVVXSSRUWHG *MR2[7]=0: SRT is disabled. $XWR6HOI5HIUHVK$65 ASR :KHQ$65LVHQDEOHGWKH6'5$0DXWRPDWLFDOO\SURYLGHV6(/)5()5(6+SRZHUPDQDJHPHQWIXQFWLRQVUHIUHVKUDWH IRUDOOVXSSRUWHGRSHUDWLQJWHPSHUDWXUHYDOXHV 05>@ $65LVHQDEOHG0PXVW :KHQ$65LVQRWHQDEOHGWKH657ELWPXVWEHSURJUDPPHGWRLQGLFDWHt23(5GXULQJ6(/)5()5(6+RSHUDWLRQ 05>@ $65LVGLVDEOHGPXVWXVHPDQXDO6(/)5()5(6+657 TABLE 64: SELF REFRESH MODE SUMMARY MR2[6] (ASR) 0 0 MR2[7] (SRT) Permitted Operating Temperature Range for Self Refresh Mode SELF REFRESH Operation 0 6(/)5()5(6+0RGHLVVXSSRUWHGLQWKHQRUPDOWHPSHUDWXUHUDQJH 1RUPDO&WR& 1 6(/)5()5(6+0RGHLVVXSSRUWHGLQQRUPDODQGH[WHQGHGd&0$; 1RUPDODQGH[WHQGHG&WR& WHPSHUDWXUHUDQJHV:KHQ657LVHQDEOHGLWLQFUHDVHVVHOIUHIUHVKSRZHU FRQVXPSWLRQ 1 0 6HOIUHIUHVKPRGHLVVXSSRUWHGLQQRUPDODQGH[WHQGHGWHPSHUDWXUHUDQJHV 1RUPDODQGH[WHQGHG&WR& 6HOIUHIUHVKSRZHUFRQVXPSWLRQPD\EHWHPSHUDWXUHGHSHQGHQW 1 1 Illegal. POWER-DOWN MODE 3RZHUGRZQLVV\QFKURQRXVO\HQWHUHGZKHQ&.(LVUHJLVWHUHG/2:FRLQFLGHQWZLWKD123RU'(6FRPPDQG&.(LVQRWDOORZHGWRJR/2:ZKLOHHLWKHUDQ 056035=4&$/5($'RU:5,7(RSHUDWLRQLVLQSURJUHVV&.(LVDOORZHGWRJR/2:ZKLOHDQ\RIWKHRWKHUOHJDORSHUDWLRQVDUHLQSURJUHVV+RZHYHUWKH 32:(5'2:1,DDVSHFLILFDWLRQVDUHQRWDSSOLFDEOHXQWLOVXFKRSHUDWLRQVKDYHEHHQFRPSOHWHG'HSHQGLQJRQWKHSUHYLRXV6'5$0VWDWHDQGWKHFRPPDQG LVVXHGSULRUWR&.(JRLQJ/2:FHUWDLQWLPLQJFRQVWUDLQWVPXVWEHVDWLVILHGDVQRWHGLQ7DEOH7LPLQJGLDJUDPVGHWDLOLQJWKHGLIIHUHQW32:(5'2:1 PRGHHQWU\DQGH[LWVDUHVKRZQLQ)LJXUHWKURXJK)LJXUH LOGIC Devices Incorporated www.logicdevices.com 137 High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module TABLE 65: COMMAND TO POWER-DOWN ENTRY PARAMETERS Last Command prior to CKE Low 1 Parameter (MIN) Parameter Value Figure Idle or Active $&7,9$7( t$&73'(1 1tCK )LJXUH Idle or Active 35(&+$5*( t353'(1 1tCK )LJXUH 5($'RU5($'$3 t5'3'(1 RL = 4t&.tCK Figure 91 :5,7(%/27)%/056%&27) t:53'(1 :/t&.t:5tCK Figure 92 :/t&.t:5tCK Figure 92 :/t&.:5tCK Figure 93 :/t&.:5tCK Figure 93 5()5(6+ t5()3'(1 1tCK Figure 94 5()5(6+ t;3'// Greater of 10tCK or 24ns Figure 98 02'(5(*,67(56(7 t0563'(1 tMOD Figure 97 SDRAM Status Active Active :5,7(%&056 Active :5,7($3%/27)%/056%&27) Active t:5$3'(1 :5,7($3%&056 Active Idle POWER-DOWN Idle (QWHULQJ32:(5'2:1PRGHGLVDEOHVWKHLQSXWDQGRXWSXWEXIIHUVH[FOXGLQJ&.&.?2'7&.(DQG5(6(7?123RU'(6FRPPDQGVDUHUHTXLUHGXQWLO t&3'('KDVEHHQVDWLVILHGDWZKLFKWLPHDOOVSHFLILHGLQSXWRXWSXWEXIIHUVZLOOEHGLVDEOHG7KH'//VKRXOGEHLQDORFNHGVWDWHZKHQ32:(5'2:1LV HQWHUHGIRUWKHIDVWHVWPRGHWLPLQJ,IWKH'//LVQRWORFNHGGXULQJWKH32:(5'2:1HQWU\WKH'//PXVWEHUHVHWDIWHUH[LWLQJ32:(5'2:1IRUSURSHU 5($'RSHUDWLRQDVZHOODVV\QFKURQRXV2'7RSHUDWLRQ 'XULQJ32:(5'2:1HQWU\LIDQ\EDQNUHPDLQVRSHQDIWHUDOOLQSURJUHVVFRPPDQGVDUHFRPSOHWHWKH6'5$0ZLOOEHLQ$&7,9(32:(5'2:1,IDOO EDQNVDUHFORVHGDIWHUDOOLQSURJUHVVFRPPDQGVDUHFRPSOHWHWKH6'5$0ZLOOEHLQ35(&+$5*(32:(5'2:1PRGHRUIDVW(;,7PRGH:KHQHQWHULQJ 35(&+$5*(32:(5'2:1WKH'//LVWXUQHGRIILQVORZH[LWPRGHRUNHSWRQLQIDVW(;,7PRGH 7KH'//UHPDLQVRQZKHQHQWHULQJ$&7,9(32:(5'2:1DVZHOO2'7KDVVSHFLDOWLPLQJFRQVWUDLQWVZKHQVORZ(;,7PRGH35(&+$5*(32:(5 '2:1LVHQDEOHGDQGHQWHUHG5HIHUWRv$V\QFKURQRXV2'70RGHwIRUGHWDLOHG2'7XVDJHUHTXLUHPHQWVLQVORZ(;,7PRGH35(&+$5*(32:(5'2:1 $VXPPDU\RIWKHWZR32:(5'2:1PRGHVLVOLVWHGLQ7DEOH :KLOHLQHLWKHU32:(5'2:1VWDWH&.(LVKHOG/2:5(6(7?LVKHOG+,*+DQGDVWDEOHFORFNVLJQDOPXVWEHPDLQWDLQHG2'7PXVWEHLQDYDOLGVWDWHEXW DOORWKHULQSXWVLJQDOVDUHDv'RQuW&DUHw,I5(6(7?JRHV/2:GXULQJ32:(5'2:1WKH6'5$0ZLOOVZLWFKRXWRI32:(5'2:1DQGJRLQWRWKH5(6(7 VWDWH$IWHU&.(LVUHJLVWHUHG/2:&.(PXVWUHPDLQ/2:XQWLO t3'0,1KDVEHHQVDWLVILHG7KHPD[LPXPWLPHDOORZHGIRU32:(5'2:1GXUDWLRQLV t3'0$;[W5(), 7KH32:(5'2:1VWDWHVDUHV\QFKURQRXVO\H[LWHGZKHQ&.(LVUHJLVWHUHG+,*+ZLWKDUHTXLUHG123RU'(6FRPPDQG&.(PXVWEHPDLQWDLQHG+,*+ until t&.(KDVEHHQVDWLVILHG$YDOLGH[HFXWDEOHFRPPDQGPD\EHDSSOLHGDIWHU32:(5'2:1(;,7/$7(1&<t;3t;3'//KDYHEHHQVDWLVILHG$VXPPDU\RIWKH32:(5'2:1PRGHVLVOLVWHGLQ7DEOH TABLE 66: POWER-DOWN MODES MR1[12] DLL State POWER-DOWN exit v'RQuW&DUHw ON FAST t;3WRDQ\RWKHUYDOLG&200$1' 1 ON FAST t;3WRDQ\RWKHUYDOLG&200$1' 0 OFF SLOW SDRAM State $&7,9(DQ\EDQNRSHQ 35(&+$5*(DOOEDQNV35(&+$5*(' Relevant Parameters t;'//WR&200$1'6WKDWUHTXLUHWKH'// WREHORFNHG5($'5'$32'721 t;3WRDQ\RWKHUYDOLG&200$1' LOGIC Devices Incorporated www.logicdevices.com 138 High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module FIGURE 88 - ACTIVE POWER-DOWN ENTRY AND EXIT T0 T1 T2 Ta0 Ta1 Ta2 Ta3 Ta4 NOP NOP NOP Valid CK# CK Command t CK t CH t CL NOP Valid NOP t PD t IS CKE Address t IH t IS t IH t CKE (MIN) Valid Valid t CPDED t XP Enter power-down mode Exit power-down mode Indicates a Break in Time Scale Don’t Care FIGURE 89 - PRECHARGE POWER-DOWN (FAST-EXIT MODE) ENTRY AND EXIT T0 T1 T2 T3 T4 T5 NOP NOP Ta0 Ta1 NOP Valid CK# CK Co m m an d t CK t CH t CL NOP NOP t CPDED t CKE (MIN) t IH t IS tCKEmin CKE tCKEmin t IS t XP t PD Enter power-down mode Exit power-down mode Indicates a Break in Time Scale LOGIC Devices Incorporated www.logicdevices.com 139 Don’t Care High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module FIGURE 90 - PRECHARGE POWER-DOWN (SLOW-EXIT MODE) ENTRY AND EXIT T0 T1 T2 T3 T4 Ta Ta1 NOP NOP Tb CK# CK t CK Command t CH t CL NOP PRE NOP Valid 1 Valid 2 t CKE (MIN) t CPDED t XP t IS t IH CKE t IS t XPDLL t PD Enter power-down mode Exit power-down mode Indicates a Break in Time Scale Notes: Don’t Care 1. Any valid command not requiring a locked DLL. 2. Any valid command requiring a locked DLL. FIGURE 91 - POWER-DOWN ENTRY AFTER READ OR READ WITH AUTO PRECHARGE (RDAP) CK# T0 T1 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Ta6 READ/ RDAP NOP NOP NOP NOP NOP NOP NOP NOP Ta7 Ta8 Ta9 Ta10 Ta11 Ta12 CK Command NOP t IS NOP t CPDED CKE Add ress Vali d t PD RL = AL + CL DQS, DQS# DQ BL8 DQ BC4 DI n DI DI n+1 n+2 DI n+3 DI n DI n+1 DI n+3 DI n+2 DI n+4 DI n+ 5 DI n+6 DI n+7 t RDPDEN Power- down or self refresh entry Indicates a break in Time Scale LOGIC Devices Incorporated www.logicdevices.com 140 Transitioning Data Don ’t Care High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module FIGURE 92 - POWER-DOWN ENTRY AFTER WRITE CK# T0 T1 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Ta6 Ta7 Tb0 WRITE NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP Tb1 Tb2 Tb3 Tb4 CK Command NOP t IS NOP t CPDED CKE Add ress Valid t WR WL = AL + CWL t PD DQS, DQS# DQ BL8 DI n DI DI n+1 n+2 DI n+3 DQ BC4 DI n DI n+1 DI n+3 DI n+2 DI n+4 DI n+5 DI n+6 DI n+7 t WRPDEN Power- down or self refresh entry 1 Indicates A Break in Time Scale Transitioning Data Don ’t Care 1. CKE can go LOW 2 tCK earlier if BC4MRS. Notes: FIGURE 93 - POWER-DOWN ENTRY AFTER WRITE WITH AUTO PRECHARGE (WRAP) CK# T0 T1 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Ta6 Ta7 Tb0 Tb1 Tb2 WRAP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP Tb3 Tb4 CK Command t IS t CPDED CKE Add ress Vali d A10 WR1 WL = AL + CWL t PD DQS, DQS# DQ BL8 DI n DI n+1 DI n+2 DI DI n+3 n+4 DQ BC4 DI n DI n+1 DI n+2 DI n+3 DI n+5 DI n+6 DI n+7 t WRAPDEN Start internal pre char ge Power- down or self refresh entry 2 Indicates a Break in Time Scale Notes: LOGIC Devices Incorporated Transitioning Data Don ’t Care is programmed through MR0[11:9] and represents t WR (MIN)ns/ t CK rounded up to the next integer t CK. 2. CKE can go LOW 2 tCK earlier if BC4MRS. 1. t WR www.logicdevices.com 141 High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module FIGURE 94 - REFRESH TO POWER-DOWN ENTRY T0 T1 T2 T3 NOP NOP Ta0 Ta1 Ta2 Tb0 NOP NOP Valid CK# CK t CK Command t CH t CL REFRESH t CPDED t CKE (MIN) t PD t IS CKE t XP (MIN) t REFPDEN t RFC (MIN)1 Indicates a Break In Time Scale Notes: Don’t Care 1. After CKE goes HIGH during t RFC, CKE must remain HIGH until t RFC is satisfied. FIGURE 95 - ACTIVATE TO POWER-DOWN ENTRY T0 T1 T2 T3 T4 T5 T6 T7 CK# CK Command Address t CK t CH t CL ACTIVE NOP NOP Valid t CPDED t IS t PD CKE t ACTPDEN tCKE Don’t Care LOGIC Devices Incorporated www.logicdevices.com 142 High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module FIGURE 96 - PRECHARGE TO POWER-DOWN ENTRY T0 T1 T2 T3 NOP NOP T4 T5 T6 T7 CK# CK t CK Command t CH t CL PRE All/single bank Address t CPDED t IS t PD CKE t PREPDEN Don’t Care FIGURE 97 - MRS COMMAND TO POWER-DOWN ENTRY T0 T1 T2 Ta0 Ta1 Ta2 Ta3 Ta4 CK# CK t CK Command MRS Address Valid t CH NOP t CL t CPDED NOP NOP NOP NOP t PD t MRSPDEN t IS CKE Indicates a Break in Time Scale LOGIC Devices Incorporated www.logicdevices.com 143 Don’t Care High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module FIGURE 98 - POWER-DOWN EXIT TO REFRESH TO POWER-DOWN ENTRY T0 T1 T2 T3 T4 Ta0 Ta1 Tb0 NOP REFRESH NOP NOP CK# CK Command t CK NOP t CH t CL NOP NOP t CPDED t XP1 t IH t IS CKE t IS t PD t XPDLL2 Enter power-down mode Exit power-down mode Enter power-down mode Indicates a Break in Time Scale Notes: Don’t Care 1. t XP must be satisfied before issuing the command. 2. t XPDLL must be satisfied (referenced to the registration of power-down exit) before the next power-down can be entered. RESET 7KH5(6(7VLJQDO5(6(7?LVDQDV\QFKURQRXVVLJQDOWKDWWULJJHUVDQ\WLPHLWGURSV/2:DQGWKHUHDUHQRUHVWULFWLRQVDERXWZKHQLWFDQJR/2:$IWHU 5(6(7?LVGULYHQ/2:LWPXVWUHPDLQ/2:IRUQV'XULQJWKLVWLPHWKHRXWSXWVDUHGLVDEOHG2'75TTWXUQVRII+,*+=DQGWKH''56'5$0UHVHWV LWVHOI&.(VKRXOGEHEURXJKW/2:SULRUWR5(6(7?EHLQJGULYHQ+,*+$IWHU5(6(7?JRHV+,*+WKH6'5$0PXVWEHUHLQLWLDOL]HGDVWKRXJKDQRUPDO SRZHUXSZHUHH[HFXWHGVHH)LJXUH$OOUHIUHVKFRXQWHUVRQWKH6'5$0DUH5(6(7DQGGDWDVWRUHGLQWKH6'5$0LVDVVXPHGXQNQRZQDIWHU5(6(7? KDVEHHQGULYHQ/2: LOGIC Devices Incorporated www.logicdevices.com 144 High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module FIGURE 99 - RESET SEQUENCE System RESET (warm boot) Sta ble an d vali d clo ck T1 T0 Tc0 Tb0 Ta0 t CK Td0 CK# CK t CL t CL T (MIN) = MAX (10ns, 5 t CK) T = 100ns (MIN) RESET# t IOZ T=10ns (MIN) t IS Vali d CKE ODT Vali d Vali d Vali d Vali d ZQ CL Vali d t IS MRS MRS MRS MRS Add ress Code Code Code Code A10 Code Code Code Code BA0 = L BA1 = H BA2 = L BA0 = H BA1 = H BA2 = L BA0 = H BA1 = L BA2 = L BA0 = L BA1 = L BA2 = L Command NOP DM BA[2:0] DQS DQ RTT A10 = H Vali d Vali d High-Z High-Z High-Z t MRD t MRD t XPR T = 500μs (MIN) MR2 All voltage supplies valid and stable Vali d MR3 DRAM rea dy for external commands t MRD MR1 with DLL ENABLE t MOD MR0 with DLL RESET ZQ CAL t ZQ INIT t DLLK Normal operation Indicates a Break in Time Scale LOGIC Devices Incorporated www.logicdevices.com Don ’t Care High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module ON-DIE TERMINATION (ODT) FUNCTIONAL REPRESENTATION OF ODT 2'7LVDIHDWXUHWKDWHQDEOHVWKH6'5$0WRHQDEOHGLVDEOHRQGLHWHUPLQDWLRQUHVLVWDQFHIRUHDFK'4/'46[/'46[?8'46[8'46[?/'0[DQG 8'0[IRUWKHIRXUZRUGVFRQWDLQHGLQ/',uV''5L02' 7KHYDOXHRI5TT2'7WHUPLQDWLRQYDOXHLVGHWHUPLQHGE\WKHVHWWLQJVRI VHYHUDOPRGHUHJLVWHUELWVVHH7DEOH7KH2'7EDOOLVLJQRUHGZKLOH LQ 6(/) 5()5(6+ PRGH PXVW EH WXUQHG RII SULRU WR 6(/) 5()5(6+ HQWU\RULIPRGHUHJLVWHUV05DQG05DUHSURJUDPPHGWRGLVDEOH2'7 2'7LVFRPSULVHGRIQRPLQDO2'7DQGG\QDPLF2'7PRGHVDQGHLWKHURI WKHVHFDQIXQFWLRQLQV\QFKURQRXVRUDV\QFKURQRXVPRGHVZKHQWKH'// LVRIIGXULQJ35(&+$5*(32:(5'2:1RUZKHQWKH'//LVV\QFKURQL]LQJ 1RPLQDO 2'7 LV WKH EDVH WHUPLQDWLRQ DQG LV XVHG LQ DQ\ DOORZDEOH 2'7VWDWH'\QDPLF2'7LVDSSOLHGRQO\GXULQJ:5,7(VDQGSURYLGHV27) VZLWFKLQJIURPQR5TT or RTT_NOM to RTT_WR. 7KH 2'7 IHDWXUH LV GHVLJQHG WR LPSURYH VLJQDO LQWHJULW\ RI WKH PHPRU\ DUUD\VXEV\VWHP E\ HQDEOLQJ WKH ''5 PHPRU\ FRQWUROOHU WR LQGHSHQGHQWO\ WXUQ RQ RU RII WKH 6'5$06 LQWHUQDO WHUPLQDWLRQ UHVLVWDQFH IRU DQ\ JURXSLQJRI6'5$0GHYLFHV7KH2'7IHDWXUHLVQRWVXSSRUWHGGXULQJ'// GLVDEOHPRGH$VLPSOHIXQFWLRQDOUHSUHVHQWDWLRQRIWKH6'5$02'7IHDWXUHLVVKRZQLQ)LJXUH7KHVZLWFKLVHQDEOHGE\WKHLQWHUQDO2'7FRQWUROORJLFZKLFKXVHVWKHH[WHUQDO2'7EDOODQGRWKHUFRQWUROLQIRUPDWLRQ 7KH DFWXDO HIIHFWLYH WHUPLQDWLRQ 5TTB()) PD\ EH GLIIHUHQW IURP WKH 5TT WDUJHWHGGXHWRQRQOLQHDULW\RIWKHWHUPLQDWLRQ)RU5TTB())YDOXHVDQG FDOFXODWLRQVVHHv2'7&KDUDFWHULVWLFVw FIGURE 100 - ON-DIE TERMINATION NOMINAL ODT 2'7 120 LV WKH EDVH WHUPLQDWLRQ UHVLVWDQFH IRU HDFK DSSOLFDEOH EDOO HQDEOHGRUGLVDEOHGYLD05>@VHH)LJXUHDQGLWLVWXUQHGRQRU RIIYLDWKH2'7EDOO ODT To other circuitry such as RCV, ... VDDQ/2 RTT Switch DQ, DQS, DQS#, DM TABLE 67: POWER-DOWN MODES MR1[9,6,2] SDRAM Termination State SDRAM State Notes 000 ODT Pin 0 RTT_NOM disabled, ODT OFF $Q\YDOLG 1,2 000 1 RTT_NOM disabled, ODT ON $Q\YDOLGH[FHSW6(/)5()5(6+5($' 1,3 000-101 0 RTT_NOM enabled, ODT OFF $Q\YDOLG 1,2 000-101 1 RTT_NOM enabled, ODT ON $Q\YDOLGH[FHSW6(/)5()5(6+5($' 1,3 110 and 111 ; RTT_NOM reserved, ODT ON or OFF Illegal 127(6 1. $VVXPHVG\QDPLF2'7LVGLVDEOHG 2. 2'7LVHQDEOHGDQGDFWLYHGXULQJPRVW:5,7(6IRUSURSHUWHUPLQDWLRQ 3. 2'7PXVWEHGLVDEOHGGXULQJ5($'V7KHRTTB120YDOXHLVUHVWULFWHG GXULQJ:5,7(6'\QDPLF2'7LVDSSOLFDEOHLIHQDEOHG EXWLWLVQRWLOOHJDOWRKDYHLWRIIGXULQJ:5,7(6 LOGIC Devices Incorporated www.logicdevices.com High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module NOMINAL ODT 1RPLQDO2'7UHVLVWDQFH5TTB120LVGHILQHGE\05>@DVVKRZQLQ)LJXUH7KH5TTB120WHUPLQDWLRQYDOXHDSSOLHVWRWKHRXWSXWSLQVSUHYLRXVO\ PHQWLRQHG''56'5$0L02'VVXSSRUWPXOWLSOH5TTB120YDOXHVEDVHGRQ5=4QZKHUHQFDQEHRUDQG5=4LV:5TTB120WHUPLQDWLRQLVDOORZHGDQ\WLPHDIWHUWKH6'5$0LVLQLWLDOL]HGFDOLEUDWHGDQGQRWSHUIRUPLQJ5($'DFFHVVHVRUZKHQLWLVQRWLQ6(/)5()5(6+PRGH :5,7(DFFHVVXVHV5TTB120LGG\QDPLF2'75TTB:5LVGLVDEOHG,I5TTB120LVXVHGGXULQJ:5,7(VRQO\5=45=4DQG5=4DUHDOORZHGVHH 7DEOH2'7WLPLQJVDUHVXPPDUL]HGLQ7DEOHDVZHOODVOLVWHGLQ7DEOH ([DPSOHVRIQRPLQDO2'7WLPLQJDUHVKRZQLQFRQMXQFWLRQZLWKWKHV\QFKURQRXVPRGHRIRSHUDWLRQLQv6\QFKURQRXV2'70RGHw TABLE 68: ODT PARAMETER Begins at Defined to Definition for All DDR3 bins Units ODTL ON 2'7V\QFKURQRXVWXUQRQGHOD\ 2'7UHJLVWHUHG+,*+ RTTB21tAON &:/$/ tCK ODTL OFF 2'7V\QFKURQRXVWXUQRIIGHOD\ 2'7UHJLVWHUHG+,*+ RTTB21tAOF &:/$/ tCK t$213' 2'7DV\QFKURQRXVRQGHOD\ 2'7UHJLVWHUHG+,*+ RTT_ON 1-9 ns t$2))3' 2'7DV\QFKURQRXVRQGHOD\ 2'7UHJLVWHUHG+,*+ RTT_OFF 1-9 ns ODT registered LOW 4tCK tCK tCK Symbol Description 2'7UHJLVWHUHG+,*+RU:5,7( 2'7+ 2'7PLQLPXP+,*+WLPHDIWHU2'7DVVHUWLRQ RU:5,7(%& UHJLVWUDWLRQZLWK2'7+,*+ 2'7+ 2'7PLQLPXP+,*+WLPHDIWHU:5,7(%/ :5,7(UHJLVWUDWLRQZLWK2'7+,*+ ODT registered LOW tCK tAON 2'7WXUQRQUHODWLYHWR2'7/RQFRPSOHWLRQ &RPSOHWLRQRI2'7/RQ RTT_ON See Table 47 SV t&.tCK tCK tAOF 2'7WXUQRIIUHODWLYHWR2'7/RIIFRPSOHWLRQ &RPSOHWLRQRI2'7/RII RTT_OFF DYNAMIC ODT ,QFHUWDLQDSSOLFDWLRQVWRIXUWKHUHQKDQFHVLJQDOLQWHJULW\RQWKHGDWDEXVLWLVGHVLUDEOHWKDWWKHWHUPLQDWLRQVWUHQJWKEHFKDQJHGZLWKRXWLVVXLQJDQ056 FRPPDQGHVVHQWLDOO\FKDQJLQJWKH2'7WHUPLQDWLRQUHVLVWDQFHRQWKHIO\:LWKG\QDPLF2'75TTB:5HQDEOHGWKH6'5$0VZLWFKHVIURPQRPLQDO2'7 (RTTB120WRG\QDPLF2'7ZKHQEHJLQQLQJD:5,7(EXUVWDQGVXEVHTXHQWO\VZLWFKHVEDFNWRQRPLQDO2'7DWWKHFRPSOHWLRQRIWKH:5,7(EXUVWVHTXHQFH 7KLVUHTXLUHPHQWDQGWKHVXSSRUWLQJ'<1$0,&2'7IHDWXUHRIWKH''56'5$0PDNHVLWIHDVLEOHDQGLVGHVFULEHGLQIXUWKHUGHWDLOEHORZ DYNAMIC ODT FUNCTIONAL DESCRIPTION: 7KHG\QDPLF2'7PRGHLVHQDEOHGLIHLWKHU05>@RUP5>@LVVHWWRvw'\QDPLF2'7LVQRWVXSSRUWHGGXULQJ'//GLVDEOHPRGHVR5TTB:5PXVWEH GLVDEOHG7KHG\QDPLF2'7IXQFWLRQLVGHVFULEHGDVIROORZV xTwo RTT values are available – RTT_NOM and RTT_WR: x7KHYDOXHRI5TTB120LVSUHVHOHFWHGYLD05>@ x7KHYDOXHIRU5TTB:5LVSUHVHOHFWHGYLD05>@ x'XULQJ6'5$0RSHUDWLRQVZLWKRXW5($'RU:5,7(FRPPDQGVWKHWHUPLQDWLRQLVFRQWUROOHGDVIROORZV x7HUPLQDWLRQ212))WLPLQJLVFRQWUROOHGYLDWKH2'7EDOODQG/$7(1&,(62'7ORQDQG2'7/RII x1RPLQDOWHUPLQDWLRQVWUHQJWK5TT_NOM is used x:KHQD:5,7(FRPPDQG:5:5$3:56:56:5$36:5$36LVUHJLVWHUHGDQGLIG\QDPLF2'7LVHQDEOHGWKH2'7WHUPLQDWLRQLVFRQWUROOHGDVIROORZV x$ODWHQF\RI2'7/&1:DIWHUWKH:5,7(FRPPDQGWHUPLQDWLRQVWUHQJWK5TTB120VZLWFKHVWR5TT_WR x$/DWHQF\RI2'7/&:1IRU%/IL[HGRU27)RU2'7/&:1IRU%&IL[HGRU27)DIWHUWKH:5,7(FRPPDQGWHUPLQDWLRQ VWUHQJWK5TTB:5VZLWFKHVEDFNWR5TT_NOM x212))WHUPLQDWLRQWLPLQJLVFRQWUROOHGYLDWKH2'7EDOODQGGHWHUPLQHGE\2'7/RQ2'7/RII2'7+DQG2'7+ x'XULQJWKHt$'&WUDQVLWLRQZLQGRZWKHYDOXHRI5TT is undefined 2'7LVFRQVWUDLQHGGXULQJ:5,7(VDQGZKHQG\QDPLF2'7LVHQDEOHGVHH7DEOH LOGIC Devices Incorporated www.logicdevices.com 147 High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module TABLE 69: DYNAMIC ODT SPECIFIC PARAMETERS Symbol Description Begins at Defined to Definition for All DDR3 bins Units ODTLCNW &KDQJHIURP5TT_NOM to RTT_WR :5,7(UHJLVWUDWLRQ RTTVZLWFKHGIURP5TT_NOM to RTT_WR WL - 2 tCK ODTLCWN4 &KDQJHIURP5TT_WR to RTTB120%& :5,7(UHJLVWUDWLRQ RTTVZLWFKHGIURP5TT_WR to RTT_NOM 4t&.2'7/2)) tCK tCK tCK ODTLCWN8 &KDQJHIURP5TT_WR to RTTB120%/ :5,7(UHJLVWUDWLRQ RTTVZLWFKHGIURP5TT_WR to RTT_NOM t&.2'7/2)) tADC RTTFKDQJHVNHZ ODTLCNW RTTWUDQVFRPSOHWH t&.tCK TABLE 70: MODE REGISTERS FOR RTT_NOM M9 MR1(RTT_NOM) M6 0 0 0 0 0 0 M2 RTT_NOM (RZQ) RTT_NOM(Ohms) RTT_NOM Mode Restriction 0 Off Off QD 1 5=4 6(/)5()5(6+ 1 0 5=4 120 1 1 5=4 40 1 0 0 5=4 20 1 0 1 5=4 30 1 1 0 Reserved Reserved QD 1 1 1 Reserved Reserved QD 6(/)5()5(6+:5,7( TABLE 71: MODE REGISTERS FOR RTT_WR MR1(RTT_NOM) M10 M2 0 0 0 1 1 0 5=4 120 1 1 Reserved Reserved QD QD QD QD QD QD QD QD QD QD QD QD QD QD QD QD RTT_NOM (RZQ) RTT_NOM(Ohms) Dynamic ODT OFF: WRITE does not affect RTT_NOM 5=4 TABLE 72: TIMING DIAGRAMS FOR DYNAMIC ODT Figure Title '\QDPLF2'72'7DVVHUWHGEHIRUHDQGDIWHUWKH:5,7(%& Figure 101 Figure 102 '\QDPLF2'7:LWKRXW:5,7(FRPPDQG Figure 103 '\QDPLF2'72'7SLQDVVHUWHGWRJHWKHUZLWK:5,7(FRPPDQGIRU&.F\FOHV%/ Figure 104 '\QDPLF2'72'7SLQDVVHUWHGZLWK:5,7(FRPPDQGIRU&.F\FOHV%& )LJXUH '\QDPLF2'72'7SLQDVVHUWHGZLWK:5,7(FRPPDQGIRU&.F\FOHV%& LOGIC Devices Incorporated www.logicdevices.com 148 High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module FIGURE 101 - DYNAMIC ODT: ODT ASSERTED BEFORE AND AFTER THE WRITE, BC4 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 NOP NOP NOP NOP WRS4 NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP CK# CK Command Add ress Vali d ODTH4 ODTL off ODTH4 ODT ODTLCWN 4 ODTL on t ADC (MIN) t AON (MIN) RTT RTT_NOM t AON (MAX) t ADC (MIN) t AOF (MIN) RTT_WR RTT_NOM t AOF (MAX) t ADC (MAX) t ADC (MAX) ODTLCNW DQS, DQS# DQ DI n WL DI n +1 DI n +2 DI n +3 Transitioning Notes: Don ’t Care 1. Via MRS or OTF. AL = 0, CWL = 5. RTT_NOM and RTT_WR are enabled. 2. ODTH4 applies to first registering ODT HIGH and then to the registration of the WRITE command. In this example, ODTH4 is satisfied if ODT goes LOW at T8 (four clocks after the WRITE command). FIGURE 102 - DYNAMIC ODT: WITHOUT WRITE COMMAND CK# CK Command T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 Vali d Vali d Vali d Vali d Vali d Vali d Vali d Vali d Vali d Vali d Vali d Vali d Add ress ODTH4 ODTL on ODTL off ODT t AON (MAX) t AOF (MIN) RTT_NOM RTT t AOF (MAX) t AON (MIN) DQS, DQS# DQ Transitionin g Notes: LOGIC Devices Incorporated Don ’t Care 1. AL = 0, CWL = 5. RTT_NOM is enabled and R TT_WR is either enabled or disabled. 2. ODTH4 is defined from ODT registered HIGH to ODT registered LOW; in this example, ODTH4 is satisfied. ODT registered LOW at T5 is also legal. www.logicdevices.com 149 High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module FIGURE 103 - DYNAMIC ODT: ODT PIN ASSERTED TOGETHER WITH WRITE COMMAND FOR 6 CLOCK CYCLES, BL8 T0 T1 T2 NOP WRS8 NOP T3 T4 T5 T6 T7 T8 T9 T10 T11 NOP NOP NOP NOP NOP NOP NOP NOP NOP CK# CK Command ODTLCNW Vali d Add ress ODTH8 ODTLOFF ODTLON ODT t ADC (MAX) t AOF (MIN) RTT_WR RTT t AON (MIN) t AOF (MAX) ODTLCWN 8 DQS, DQS# WL DI b DQ DI b+1 DI b+2 DI b+3 DI b+4 DI b+5 DI b+7 DI b+6 Transitioning Notes: Don ’t Care 1. Via MRS or OTF; AL = 0, CWL = 5. If RTT_NOM can be either enabled or disabled, ODT can be HIGH. RTT_WR is enabled. 2. In this example, ODTH8 = 6 is satisfied exactly. FIGURE 104 - DYNAMIC ODT: ODT PIN ASSERTED WITH WRITE COMMAND FOR 6 CLOCK CYCLES, BC4 T0 T1 T2 NOP WRS4 NOP T3 T4 T5 T6 NOP NOP NOP NOP T7 T8 T9 T10 T11 NOP NOP NOP NOP NOP CK# CK Command ODTLCNW Address Vali d ODTH4 ODTL off ODT ODTL on t ADC (MAX) RTT t AOF (MIN) t ADC (MIN) RTT_WR RTT_NOM t AON (MIN) t ADC (MAX) t AOF (MAX) ODTLCWN 4 DQS, DQS# DI n DQ DI n+1 DI n+2 DI n+3 WL Transitioning Notes: LOGIC Devices Incorporated Don ’t Care 1. Via MRS or OTF. AL = 0, CWL = 5. RTT_NOM and RTT_WR are enabled. 2. ODTH4 is defined from ODT registered HIGH to ODT registered LOW, so in this example, ODTH4 is satisfied. ODT registered LOW at T5 is also legal. www.logicdevices.com High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module FIGURE 105 - DYNAMIC ODT: ODT PIN ASSERTED WITH WRITE COMMAND FOR 4 CLOCK CYCLES, BC4 T0 T1 T2 NOP WRS4 NOP T3 T4 T5 T6 T7 T8 T9 T10 T11 NOP NOP NOP NOP NOP NOP NOP NOP NOP CK# CK Command ODTLCNW Add ress Valid ODTL off ODTH4 ODT t AOF (MIN) t ADC (MAX) ODTL on RTT R_TTWR _WR RTT t AON (MIN) t AOF (MAX) ODTLCWN 4 DQS, DQS# WL DI n DQ DI n+1 DI n+2 DI n+3 Transitioning Notes: 1. Via MRS or OTF. AL = 0, CWL = 5. RTT_NOM can be either enabled or disabled. If disabled, ODT can remain HIGH. RTT_WR is enabled. 2. In this example ODTH4 = 4 is satisfied exactly. SYNCHRONOUS ODT MODE ODT LATENCY AND POSTED ODT 6\QFKURQRXV2'7LVVHOHFWHGZKHQHYHUWKH'//LVWXUQHGRQDQGORFNHG ZKLOH 5TT_NOM or RTTB:5 LV HQDEOHG %DVHG RQ WKH 32:(5'2:1 GHILQLWLRQWKHVHPRGHVDUH ,QV\QFKURQRXV2'7PRGH5TTWXUQVRQ2'7/RQFORFNF\FOHVDIWHU2'7 LVVDPSOHG+,*+E\DULVLQJFORFNHGJHDQGWXUQVRII2'7/RIIFORFNF\FOHV DIWHU2'7LVUHJLVWHUHG/2:E\DULVLQJFORFNHGJH7KHDFWXDORQRIIWLPHV YDULHVE\tAON and t$2)DURXQGHDFKFORFNHGJHVHH7DEOH7KH2'7 /$7(1&<LVWLHGWRWKH:5,7(/$7(1&<:/E\2'7/RQ :/DQG ODTL off = WL- 2. x$Q\EDQN$&7,9(ZLWK&.(+,*+ x5()5(6+PRGHZLWK&.(+,*+ x'/(PRGHZLWK&.(+,*+ x$&7,9(32:(5'2:1PRGHUHJDUGOHVVRI 05>@ x35(&+$5*(32:(5'2:1PRGHLI'//LV HQDEOHGGXULQJ35(&+$5*(32:(5'2:1E\ MR0[12] LOGIC Devices Incorporated Don ’t Care www.logicdevices.com 6LQFH:5,7(/$7(1&<LVPDGHXSRI&$6:5,7(/$7(1&<&:/DQG $'',7,9(/$7(1&<$/WKH$/YDOXHSURJUDPPHGLQWRWKHPRGHUHJLVWHU05>@DOVRDSSOLHVWRWKH2'7VLJQDO7KH6'5$0uVLQWHUQDO2'7 VLJQDOLVGHOD\HGDQXPEHURIFORFNF\FOHVGHILQHGE\WKH$/UHODWLYHWRWKH H[WHUQDO2'7VLJQDO7KXV2'7/RQ &:/$/yDQG2'7/RII &:/ $/y High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module SYNCHRONOUS ODT TIMING PARAMETERS 6\QFKURQRXV2'7PRGHXVHVWKHIROORZLQJWLPLQJSDUDPHWHUV2'7/RQ2'7/RII2'7+2'7+ tAON and t$2)VHH7DEOHDQG)LJXUH7KH PLQLPXP5TTWXUQRQWLPHt$21>0,1@LVWKHSRLQWDWZKLFKWKHGHYLFHOHDYHV+,*+$DQG2'7UHVLVWDQFHEHJLQVWRWXUQRQ0D[LPXP5TTWXUQRQWLPH (t$21>0$;@LVWKHSRLQWDWZKLFK2'7UHVLVWDQFHLVIXOO\RQ%RWKDUHPHDVXUHGUHODWLYHWR2'7/RQ7KHPLQLPXP5TTWXUQRIIWLPHt$2)>PLQ@LVWKH SRLQWDWZKLFKWKHGHYLFHVWDUWVWRWXUQRII2'7UHVLVWDQFH0D[LPXP5TTWXUQRIIWLPHt$2)>0$;@LVWKHSRLQWDWZKLFK2'7KDVUHDFKHG+,*+=%RWKDUH PHDVXUHGIURP2'7/RII :KHQ2'7LVDVVHUWHGLWPXVWUHPDLQ+,*+XQWLO2'7+LVVDWLVILHG,ID:5,7(FRPPDQGLVUHJLVWHUHGE\WKH6'5$0ZLWK2'7+,*+WKHQ2'7PXVW UHPDLQ+,*+XQWLO2'7+%&RU2'7+%/DIWHUWKH:5,7(FRPPDQGVHH)LJXUH2'7+DQG2'7+DUHPHDVXUHGIURP2'7UHJLVWHUHG+,*+ WR2'7UHJLVWHUHG/2:RUIURPWKHUHJLVWUDWLRQRID:5,7(FRPPDQGXQWLO2'7LVUHJLVWHUHG/2: TABLE 73: SYNCHRONOUS ODT PARAMETERS Symbol Description Begins at Defined to Definition for All DDR3 bins Units ODTL ON 2'7V\QFKURQRXV785121GHOD\ 2'7UHJLVWHUHG+,*+ RTTB21tAON &:/$/ tCK ODTL OFF 2'7V\QFKURQRXV78512))GHOD\ 2'7UHJLVWHUHG+,*+ RTTB2))tAOF &:/$/ tCK ODT registered LOW 4tF. tCK 2'7UHJLVWHUHG+,*+RU:5,7( 2'7+ 2'70LQLPXP+,*+WLPHDIWHU2'7 DVVHUWLRQRU:5,7(%& UHJLVWUDWLRQZLWK2'7+,*+ 2'7+ 2'70LQLPXP+,*+WLPHDIWHU :5,7(UHJLVWUDWLRQZLWK2'7+,*+ ODT registered LOW tF. tCK tAON 2'7785121UHODWLYHWR2'7/RQ &RPSOHWLRQRI2'7/RQ RTT_ON See Table 47 SV tAOF 2'778512))UHODWLYHWR2'7/RII &RPSOHWLRQRI2'7/RII RTT_OFF tF.tF. tCK :5,7(%/ FRPSOHWLRQ FRPSOHWLRQ FIGURE 106 - SYNCHRONOUS ODT T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 CK# CK CKE AL = 3 CWL - AL = 3 ODT ODTH4 (MIN) ODTL off = CWL + AL - 2 ODTL on = CWL + AL - 2 t AON (MIN) RTT RTT_NOM t AON (MAX) Notes: LOGIC Devices Incorporated 1. AL = 3; CWL = 5; ODTL on = WL = 6.0; ODTL off = WL - 2 = 6. R TT_NOM is enabled. www.logicdevices.com High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module FIGURE 107 - SYNCHRONOUS ODT (BC4) T0 T1 T2 NOP NOP NOP T3 T4 T5 T6 T7 NOP NOP NOP WRS4 T8 T9 T10 NOP NOP NOP T11 T12 T13 T14 T15 T16 T17 NOP NOP NOP NOP NOP NOP CK# CK CKE Command NOP NOP ODTH4 (MIN) ODTH4 ODTH4 ODT ODTLoff = WL - 2 ODTL off = WL - 2 ODTL on = WL - 2 ODTL on = WL - 2 t AON (MIN) RTT t AON (MAX) t AOF (MIN) t AOF (MIN) RTT_NOM RTT_NOM t AOF (MAX) t AON (MAX) t AON (MIN) t AOF (MAX) Transitioning Notes: Don ’t Care 1. 2. 3. 4. WL = 7. RTT_NOM is enabled. R TT_WR is disabled. ODT must be held HIGH for at least ODTH4 after assertion (T1). ODT must be kept HIGH ODTH4 (BC4) or ODTH8 (BL8) after the WRITE command (T7). ODTH is measured from ODT first registered HIGH to ODT first registered LOW or from the registration of the WRITE command with ODT HIGH to ODT registered LOW. 5. Although ODTH4 is satisfied from ODT registered HIGH at T6, ODT must not go LOW before T11 as ODTH4 must also be satisfied from the registration of the WRITE command at T7. ODT OFF DURING READS $VWKH''56'5$0FDQQRWWHUPLQDWHDQGGULYHDWWKHVDPHWLPH5TTPXVWEHGLVDEOHGDWOHDVWRQHKDOIFORFNF\FOHEHIRUHWKH5($'SUHDPEOHE\GULYLQJ WKH2'7EDOO/2:5TTPD\QRWEHHQDEOHGXQWLOWKHHQGRIWKHSRVWDPEOHDVVKRZQLQ)LJXUH FIGURE 108 - ODT DURING READS T0 T1 T2 T3 T4 T5 T6 Command READ NOP NOP NOP NOP NOP NOP Add ress Vali d T7 T8 T9 T10 T11 T12 T13 T14 T15 NOP NOP NOP NOP NOP NOP NOP NOP T16 T17 NOP NOP CK# CK NOP ODTL on = CWL + AL - 2 ODTL off = CWL + AL - 2 ODT t AOF (MIN) RTT RTT_NOM RTT_NOM t AOF (MAX) RL = AL + CL t AON (MAX) DQS, DQS# DQ DI b DI b+1 DI b+2 DI b+3 DI b+4 DI b+5 DI b+6 DI b+7 Transitioning Notes: LOGIC Devices Incorporated Don ’t Care 1. ODT must be disabled externally during READs by driving ODT LOW. For example, CL = 6; AL = CL - 1 = 5; RL = AL + CL = 11; CWL = 5; ODTL on = CWL + AL - 2 = 8; ODTL off = CWL + AL - 2 = 8. RTT_NOM is enabled. R TT_WR is a “Don’t Care.” www.logicdevices.com High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module ASYNCHRONOUS ODT MODE $V\QFKURQRXV2'7PRGHLVDYDLODEOHZKHQWKH6'5$0UXQVLQ'//21PRGHDQGZKHQHLWKHU5TT_NOM or RTTB:5LVHQDEOHGKRZHYHUWKH'//LVWHPSRUDULO\WXUQHGRIILQ35(&+$5*('32:(5'2:1VWDQGE\YLD05>@$GGLWLRQDOO\2'7RSHUDWHVDV\QFKURQRXVO\ZKHQWKH'//LVV\QFKURQL]LQJDIWHU EHLQJ5(6(76HHv32:(5'2:102'(wIRUGHILQLWLRQDQGJXLGDQFHRYHU32:(5'2:1GHWDLOV ,QDV\QFKURQRXV2'7WLPLQJPRGHWKHLQWHUQDO2'7FRPPDQGLVQRWGHOD\HGE\$/UHODWLYHWRWKHH[WHUQDO2'7FRPPDQG,QDV\QFKURQRXV2'7PRGH2'7 FRQWUROV5TTE\DQDORJWLPH7KHWLPLQJSDUDPHWHUVt$213'DQGt$2)3'VHH7DEOHUHSODFH2'7/RQt$21DQG2'7/RIIt$2)UHVSHFWLYHO\ZKHQ2'7 RSHUDWHVDV\QFKURQRXVO\VHH)LJXUH 7KHPLQLPXP5TTWXUQRQWLPHt$213'>0,1@LVWKHSRLQWDWZKLFKWKHGHYLFHWHUPLQDWLRQFLUFXLWOHDYHV+,*+=DQG2'7UHVLVWDQFHEHJLQVWRWXUQRQ0D[LPXP5TTWXUQRQWLPHt$213'>0$;@LVWKHSRLQWDWZKLFK2'7UHVLVWDQFHLVIXOO\RQt$213'0,1DQGt$213'0$;DUHPHDVXUHGIURP2'7EHLQJ VDPSOHG+,*+ 7KHPLQLPXP5TTWXUQRIIWLPHt$2)3'>0,1@LVWKHSRLQWDWZKLFKWKHGHYLFHWHUPLQDWLRQFLUFXLWVWDUWVWRWXUQRII2'7UHVLVWDQFH0D[LPXP5TTWXUQRIIWLPH (t$2)3'>0$;@LVWKHSRLQWDWZKLFK2'7KDVUHDFKHG+,*+=t$2)3'0,1DQGt$2)3'0$;DUHPHDVXUHGIURP2'7EHLQJVDPSOHG/2: FIGURE 109 - ASYNCHRONOUS ODT TIMING WITH FAST ODT TRANSITION T0 T1 T2 T3 T4 T5 T6 T7 T8 T10 T9 T11 T12 T13 T14 T15 T16 T17 CK# CK CKE t IH t IS t IH t IS ODT t AOFPD (MIN) t AONPD (MIN) RTT RTT_NOM t AONPD (MAX) t AOFPD (MAX) Transitioning Notes: Don ’t Care 1. AL is ignored. TABLE 74: ASYNCHRONOUS ODT TIMING PARAMETERS FOR ALL SPEED BINS Symbol MIN MAX Units tAON 3' $V\QFKURQRXV5TT785121GHOD\32:(5'2:1ZLWK'//RII 2 ns tAOF 3' $V\QFKURQRXV5TT78512))GHOD\32:(5'2:1ZLWK'//RII 2 ns LOGIC Devices Incorporated Description www.logicdevices.com High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module SYNCHRONOUS TO ASYNCHRONOUS ODT MODE TRANSITION (POWER-DOWN ENTRY) 7KHUHLVDWUDQVLWLRQSHULRGDURXQG32:(5'2:1(175<3'(ZKHUHWKH6'5$0uV2'7PD\H[KLELWHLWKHUV\QFKURQRXVRUDV\QFKURQRXVEHKDYLRU7KLV WUDQVLWLRQSHULRGRFFXUVLIWKH'//LVVHOHFWHGWREHRIIZKHQLQ35(&+$5*(32:(5'2:1PRGHE\WKHVHWWLQJRI05>@ 32:(5'2:1HQWU\ begins t$13'SULRUWR&.(ILUVWEHLQJUHJLVWHUHG/2:DQGLWHQGVZKHQ&/(LVILUVWUHJLVWHUHG/2:t$13'LVHTXDOWRWKHJUHDWHURI2'7/RIItCK or ODTL RQt&.,ID5()5(6+FRPPDQGKDVEHHQLVVXHGDQGLWLVLQSURJUHVVZKHQ&.(JRHV/2:32:(5'2:1HQWU\ZLOOHQG t5)&DIWHUWKH5()5(6+ FRPPDQGUDWKHUWKDQZKHQ&.(LVILUVWUHJLVWHUHG/2:32:(5'2:1(175<ZLOOWKHQEHFRPHWKHJUHDWHURI t$13'DQG t5)&y5()5(6+FRPPDQG WR&.(UHJLVWHUHG/2: 2'7DVVHUWLRQGXULQJ32:(5'2:1(175<UHVXOWVLQDQ5TTFKDQJHDVHDUO\DVWKHOHVVHURIt$213'0,1DQG2'7/RQ[t&.t$210,1RUDVODWH DVWKHJUHDWHURIt$213'0$;DQG2'7/RQ[t&.t$210$;2'7GHDVVHUWLRQGXULQJ32:(5'2:1(175<PD\UHVXOWLQDQ5TTFKDQJHDVHDUO\ DVWKHOHVVHURI t$2)3'0,1DQG2'7/RII[ t&. t$2)0,1RUDVODWHDVWKHJUHDWHURI t$2)3'0$;DQG2'7/RII[ t&. t$2)0$;7DEOH VXPPDUL]HVWKHVHSDUDPHWHUV ,IWKH$/KDVDODUJHYDOXHWKHXQFHUWDLQW\RIWKHVWDWHRI5TTEHFRPHVTXLWHODUJH7KLVLVEHFDXVH2'7/RQDQG2'7/RIIDUHGHULYHGIURPWKH:/DQG:/ LVHTXDOWR&:/$/)LJXUHVKRZVWKUHHGLIIHUHQWFDVHV x2'7B$6\QFKURQRXVEHKDYLRUEHIRUHt$13' x2'7B%2'7VWDWHFKDQJHVGXULQJWKHWUDQVLWLRQSHULRGZLWKt$213'0,1OHVVWKDQ2'7/RQ[t&.t$210,1DQGt$213'0$; JUHDWHUWKDQ2'7/RQ[t&.t$210$; x2'7B&2'7VWDWHFKDQJHVDIWHUWKHWUDQVLWLRQSHULRGZLWKDV\QFKURQRXVEHKDYLRU TABLE 75: ODT PARAMETERS FOR POWER-DOWN (DLL OFF) ENTRY AND EXIT TRANSITION PERIOD Description MIN tAN 32:(5'2:1HQWU\WUDQVLWLRQ32:(5'2:1H[LW ODT to RTT785121GHOD\2'7/RQ :/ ODT to RTT 78512))GHOD\2'7/RII :/ tAN LOGIC Devices Incorporated t 3' ;3'// Lesser of: tAN3'0,1>QV@RU Lesser of: tAN3'0,1>QV@RU ODL on x t&.t$210,1 ODL on x t&.t$210,1 Lesser of: tAOF3'0,1>QV@RU Lesser of: tAOF3'0,1>QV@RU ODL off x t&.t$2)0,1 ODL off x t&.t$2)0,1 :/*UHDWHURI2'7/RIIRU2'7/RQ 3' www.logicdevices.com MAX Greater of: tAN3' or t5)&5()5(6+WR&.(/2: 32:(5'2:1HQWU\WUDQVLWLRQSHULRG32:(5'2:1HQWU\ High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module FIGURE 110 - SYNCHRONOUS TO ASYNCHRONOUS TRANSITION DURING PRECHARGE POWER-DOWN (DLL OFF) ENTRY T0 T1 T2 T3 T4 NOP REF NOP NOP NOP T5 T6 T7 T8 T9 T10 T11 T12 T13 Ta0 Ta1 Ta2 Ta3 NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP CK# CK CKE Command t RFC (MIN) t ANPD PDE transition period ODT A synchronous DRAM RTT A synchronous t AOF (MIN) RTT_NOM ODTL off ODTL off + t AOFPD (MIN) t AOF (MAX) t AOFPD (MAX) ODT B asynchronous or synchronous DRAM RTT B asynchronous or synchronous t AOFPD (MIN) RTT_NOM ODTL off + t AOFPD (MAX) ODT C asynchronous t AOFPD (MIN) DRAM RTT C asynchronous RTT_NOM t AOFPD (MAX) Indicates a Break In Time Scale Notes: Transitioning Don ’t Care 1. AL = 0; CWL = 5; ODTL off = WL - 2 = 3. ASYNCHRONOUS TO SYNCHRONOUS ODT MODE TRANSITION (POWER-DOWN EXIT) 7KH6'5$0uV2'7PD\H[KLELWHLWKHUDV\QFKURQRXVRUV\QFKURQRXVEHKDYLRUGXULQJ32:(5'2:1(;,73';7KLVWUDQVLWLRQSHULRGRFFXUVLIWKH'//LV VHOHFWHGWREHRIIZKHQLQ35(&+$5*(32:(5'2:1PRGHE\VHWWLQJ05>@WRvw32:(5'2:1H[LWEHJLQVt$13'SULRUWR&.(ILUVWEHLQJUHJLVWHUHG+,*+DQGLWHQGVt;3'//DIWHU&.(LVILUVWUHJLVWHUHG+,*+t$13'LVHTXDOWRWKHJUHDWHURI2'7/RIIt&.RU2'7/RQt&.7KHWUDQVLWLRQSHULRG is t$13'SOXVt;3'// 2'7DVVHUWLRQGXULQJ32:(5'2:1H[LWUHVXOWVLQDQ5TTFKDQJHDVHDUO\DVWKHOHVVHURI t$213'0,1DQG2'7/RQ[ tC.t$210,1RUDVODWHDV WKHJUHDWHURIt$213'0$;DQG2'7/RQ[t&.t$210$;2'7GHDVVHUWLRQGXULQJ32:(5'2:1(;,7PD\UHVXOWLQDQ5TTFKDQJHDVHDUO\DVWKH lesser of t$2)3'0,1DQG2)7/RII[t&.t$2)0,1RUDVODWHDVWKHJUHDWHURIt$2)3'0$;DQG2'7/RII[t&.t$2)0$;7DEOHVXPPDUL]HV WKHVHSDUDPHWHUV ,IWKH$/KDVDODUJHYDOXHWKHXQFHUWDLQW\RIWKH5TTVWDWHEHFRPHVTXLWHODUJH7KLVLVEHFDXVH2'7/RQDQG2'7/RIIDUHGHULYHGIURPWKH:/DQGWKH:/ LVHTXDOWR&:/$/)LJXUHVKRZVWKUHHGLIIHUHQWFDVHV x2'7&$V\QFKURQRXVEHKDYLRUEHIRUHt$13' x2'7%2'7VWDWHFKDQJHVGXULQJWKHWUDQVLWLRQSHULRGZLWKt$2)3'0,1OHVVWKDQ2'7/RII[t&.t$2)0,1DQG2'7/RII[t&. t$2)0$;JUHDWHUWKDQt$2)3'0$; x2'7$2'7VWDWHFKDQJHVDIWHUWKHWUDQVLWLRQSHULRGZLWKV\QFKURQRXVUHVSRQVH LOGIC Devices Incorporated www.logicdevices.com High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B LOGIC Devices Incorporated www.logicdevices.com DRAM RTT C synchronous ODT C synchronous ODT B asynchronous or synchronous RTT B asynchronous or synchronous DRAM RTT A asynchronous ODT A asynchronous COMMAND CKE CK# CK T0 RTT_NOM T1 t ANPD RTT_NOM t AOFPD (MAX) t AOFPD (MIN) T2 Ta0 NOP Ta1 Notes: NOP Ta2 NOP Ta4 NOP Ta5 t XPDLL NOP Ta 6 NOP T b0 NOP Tb1 NOP Tb2 NOP Tc0 NOP Tc1 Indicates A Break in Time Scale 1. CL = 6; AL = CL - 1; CWL = 5; ODTL off = WL - 2 = 8. RTT_NOM ODTL off + t AOF (MAX) t AOFPD (MAX) ODTL off + t AOF (MIN) PDX transition period t AOFPD (MIN) NOP Ta3 Transitioning ODTL off NOP Tc2 NOP Td1 Don ’t Care t AOF (MIN) t AOF (MAX) NOP Td0 L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module FIGURE 111 - ASYNCHRONOUS TO SYNCHRONOUS TRANSITION DURING PRECHARGE POWER-DOWN (DLL OFF) EXIT High Performance, Integrated Memory Module Product August 27, 2014 LDS-L9D3xxxM32SBG1 Rev B L9D3256M32SBG1 L9D3512M32SBG1 8-16 Gb, DDR3, 256-512M x 32 Single Channel Memory Module ASYNCHRONOUS TO SYNCHRONOUS ODT MODE TRANSITION (SHORT CKE PULSE) ,IWKHWLPHLQWKH35(&+$5*(32:(5'2:1RU,'/(VWDWHVLVYHU\VKRUWVKRUW&.(/2:SXOHVWKH32:(5'2:1(175<DQG32:(5'2:1(;,7 WUDQVLWLRQSHULRGVZLOORYHUODS:KHQRYHUODSRFFXUVWKHUHVSRQVHRIWKH6'5$0uV5TTWRDFKDQJHLQWKH2'7VWDWHPD\EHV\QFKURQRXVRUDV\QFKURQRXV IURPWKHVWDUWRIWKH32:(5'2:1(175<WUDQVLWLRQSHULRGWRWKHHQGRIWKH32:(5'2:1(;,7WUDQVLWLRQSHULRGHYHQLIWKH(175<SHULRGHQGVODWHU WKDQWKH(;,7SHULRGVHH)LJXUH ,IWKHWLPHLQWKHLGOHVWDWHLVYHU\VKRUWVKRUW&.(+,*+SXOVHWKH32:(5'2:1(;,7DQG32:(5'2:1(175<WUDQVLWLRQSHULRGVRYHUODS:KHQWKLV RYHUODSRFFXUVWKHUHVSRQVHRIWKH6'5$0uV5TTWRDFKDQJHLQWKH2'7VWDWHPD\EHV\QFKURQRXVRUDV\QFKURQRXVIURPWKHVWDUWRIWKH32:(5'2:1 (;,7WUDQVLWLRQSHULRGWRWKHHQGRIWKH32:(5'2:1(175<WUDQVLWLRQSHULRGVHH)LJXUH FIGURE 112 - TRANSITION PERIOD FOR SHORT CKE LOW CYCLES WITH ENTRY AND EXIT PERIOD OVERLAPPING T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 Ta0 Ta1 Ta2 Ta3 Ta4 REF NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP CK# CK Command CKE PDE transition period t ANPD t RFC(MIN) PDX transition perio d t XPDLL t ANPD Short CKE LOW transition period (RTT chan ge asynchronous or syn chronous) Indicates a Break in Time Scale Notes: Transitionin g Don ’t Care 1. AL = 0, WL = 5, t ANPD = 4. FIGURE 113 - TRANSITION PERIOD FOR SHORT CKE HIGH CYCLES WITH ENTRY AND EXIT PERIOD OVERLAPPING T0 T1 T2 T3 T4 T5 T6 NOP NOP N NOP OP NOP NOP NOP NOP T7 T8 T9 NOP NOP NOP Ta0 Ta1 Ta2 Ta3 Ta4 NOP NOP NOP NOP NOP CK# CK Command CKE t ANPD t XPDLL t ANPD Short CKE HIGH transition period (R TT chan ge asynchronous or synchonous) Indicates A Break in Time Scale Notes: LOGIC Devices Incorporated www.logicdevices.com Transitionin g Don ’t Care 1. AL = 0, WL = 5, t ANPD = 4. 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