RT9912A Multi-Channel Power Management IC for Portable Device General Description Features The RT9912A is a multi-channel power management IC providing power conversion and system power management functions for one or two alkaline battery powered portable handheld device. z 300mA Sync. Step Down Converter for VCORE z 300mA Sync. Step Up Converter for IO and Memory High Efficiency Up to 92% Low Dropout Linear Regulator Adjustable Voltage Detector for Reset Function Current Limit Protection Thermal Shutdown Protection Low Operation Current Consumption Small 24-Lead WQFN Package RoHS Compliant and Halogen Free z z z z z z z DSC Portable Multimedia Player GPS Pin Configurations RoHS compliant and compatible with the current require- Marking Information For marking information, contact our sales representative directly or through a Richtek distributor located in your area. 23 GND 24 CT Suitable for use in SnPb or Pb-free soldering processes. 22 21 20 19 VDD1 1 18 FB1 2 17 VDD4 3 16 RESET 15 ENBUK 14 VDD3 13 FB3 ENSW PSW 4 NC 5 ENBST 6 GND 25 FB2 7 8 9 10 11 12 VDD2 ` LX1 (TOP VIEW) ments of IPC/JEDEC J-STD-020. VOUT1 ` z VOUT3 Richtek products are : z VBAT Note : Applications PGND1 Package Type QW : WQFN-24L 4x4 (W-Type) Lead Plating System G : Green (Halogen Free and Pb Free) PVDD2 RT9912A z LX2 Ordering Information PGND2 The RT9912A integrates one high efficiency synchronous buck regulator, one high efficiency boost regulator, one linear regulator and one adjustable voltage detector for reset function. z FB4 WQFN-24L 4x4 DS9912A-01 April 2011 www.richtek.com 1 RT9912A Typical Application Circuit V BAT RT9912A C1 1uF VDD3 C3 1uF 1 VDD1 LX1 23 22 VBAT 14 VDD3 17 R3 1M D1 C6 2.2pF C5 C13 22nF C7 22uF R2 120k PSW 4 VDD4 Q1 R5 590k FB4 R4 120k V OUT3 3V C8 1nF FB3 13 20 CT PVDD2 10 VDD2 11 GND 16 RESET 3 ENSW 15 ENBUK 6 ENBST LX2 9 VDD3V3_IO C16 22uF VDD2 C12 1uF L2 4.7uH R7 1.6M FB2 C9 4.7uF R6 390k PGND1 21 PGND2 8 19, Exposed Pad (25) V OUT2 R1 1.2M FB1 2 VOUT3 12 18 C4 1nF L1 4.7uH 10uF C2 1uF VDD3V3_IO V OUT1 3.3V VOUT1 24 7 V OUT2 1.8V C10 100pF C11 10uF R8 330k Power ON Sequence : VOUT2 → VDD3V3_IO → VOUT3 ENBUK ENBST V OUT2 PSW VDD3V3_IO V OUT3 www.richtek.com 2 DS9912A-01 April 2011 RT9912A Function Block Diagram PVDD1 VOUT1 VDD1 VDD1 PGND1 VBAT CH1 Syn-Boost PFM FB1 LX1 PVDD1 PGND1 ENBST CH1 Power Ready PGND1 PSW ENSW PVDD2 PVDD2 ENBUK CH2 Syn-Buck PFM FB2 PGND2 LX2 PVDD2 VDD2 PGND2 PGND2 LDOOK VDD3 VDD3 CH3 LDO Regulator ENLDO FB3 VOUT3 FB3 GND VDD4 VDD4 FB4 CH4 Reset RESET Reset Signal Delay CT Thermal Protection DS9912A-01 April 2011 www.richtek.com 3 RT9912A Functional Pin Description Pin No. Pin Name Pin Function 1 VDD1 CH1 Power Input Pin. 2 FB1 CH1 Feedback Input Pin. 3 ENSW Load Disconnect Enable Pin. 4 PSW Load Disconnect P-MOSFET Gate Drive Pin. 5 NC No Internal Connection. This pin must be floating. 6 ENBST Boost Enable Pin. 7 FB2 CH2 Feedback Input. 8 PGND2 Power Ground for CH2. 9 LX2 CH2 Switch Node. 10 PVDD2 CH2 Power Input Pin. 11 VDD2 CH2 Power Input Pin for Analog. 12 VOUT3 CH3 Output Voltage. 13 FB3 CH3 Feedback Input. 14 VDD3 CH3 Power Input Pin. 15 ENBUK BUCK Enable Pin. 16 RESET Reset Pulse Output, Negative Pulse. 17 VDD4 CH4 Power Input Pin. 18 FB4 CH4 Feedback Input. 19, Exposed Pad (25) GND Analog Ground. The exposed pad must be soldered to a large PCB and connected to GND for maximum power dissipation. 20 CT External Delay Adjust Pin. 21 PGND1 Power Ground for CH1. 22 VBAT Battery Power Input Pin. 23 LX1 CH1 Switch Node. 24 VOUT1 CH1 Output Voltage. www.richtek.com 4 DS9912A-01 April 2011 RT9912A Absolute Maximum Ratings z z z z z z z z z (Note 1) Supply Voltage, VDD1, VDD2, VDD3, VDD4, PVDD2 -------------------------------------------------------------------LX1 and LX2 Pin Switch Voltage ---------------------------------------------------------------------------------------Other I/O Pin Voltage -----------------------------------------------------------------------------------------------------Power Dissipation, PD @ TA = 25°C WQFN-24L 4x4 ------------------------------------------------------------------------------------------------------------Package Thermal Resistance (Note 2) WQFN-24L 4x4, θJA -------------------------------------------------------------------------------------------------------WQFN-24L 4x4, θJC ------------------------------------------------------------------------------------------------------Junction Temperature -----------------------------------------------------------------------------------------------------Lead Temperature (Soldering, 10 sec.) -------------------------------------------------------------------------------Storage Temperature Range --------------------------------------------------------------------------------------------ESD Susceptibility (Note 3) HBM (Human Body Mode) ----------------------------------------------------------------------------------------------MM (Machine Mode) ------------------------------------------------------------------------------------------------------- Recommended Operating Conditions z z z −0.3V to 6.5V −0.3V to 6.5V −0.3V to 6.5V 1.852W 54°C/W 7°C/W 150°C 260°C −65°C to 150°C 2kV 200V (Note 4) Supply Input Voltage, VBAT ----------------------------------------------------------------------------------------------- 1.7V to 5V Junction Temperature Range --------------------------------------------------------------------------------------------- −40°C to 125°C Ambient Temperature Range --------------------------------------------------------------------------------------------- −40°C to 85°C Electrical Characteristics (VDD1 = VDD2 = VDD3 = VDD4 = 3.3V, TA = 25°C, unless otherwise specified) Parameter Symbol Test Condition Min Typ Max Units -- -- 1.7 V Supply Voltage Minimum Operating Input Voltage RL = 3kΩ Minimum Startup Voltage (Boost) V ST -- 0.8 1.1 V 1.7 -- 5 V 1.7 -- 5 V V DD3 2.5 -- 5 V V DD4 1.5 -- 5 V 5.1 6 6.5 V -- -- 10 uA -- 45 70 uA -- 85 140 uA VDD1 Operating Voltage V DD1 VDD2 Operating Voltage V DD2 VDD3 Operating Voltage VDD4 Operating Voltage RL = 3kΩ VDD2, PVDD2 Pin Voltage VDD1 Over Voltage Protection Supply Current Shutdown Supply Current Boost Supply Current IOFF IVDD1 VENBST = V ENSW = 0V VDD4 = 0V = VDD3 VDD1 = 3.3V, VFB1 = 0.9V VENBST = V ENSW = 3.3V VOUT1 = 3.3V VDD2 = V DD3 = VDD4 = 0V (no switching) VDD2 = 3.3V, VFB2 = 0.9V Buck Supply Current IVDD2 VENBST = V ENSW = 0V VDD1 = V DD3 = VDD4 = 0V (no switching) To be continued DS9912A-01 April 2011 www.richtek.com 5 RT9912A Parameter Symbol LDO Supply Current IVDD3 Test Condition Min Typ Max Units -- 90 130 uA -- 10 -- uA 0.292 0.3 0.312 V -- -- 8 mV -- 200 400 mΩ -- 1.2 -- A N-MOSFET, VDD2 = 3.3V -- 320 450 mΩ P-MOSFET, VDD2 = 3.3V -- 400 560 mΩ P-MOSFET -- 0.6 -- A 0.292 0.3 0.308 V -- 25 -- mV -- 3 -- mA 0.65 0.8 1 V -- 1 -- uA −2 -- +2 % -- 1.2 -- V 400 600 -- mA -- 0.3 0.4 V -- -- 0.5 % -- -- 30 mV -- -- 1.1 V VDD3 = 5V VENBST = V ENSW = 0V VDD1 = V DD2 = VDD4 = 0V VDD4 = 3.3V Voltage Detector Supply Current IVDD4 VENBST = V ENSW = 0V VDD1 = V DD3 = VDD3 = 0V Feedback Voltage (CH1, CH2) Feedback Voltage V FB FB1, FB2 Line Regulation of Feedback Voltage of CH1 ︱ΔV FB ︱ IL = 30mA, V OUT = 2.8V VB AT = 0.9 to 1.5V Power Switch CH1 On Resistance of MOSFET CH1 Current Limitation RDS(ON) N-MOSFET, VOUT1 = 3.3V P-MOSFET, V OUT1 = 3.3V (Note 5) CH2 On Resistance of MOSFET RDS(ON) CH2 Current Limitation Voltage Detector Feedback Voltage V FB4 Threshold Hysteresis FB4 Falling Edge Refer to FB4 N-MOSFET, VDD4 = 3.3V, VDS = 0.5V RESET Output Current P-MOSFET, V DD4 = 3.3V, VDS = -0.5V CT Pin Threshold Voltage V CT CT Pin Output Current ICT VDD4 = 3.3V Linear Regulator IL = 1mA, Output Voltage Accuracy VOUT3 = 3.5V, 3.3V, 3V Feedback Voltage V FB3 Current Limit IOUT3_L IM Dropout Voltage V DROP Line Regulation ΔV LINE Load Regulation ΔV OUT3 IVOUT3 = 200mA VDD3 = (V OUT3 + 1V) to 5.5V IOUT3 = 1mA IOUT3 = 50mA to 200mA VDD3 = 4.8V, VOUT3 = 3.3V Control ENLDO Input High Level Threshold VDD1 = 2.8V To be continued www.richtek.com 6 DS9912A-01 April 2011 RT9912A Parameter Symbol Min Typ Max Units 0.4 -- -- V V BAT = 1V -- -- 0.7 V V BAT = 1V 0.2 -- -- V ENBST Pull Low Current -- 1 -- uA ENBUK Pull Low Current -- 1 -- uA ENLDO Input Low Level Test Condition V DD1 = 2.8V Threshold ENBST/ ENSW Input High Level Threshold ENBST/ ENSW Input Low Level Threshold Thermal Protection Thermal Shutdown TSD -- 160 -- °C Thermal Shutdown Hysteresis ΔTSD -- 10 -- °C Note 1. Stresses listed as the above “Absolute Maximum Ratings” may cause permanent damage to the device. These are for stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. Note 2. θJA is measured in the natural convection at TA = 25°C on a high effective four layers thermal conductivity test board of JEDEC 51-7 thermal measurement standard. The case point of θJC is on the expose pad for the package. Note 3. Devices are ESD sensitive. Handling precaution is recommended. Note 4. The device is not guaranteed to function outside its operating conditions. DS9912A-01 April 2011 www.richtek.com 7 RT9912A Typical Operating Characteristics CH2 Efficiency vs. Output Current CH1 Efficiency vs. Output Current 100 100 90 90 VIN = 3V VIN = 2.5V VIN = 1.8V 70 80 Efficiency (%) Efficiency (%) 80 60 50 40 30 20 VIN = 3.3V VIN = 2.5V VIN = 2V 70 60 50 40 30 20 10 10 VOUT = 3.3V 0 0.001 0.01 0.1 VOUT = 1.8V 0 0.001 1 0.01 Output Current (A) CH1 Output Voltage vs. Temperature CH1 Output Voltage vs. Output Current 4.0 3.8 Output Voltage (V) 3.35 3.30 3.25 VIN = 3.3V VIN = 2.5V VIN = 1.8V 3.20 3.15 3.5 3.3 VIN = 3V VIN = 2.5V VIN = 1.8V 3.0 2.8 2.5 2.3 VOUT = 3.3V, No Load VOUT = 3.3V 3.10 2.0 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 -40 -20 0 Output Current (A) 20 40 60 80 100 120 Temperature (°C) CH2 Output Voltage vs. Output Current CH2 Output Voltage vs. Temperature 1.90 1.90 1.85 1.85 1.80 Output Voltage (V) Output Voltage(V) 1 Output Current (A) 3.40 Output Voltage (V) 0.1 1.75 1.70 VIN = 4.2V VIN = 3.3V VIN = 2.5V 1.65 1.60 1.80 1.75 VIN = 3.3V VIN = 2.5V VIN = 2V 1.70 1.65 1.55 VOUT = 1.8V VOUT = 1.8V, No Load 1.60 1.50 0 0.05 0.1 0.15 0.2 0.25 Output Current (A) www.richtek.com 8 0.3 0.35 0.4 -40 -20 0 20 40 60 80 100 120 Temperature (°C) DS9912A-01 April 2011 RT9912A CH3 Output Voltage vs. Temperature 3.3 3.5 3.2 Output Voltage (V) Output Voltage (V) CH3 Output Voltage vs. Output Current 4.0 3.0 VIN = 4.5V VIN = 3.9V VIN = 3.3V 2.5 2.0 1.5 3.1 3.0 VIN = 4.5V VIN = 3.9V VIN = 3.3V 2.9 2.8 VOUT = 3.3V VOUT = 3V, No Load 1.0 2.7 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 -40 -20 Output Current (A) 20 40 60 80 100 120 Temperature (°C) LDO Output Voltage vs. Input Voltage LDO Dropout Voltage vs. Output Current 3.10 400 3.08 350 Dropout Voltage (mV) Output Voltage (V) 0 3.05 3.03 3.00 2.98 2.95 300 250 200 150 100 50 2.93 IOUT = 200mA VOUT = 3V 0 2.90 3.3 3.55 3.8 4.05 4.3 4.55 4.8 5.05 0 5.3 50 100 150 200 Input Voltage (V) Output Current (mA) RESET Power On RESET Power Off FB4 (200mV/Div) FB4 (200mV/Div) RESET (1V/Div) RESET (1V/Div) VDD4 = 1V Time (5ms/Div) DS9912A-01 April 2011 250 300 VDD4 = 1V Time (5ms/Div) www.richtek.com 9 RT9912A Application Information RT9912A is a four-channel power management IC (PMIC) including one step-up DC-DC converter (Boost), one stepdown DC-DC converter (Buck), one low dropout regulator (LDO) and one voltage detector. For optimizing the application of portable hand-held system with one or two alkaline battery, several special logics are designed in this chip. An external P-MOSFET is also needed for loaddisconnected function. Step-Up DC-DC Converter (Boost) The step-up DC-DC convert can start up even with the input voltage as low as 0.8V and operates with the input voltage down to 0.7V. The cost of system is reduced by the internal synchronous rectifier from eliminating an external Schottky diode. The efficiency of light load is improved by the pulse frequency modulation mode (PFM) low quiescent current 30uA. The efficiency of heavy load is also maintained by the internal synchronous rectifier with resistance low to 0.2Ω. The step-up DC-DC converter is designed as a bootstrapped structure. As the chip is in the start-up period, a low voltage start-up circuit will pull the output voltage to a higher voltage (~1.5V). After the output voltage reaches a certain level, the main DC-DC circuitry will keep working to pull the output voltage to the expected value set by output divided resistor. The control scheme of the stepup DC-DC converter is pulse frequency modulation mode (PFM) with constant-on-time and minimum-off-time. This scheme can keep high efficiency during a wide load range. An internal soft-start is also included in the step-up DCDC converter to limit the inrush current to less than a half of the OCP level. As the ENBST is pulled low, the step-up DC-DC converter will enter shutdown mode and all function will be disabled. As the ENSW is pulled high, the PSW will be pulled low when the output of the step-up DC-DC converter is ready (soft-start is finished). An external P-MOSFET is needed to be a load-disconnected switch. The PSW is a signal to control the external P-MOSFET. All loadings of the system should be connected to the drain pin of the P-MOSFET to prevent the step-up DC-DC converter startup in heavy load condition. www.richtek.com 10 The maximum duty (D) of the step-up DC-DC converter is around 50% so that the maximum output voltage is ideally to be VIN / (1-D) = 2 x VIN. Actually, some voltage will drop on the internal N-MOSFET and inductor. Therefore, the maximum output voltage will be lower than the ideal value and to be 2 x VIN. The function of R9 and C14 is preventing the charge sharing issue from the capacitor in Q1's source pin to the capacitor in Q1's drain pin. If the capacitor in Q1's source pin is 10 times larger than the capacitor in Q1's drain pin, R9 and C14 can be removed. Step-Down DC-DC Converter (Buck) The step-down DC-DC convert can reduce the cost of system by the internal synchronous rectifier from eliminating an external Schottky diode. The light load efficiency is improved by the pulse frequency modulation mode (PFM) and internal synchronous rectifier. For heavy load, the efficiency is maintained by the internal synchronous rectifier with the resistance low to 0.4Ω. The control scheme of the step-down DC-DC converter is pulse frequency modulation mode (PFM) with over-currentprotection (OCP) and minimum-off-time. This scheme can keep high efficiency during a wide load range. An internal soft-start is also included in the step-down DC-DC converter to limit the inrush current less than a half of OCP level. This step-down converter can operate in low-drop mode and its output voltage depends on the voltage drop cross the internal P-MOSFET and inductor. Normally, the value is near VDD2 as the ESR of inductor is 0.1Ω and 60mA loading. The minimum output voltage is 0.6V, which is decided by the operation range of the internal circuit. Low Dropout Regulator (LDO) The low dropout regulator can regulate the output voltage by setting the external resistor of FB3. An internal compensation structure is designed for keeping stability as wide range output capacitor and wide range loading. The voltage detector is a comparator with reference to detect the voltage of FB4. DS9912A-01 April 2011 RT9912A The maximum output voltage for LDO depends on the voltage drop cross the internal P-MOSFET. Normally, the value is (VDD3 − 0.4V) as 200mA loading. The minimum output voltage is 1.6V, which is decided by the working range of the internal circuit. Output Voltage Setting The regulated output voltage can be calculated following formula : R1 ⎞ ⎛ VOUT = VFB × ⎜ 1 + ⎟ R2 ⎝ ⎠ Inductor Selection To select suitable inductance value is very important for optimal performance. For boost converter, the control method is constant on time and minimum off time. If the inductance is low, it will cause effects of high in ductor current and high output voltage ripple. The inductance value can be calculated by following formula. LMIN ≥ VIN(MAX) × TON VLIM(MIN) Where LMIN = minimum inductance To place the resistor-divider as close as possible to chip can reduce noise sensitivity. VIN(MAX) = maximum input voltage Voltage Detector ILIM(MIN) = 0.8A The RT9912A integrates a voltage detector with push-pull output. The voltage detector senses VDD3V3_IO through a resistor divider and compares it with internal 0.3V reference voltage. When the sensed voltage is lower than the reference voltage, the RESET pin output logic low signal for system access. Connecting a capacitor from the CT pin to GND can set the detect delay time according to Figure 1. A 4.7uH inductor is recommended for typical application. For buck converter, a 4.7uH inductor is recommended when VIN is less than 2.6V. In addition, make sure the inductor saturation current rating should be greater than the inductor peak current. Input Capacitor Selection For better input bypassing, low-ESR ceramic capacitor is recommended for better performance. A 10uF input capacitor is sufficient and it is flexible to reduce the value for a lower output power requirement. CH4 Detecter Delay Time 120 100 Delay Time (ms) TON = 0.75us 80 Output Capacitor Selection For lower output voltage ripple, low-ESR ceramic capacitor is recommended. The output voltage ripple consists of two components : one is the pulsating output ripple current flowing through the ESR, and the other is the capacitive ripple caused by charging and discharging. 60 40 20 0 0 10 20 30 40 50 60 70 Capacitance (nF) Figure 1. Detector Delay Time 80 90 100 For ceramic capacitor, the voltage ripple value is approximated by : VRIPPLE ≅ VRIPPLE_C For boost converter, calculate the minimum output capacitance as the following formula : COUT ≥ DS9912A-01 April 2011 L × 0.5IPEAK 2 VREPPLE_C www.richtek.com 11 RT9912A For buck converter, calculate the minimum output capacitance as the following formula : THERMAL CONSIDERATIONS For continuous operation, do not exceed absolute maximum operation junction temperature. The maximum power dissipation depends on the thermal resistance of IC package, PCB layout, the rate of surroundings airflow and temperature difference between junction to ambient. The maximum power dissipation can be calculated by following formula : PD(MAX) = (TJ(MAX) − TA) / θJA 2.0 Maximum Power Dissipation (W) COUT ⎛ IOUT(MAX) ⎞ IOUT(MAX) × ⎜ 1 − ⎟ IPEAK ⎠ ⎝ ≥ f × VREPPLE_C 2 Four Layers PCB 1.8 1.6 1.4 WQFN-24L 4x4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 0 25 50 75 100 125 Ambient Temperature (°C) Figure 2. Derating Curves for RT9912A Packages Where T J(MAX) is the maximum operation junction temperature 125°C, TA is the ambient temperature and the θJA is the junction to ambient thermal resistance. Layout Considerations For recommended operating conditions specification of RT9912A, where T J(MAX) is the maximum junction temperature of the die (125°C) and TA is the maximum ambient temperature. The junction to ambient thermal resistance θJA is layout dependent. For WQFN-24L 4x4 packages, the thermal resistance θJA is 54° C/W on the standard JEDEC 51-7 four layers thermal test board. The maximum power dissipation at TA = 25°C can be calculated by following formula : ` Place the input and output capacitors as close as possible to the input and output pins respectively for good filtering. PD(MAX) = (125°C − 25°C) / (54°C/W) = 1.852W for WQFN-24L 4x4 packages The maximum power dissipation depends on operating ambient temperature for fixed T J(MAX) and thermal resistance θJA. For RT9912A packages, the Figure 2 of derating curves allows the designer to see the effect of rising ambient temperature on the maximum power allowed. www.richtek.com 12 For the best performance of the RT9912A, the following PCB Layout guidelines must be strictly followed. ` Keep the main power traces as possible as wide and short. ` The switching node area connected to LX and inductor should be minimized for lower EMI. ` Place the feedback components as close as possible to the FB pin and keep these components away from the noisy devices. ` Connect the GND and Exposed Pad to a strong ground plane for maximum thermal dissipation and noise protection. DS9912A-01 April 2011 RT9912A Input/Output capacitors must be placed as close as possible to the Input/ Output pins. V BAT PGND VDD3V3_IO LX should be connected to inductor by wide and short trace, keep sensitive components away from trace. PGND C7 C23 C5 D1 C4 GND 21 20 19 R4 1 18 FB1 2 17 VDD4 ENSW 3 16 RESET PSW 4 15 ENBUK NC 5 14 VDD3 ENBST 6 13 FB3 GND 25 FB2 R8 9 10 11 L2 C2 R3 FB4 12 VOUT3 GND R7 8 LX2 7 PVDD2 VDD3V3_IO C16 GND 22 PGND1 23 CT VBAT 24 PGND GND C1 VDD1 GND Q1 LX1 R1 PGND2 C6 VOUT1 L1 VDD2 V OUT1 3.3V R6 VDD3V3_IO C8 R5 PGND GND C9 C10 C3 V OUT3 3.3V C11 C12 PGND PGND V OUT2 1.8V V OUT1 3.3V Place the feedback components as close as possible to the FB pin and keep away from noisy devices. PGND Connect the exposed pad to a ground plane. Figure 3. PCB Layout Guide DS9912A-01 April 2011 www.richtek.com 13 RT9912A Outline Dimension D2 D SEE DETAIL A L 1 E E2 e b 1 1 2 2 DETAIL A Pin #1 ID and Tie Bar Mark Options A A3 A1 Note : The configuration of the Pin #1 identifier is optional, but must be located within the zone indicated. Symbol Dimensions In Millimeters Dimensions In Inches Min Max Min Max A 0.700 0.800 0.028 0.031 A1 0.000 0.050 0.000 0.002 A3 0.175 0.250 0.007 0.010 b 0.180 0.300 0.007 0.012 D 3.950 4.050 0.156 0.159 D2 2.300 2.750 0.091 0.108 E 3.950 4.050 0.156 0.159 E2 2.300 2.750 0.091 0.108 e L 0.500 0.350 0.020 0.450 0.014 0.018 W-Type 24L QFN 4x4 Package Richtek Technology Corporation Richtek Technology Corporation Headquarter Taipei Office (Marketing) 5F, No. 20, Taiyuen Street, Chupei City 5F, No. 95, Minchiuan Road, Hsintien City Hsinchu, Taiwan, R.O.C. Taipei County, Taiwan, R.O.C. Tel: (8863)5526789 Fax: (8863)5526611 Tel: (8862)86672399 Fax: (8862)86672377 Email: [email protected] Information that is provided by Richtek Technology Corporation is believed to be accurate and reliable. Richtek reserves the right to make any change in circuit design, specification or other related things if necessary without notice at any time. No third party intellectual property infringement of the applications should be guaranteed by users when integrating Richtek products into any application. No legal responsibility for any said applications is assumed by Richtek. www.richtek.com 14 DS9912A-01 April 2011