SCAS238A − MAY 1992 − REVISED APRIL 1996
D Members of the Texas Instruments
D
D
D
D
D
D
D
54ACT16474 . . . WD PACKAGE
74ACT16474 . . . DL PACKAGE
(TOP VIEW)
Widebus Family
Inputs Are TTL-Voltage Compatible
3-State Outputs Drive Bus Lines Directly
Flow-Through Architecture Optimizes
PCB Layout
Distributed VCC and GND Pin
Configurations Minimize High-Speed
Switching Noise
EPIC (Enhanced-Performance Implanted
CMOS) 1-µm Process
500-mA Typical Latch-Up Immunity at
125°C
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) Packages Using
25-mil Center-to-Center Pin Spacings and
380-mil Fine-Pitch Ceramic Flat (WD)
Packages Using 25-mil Center-to-Center
Pin Spacings
1OEAB
1CLKAB
1A1
GND
1A2
1A3
VCC
1A4
1A5
1A6
GND
1A7
1A8
1A9
2A1
2A2
2A3
GND
2A4
2A5
2A6
VCC
2A7
2A8
GND
2A9
2CLKAB
2OEAB
description
The ’ACT16474 are noninverting 18-bit registered
bus transceivers composed of two 9-bit sections
with separate control signals. For either 9-bit
transceiver section, data flow in the A-to-B mode
is controlled by output-enable (1OEAB or 2OEAB)
and clock (1CLKAB or 2CLKAB) inputs. When
1OEAB or 2OEAB is low, the corresponding
outputs are active (high or low) and take on either
the current data on low-to-high transition of
1CLKAB or 2CLKAB or the previously stored data
if 1CLKAB or 2CLKAB is low.
1
56
2
55
3
54
4
53
5
52
6
51
7
50
8
49
9
48
10
47
11
46
12
45
13
44
14
43
15
42
16
41
17
40
18
39
19
38
20
37
21
36
22
35
23
34
24
33
25
32
26
31
27
30
28
29
1OEBA
1CLKBA
1B1
GND
1B2
1B3
VCC
1B4
1B5
1B6
GND
1B7
1B8
1B9
2B1
2B2
2B3
GND
2B4
2B5
2B6
VCC
2B7
2B8
GND
2B9
2CLKBA
2OEBA
When 1OEAB or 2OEAB is high, the corresponding outputs are in the high-impedance state. 1OEAB or 2OEAB
does not affect the operation on the internal registers. Previously stored data can be retained or new data can
be entered while the outputs are in the high-impedance state.
Data flow from B to A is similar, but uses 1OEBA and/or 2OEBA and 1CLKBA and/or 2CLKBA.
The 74ACT16474 is packaged in TI’s shrink small-outline package, which provides twice the I/O pin count and
functionality of standard small-outline packages in the same printed-circuit-board area.
The 54ACT16474 is characterized for operation over the full military temperature range of −55°C to 125°C. The
74ACT16474 is characterized for operation from −40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
Copyright 1996, Texas Instruments Incorporated
!"#$%&' #"'(' ')"*%("' #$**&' ( ") +$,-#("' !(&. *"!$# #"')"*% "
+&#)#("' +&* & &*% ") &/( '*$%&' ('!(*! 0(**('1.
*"!$#"' +*"#&'2 !"& '" '&#&(*-1 '#-$!& &'2 ") (-+(*(%&&*.
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1
SCAS238A − MAY 1992 − REVISED APRIL 1996
FUNCTION TABLE†
INPUTS
CLKAB
OEAB
A
OUTPUT
B
X
H
X
Z
L
L
X
↑
L
H
B0‡
H
↑
L
L
L
† A-to-B data flow is shown: B-to-A flow is
similar but uses CLKBA, and OEBA.
‡ Output level before the indicated steadystate input conditions were established
logic symbol§
1CLKAB
1OEAB
1CLKBA
1OEBA
2CLKAB
2
1
2CLKBA
56
1A3
1A4
1A5
1A6
1A7
1A8
1A9
2A1
2A2
2A3
2A4
2A5
2A6
2A7
2A8
2A9
EN4
C5
EN6
30
2OEBA
1A2
C3
27
29
1A1
EN2
55
28
2OEAB
C1
3
C7
EN8
1D
1
2
4
1
5D
5
52
6
51
8
49
9
48
10
47
12
45
13
44
14
43
15
5D
1
6
8
1
7D
42
16
41
17
40
19
38
20
37
21
36
23
34
24
33
26
31
§ This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
2
54
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•
1B1
1B2
1B3
1B4
1B5
1B6
1B7
1B8
1B9
2B1
2B2
2B3
2B4
2B5
2B6
2B7
2B8
2B9
SCAS238A − MAY 1992 − REVISED APRIL 1996
logic diagram (positive logic)
1CLKBA
1OEBA
1OEAB
1CLKAB
55
56
1
2
C1
1D
1A1
54
3
1B1
C1
1D
To Eight Other Channels
2CLKBA
2OEBA
2OEAB
2CLKAB
30
29
28
27
C1
1D
2A1
42
15
2B1
C1
1D
To Eight Other Channels
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3
SCAS238A − MAY 1992 − REVISED APRIL 1996
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 to VCC + 0.5 V
Input voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 to VCC + 0.5 V
Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±450 mA
Maximum package power dissipation at TA = 55°C (in still air) (see Note 2): DL package . . . . . . . . . . . 1.4 W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.
recommended operating conditions (see Note 3)
54ACT16474
MIN
NOM
MAX
MIN
NOM
MAX
4.5
5
5.5
4.5
5
5.5
VCC
VIH
Supply voltage
VIL
VI
Low-level input voltage
Input voltage
0
VO
IOH
Output voltage
0
High-level output current
IOL
∆t/∆v
Low-level output current
High-level input voltage
2
2
0.8
Input transition rise or fall rate
0
TA
Operating free-air temperature
−55
NOTE 3: Unused pins (input or I/O) must be held high or low to prevent them from floating.
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4
74ACT16474
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UNIT
V
V
0.8
V
VCC
VCC
V
−24
−24
mA
24
24
mA
VCC
VCC
0
0
V
10
0
10
ns/V
125
−40
85
°C
SCAS238A − MAY 1992 − REVISED APRIL 1996
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
II
IOZ‡
4.4
4.4
4.4
5.5 V
5.4
5.4
5.4
4.5 V
3.94
3.8
3.8
IOH = −24 mA
5.5 V
4.94
4.8
4.8
IOH = −75 mA†
5.5 V
A or B ports
ICC
VO = VCC or GND
VI = VCC or GND,
Control inputs
0.1
IO = 0
MAX
MIN
MAX
UNIT
V
3.85
0.1
0.1
5.5 V
0.1
0.1
0.1
4.5 V
0.36
0.44
0.44
5.5 V
0.36
0.44
0.44
1.65
1.65
±1
±1
µA
5.5 V
One input at 3.4 V,
Other inputs at VCC or GND
∆ICC§
Ci
IOL = 75 mA†
VI = VCC or GND
MIN
3.85
4.5 V
IOL = 24 mA
Control inputs
74ACT16474
4.5 V
IOL = 50 µA
A
VOL
54ACT16474
MIN
IOH = −50 µA
A
VOH
TA = 25°C
TYP
MAX
VCC
V
5.5 V
±0.1
5.5 V
±0.5
±5
±5
µA
5.5 V
8
80
80
µA
5.5 V
0.9
1
1
mA
VI = VCC or GND
VO = VCC or GND
5V
3
pF
Cio
A or B ports
5V
11.5
† Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
‡ For I/O ports, the parameter IOZ includes the input leakage current.
§ This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC.
pF
timing requirements over recommended operating free-air temperature range,
VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
TA = 25°C
MIN
MAX
fclock
Clock frequency
0
CLK high
75
54ACT16474
74ACT16474
MIN
MAX
MIN
MAX
0
75
0
75
UNIT
MHz
4
4
4
CLK low
6.6
6.6
6.6
5.5
5.5
5.5
ns
1
1
1
ns
tw
Pulse duration
tsu
th
Setup time
Data before CLK↑
Hold time
Data after CLK↑
ns
switching characteristics over recommended operating free-air temperature range,
VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
fmax
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
FROM
(INPUT)
TA = 25°C
MIN
TYP
MAX
TO
(OUTPUT)
75
CLK
A or B
OE
A or B
OE
A or B
54ACT16474
MIN
MAX
75
74ACT16474
MIN
MAX
75
UNIT
MHz
4
8
10.2
4
11.5
4
11.5
4.2
8
10.2
4.2
11.4
4.2
11.4
3
7.8
10.3
3
11.7
3
11.7
3.7
9.2
11.6
3.7
13.1
3.7
13.1
4.8
7.1
8.8
4.8
9.5
4.8
9.5
4.4
6.6
8.4
4.4
9
4.4
9
ns
ns
ns
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+&#)#("' (*& !&2' 2"(-. &/( '*$%&' *&&*3& & *2 "
#('2& "* !#"''$& && +*"!$# 0"$ '"#&.
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5
SCAS238A − MAY 1992 − REVISED APRIL 1996
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER
TEST CONDITIONS
TYP
Outputs enabled
Cpd
Power dissipation capacitance per transceiver
UNIT
61
CL = 50 pF,
Outputs disabled
f = 1 MHz
37
pF
PARAMETER MEASUREMENT INFORMATION
2 × VCC
S1
500 Ω
From Output
Under Test
Open
GND
CL = 50 pF
(see Note A)
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
500 Ω
LOAD CIRCUIT
3V
Timing Input
1.5 V
0V
tw
tsu
3V
Input
1.5 V
th
1.5 V
3V
1.5 V
1.5 V
Data Input
0V
0V
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
Output
Control
(low-level
enabling)
3V
Input
1.5 V
1.5 V
0V
tPHL
tPLH
In-Phase
Output
tPLH
tPHL
Out-of-Phase
Output
Output
Waveform 2
S1 at GND
(see Note B)
VOH
50% VCC
VOL
50% VCC
0V
tPZL
tPLZ
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
VOH
50% VCC
VOL
50% VCC
3V
1.5 V
1.5 V
50% VCC
VOL
tPHZ
tPZH
VOLTAGE WAVEFORMS
[ VCC
20% VCC
50% VCC
80% VCC
VOH
[0V
VOLTAGE WAVEFORMS
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns.
D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
6
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