SCAS073A − JUNE 1989 − REVISED APRIL 1993
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54AC11112 . . . J PACKAGE
74AC11112 . . . D OR N PACKAGE
(TOP VIEW)
Flow-Through Architecture Optimizes
PCB Layout
Center-Pin VCC and GND Configuration
Minimizes High-Speed Switching Noise
EPIC (Enhanced-Performance Implanted
CMOS) 1-µm Process
500-mA Typical Latch-Up Immunity
at 125°C
ESD Protection Exceeds 2000 V,
MIL STD-883C Method 3015
Package Options Include Plastic SmallOutline Packages, Ceramic Chip Carriers,
and Standard Plastic and Ceramic
300-mil DIPs
1PRE
1Q
1Q
GND
2Q
2Q
2PRE
2J
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
1J
1K
1CLK
1CLR
VCC
2CLR
2CLK
2K
54AC11112 . . . FK PACKAGE
(TOP VIEW)
1CLK
1CLR
NC
V CC
2CLR
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description
These devices contain two independent J-K
negative-edge-triggered flip-flops. A low level at
the preset (PRE) or clear (CLR) inputs sets or
resets the outputs regardless of the levels of the
other inputs. When preset and clear are inactive
(high), data at the J and K inputs meeting the setup
time requirements are transferred to the outputs
on the negative-going edge of the clock pulse.
Clock triggering occurs at a voltage level and is not
directly related to the fall time of the clock pulse.
Following the hold time interval, data at the J and
K inputs may be changed without affecting the
levels at the outputs. These versatile flip-flops can
perform as toggle flip-flops by tying J and K high.
4
3 2 1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
2CLK
2K
NC
2J
2PRE
1Q
GND
NC
2Q
2Q
1K
1J
NC
1PRE
1Q
NC − No internal connection
The 54AC11112 is characterized for operation over the full military temperature range of −55°C to 125°C. The
74AC11112 is characterized for operation from − 40°C to 85°C.
FUNCTION TABLE
(each gate)
INPUTS
OUTPUTS
PRE
CLR
CLK
J
K
Q
Q
L
H
X
X
X
H
L
H
L
X
X
X
L
H
L
L
X
X
X
H{
H{
H
H
↓
L
L
QO
QO
H
H
↓
H
L
H
L
H
H
↓
L
H
L
H
H
H
↓
H
H
H
H
H
X
X
Toggle
QO
QO
† This configuration is nonstable; that is, it will not persist
when either PRE or CLR returns to its inactive (high) level.
EPIC is a trademark of Texas Instruments Incorporated.
Copyright 1993, Texas Instruments Incorporated
!"#$%&'#! ( )*$$+!' &( #" ,*-.)&'#! /&'+0
$#/*)'( )#!"#$% '# (,+)")&'#!( ,+$ '1+ '+$%( #" +2&( !('$*%+!'(
('&!/&$/ 3&$$&!'40 $#/*)'#! ,$#)+((!5 /#+( !#' !+)+((&$.4 !).*/+
'+('!5 #" &.. ,&$&%+'+$(0
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•
2−1
SCAS073A − JUNE 1989 − REVISED APRIL 1993
logic symbol†
1
1PRE
1J
1CLK
1K
S
16
C1
15
2K
1Q
R
7
2CLK
3
1K
1CLR
2J
1Q
14
13
2PRE
2
1J
S
8
6
2J
10
2Q
C2
9
5
2Q
2K
11
R
2CLR
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, J, and N packages.
logic diagram, each flip-flop (positive logic)
PRE
C
J
C
TG
Q
TG
C
K
CLK
C
C
C
C
C
TG
TG
C
C
Q
CLR
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)‡
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 100 mA
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −ā 65°C to 150°C
‡ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2−2
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SCAS073A − JUNE 1989 − REVISED APRIL 1993
recommended operating conditions
54AC11112
VCC
Supply voltage
VIH
High-level input voltage
VCC = 3 V
VCC = 4.5 V
VCC = 5.5 V
VCC = 3 V
VIL
Low-level input voltage
VI
VO
MAX
3
5
5.5
Low-level output current
∆t /∆v
Input transition rise or fall rate
TA
Operating free-air temperature
MIN
NOM
MAX
3
5
5.5
2.1
2.1
3.15
3.15
3.85
3.85
VCC = 3 V
VCC = 4.5 V
UNIT
V
V
0.9
0.9
1.35
1.35
1.65
1.65
VCC
VCC
0
High-level output current
IOL
NOM
0
Output voltage
IOH
MIN
VCC = 4.5 V
VCC = 5.5 V
Input voltage
74AC11112
0
VCC
VCC
0
−4
−4
−24
−24
VCC = 5.5 V
VCC = 3 V
−24
−24
12
12
VCC = 4.5 V
VCC = 5.5 V
24
24
24
24
V
V
V
mA
mA
0
10
0
10
ns/ V
−55
125
−40
85
°C
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = − 50 µA
VOH
IOH = − 4 mA
IOH = − 24 mA
IOH = − 50 mA†
IOH = − 75 mA†
IOL = 50 µA
VOL
IOL = 12 mA
IOL = 24 mA
II
ICC
TA = 25°C
TYP
MAX
54AC11112
74AC11112
MIN
MIN
VCC
MIN
3V
2.9
2.9
2.9
4.5 V
4.4
4.4
4.4
5.5 V
5.4
5.4
5.4
3V
2.58
2.4
2.48
4.5 V
3.94
3.7
3.8
5.5 V
4.94
4.7
4.8
5.5 V
MAX
MAX
V
3.85
5.5 V
3.85
3V
0.1
0.1
0.1
4.5 V
0.1
0.1
0.1
5.5 V
0.1
0.1
0.1
3V
0.36
0.5
0.44
4.5 V
0.36
0.5
0.44
5.5 V
0.36
0.5
0.44
IOL = 50 mA†
IOL = 75 mA†
5.5 V
VI = VCC or GND
VI = VCC or GND,
5.5 V
UNIT
V
1.65
5.5 V
1.65
± 0.1
IO = 0
5.5 V
4
VI = VCC or GND
5V
3.5
† Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
Ci
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±1
±1
µA
80
40
µA
pF
2−3
SCAS073A − JUNE 1989 − REVISED APRIL 1993
timing requirements, VCC = 3.3 V ± 0.3 V (see Figure 1)
TA = 25°C
MIN
MAX
fclock
Clock frequency
0
tw
Pulse duration
tsu
Setup time before CLK↓
th
Hold time after CLK↓
100
54AC11112
74AC11112
MIN
MAX
MIN
MAX
0
70
0
70
PRE or CLR low
5
5
5
CLK low or CLK high
5
5
5
Data high or low
PRE or CLR inactive
5
5
5
2.5
2.5
2.5
0.5
0.5
0.5
UNIT
MHz
ns
ns
ns
timing requirements, VCC = 5 V ± 0.5 V (see Figure 1)
TA = 25°C
MIN
MAX
fclock
Clock frequency
0
tw
Pulse duration
tsu
Setup time before CLK↓
th
Hold time after CLK↓
125
54AC11112
74AC11112
MIN
MAX
MIN
MAX
0
125
0
125
PRE or CLR low
4
4
4
CLK low or CLK high
4
4
4
3.5
3.5
3.5
2
2
2
1
1
1
Data high or low
PRE or CLR inactive
UNIT
MHz
ns
ns
ns
switching characteristics over recommended operating free-air temperature range,
VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
PARAMETER
fmax
tPLH
tPHL
tPLH
tPHL
FROM
(INPUT)
TO
(OUTPUT)
PRE or CLR
Q or Q
CLK
Q or Q
MIN
TA = 25°C
TYP
MAX
54AC11112
74AC11112
MIN
MIN
MAX
100
MAX
100
150
100
1.5
4.9
6.7
1.5
7.6
1.5
7.3
1.5
7
9.2
1.5
10.3
1.5
9.9
1.5
5.4
7.1
1.5
7.9
1.5
7.6
1.5
6
7.9
1.5
9
1.5
8.5
UNIT
MHz
ns
ns
switching characteristics over recommended operating free-air temperature range,
VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
fmax
tPLH
tPHL
tPLH
tPHL
FROM
(INPUT)
TO
(OUTPUT)
PRE or CLR
Q or Q
CLK
Q or Q
MIN
TA = 25°C
TYP
MAX
54AC11112
74AC11112
MIN
MIN
MAX
125
MAX
125
175
125
1.5
3.3
5.1
1.5
5.6
1.5
5.4
1.5
4.6
6.7
1.5
7.7
1.5
7.3
1.5
3.4
5.1
1.5
5.8
1.5
5.6
1.5
4.2
6.3
1.5
7.4
1.5
7
UNIT
MHz
ns
ns
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER
Cpd
2−4
TEST CONDITIONS
Power dissipation capacitance per gate
CL = 50 pF,
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f = 1 MHz
TYP
UNIT
37
pF
SCAS073A − JUNE 1989 − REVISED APRIL 1993
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
tw
CL = 50 pF
(see Note A)
VCC
500 Ω
Input
50%
50%
0V
VOLTAGE WAVEFORMS
LOAD CIRCUIT
VCC
Input
(see Note B)
Timing Input
(see Note B)
VCC
50%
0V
Data Input
50%
0V
tPHL
tPLH
In-Phase
Output
th
tsu
50%
50% VCC
VCC
50%
tPLH
tPHL
50%
0V
Out-of-Phase
Output
VOH
50% VCC
VOL
50% VCC
VOH
50% VCC
VOL
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns.
C. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
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2−5
SCAS073A − JUNE 1989 − REVISED APRIL 1993
2−6
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