SCBS157A − JANUARY 1991 − REVISED JULY 1994
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SN54ABT543 . . . JT PACKAGE
SN74ABT543 . . . DB, DW, OR NT PACKAGE
(TOP VIEW)
State-of-the-Art EPIC-ΙΙB BiCMOS Design
Significantly Reduces Power Dissipation
ESD Protection Exceeds 2000 V Per
MIL-STD-883C, Method 3015; Exceeds
200 V Using Machine Model (C = 200 pF,
R = 0)
Latch-Up Performance Exceeds 500 mA
Per JEDEC Standard JESD-17
Typical VOLP (Output Ground Bounce)
< 1 V at VCC = 5 V, TA = 25°C
High-Drive Outputs (− 32-mA IOH,
64-mA IOL )
Package Options Include Plastic
Small-Outline (DW) and Shrink
Small-Outline (DB) Packages, Ceramic
Chip Carriers (FK), and Plastic (NT) and
Ceramic (JT) DIPs
LEBA
OEBA
A1
A2
A3
A4
A5
A6
A7
A8
CEAB
GND
1
24
2
23
3
22
4
21
5
20
6
19
7
18
8
17
9
16
10
15
11
14
12
13
VCC
CEBA
B1
B2
B3
B4
B5
B6
B7
B8
LEAB
OEAB
SN54ABT543 . . . FK PACKAGE
(TOP VIEW)
A1
OEBA
LEBA
NC
VCC
description
The ′ABT543 octal transceivers contain two sets
of D-type latches for temporary storage of data
flowing in either direction. Separate latch-enable
(LEAB or LEBA) and output-enable (OEAB or
OEBA) inputs are provided for each register to
permit independent control in either direction of
data flow.
5
3 2 1 28 27 26
25
6
24
7
23
8
22
9
21
10
20
4
A2
A3
A4
NC
A5
A6
A7
19
11
12 13 14 15 16 17 18
B2
B3
B4
NC
B5
B6
B7
A8
CEAB
GND
NC
OEAB
LEAB
B8
The A-to-B enable (CEAB) input must be low in
order to enter data from A or to output data from
B. If CEAB is low and LEAB is low, the A-to-B
latches are transparent; a subsequent low-to-high
transition of LEAB puts the A latches in the storage
mode. With CEAB and OEAB both low, the 3-state
B outputs are active and reflect the data present
at the output of the A latches. Data flow from B to
A is similar but requires using the CEBA, LEBA,
and OEBA inputs.
CEBA
B1
•
NC − No internal connection
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN74ABT543 is available in TI’s shrink small-outline package (DB), which provides the same I/O pin count
and functionality of standard small-outline packages in less than half the printed-circuit-board area.
The SN54ABT543 is characterized for operation over the full military temperature range of −55°C to 125°C. The
SN74ABT543 is characterized for operation from − 40°C to 85°C.
EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.
Copyright 1994, Texas Instruments Incorporated
!"#$% !%&% %'(#&% !"(($% & ' )"*+!&% &$, ("! !%'(# )$!'!&% )$( $ $(# ' $-& %("#$% &%&( .&((&%/,
("!% )(!$%0 $ % %$!$&(+/ %!+"$ $%0 ' &++
)&(&#$$(,
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2−1
SCBS157A − JANUARY 1991 − REVISED JULY 1994
FUNCTION TABLE†
INPUTS
OEAB
A
OUTPUT
B
X
X
X
Z
X
H
X
Z
L
H
L
X
L
L
L
L
B0‡
L
L
L
L
H
CEAB
LEAB
H
X
H
† A-to-B data flow is shown; B-to-A flow control is the
same except that it uses CEBA, LEBA, and OEBA.
‡ Output level before the indicated steady-state input
conditions were established.
logic symbol§
2
OEBA
23
CEBA
1
LEBA
13
OEAB
11
CEAB
14
LEAB
A1
A2
A3
A4
A5
A6
A7
A8
1EN3
G1
1C5
2EN4
G2
2C6
3
4
3
1
5D
6D
1
4
22
21
5
20
6
19
7
18
8
17
9
16
10
15
§ This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the DB, DW, JT, and NT packages.
2−2
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B1
B2
B3
B4
B5
B6
B7
B8
SCBS157A − JANUARY 1991 − REVISED JULY 1994
logic diagram (positive logic)
OEBA
CEBA
LEBA
OEAB
CEAB
LEAB
A1
2
23
1
13
11
14
C1
3
1D
22
B1
C1
1D
To Seven Other Channels
Pin numbers shown are for the DB, DW, JT, and NT packages.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input voltage range, VI (except I/O ports) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Voltage range applied to any output in the high state or power-off state, VO . . . . . . . . . . . . . −0.5 V to 5.5 V
Current into any output in the low state, IO: SN54ABT543 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA
SN74ABT543 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −18 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Maximum power dissipation at TA = 55°C (in still air) (see Note 2): DB package . . . . . . . . . . . . . . . . . . . 0.65 W
DW package . . . . . . . . . . . . . . . . . . . 1.7 W
NT package . . . . . . . . . . . . . . . . . . . . 1.3 W
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils,
except for the NT package, which has a trace length of zero. For more information, refer to the Package Thermal Considerations
application note in the 1994 ABT Advanced BiCMOS Technology Data Book, literature number SCBD002B.
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SCBS157A − JANUARY 1991 − REVISED JULY 1994
recommended operating conditions (see Note 3)
SN54ABT543
VCC
VIH
Supply voltage
VIL
VI
Low-level input voltage
IOH
IOL
High-level output current
∆t /∆v
Input transition rise or fall rate
High-level input voltage
SN74ABT543
MIN
MAX
MIN
MAX
4.5
5.5
4.5
5.5
2
2
0.8
Input voltage
0
Low-level output current
Outputs enabled
TA
Operating free-air temperature
NOTE 3: Unused or floating pins (input or I/O) must be held high or low.
−55
0
V
V
0.8
VCC
−24
UNIT
VCC
−32
V
V
mA
48
64
mA
5
5
ns / V
85
°C
125
−40
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
VIK
VOH
TEST CONDITIONS
VCC = 4.5 V,
VCC = 4.5 V,
II = − 18 mA
IOH = − 3 mA
VCC = 5 V,
VCC = 4.5 V
TA = 25°C
TYP†
MAX
SN54ABT543
MIN
−1.2
MAX
SN74ABT543
MIN
−1.2
2.5
2.5
IOH = − 3 mA
IOH = −24 mA
3
3
3
2
2
IOH = − 32 mA
IOL = 48 mA
2*
II
VCC = 5.5 V,
VI = VCC or GND
IOZH‡
IOZL‡
VCC = 5.5 V,
VCC = 5.5 V,
VO = 2.7 V
VO = 0.5 V
Ioff
ICEX
IO¶
VCC = 0,
VCC = 5.5 V,
VI or VO ≤ 4.5 V
VO = 5.5 V
Outputs high
VCC = 5.5 V,
VO = 2.5 V
IOL = 64 mA
0.55
A or B ports
0.55
±1
±1
±100
10§
±100
10§
±100
10§
−10§
−10§
−10§
µA
±100
µA
50
µA
±100
50
50
−180
−180
mA
1
Outputs low
24
250
34§
250
34§
250
34§
mA
Outputs disabled
0.5
250
250
250
µA
1.5
1.5
1.5
mA
VCC = 5.5 V,
IO = 0,
VI = VCC or GND
∆ICC#
VCC = 5.5 V,
One input at 3.4 V,
Other inputs at VCC or GND
Ci
VI = 2.5 V or 0.5 V
VO = 2.5 V or 0.5 V
−180
−50
µA
−100
ICC
−50
µA
A
Outputs high
µA
Control inputs
4
pF
A or B ports
7
pF
* On products compliant to MIL-STD-883, Class B, this parameter does not apply.
† All typical values are at VCC = 5 V.
‡ The parameters IOZH and IOZL include the input leakage current.
§ This data sheet limit may vary among suppliers.
¶ Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
# This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
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2−4
V
±1
Control inputs
A or B ports
V
V
0.55*
−50
UNIT
2
0.55
VCC = 4.5 V
MAX
−1.2
2.5
VOL
Cio
MIN
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•
SCBS157A − JANUARY 1991 − REVISED JULY 1994
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
VCC = 5 V,
TA = 25°C
MIN
tw
Pulse duration, LEAB or LEBA low
Data before LEAB or LEBA↑
tsu
Setup time
Data before CEAB or CEBA↑
th
Hold time
SN54ABT543
MAX
MIN
MAX
SN74ABT543
MIN
3.5
3.5
3.5
High
3.5
3.5
3.5
Low
3
3
3
High
3.5
3.5
3.5
Low
3
1†
1†
3
1†
1†
3
1†
1†
Data after LEAB or LEBA↑
Data after CEAB or CEBA↑
UNIT
MAX
ns
ns
ns
† This data sheet limit may vary among suppliers.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, CL = 50 pF (unless otherwise noted) (see Figure 1)
FROM
(INPUT)
TO
(OUTPUT)
tPLH
tPHL
A or B
B or A
tPLH
tPHL
LEBA or LEAB
A or B
tPZH
tPZL
OEBA or OEAB
A or B
tPHZ
tPLZ
OEBA or OEAB
A or B
tPZH
tPZL
CEBA or CEAB
A or B
tPHZ
tPLZ
CEBA or CEAB
A or B
PARAMETER
VCC = 5 V,
TA = 25°C
SN54ABT543
MIN
TYP
MAX
MIN
1.9
4.4
5.9
1.9
4.4
5.9
1.6
4.1
2.1
4.6
1.4
2.5
2.5†
MAX
SN74ABT543
MIN
MAX
1.9
1.9
6.9
1.9
1.9
6.9
5.6
1.6
1.6
6.6
6.1
2.1
2.1
7.1
3.9
5.4
1.4
1.4
6.4
5
6.5
7.4
2.5
2.5†
7.5
5.9
2.5
2.5†
3
5.5
7
3
3
8
1.4
3.9
5.4
1.4
1.4
6.4
2.5
3.2†
5
6.5
7.4
2.5
3.2†
7.5
5.9
2.5
3.2†
3
5.5
7
3
3
8
UNIT
ns
ns
ns
8.4
8.4
ns
ns
ns
† This data sheet limit may vary among suppliers.
%'(#&% !%!$(% )("! % $ '(#&1$ (
$0% )&$ ' $1$+)#$%, &(&!$(! && &% $(
)$!'!&% &($ $0% 0&+, $-& %("#$% ($$(1$ $ (0 !&%0$ ( !%%"$ $$ )("! ." %!$,
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•
2−5
SCBS157A − JANUARY 1991 − REVISED JULY 1994
PARAMETER MEASUREMENT INFORMATION
7V
S1
500 Ω
From Output
Under Test
Open
GND
CL = 50 pF
(see Note A)
500 Ω
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
7V
Open
LOAD CIRCUIT FOR OUTPUTS
3V
Timing Input
1.5 V
0V
tw
tsu
3V
Input
1.5 V
th
3V
1.5 V
Data Input
1.5 V
1.5 V
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3V
Input
(see Note B)
1.5 V
0V
Output
1.5 V
VOL
tPLH
tPHL
Output
Waveform 2
S1 at Open
(see Note C)
VOH
Output
1.5 V
1.5 V
0V
tPLZ
Output
Waveform 1
S1 at 7 V
(see Note C)
VOH
1.5 V
1.5 V
tPZL
tPHL
tPLH
3V
Output
Control
1.5 V
1.5 V
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
1.5 V
tPZH
3.5 V
VOL + 0.3 V
VOL
tPHZ
1.5 V
VOH − 0.3 V
VOH
[0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
2−6
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