54ACT534 Octal D Flip-Flop with TRI-STATE ® Outputs General Description The ’ACT534 is a high-speed, low-power octal D-type flip-flop featuring separate D-type inputs for each flip-flop and TRI-STATE outputs for bus-oriented applications. A buffered Clock (CP) and Output Enable (OE) are common to all flip-flops. The ’ACT534 is the same as the ’ACT374 except that the outputs are inverted. n n n n n n n Edge-triggered D-type inputs Buffered positive edge-triggered clock TRI-STATE outputs for bus-oriented applications Outputs source/sink 24 mA ’ACT534 has TTL-compatible inputs Inverted output version of ’ACT374 Standard Microcircuit Drawing (SMD) 5962-8965801 Features n ICC and IOZ reduced by 50% Logic Symbols IEEE/IEC DS100292-1 DS100292-2 Pin Names D0–D7 Description Data Inputs CP Clock Pulse Input OE TRI-STATE Output Enable Input O0–O7 Complementary TRI-STATE Outputs TRI-STATE ® is a registered trademark of National Semiconductor Corporation. FACT™ is a trademark of Fairchild Semiconductor Corporation. © 1998 National Semiconductor Corporation DS100292 www.national.com 54ACT534 Octal D Flip-Flop with TRI-STATE Outputs July 1998 Connection Diagrams Pin Assignment for DIP and Flatpak Pin Assignment for LCC DS100292-4 DS100292-3 Functional Description times requirements on the LOW-to-HIGH Clock (CP) transition. With the Output Enable (OE) LOW, the contents of the eight flip-flops are available at the outputs. When the OE is HIGH, the outputs go to the high impedance state. Operation of the OE input does not affect the state of the flip-flops. The ’ACT534 consists of eight edge-triggered flip-flops with individual D-type inputs and TRI-STATE complementary outputs. The buffered clock and buffered Output Enable are common to all flip-flops. The eight flip-flops will store the state of their individual D inputs that meet the setup and hold Logic Diagram DS100292-5 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. Function Table Inputs Output CP OE D N L H O L N L L H L L X O0 X H X Z H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial N = LOW-to-HIGH Clock Transition Z = High Impedance O0 = Value stored from previous clock cycle www.national.com 2 Absolute Maximum Ratings (Note 1) Junction Temperature (TJ) CDIP If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) DC Input Diode Current (IIK) VI = −0.5V VI = VCC + 0.5V DC Input Voltage (VI) DC Output Diode Current (IOK) VO = −0.5V VO = VCC + 0.5V DC Output Voltage (VO) DC Output Source or Sink Current (IO) DC VCC or Ground Current per Output Pin (ICC or IGND) Storage Temperature (TSTG) 175˚C Recommended Operating Conditions −0.5V to +7.0V Supply Voltage (VCC) ’ACT Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) 54ACT Minimum Input Edge Rate (∆V/∆t) ’ACT Devices VIN from 0.8V to 2.0V VCC @ 4.5V, 5.5V −20 mA +20 mA −0.5V to VCC + 0.5V −20 mA +20 mA −0.5V to VCC + 0.5V ± 50 mA 4.5V to 5.5V 0V to VCC 0V to VCC −55˚C to +125˚C 125 mV/ns Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. National does not recommend operation of FACT™ circuits outside databook specifications. ± 50 mA −65˚C to +150˚C DC Characteristics for ’ACT Family Devices Symbol Parameter VCC 54ACT TA = (V) −55˚C to +125˚C Units Conditions Guaranteed Limits VIH VIL VOH Minimum High Level 4.5 2.0 Input Voltage 5.5 2.0 Maximum Low Level 4.5 0.8 Input Voltage 5.5 0.8 Minimum High Level 4.5 4.4 Output Voltage 5.5 5.4 V VOUT = 0.1V V or VCC − 0.1V VOUT = 0.1V V or VCC − 0.1V IOUT = −50 µA (Note 2) VIN = VIL or VIH VOL 4.5 3.70 5.5 4.70 Maximum Low Level 4.5 0.1 Output Voltage 5.5 0.1 V IOH = −24 mA V IOH = −24 mA IOUT = 50 µA (Note 2) VIN = VIL or VIH 4.5 0.50 5.5 0.50 V IOL = 24 mA IOL = 24 mA VI = VCC, GND IIN Maximum Input Leakage Current 5.5 ± 1.0 µA IOZ Maximum TRI-STATE 5.5 ± 5.0 µA VI = VIL, VIH VO = VCC, GND VI = VCC − 2.1V VOLD = 1.65V Max Current ICCT Maximum ICC/Input 5.5 1.6 mA IOLD Minimum Dynamic 5.5 50 mA IOHD Output Current (Note 3) 5.5 −50 mA ICC Maximum Quiescent 5.5 80.0 µA Supply Current VOHD = 3.85V Min VIN = VCC or GND Note 2: All outputs loaded; thresholds on input associated with output under test. Note 3: Maximum test duration 2.0 ms, one output loaded at a time. Note 4: ICC for 54ACT @ 25˚C is identical to 74ACT @ 25˚C. 3 www.national.com AC Electrical Characteristics 54ACT TA = −55˚C VCC Symbol Parameter (V) (Note 5) Min fmax Maximum Clock Fig. to +125˚C CL = 50 pF Units No. Max 5.0 85 MHz 5.0 1.5 14.0 ns 5.0 1.5 13.0 ns Frequency tPLH Propagation Delay CP to Qn tPHL Propagation Delay CP to Qn tPZH Output Enable Time 5.0 1.5 14.0 ns tPZL Output Enable Time 5.0 1.5 13.0 ns tPHZ Output Disable Time 5.0 1.5 14.5 ns tPLZ Output Disable Time 5.0 1.5 11.5 ns Note 5: Voltage Range 5.0 is 5.0V ± 0.5V AC Operating Requirements 54ACT TA = −55˚C VCC Symbol Parameter (V) to +125˚C CL = 50 pF (Note 6) Fig. Units Guaranteed Minimum ts Setup Time, HIGH or LOW 5.0 5.0 ns 5.0 3.0 ns 5.0 5.0 ns Dn to CP th Hold Time, HIGH or LOW Dn to CP tw CP Pulse Width HIGH or LOW Note 6: Voltage Range 5.0 is 5.0V ± 0.5V Capacitance Symbol CIN CPD Typ Units Input Capacitance Parameter 4.5 pF Power Dissipation 40.0 pF Capacitance www.national.com 4 Conditions VCC = OPEN VCC = 5.0V No. Physical Dimensions inches (millimeters) unless otherwise noted 20 Terminal Ceramic Leadless Chip Carrier (L) NS Package Number E20A 16 Lead Ceramic Dual-In-Line Package (D) NS Package Number J16A 5 www.national.com 54ACT534 Octal D Flip-Flop with TRI-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16 Lead Ceramic Flatpak (F) NS Package Number W16A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or sysdevice or system whose failure to perform can be reatems which, (a) are intended for surgical implant into sonably expected to cause the failure of the life support the body, or (b) support or sustain life, and whose faildevice or system, or to affect its safety or effectiveness. ure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 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