54ACTQ377 Octal D Flip-Flop with Clock Enable General Description Features The ACTQ377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) input loads all flip-flops simultaneously, when the Clock Enable (CE) is LOW. n Ideal for addressable register applications n Clock enable for address and data synchronization applications n Eight edge-triggered D flip-flops n Buffered common clock n Outputs source/sink 24 mA n See ’273 for master reset version n See ’373 for transparent latch version n See ’374 for TRI-STATE ® version n Guaranteed simultaneous switching noise level and dynamic threshold performance n TTL-compatible inputs and outputs n Standard Microcircuit Drawing (SMD) 5962-9219001 The register is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop’s Q output. The CE input must be stable only one setup time prior to the LOW-to-HIGH clock transition for predictable operation. The ACTQ377 utilizes FACT Quiet Series ® technology to guarantee quiet output switching and improved dynamic threshold performance. FACT Quiet Series features GTO ® output control and undershoot corrector in addition to a split ground bus for superior performance. Logic Symbols IEEE/IEC DS100357-1 DS100357-2 Pin Names Description D0–D7 Data Inputs CE Clock Enable (Active LOW) Q0–Q7 Data Outputs CP Clock Pulse Input GTO ® is a trademark of National Semiconductor Corporation. TRI-STATE ® is a registered trademark of National Semiconductor Corporation. FACT ® and FACT Quiet Series ® are registered trademarks of Fairchild Semiconductor Corporation. © 1998 National Semiconductor Corporation DS100357 www.national.com 54ACTQ377 Octal D Flip-Flop with Clock Enable September 1998 Connection Diagrams Pin Assignment for DIP and Flatpak Pin Assignment for LCC DS100357-4 DS100357-3 Mode Select-Function Table Operating Mode Inputs Outputs CP CE Dn Qn Load ‘1’ N L H H Load ‘0’ N L L Hold (Do Nothing) N H X No Change X H X No Change L H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial N = LOW-to-HIGH Clock Transition Logic Diagram DS100357-5 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.national.com 2 Absolute Maximum Ratings (Note 1) CDIP If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) DC Input Diode Current (IIK) VI = −0.5V VI = VCC + 0.5V DC Input Voltage (VI) DC Output Diode Current (IOK) VO = −0.5V VO = VCC + 0.5V DC Output Voltage (VO) DC Output Source or Sink Current (IO) DC VCC or Ground Current per Output Pin (ICC or IGND) Storage Temperature (TSTG) Junction Temperature (TJ) 175˚C Recommended Operating Conditions −0.5V to +7.0V Supply Voltage (VCC) ’ACTQ Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) 54ACTQ Minimum Input Edge Rate (∆V/∆t) ’ACTQ Devices VIN from 0.8V to 2.0V VCC @ 4.5V, 5.5V −20 mA +20 mA −0.5V to VCC + 0.5V −20 mA +20 mA −0.5V to VCC + 0.5V ± 50 mA 4.5V to 5.5V 0V to VCC 0V to VCC −55˚C to +125˚C 125 mV/ns Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. National does not recommend operation of FACT ® circuits outside databook specifications. ± 50 mA −65˚C to +150˚C DC Characteristics for ’ACTQ Family Devices Symbol Parameter VCC 54ACTQ TA = (V) −55˚C to +125˚C Units Conditions Guaranteed Limits VIH VIL VOH VOL IIN Minimum High Level 4.5 2.0 Input Voltage 5.5 2.0 Maximum Low Level 4.5 0.8 Input Voltage 5.5 0.8 Minimum High Level 4.5 4.4 Output Voltage 5.5 5.4 4.5 3.70 5.5 4.70 Maximum Low Level 4.5 0.1 Output Voltage 5.5 0.1 Maximum Input V VOUT = 0.1V V or VCC − 0.1V VOUT = 0.1V V or VCC − 0.1V IOUT = −50 µA V (Note 2) VIN = VIL or VIH IOH = −24 mA V IOH = −24 mA IOUT = 50 µA V (Note 2) VIN = VIL or VIH IOL = 24 mA 4.5 0.50 5.5 0.50 5.5 ± 1.0 µA IOL = 24 mA VI = VCC, GND 5.5 1.6 mA VI = VCC − 2.1V 5.5 50 mA VOLD = 1.65V Max VOHD = 3.85V Min VIN = VCC Leakage Current ICCT Maximum ICC/Input IOLD (Note 3) Minimum Dynamic IOHD Output Current 5.5 −50 mA ICC Maximum Quiescent 5.5 160.0 µA 5.0 1.5 V Supply Current VOLP Quiet Output Maximum Dynamic VOL or GND 3 (Note 4) www.national.com DC Characteristics for ’ACTQ Family Devices Symbol Parameter (Continued) VCC 54ACTQ TA = (V) −55˚C to +125˚C Units Conditions V (Note 4) Guaranteed Limits VOLV Quiet Output Minimum Dynamic VOL 5.0 -1.2 Note 2: *All outputs loaded; thresholds on input associated with output under test. Note 3: †Maximum test duration 2.0 ms, one output loaded at a time. Note 4: Max number of outputs defined as (n). Data inputs are driven 0V to 3V. one output GND. AC Electrical Characteristics 54ACTQ TA = −55˚C VCC Symbol Parameter (V) (Note 5) Min fmax Maximum Clock Fig. to +125˚C CL = 50 pF Units No. Max 5.0 85 MHz 5.0 1.5 10.0 ns 5.0 1.5 10.0 ns Frequency tPLH Propagation Delay CP to Qn tPHL Propagation Delay CP to Qn Note 5: Voltage Range 5.0 is 5.0V ± 0.5V AC Operating Requirements 54ACTQ TA = −55˚C VCC Symbol Parameter (V) to +125˚C CL = 50 pF (Note 6) Fig. Units Guaranteed Minimum ts Setup Time, HIGH or LOW 5.0 4.0 ns 5.0 1.5 ns 5.0 5.0 ns 5.0 1.5 ns 5.0 5.0 ns Dn to CP th Hold Time, HIGH or LOW Dn to CP ts Setup Time, HIGH or LOW CE to CP th Hold Time, HIGH or LOW CE to CP tw CP Pulse Width HIGH or LOW Note 6: Voltage Range 5.0 is 5.0V ± 0.5V Capacitance Symbol CIN CPD Typ Units Input Capacitance Parameter 10.0 pF Power Dissipation 80.0 pF Capacitance www.national.com 4 Conditions VCC = OPEN VCC = 5.0V No. Physical Dimensions inches (millimeters) unless otherwise noted 20 Terminal Ceramic Leadless Chip Carrier (L) NS Package Number E20A 20 Lead Ceramic Dual-In-Line Package (D) NS Package Number J20A 5 www.national.com 54ACTQ377 Octal D Flip-Flop with Clock Enable Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20 Lead Ceramic Flatpak (F) NS Package Number W20A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or sysdevice or system whose failure to perform can be reatems which, (a) are intended for surgical implant into sonably expected to cause the failure of the life support the body, or (b) support or sustain life, and whose faildevice or system, or to affect its safety or effectiveness. ure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation Americas Tel: 1-800-272-9959 Fax: 1-800-737-7018 Email: [email protected] www.national.com National Semiconductor Europe Fax: +49 (0) 1 80-530 85 86 Email: [email protected] Deutsch Tel: +49 (0) 1 80-530 85 85 English Tel: +49 (0) 1 80-532 78 32 Français Tel: +49 (0) 1 80-532 93 58 Italiano Tel: +49 (0) 1 80-534 16 80 National Semiconductor Asia Pacific Customer Response Group Tel: 65-2544466 Fax: 65-2504466 Email: [email protected] National Semiconductor Japan Ltd. Tel: 81-3-5620-6175 Fax: 81-3-5620-6179 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.