NSC 5962-9314901

54FCT374
Octal D-Type Flip-Flop with TRI-STATE ® Outputs
General Description
Features
The ’FCT374 is an octal D-type flip-flop featuring separate
D-type inputs for each flip-flop and TRI-STATE outputs for
bus-oriented applications. A buffered Clock (CP) and Output
Enable (OE) are common to all flip-flops.
n
n
n
n
n
n
Edge-triggered D-type inputs
Buffered positive edge-triggered clock
TRI-STATE outputs for bus-oriented applications
TTL input and output level compatible
Low CMOS power consumption
Output sink capability of 32 mA, source capability of
12 mA
n Standard Microcircuit Drawing (SMD) 5962-9314901
Ordering Code
Military
Package
Package Description
Number
54FCT374DMQB
J20A
20-Lead Ceramic Dual-In-Line
54FCT374FMQB
W20A
20-Lead Cerpack
54FCT374LMQB
E20A
20-Lead Ceramic Leadless Chip Carrier, Type C
Connection Diagrams
Pin Assignment for DIP
and Flatpak
Pin Assignment
for LCC
DS100964-2
DS100964-1
TRI-STATE ® is a registered trademark of National Semiconductor Corporation.
© 1999 National Semiconductor Corporation
DS100964
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54FCT374 Octal D-Type Flip-Flop with TRI-STATE Outputs
September 1998
54FCT374
Pin Descriptions
Pin
Functional Description
The ’FCT374 consists of eight edge-triggered flip-flops with
individual D-type inputs and TRI-STATE true outputs. The
buffered clock and buffered Output Enable are common to all
flip-flops. The eight flip-flops will store the state of their individual D inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock (CP) transition. With the
Output Enable (OE) LOW, the contents of the eight flip-flops
are available at the outputs. When OE is HIGH, the outputs
are in a high impedance state. Operation of the OE input
does not affect the state of the flip-flops.
Description
Names
D0–D7
Data Inputs
CP
Clock Pulse Input (Active
Rising Edge)
OE
TRI-STATE Output Enable
Input (Active LOW)
O0–O7
TRI-STATE Outputs
Function Table
Inputs
Internal
Outputs
D
Q
O
H
L
NC
Z
Hold
H
H
NC
Z
Hold
H
N
L
L
Z
Load
H
N
H
H
Z
Load
L
N
L
L
L
Data Available
L
N
H
H
H
L
H
L
NC
NC
No Change in Data
L
H
H
NC
NC
No Change in Data
OE
CP
H
H
Function
Data Available
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
N = LOW-to-HIGH Transition
NC = No Change
Logic Diagram
DS100964-3
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
Power-Off State
in the HIGH State
Current Applied to Output
in LOW State (Max)
Storage Temperature
Ambient Temperature under Bias
Junction Temperature under Bias
Ceramic
VCC Pin Potential to
Ground Pin
Input Voltage
Input Current
Voltage Applied to Any Output
in the Disabled or
−65˚C to +150˚C
−55˚C to +125˚C
−0.5V to +5.5V
−0.5V to VCC
twice the rated IOL (mA)
Recommended Operating
Conditions
−55˚C to +175˚C
Free Air Ambient Temperature
Military
Supply Voltage
Military
−0.5V to +7.0V
−0.5V to +7.0V
−30 mA to +5.0 mA
−55˚C to +125˚C
+4.5V to +5.5V
Note 1: Absolute maximum ratings are values beyond which the device may
be damaged or have its useful life impaired. Functional operation under these
conditions is not implied.
DC Electrical Characteristics
Symbol
Parameter
FCT374
Min
Units
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
0.8
V
VCD
Input Clamp Diode Voltage
−1.2
V
VOH
Output HIGH
Voltage
VOL
2.0
Output LOW Voltage
VCC
Conditions
Max
V
Recognized HIGH Signal
Min
54FCT
4.3
V
Min
54FCT
2.4
V
Min
54FCT
0.2
V
Min
54FCT
0.5
V
Min
µA
Max
µA
Max
IIH
Input HIGH Current
5
IIL
Input LOW Current
−5
5
−5
Recognized LOW Signal
IIN = −18 mA
IOH = −300 µA
IOH = −12 mA
IOL = 300 µA
IOL = 32mA
VIN = 2.7V (Note 3)
VIN = VCC
VIN = 0.5V (Note 3)
VIN = 0.0V
VOUT = 2.7V; OE = 2.0V
IOZH
Output Leakage Current
10
µA
0 − 5.5V
IOZL
Output Leakage Current
−10
µA
0 − 5.5V
IOS
Output Short-Circuit Current
mA
Max
ICCQ
Power Supply Current
1.5
mA
Max
VIN = 0.2V or VIN = 5.3V, fI =
0MHz
∆ICC
Power Supply Current
2.0
mA
Max
ICCT
Additional
ICC/Input
6.0
mA
Max
5.5
mA
Max
VIN = 3.4V
VI = VCC − 2.1V or VIN = GND, fCP
= 10MHz, Outputs open, OE =
GND, one bit toggling at fI = 5MHz,
50% duty cycle
VI = 5.3V or VCC = 0.2V, fCP =
10MHz, Outputs open, OE = GND,
one bit toggling at fI = 5MHz, 50%
duty cycle
0.4
mA/
MHz
Max
ICCD
Dynamic ICC
−60
No Load
VOUT = 0.5V; OE = 2.0V
VOUT = 0.0V
Outputs Open, OE = GND, One bit
toggling, 50% duty cycle, VIN =
5.3V or VIN = 0.2V
Note 2: For 8-bit toggling, ICCD < 0.8 mA/MHz.
Note 3: Guaranteed, but not tested.
3
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54FCT374
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
54FCT374
AC Electrical Characteristics
Symbol
Parameter
54FCT
TA = −55˚C to +125˚C
VCC = 4.5V to 5.5V
Units
CL = 50 pF
Min
Max
tPLH
Propagation Delay
2.0
11.0
tPHL
CP to On
2.0
11.0
tPZH
Output Enable Time
tPZL
tPHZ
Output Disable Time
tPLZ
1.5
14.0
1.5
14.0
1.5
8.0
1.5
8.0
ns
ns
ns
AC Operating Requirements
Symbol
54FCT
TA = −55˚C to +125˚C
VCC = 4.5V to 5.5V
Parameter
Units
CL = 50 pF
Min
ts(H)
Setup Time, HIGH
2.5
ts(L)
or LOW Dn to CP
2.5
th(H)
Hold Time, HIGH
2.5
th(L)
or LOW Dn to CP
2.5
tw(H)
Pulse Width, CP
7.0
tw(L)
HIGH or LOW
7.0
Max
ns
ns
ns
Capacitance
Typ
Units
CIN
Symbol
Input Capacitance
Parameter
5.0
pF
COUT (Note 4)
Output Capacitance
9.0
pF
Note 4: COUT is measured at frequency f = 1 MHz, per MIL-STD-883B, Method 3012.
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4
Conditions (TA = 25˚C)
VCC = 0V
VCC = 5.0V
54FCT374
Capacitance
(Continued)
AC Loading
DS100964-8
FIGURE 4. Propagation Delay Waveforms for
Inverting and Non-Inverting Functions
DS100964-4
*Includes jig and probe capacitance
FIGURE 1. Standard AC Test Load
DS100964-5
FIGURE 5. Propagation Delay,
Pulse Width Waveforms
DS100964-6
FIGURE 2. VM = 1.5V
Input Pulse Requirements
Amplitude
Rep. Rate
tw
tr
tf
3.0V
1 MHz
500 ns
2.5 ns
2.5 ns
FIGURE 3. Test Input Signal Requirements
DS100964-7
FIGURE 6. TRI-STATE Output HIGH
and LOW Enable and Disable Times
DS100964-9
FIGURE 7. Setup Time, Hold Time
and Recovery Time Waveforms
5
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54FCT374
Physical Dimensions
inches (millimeters) unless otherwise noted
20-Terminal Ceramic Chip Carrier (L)
NS Package Number E20A
20-Lead Ceramic Dual-In-Line (D)
NS Package Number J20A
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6
54FCT374 Octal D-Type Flip-Flop with TRI-STATE Outputs
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
20-Lead Ceramic Flatpak (F)
NS Package Number W20A
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