54ACTQ574 Quiet Series Octal D Flip-Flop with TRI-STATE ® Outputs General Description Features The ACTQ574 is a high-speed, low-power octal D-type flip-flop with a buffered Common Clock (CP) and a buffered common Output Enable (OE). The information presented to the D inputs is stored in the flip-flops on the LOW-to-HIGH clock (CP) transition. n ICC and IOZ reduced by 50% n Guaranteed simultaneous switching noise level and dynamic threshold performance n Inputs and outputs on opposite sides of the package allowing easy interface with microprocessors n Functionally identical to the ACTQ374 n TRI-STATE outputs drive bus lines or buffer memory address registers n Outputs source/sink 24 mA n Faster prop delays than the standard ACT574 n 4 kV minimum ESD immunity ACTQ574 utilizes Quiet Series technology to guarantee quiet output switching and improve dynamic threshold performance. FACT Quiet Series™ features GTO™ output control and undershoot corrector in addition to a split ground bus for superior performance. The ACTQ574 is functionally identical to the ’ACTQ374 but with different pin-out. Logic Diagrams IEEE/IEC DS100243-1 DS100243-2 Pin Names Description D0–D7 Data Inputs CP Clock Pulse Input OE TRI-STATE Output Enable Input O0–O7 TRI-STATE Outputs GTO™ is a trademark of National Semiconductor Corporation. TRI-STATE ® is a registered trademark of National Semiconductor Corporation. FACT ® is a registered trademark of Fairchild Semiconductor Corporation. FACT Quiet Series™ is a trademark of Fairchild Semiconductor Corporation. © 1998 National Semiconductor Corporation DS100243 www.national.com 54ACTQ574 Quiet Series Octal D Flip-Flop with TRI-STATE Outputs August 1998 Connection Diagrams Functional Description The ACTQ574 consists of eight edge-triggered flip-flops with individual D-type inputs and TRI-STATE true outputs. The buffered clock and buffered Output Enable are common to all flip-flops. The eight flip-flops will store the state of their individual D inputs that meet the setup and hold time requirements on the LOW-to-HIGH Clock (CP) transition. With the Output Enable (OE) LOW, the contents of the eight flip-flops are available at the outputs. When OE is HIGH, the outputs go to the high impedance state. Operation of the OE input does not affect the state of the flip-flops. Pin Assignment for DIP and Flatpak Function Table Inputs DS100243-3 Pin Assignment for LCC Internal Outputs Q ON Function OE CP H H L NC Z Hold H H H NC Z Hold Load D H N L L Z H N H H Z Load L N L L L Data Available L N H H H Data Available L H L NC NC No Change in Data L H H NC NC No Change in Data H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance N = LOW-to-HIGH Transition NC = No Change DS100243-4 Logic Diagram DS100243-5 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. www.national.com 2 Absolute Maximum Ratings (Note 2) CDIP If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) DC Input Diode Current (IIK) VI = −0.5V VI = VCC + 0.5V DC Input Voltage (VI) DC Output Diode Current (IOK) VO = −0.5V VO = VCC + 0.5V DC Output Voltage (VO) DC Output Source or Sink Current (IO) DC VCC or Ground Current per Output Pin (ICC or IGND) Storage Temperature (TSTG) DC Latch-Up Source or Sink Current Junction Temperature (TJ) 175˚C Recommended Operating Conditions −0.5V to +7.0V Supply Voltage (VCC) ’ACTQ Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) 54ACTQ Minimum Input Edge Rate ∆V/∆t ’ACTQ Devices VIN from 0.8V to 2.0V VCC @ 4.5V, 5.5V −20 mA +20 mA −0.5V to VCC + 0.5V −20 mA +20 mA −0.5V to VCC + 0.5V ± 50 mA 4.5V to 5.5V 0V to VCC 0V to VCC −55˚C to +125˚C 125 mV/ns Note 1: All commercial packaging is not recommended for applications requiring greater than 2000 temperature cycles from −40˚C to +125˚C. ± 50 mA −65˚C to +150˚C Note 2: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. National does not recommend operation of FACT™ circuits outside databook specifications. ± 300 mA DC Electrical Characteristics for ’ACTQ Family Devices Symbol Parameter VCC 54ACTQ TA = (V) −55˚C to +125˚C Units Conditions Guaranteed Limits VIH VIL VOH VOL Minimum High Level 4.5 2.0 Input Voltage 5.5 2.0 Maximum Low Level 4.5 0.8 Input Voltage 5.5 0.8 Minimum High Level 4.5 4.4 Output Voltage 5.5 5.4 4.5 3.70 5.5 4.70 Maximum Low Level 4.5 0.1 Output Voltage 5.5 0.1 V VOUT = 0.1V V or VCC − 0.1V VOUT = 0.1V V or VCC − 0.1V IOUT = −50 µA V (Note 3) VIN = VIL or VIH IOH = −24 mA V IOH = −24 mA IOUT = 50 µA V (Note 3) VIN = VIL or VIH IOL = 24 mA IOL = 24 mA VI = VCC, GND 4.5 0.50 5.5 0.50 µA µA VI = VIL, VIH VO = VCC, GND VI = VCC − 2.1V VOLD = 1.65V Max IIN Maximum Input Leakage Current 5.5 IOZ Maximum TRI-STATE 5.5 ± 1.0 ± 5.0 Leakage Current ICCT Maximum ICC/Input 5.5 1.6 mA IOLD (Note 4) 5.5 50 mA Minimum Dynamic IOHD Output Current 5.5 −50 mA ICC Maximum Quiescent 5.5 80.0 µA Supply Current VOHD = 3.85V Min VIN = VCC or GND (Note 5) 3 www.national.com DC Electrical Characteristics for ’ACTQ Family Devices Symbol Parameter VCC 54ACTQ TA = (V) −55˚C to +125˚C (Continued) Units Conditions Guaranteed Limits VOLP Quiet Output 5.0 1.5 V (Notes 6, 7) 5.0 −1.2 V (Notes 6, 7) Maximum Dynamic VOL VOLV Quiet Output Minimum Dynamic VOL Note 3: All outputs loaded; thresholds on input associated with output under test. Note 4: Maximum test duration 2.0 ms, one output loaded at a time. Note 5: ICC for 54ACTQ @ 25˚C is identical to 74ACTQ @ 25˚C. Note 6: Plastic DIP package. Note 7: Max number of outputs defined as (n). Data inputs are driven 0V to 3V. One output @ GND. Note 8: Max number of data inputs (n) switching. (n−1) inputs switching 0V to 3V (’ACTQ). Input-under-test switching: 3V to threshold (VILD), 0V to threshold (VIHD), f = 1 MHz. AC Electrical Characteristics 54ACTQ TA = −55˚C VCC Symbol Parameter (V) to +125˚C CL = 50 pF (Note 9) Min fmax Units Max Maximum Clock Frequency 5.0 95 MHz tPLH, Propagation Delay 5.0 1.0 11.0 ns tPHL CP to On tPZH, Output Enable Time 5.0 1.0 11.0 ns Output Disable Time 5.0 1.0 10.0 ns tPZL tPHZ, tPLZ Note 9: Voltage Range 5.0 is 5.0V ± 0.5V. Note 10: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH to LOW (tOSHL) or LOW to HIGH (tOSLH). Parameter guaranteed by design. AC Operating Requirements VCC Symbol Parameter (V) (Note 11) 54ACTQ TA = −55˚C to +125˚C CL = 50 pF Units Guaranteed Minimum tS Setup Time, HIGH or LOW 5.0 3.5 ns 5.0 2.0 ns 5.0 5.0 ns Dn to CP tH Hold Time, HIGH or LOW Dn to CP tW CP Pulse Width, HIGH or LOW Note 11: Voltage Range 5.0 is 5.0V ± 0.5V www.national.com 4 Capacitance Typ Units CIN Symbol Input Capacitance Parameter 4.5 pF CPD Power Dissipation Capacitance 40.0 pF 5 Conditions VCC = OPEN VCC = 5.0V www.national.com Physical Dimensions inches (millimeters) unless otherwise noted 20-Terminal Ceramic Leadless Chip Carrier (L) NS Package Number E20A 20-Lead Ceramic Dual-In-Line Package (D) NS Package Number J20A www.national.com 6 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Small Outline Integrated Circuit (S) NS Package Number M20B 20-Lead Plastic Dual-In-LIne Package (P) NS Package Number N20B 7 www.national.com 54ACTQ574 Quiet Series Octal D Flip-Flop with TRI-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Ceramic Flatpak (F) NS Package Number W20A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. 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