KERSEMI IRFR13N15D

IRFR/U13N15D
SMPS MOSFET
HEXFET® Power MOSFET
Applications
High frequency DC-DC converters
l
VDSS
150V
Benefits
l Low Gate-to-Drain Charge to Reduce
Switching Losses
l Fully Characterized Capacitance Including
Effective COSS to Simplify Design, (See
App. Note AN1001)
l Fully Characterized Avalanche Voltage
and Current
RDS(on) max
ID
0.18Ω
14A
D-Pak
IRFR13N15D
I-Pak
IRFU13N15D
Absolute Maximum Ratings
Parameter
ID @ TC = 25°C
ID @ TC = 100°C
IDM
PD @TC = 25°C
VGS
dv/dt
TJ
TSTG
Continuous Drain Current, VGS @ 10V
Continuous Drain Current, VGS @ 10V
Pulsed Drain Current 
Power Dissipation
Linear Derating Factor
Gate-to-Source Voltage
Peak Diode Recovery dv/dt ƒ
Operating Junction and
Storage Temperature Range
Soldering Temperature, for 10 seconds
Max.
14
9.8
56
86
0.57
± 30
3.8
-55 to + 175
Units
A
W
W/°C
V
V/ns
°C
300 (1.6mm from case )
Typical SMPS Topologies
l
1 / 10
Telecom 48V input Active Clamp Forward Converter
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IRFR/U13N15D
Static @ TJ = 25°C (unless otherwise specified)
Parameter
Drain-to-Source Breakdown Voltage
∆V(BR)DSS/∆TJ Breakdown Voltage Temp. Coefficient
RDS(on)
Static Drain-to-Source On-Resistance
VGS(th)
Gate Threshold Voltage
V(BR)DSS
IDSS
Drain-to-Source Leakage Current
IGSS
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Min.
150
–––
–––
3.0
–––
–––
–––
–––
Typ.
–––
0.17
–––
–––
–––
–––
–––
–––
Max. Units
Conditions
–––
V
VGS = 0V, ID = 250µA
––– V/°C Reference to 25°C, ID = 1mA †
0.18
Ω
VGS = 10V, ID = 8.3A „
5.5
V
VDS = VGS, ID = 250µA
25
VDS = 150V, VGS = 0V
µA
250
VDS = 120V, VGS = 0V, TJ = 150°C
100
VGS = 30V
nA
-100
VGS = -30V
Dynamic @ TJ = 25°C (unless otherwise specified)
gfs
Qg
Qgs
Qgd
td(on)
tr
td(off)
tf
Ciss
Coss
Crss
Coss
Coss
Coss eff.
Parameter
Forward Transconductance
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Output Capacitance
Output Capacitance
Effective Output Capacitance
Min.
5.0
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
Typ.
–––
19
5.5
9.4
8.0
26
12
11
620
130
38
780
62
110
Max. Units
Conditions
–––
S
VDS = 50V, ID = 8.3A
29
ID = 8.3A
8.2
nC
VDS = 120V
14
VGS = 10V, „
–––
VDD = 75V
–––
ID = 8.3A
ns
–––
RG = 11Ω
–––
VGS = 10V „
–––
VGS = 0V
–––
VDS = 25V
–––
pF
ƒ = 1.0MHz
–––
VGS = 0V, VDS = 1.0V, ƒ = 1.0MHz
–––
VGS = 0V, VDS = 120V, ƒ = 1.0MHz
–––
VGS = 0V, VDS = 0V to 120V …
Avalanche Characteristics
Parameter
EAS
IAR
EAR
Single Pulse Avalanche Energy‚
Avalanche Current
Repetitive Avalanche Energy
Typ.
Max.
Units
–––
–––
–––
130
8.3
8.6
mJ
A
mJ
Typ.
Max.
Units
–––
–––
–––
1.75
50
110
°C/W
Thermal Resistance
Parameter
RθJC
RθJA
RθJA
Junction-to-Case
Junction-to-Ambient (PCB mount)*
Junction-to-Ambient
Diode Characteristics
IS
ISM
VSD
trr
Qrr
ton
2 / 10
Parameter
Continuous Source Current
(Body Diode)
Pulsed Source Current
(Body Diode) 
Diode Forward Voltage
Reverse Recovery Time
Reverse RecoveryCharge
Forward Turn-On Time
Min. Typ. Max. Units
Conditions
D
MOSFET symbol
14
––– –––
showing the
A
G
integral reverse
56
––– –––
S
p-n junction diode.
––– ––– 1.3
V
TJ = 25°C, IS = 8.3A, VGS = 0V „
––– 110 –––
ns
TJ = 25°C, IF = 8.3A
––– 520 –––
nC
di/dt = 100A/µs „
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
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IRFR/U13N15D
100
100
VGS
15V
12V
10V
8.0V
7.0V
6.0V
5.5V
BOTTOM 5.0V
VGS
15V
12V
10V
8.0V
7.0V
6.0V
5.5V
BOTTOM 5.0V
TOP
10
I D , Drain-to-Source Current (A)
I D , Drain-to-Source Current (A)
TOP
1
5.0V
0.1
10
5.0V
1
20µs PULSE WIDTH
TJ = 25 °C
0.01
0.1
1
10
100
0.1
0.1
VDS , Drain-to-Source Voltage (V)
TJ = 175 ° C
10
TJ = 25 ° C
1
V DS = 50V
20µs PULSE WIDTH
6
7
8
9
10
Fig 3. Typical Transfer Characteristics
3 / 10
RDS(on) , Drain-to-Source On Resistance
(Normalized)
I D , Drain-to-Source Current (A)
3.0
VGS , Gate-to-Source Voltage (V)
10
100
Fig 2. Typical Output Characteristics
100
5
1
VDS , Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
0.1
20µs PULSE WIDTH
TJ = 175 °C
11
ID = 14A
2.5
2.0
1.5
1.0
0.5
0.0
-60 -40 -20
VGS = 10V
0
20 40 60 80 100 120 140 160 180
TJ , Junction Temperature ( °C)
Fig 4. Normalized On-Resistance
Vs. Temperature
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IRFR/U13N15D
VGS = 0V,
f = 1 MHZ
Ciss = Cgs + Cgd , Cds SHORTED
Crss = Cgd
C, Capacitance(pF)
Coss = Cds + Cgd
1000
Ciss
Coss
100
Crss
VGS , Gate-to-Source Voltage (V)
20
10000
ID = 8.3A
VDS = 120V
VDS = 75V
VDS = 30V
16
12
8
4
FOR TEST CIRCUIT
SEE FIGURE 13
10
1
10
100
1000
0
0
VDS , Drain-to-Source Voltage (V)
5
10
15
20
25
30
Q G , Total Gate Charge (nC)
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
1000
100
TJ = 175 ° C
100
I D , Drain Current (A)
ISD , Reverse Drain Current (A)
OPERATION IN THIS AREA LIMITED
BY RDS(on)
10
TJ = 25 ° C
1
10
100us
1ms
1
0.1
0.2
V GS = 0 V
0.4
0.6
0.8
1.0
1.2
VSD ,Source-to-Drain Voltage (V)
Fig 7. Typical Source-Drain Diode
Forward Voltage
4 / 10
10us
1.4
10ms
TC = 25 ° C
TJ = 175 ° C
Single Pulse
0.1
1
10
100
VDS , Drain-to-Source Voltage (V)
Fig 8. Maximum Safe Operating Area
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1000
IRFR/U13N15D
14
VDS
VGS
12
RD
D.U.T.
I D , Drain Current (A)
RG
+
-VDD
10
VGS
8
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
6
Fig 10a. Switching Time Test Circuit
4
VDS
2
90%
0
25
50
75
100
125
TC , Case Temperature
150
175
( °C)
10%
VGS
Fig 9. Maximum Drain Current Vs.
Case Temperature
td(on)
tr
t d(off)
tf
Fig 10b. Switching Time Waveforms
Thermal Response (Z thJC )
10
1
D = 0.50
0.20
0.10
P DM
0.05
0.1
0.01
0.00001
0.02
0.01
SINGLE PULSE
(THERMAL RESPONSE)
t1
t2
Notes:
1. Duty factor D = t 1 / t 2
2. Peak T J = P DM x Z thJC + TC
0.0001
0.001
0.01
t1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
5 / 10
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0.1
IRFR/U13N15D
240
D R IV E R
L
VDS
D .U .T
RG
+
V
- DD
IA S
20V
A
0 .0 1 Ω
tp
Fig 12a. Unclamped Inductive Test Circuit
V (B R )D SS
tp
EAS , Single Pulse Avalanche Energy (mJ)
1 5V
TOP
200
BOTTOM
ID
3.4A
5.9A
8.3A
160
120
80
40
0
25
50
75
100
125
150
Starting TJ , Junction Temperature ( °C)
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
IAS
Fig 12b. Unclamped Inductive Waveforms
Current Regulator
Same Type as D.U.T.
QG
50KΩ
12V
.2µF
.3µF
QGS
QGD
D.U.T.
VG
+
V
- DS
VGS
3mA
Charge
Fig 13a. Basic Gate Charge Waveform
6 / 10
IG
ID
Current Sampling Resistors
Fig 13b. Gate Charge Test Circuit
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175
IRFR/U13N15D
Peak Diode Recovery dv/dt Test Circuit
+
D.U.T
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
ƒ
+
‚
-
-
„
+

•
•
•
•
RG
dv/dt controlled by RG
Driver same type as D.U.T.
ISD controlled by Duty Factor "D"
D.U.T. - Device Under Test
Driver Gate Drive
P.W.
D=
Period
+
-
VDD
P.W.
Period
VGS=10V
*
D.U.T. ISD Waveform
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
Body Diode
VDD
Forward Drop
Inductor Curent
Ripple ≤ 5%
ISD
* VGS = 5V for Logic Level Devices
Fig 14. For N-Channel HEXFET® Power MOSFETs
7 / 10
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IRFR/U13N15D
D-Pak (TO-252AA) Tape & Reel Information
Dimensions are shown in millimeters (inches)
TR
TRR
16.3 ( .641 )
15.7 ( .619 )
12.1 ( .47 6 )
11.9 ( .46 9 )
F E E D D IR E C T IO N
TRL
16 .3 ( .641 )
15 .7 ( .619 )
8.1 ( .318 )
7.9 ( .312 )
FE E D D IR E C T IO N
N O T ES :
1 . C O N T R O LLIN G D IME N S IO N : M ILL IM ET E R .
2 . A LL D IM EN S IO N S A R E SH O W N IN M ILLIM ET E R S ( IN C H E S ).
3 . O U TL IN E C O N FO R MS T O E IA -481 & E IA -54 1.
1 3 IN C H
16 m m
N O TE S :
1. O U TL IN E C O N F O R M S T O E IA -481 .
Notes:
 Repetitive rating; pulse width limited by
max. junction temperature.
‚ Starting TJ = 25°C, L = 3.8mH
RG = 25Ω, IAS = 8.3A.
„ Pulse width ≤ 300µs; duty cycle ≤ 2%.
… Coss eff. is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS
ƒ ISD ≤ 8.3A, di/dt ≤ 280A/µs, VDD ≤ V(BR)DSS,
TJ ≤ 175°C
10 / 10
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