AOC2800 Common-Drain Dual N-Channel Enhancement Mode Field Effect Transistor General Description The AOC2800 uses advanced trench technology to provide excellent RSS(ON) , low gate charge and operation with gate voltages as low as 2.5V while retaining a 12V VGS(MAX) rating.It is ESD protected. This device is suitable for use as a unidirectional or bi-directional load switch, facilitated by its common-drain configuration. Features Vss 30V ID (at VGS=4.5V) 6A RSS(ON) (at VGS=4.5V) < 42mΩ RSS(ON) (at VGS=4.0V) < 44mΩ RSS(ON) (at VGS=3.1V) < 49mΩ RSS(ON) (at VGS=2.5V) < 61mΩ WLCSP 1.57x1.57_4 Equivalent Circuit Bottom View G2 G1 S2 G1 G2 Pin1(S1) S1 S2 S1 Absolute Maximum Ratings TA=25°C unless otherwise noted Parameter Symbol Source-Source Voltage VSS Gate-Source Voltage Source Current (DC) VGS Note1 TA=25°C Source Current (Pulse) Note2 Power Dissipation Note1 TA=25°C Junction and Storage Temperature Range Note 1. Mounted on minimum pad PCB Note 2. PW <300 µs pulses, duty cycle 0.5% max 1/5 D2 D1 Top View Maximum 30 Units V ±12 V IS 6 ISM 60 PD 1.3 TJ, TSTG A W -55 to 150 °C www.freescale.net.cn AOC2800 Common-Drain Dual N-Channel Enhancement Mode Field Effect Transistor Electrical Characteristics (TJ=25°C unless otherwise noted) Parameter Symbol STATIC PARAMETERS BVSSS Source-Source Breakdown Voltage Conditions Min IS=250µA, VGS=0V, Test Circuit 6 Units V 1 Zero Gate Voltage Source Current IGSS Gate leakage current VSS=0V, VGS= ±10V, Test Circuit 2 BVGSO Gate-Source Breakdown Voltage VSS=0V, IG=±250µA, Test Circuit 7 ±12 VGS(th) Gate Threshold Voltage VSS=VGS IS=250µA, Test Circuit 3 0.5 TJ=55°C µA 5 VGS=4.5V, IS=3A, Test Circuit 4 1 10 1 1.5 V 35 42 53 63 VGS=4.0V, IS=3A, Test Circuit 4 37 44 VGS=3.1V, IS=3A, Test Circuit 4 41 49 61 TJ=125°C Static Source to Source On-Resistance Note Max 30 VSS=20V, VGS=0V, Test Circuit 1 ISSS RSS(ON) Typ VGS=2.5V, IS=3A, Test Circuit 4 49 gFS Forward Transconductance Note VSS=5V, IS=3A, Test Circuit 3 21 VFSS Diode Forward Voltage Note IS=1A,VGS=0V, Test Circuit 5 0.7 1 984 1180 DYNAMIC PARAMETERS Ciss Input Capacitance V mΩ S V pF VGS=0V, VSS=15V, f=1MHz, 93 57 pF VGS=0V, VSS=0V, f=1MHz 1.5 kΩ SWITCHING PARAMETERS tD(on) Turn-On DelayTime 320 ns tr Turn-On Rise Time 800 ns tD(off) Turn-Off DelayTime 3.8 µs tf Turn-Off Fall Time Coss Output Capacitance Crss Reverse Transfer Capacitance Rg Gate resistance Qg Total Gate Charge Note: Pulsed VGS=10V, VSS=15V, RL=2.4Ω, RGEN=6Ω , VG1S1=4.5V, VSS=15V, IS=6A 3.6 µs 9.1 nC THIS PRODUCT HAS BEEN DESIGNED AND QUALIFIED FOR THE CONSUMER MARKET. APPLICATIONS OR USES AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS ARE NOT AUTHORIZED. AOS DOES NOT ASSUME ANY LIABILITY ARISING OUT OF SUCH APPLICATIONS OR USES OF ITS PRODUCTS. AOS RESERVES THE RIGHT TO IMPROVE PRODUCT DESIGN, FUNCTIONS AND RELIABILITY WITHOUT NOTICE 2/5 pF www.freescale.net.cn AOC2800 Common-Drain Dual N-Channel Enhancement Mode Field Effect Transistor TYPICAL ELECTRICAL AND THERMAL CHARACTERISTICS 60 20 4.5V 3V 4V 3.5V 50 VSS=5V 16 40 12 IS(A) IS (A) 2.5V 30 20 125°C 8 VGS=2V 25°C 75°C 10 4 -25°C 0 0 1 2 3 4 5 0 1 VSS (Volts) Fig 1: On-Region Characteristics 1.25 1.5 1.75 75 2.25 2.5 1.6 VGS=4V Normalized On-Resistance 70 65 RSS(ON) (mΩ Ω) 2 VGS(Volts) Figure 2: Transfer Characteristics 60 VGS=2.5V 55 VGS=3.1 50 45 VGS=4V 40 VGS=4.5V 1.4 VGS=3.1V 1.2 VGS=2.5V 1 VGS=4.5V 35 30 0 5 10 15 0.8 20 0 IS (A) Figure 3: On-Resistance vs. Drain Current and Gate Voltage 25 50 75 100 125 150 175 Temperature (°C) Figure 4: On-Resistance vs. Junction Temperature 1.0E+01 100 IS=3A 90 1.0E+00 80 1.0E-01 60 125°C IS (A) RSS(ON) (mΩ Ω) 70 50 75°C 1.0E-03 25°C 40 1.0E-04 25°C 30 -25°C 1.0E-05 20 10 0 2 4 6 8 10 12 VGS (Volts) Figure 5: On-Resistance vs. Gate-Source Voltage 3/5 125°C 1.0E-02 1.0E-06 0.0 0.5 1.0 1.5 2.0 2.5 VSS (Volts) Figure 6: Body-Diode Characteristics www.freescale.net.cn AOC2800 Common-Drain Dual N-Channel Enhancement Mode Field Effect Transistor TYPICAL ELECTRICAL AND THERMAL CHARACTERISTICS 1400 6 VSS=15V IS=6A 5 1200 Capacitance (pF) VGS (Volts) 4 3 2 1000 Ciss 800 600 Coss 400 Crss 1 200 0 0 2 4 6 8 10 12 0 14 0 Qg (nC) Figure 7: Gate-Charge Characteristics 5 10 15 20 25 30 VSS (Volts) Figure 8: Capacitance Characteristics 50 100.0 TJ(Max)=150°C TA=25°C 10µs 40 RSS(ON) limited 100µs 1ms 1.0 DC 10ms 0.0 0.01 0.1 30 20 100ms TJ(Max)=150°C TA=25°C 0.1 Power (W) IS (Amps) 10.0 10 1s 1 10 0 0.001 100 VSS (Volts) Figure 9: Maximum Forward Biased Safe Operating Area (Note E) 0.01 0.1 1 10 100 1000 Pulse Width (s) Figure 10: Single Pulse Power Rating Junction-toAmbient (Note E) Zθ JA Normalized Transient Thermal Resistance 10 In descending order D=0.5, 0.3, 0.1, 0.05, 0.02, 0.01, single pulse D=Ton/(Ton+T) TJ,PK=TA+PD.ZθJA.RθJA RθJA=100°C/W 1 0.1 PD Single Pulse 0.01 0.00001 0.0001 0.001 0.01 Ton 0.1 1 10 T 100 1000 Pulse Width (s) Figure 11: Normalized Maximum Transient Thermal Impedance 4/5 www.freescale.net.cn AOC2800 Common-Drain Dual N-Channel Enhancement Mode Field Effect Transistor TEST CIRCUIT 1 Isss TEST CIRCUIT 2 Igss1,2 POSITIVE VSS FOR ISSS+ POSITIVE VGS FOR IGSS1+ S2 NEGATIVE VSS FOR ISSS- S2 NEGATIVE VGS FOR IGSS1When FET1 is measured between GATE and SOURCE A G2 G2 of FET2 are shorted D2 D2 D1 D1 VSS G1 G1 A VG S1 TEST CIRCUIT 3 Vgs (off ) S1 TEST CIRCUIT 4 Rss (on ) S2 S2 When FET1 is measured Vss/Is between GATE and SOURCE of FET2 are shorted G2 A G2 Is D2 D2 D1 D1 VSS G1 V G1 VSS VGS VGS S1 TEST CIRCUIT 5 V TEST CIRCUIT 6 BV F(SS)1,2 S1 DSS POSITIVE VSS FOR ISSS+ NEGATIVE VSS FOR ISSS- S2 S2 4.5V When FET1 measured G2 G2 IF FET2 VGS=4.5V Is D2 D2 D1 D1 V G1 V G1 VSS VGS=0 S1 TEST CIRCUIT 7 BV S1 GSO1,2 POSITIVE VSS FOR ISSS+ NEGATIVE VSS FOR ISSS- S2 When FET1 is measured between GATE and SOURCE G2 of FET2 are shorted D2 D1 G1 V IG 5/5 S1 www.freescale.net.cn