July 20, 2009 54ACT112 Dual JK Negative Edge-Triggered Flip-Flop General Description The 'ACT112 contains two independent, high-speed JK flipflops with Direct Set and Clear inputs. Synchronous state changes are initiated by the falling edge of the clock. Triggering occurs at a voltage level of the clock and is not directly related to the transition time. The J and K inputs can change when the clock is in either state without affecting the flip-flop, provided that they are in the desired state during the recommended setup and hold times relative to the falling edge of the clock. A LOW signal on SD or CD prevents clocking and forces Q or Q HIGH, respectively. Simultaneous LOW signals on SD and CD force both Q and Q HIGH. Asynchronous Inputs: Connection Diagrams LOW input to SD sets Q to HIGH level LOW input to CD sets Q to LOW level Clear and Set are independent of clock Simultaneous LOW on CD and SD makes both Q and Q HIGH Features ■ 'ACT112 has TTL-compatible inputs ■ Outputs source/sink 24 mA ■ Standard Microcircuit Drawing (SMD) 5962-8995001 Pin Descriptions Pin Names Pin Assigment for DIP and Flatpack Description J1, J2, K1, K2 Data Inputs CP1, CP2 CD1, CD2 Clock Pulse Inputs (Active Falling Edge) Direct Clear Inputs (Active LOW) SD1, SD2 Direct Set Inputs (Active LOW) Q1, Q2, Q1, Q2 Outputs 10097603 Pin Assigment for LCC 10097605 FACT™ is a trademark of Fairchild Semiconductor © 2009 National Semiconductor Corporation 100976 100976 Version 2 Revision 2 www.national.com Print Date/Time: 2009/07/20 16:20:36 54ACT112 Dual JK Negative Edge-Triggered Flip-Flop OBSOLETE 54ACT112 Logic Symbols IEEE/IEC 10097601 10097604 10097602 Truth Table Inputs Outputs SD CD CP J K Q Q L H L H H L L H X X X M X X X h X X X h H L H Q0 L H H Q0 H H H H H H M M M l h l h l l L H Q0 H L Q0 H (h) = HIGH Voltage Level L (l) = LOW Voltage Level X = Immaterial M = HIGH-to-LOW Clock Transition Q0 (Q0) = Before HIGH-to-LOW Transition of Clock Lower case letters indicate the state of the referenced input or output one setup time prior to the HIGH-to-LOW clock transition. www.national.com 2 100976 Version 2 Revision 2 Print Date/Time: 2009/07/20 16:20:36 54ACT112 Logic Diagram (One Half Shown) 10097606 3 100976 Version 2 Revision 2 Print Date/Time: 2009/07/20 16:20:36 www.national.com 54ACT112 Absolute Maximum Ratings (Note 1) Recommended Operating Conditions If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) DC Input Diode Current (IIK) VI = −0.5V VI = VCC + 0.5V DC Input Voltage (VI) DC Output Diode Current (IOK) VO = −0.5V VO = VCC + O.5 DC Output Voltage (VO) DC Output Source or Sink Current (IO) DC VCC or Ground Current per Output Pin (ICC or IGND) Storage Temperature (TSTG) Junction Temperature (TJ) CDIP Supply Voltage (VCC) Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) −0.5V to +7.0V −20 mA +20 mA −0.5V to VCC + 0.5V 4.5V to 5.5V 0V to VCC 0V to VCC −55°C to +125°C Minimum Input Edge Rate (ΔV/Δt) VIN from 0.8V to 2.0V VCC @ 4.5V, 5.5V 125 mV/ns Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACT™ circuits outside databook specifications. −20 mA +20 mA −0.5V to VCC +0.5V ±50 mA ±50 mA −65°C to +150°C 175°C DC Characteristics for 'ACT Family Devices Symbol VIH VIL VOH Parameter VCC TA = −55°C to +125°C (V) Guaranteed Limits Minimum High Level 4.5 2.0 Input Voltage 5.5 2.0 Maximum Low Level 4.5 0.8 Input Voltage 5.5 0.8 Minimum High Level 4.5 4.4 Output Voltage 5.5 5.4 4.5 3.70 5.5 4.70 Maximum Low Level 4.5 0.1 Output Voltage 5.5 0.1 4.5 0.5 5.5 0.5 Units V Conditions VOUT = 0.1V or VCC − 0.1V V VOUT = 0.1V or VCC − 0.1V V IOUT = −50 μA VIN = VIL or VIH V IOH = −24 mA IOH = −24 mA (Note 2) VOL V IOUT = 50 μA VIN = VIL or VIH V IOL = 24 MA IOL = 24 mA (Note 2) IIN Maximum Input Leakage Current 5.5 ± 1.0 μA VI = VCC, GND ICCT Maximum ICC/Input 5.5 1.6 mA VI = VCC − 2.1V IOLD Minimum Dynamic 5.5 50 mA VOLD = 1.65V Max IOHD Output Current(Note 3) 5.5 −50 mA VOHD = 3.85V Min ICC Maximum Quiescent Supply Current 5.5 80.0 μA VIN = VCC or GND Note 2: All outputs loaded; thresholds on input associated with output under test. Note 3: Maximum test duration 2.0 ms, one output loaded at a time. www.national.com 4 100976 Version 2 Revision 2 Print Date/Time: 2009/07/20 16:20:36 Symbol fmax Parameter VCC TA = −55°C to +125°C (V) CL = 50 pF Units (Note 4) Min 5.0 80 5.0 1.0 14.0 ns 5.0 1.0 14.0 ns 5.0 1.0 13.5 ns 5.0 1.0 13.5 ns Maximum Clock Fig. No. Max MHz Frequency tPLH Propagation Delay CPn to Qn or Qn tPHL Propagation Delay CPn to Qn or Qn tPLH Propagation Delay CDn or SDn to Qn or Qn tPHL Propagation Delay CDn or SDn to Qn or Qn Note 4: Voltage Range 5.0 is 5.0V ±0.5V AC Operating Requirements: Symbol tS Parameter VCC TA = −55°C to +125°C (V) CL = 50 pF (Note 5) Guaranteed Minimum 5.0 8.0 ns 5.0 1.5 ns 5.0 5.0 ns 5.0 3.0 ns Setup Time, HIGH or LOW Units Fig. No. Jn or Kn to CPn tH Hold Time, HIGH or LOW Jn or Kn to CPn tW Pulse Width CPn or CDn or SDn trec Recovery Time CDn or SDn to CPn Note 5: Voltage Range 5.0 is 5.0V ±0.5V Capacitance Symbol Parameter CIN Input Capacitance CPD Power Dissipation Capacitance Max Units 10.0 pF VCC = OPEN 60 pF VCC = 5.0V 5 100976 Version 2 Revision 2 Print Date/Time: 2009/07/20 16:20:36 Conditions www.national.com 54ACT112 AC Electrical Characteristics for 'ACT Family Devices 54ACT112 Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Ceramic Dual-in-line Package Number J16A 16-Lead Cerpack Package Number W16A www.national.com 6 100976 Version 2 Revision 2 Print Date/Time: 2009/07/20 16:20:36 54ACT112 20-Lead Ceramic Leadless Chip Carrier Package Number E20A 7 100976 Version 2 Revision 2 Print Date/Time: 2009/07/20 16:20:36 www.national.com 54ACT112 Dual JK Negative Edge-Triggered Flip-Flop Notes For more National Semiconductor product information and proven design tools, visit the following Web sites at: Products Design Support Amplifiers www.national.com/amplifiers WEBENCH® Tools www.national.com/webench Audio www.national.com/audio App Notes www.national.com/appnotes Clock and Timing www.national.com/timing Reference Designs www.national.com/refdesigns Data Converters www.national.com/adc Samples www.national.com/samples Interface www.national.com/interface Eval Boards www.national.com/evalboards LVDS www.national.com/lvds Packaging www.national.com/packaging Power Management www.national.com/power Green Compliance www.national.com/quality/green Switching Regulators www.national.com/switchers Distributors www.national.com/contacts LDOs www.national.com/ldo Quality and Reliability www.national.com/quality LED Lighting www.national.com/led Feedback/Support www.national.com/feedback Voltage Reference www.national.com/vref Design Made Easy www.national.com/easy www.national.com/powerwise Solutions www.national.com/solutions Mil/Aero www.national.com/milaero PowerWise® Solutions Serial Digital Interface (SDI) www.national.com/sdi Temperature Sensors www.national.com/tempsensors SolarMagic™ www.national.com/solarmagic Wireless (PLL/VCO) www.national.com/wireless www.national.com/training PowerWise® Design University THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION (“NATIONAL”) PRODUCTS. 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