NSC 54AC273F

General Description
Features
The ’273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock
(CP) and Master Reset (MR) input load and reset (clear) all
flip-flops simultaneously.
The register is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop’s Q output.
All outputs will be forced LOW independently of Clock or
Data inputs by a LOW voltage level on the MR input. The device is useful for applications where the true output only is required and the Clock and Master Reset are common to all
storage elements.
n
n
n
n
n
n
n
n
n
n
Ideal buffer for microprocessor or memory
Eight edge-triggered D flip-flops
Buffered common clock
Buffered, asynchronous master reset
See ’377 for clock enable version
See ’373 for transparent latch version
See ’374 for TRI-STATE ® version
Outputs source/sink 24 mA
’ACT has TTL-compatible inputs
Standard Military Drawing (SMD)
— ’AC273: 5962-87756
54AC273
54AC273
Octal D Flip-Flop
54AC273 Octal D Flip-Flop
July 1998
Logic Symbols
IEEE/IEC
DS100288-1
DS100288-2
Pin Names
Description
D0–D7
Data Inputs
MR
Master Reset
CP
Clock Pulse Input
Q0–Q7
Data Outputs
TRI-STATE ® is a registered trademark of National Semiconductor Corporation.
FACT™ is a trademark of National Semiconductor Corporation.
© 1998 National Semiconductor Corporation
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DS100288
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Connection Diagrams
Pin Assignment
for DIP and Flatpak
Pin Assignment
for LCC
DS100288-3
DS100288-4
Mode Select-Function Table
Operating Mode
Inputs
Outputs
MR
CP
Dn
Reset (Clear)
L
X
X
L
Load ‘1’
H
N
H
H
Load ‘0’
H
N
L
L
Qn
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
N = LOW-to-HIGH Transition
Logic Diagram
DS100288-5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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Absolute Maximum Ratings (Note 1)
Junction Temperature (TJ)
CDIP
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (VCC)
DC Input Diode Current (IIK)
VI = −0.5V
VI = VCC + 0.5V
DC Input Voltage (VI)
DC Output Diode Current (IOK)
VO = −0.5V
VO = VCC + 0.5V
DC Output Voltage (VO)
DC Output Source
or Sink Current (IO)
DC VCC or Ground Current
per Output Pin (ICC or IGND)
Storage Temperature (TSTG)
175˚C
Recommended Operating
Conditions
−0.5V to +7.0V
Supply Voltage (VCC)
’AC
Input Voltage (VI)
Output Voltage (VO)
Operating Temperature (TA)
54AC
Minimum Input Edge Rate (∆V/∆t)
’AC Devices
VIN from 30% to 70% of VCC
VCC @ 3.3V, 4.5V, 5.5V
−20 mA
+20 mA
−0.5V to VCC + 0.5V
−20 mA
+20 mA
−0.5V to to VCC + 0.5V
± 50 mA
2.0V to 6.0V
0V to VCC
0V to VCC
−55˚C to +125˚C
125 mV/ns
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
exception, to ensure that the system design is reliable over its power supply,
temperature, and output/input loading variables. National does not recommend operation of FACT™ circuits outside databook specifications.
± 50 mA
−65˚C to +150˚C
DC Characteristics for ’AC Family Devices
Symbol
Parameter
VCC
54AC
TA =
(V)
−55˚C to +125˚C
Units
Conditions
Guaranteed
Limits
VIH
VIL
VOH
VOL
IIN
Minimum High Level
3.0
2.1
Input Voltage
4.5
3.15
5.5
3.85
Maximum Low Level
3.0
0.9
Input Voltage
4.5
1.35
5.5
1.65
Minimum High Level
3.0
2.9
Output Voltage
4.5
4.4
5.5
5.4
3.0
2.4
4.5
3.7
5.5
4.7
Maximum Low Level
3.0
0.1
Output Voltage
4.5
0.1
5.5
0.1
Maximum Input
VOUT = 0.1V
V
or VCC − 0.1V
V
or VCC − 0.1V
VOUT = 0.1V
IOUT = −50 µA
V
(Note 2)
VIN = VIL or VIH
IOH = −12 mA
V
IOH = −24 mA
IOH = −24 mA
IOUT = 50 µA
V
(Note 2)
VIN = VIL or VIH
IOL = 12 mA
3.0
0.50
4.5
0.50
5.5
0.50
5.5
± 1.0
µA
IOL = 24 mA
IOL = 24 mA
VI = VCC, GND
5.5
50
mA
VOLD = 1.65V Max
5.5
−50
mA
VOHD = 3.85V Min
V
Leakage Current
IOLD
IOHD
(Note 3)
Minimum Dynamic
Output Current
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DC Characteristics for ’AC Family Devices
Symbol
Parameter
(Continued)
VCC
54AC
TA =
(V)
−55˚C to +125˚C
Units
Conditions
Guaranteed
Limits
ICC
Maximum Quiescent
5.5
80.0
VIN = VCC
µA
Supply Current
or GND
Note 2: All outputs loaded; thresholds on input associated with output under test.
Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
Note 4: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC.
ICC for 54AC @ 25˚C is identical to 74AC @ 25˚C.
AC Electrical Characteristics
54AC
TA = −55˚C
VCC
Symbol
Parameter
(V)
to +125˚C
CL = 50 pF
(Note 5)
Min
fmax
tPLH
tPHL
tPHL
Fig.
Units
No.
Max
Maximum Clock
3.3
75
Frequency
5.0
90
MHz
Propagation Delay
3.3
1.0
15.0
Clock to Output
5.0
1.0
11.0
Propagation Delay
3.3
1.0
16.0
Clock to Output
5.0
1.0
11.5
Propagation Delay
3.3
1.0
16.0
MR to Output
5.0
1.0
11.5
ns
ns
ns
Note 5: Voltage Range 3.3 is 3.3V ± 0.3V. Voltage Range 5.0 is 5.0V ± 0.5V
AC Operating Requirements
54AC
TA = −55˚C
VCC
Symbol
Parameter
(V)
to +125˚C
CL = 50 pF
(Note 6)
Fig.
Units
No.
Guaranteed
Minimum
ts
th
tw
tw
trec
Setup Time, HIGH or LOW
3.3
8.0
Data to CP
5.0
5.0
Hold Time, HIGH or LOW
3.3
0
Data to CP
5.0
1.0
Clock Pulse Width
3.3
6.5
HIGH or LOW
5.0
5.0
MR Pulse Width
3.3
10.0
HIGH or LOW
5.0
6.5
Recovery Time
3.3
6.0
MR to CP
5.0
4.0
ns
ns
ns
ns
ns
Note 6: Voltage Range 3.3 is 3.3V ± 0.3V. Voltage Range 5.0 is 5.0V ± 0.5V
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Capacitance
Symbol
CIN
CPD
Typ
Units
Input Capacitance
Parameter
4.5
pF
Power Dissipation
50.0
pF
Conditions
VCC = Open
VCC = 5.0V
Capacitance
Book
Extract
End
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THIS PAGE IS IGNORED IN THE DATABOOK
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Physical Dimensions
inches (millimeters) unless otherwise noted
20 Terminal Ceramic Leadless Chip Carrier (L)
NS Package Number E20A
20 Lead Ceramic Dual-In-Line Package (D)
NS Package Number J20A
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54AC273 Octal D Flip-Flop
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
20 Lead Ceramic Flatpak (F)
NS Package Number W20A
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2. A critical component in any component of a life support
1. Life support devices or systems are devices or sysdevice or system whose failure to perform can be reatems which, (a) are intended for surgical implant into
sonably expected to cause the failure of the life support
the body, or (b) support or sustain life, and whose faildevice or system, or to affect its safety or effectiveness.
ure to perform when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
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National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
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