Standard Products UT54LVDSC031 Quad Driver Data Sheet April 2, 2001 FEATURES INTRODUCTION q q q q q q q q q The UT54LVDSC031 Quad Driver is a quad CMOS differential line driver designed for applications requiring ultra low power dissipation and high data rates. The device is designed to support data rates in excess of 155.5 Mbps (77.7 MHz) utilizing Low Voltage Differential Signaling (LVDS) technology. q q q q >155.5 Mbps (77.7 MHz) switching rates +340mV nominal differential signaling 5 V power supply Cold Spare LVDS outputs TTL compatible inputs Ultra low power CMOS technology 5.0ns maximum, propagation delay 3.0ns maximum, differential skew Radiation-hardened design; total dose irradiation testing to MIL-STD-883 Method 1019 - Total-dose: 300 krad(Si) - Latchup immune (LET > 111 MeV-cm2/mg) Packaging options: - 16-lead flatpack (dual in-line) Standard Microcircuit Drawing 5962-95833 - QML Q and V compliant part Compatible with IEEE 1596.3SCI LVDS Compatible with ANSI/TIA/EIA 644-1996 LVDS Standard DIN1 The UT54LVDSC031 accepts TTL input levels and translates them to low voltage (340mV) differential output signals. In addition, the driver supports a three-state function that may be used to disable the output stage, disabling the load current, and thus dropping the device to an ultra low idle power state. The UT54LVDSC031 and companion quad line receiver UT54LVDSC032 provide new alternatives to high power pseudo-ECL devices for high speed point-to-point interface applications. All LVDS pins have Cold Spare buffers. These buffers will be high impedance when VDD is tied to VSS. DOUT1+ D1 DOUT1- DIN2 DOUT2+ D2 DOUT2- DIN3 DOUT3+ D3 DOUT3- DIN4 DOUT4+ D4 DOUT4- EN EN Figure 1. UT54LVDSC031 Quad Driver Block Diagram APPLICATIONS INFORMATION DIN1 1 16 DOUT1+ 2 3 15 DOUT1EN 4 5 UT54LVDSC031 Driver VDD DIN4 14 DOUT4+ DOUT4EN DOUT2+ 6 13 12 11 DIN2 7 10 DOUT3+ VSS 8 9 DIN3 DOUT2- The UT54LVDSC031 driver’s intended use is primarily in an uncomplicated point-to-point configuration as is shown in Figure 3. This configuration provides a clean signaling environment for quick edge rates of the drivers. The receiver is connected to the driver through a balanced media such as a standard twisted pair cable, a parallel pair cable, or simply PCB traces. Typically, the characteristic impedance of the media is in the range of 100Ω. A termination resistor of 100Ω should be selected to match the media and is located as close to the receiver input pins as possible. The termination resistor converts the current sourced by the driver into voltages that are detected by the receiver. Other configurations are possible such as a multireceiver configuration, but the effects of a mid-stream connector(s), cable stub(s), and other impedance discontinuities, as well as ground shifting, noise margin limits, and total termination loading must be taken into account. D OUT3- Figure 2. UT54LVDSC031 Pinout TRUTH TABLE ENABLE Enables Input Output EN EN DIN DOUT+ DOUT- L H X Z Z L L H H H L All other combinations of ENABLE inputs DATA INPUT 1/4 UT54LVDSC031 RT 100Ω + - 1/4 UT54LVDSC031 DATA OUTPUT Figure 3. Point-to-Point Application PIN DESCRIPTION Pin No. Name Description 1, 7, 9, 15 DIN Driver input pin, TTL/CMOS compatible 2, 6, 10, 14 DOUT+ Non-inverting driver output pin, LVDS levels 3, 5, 11, 13 DOUT- Inverting driver output pin, LVDS levels 4 EN Active high enable pin, OR-ed with EN 12 EN Active low enable pin, OR-ed with EN 16 VDD Power supply pin, +5V + 10% 8 VSS Ground pin The UT54LVDSC031 differential line driver is a balanced current source design. A current mode driver, has a high output impedance and supplies a constant current for a range of loads (a voltage mode driver on the other hand supplies a constant voltage for a range of loads). Current is switched through the load in one direction to produce a logic state and in the other direction to produce the other logic state. The current mode requires (as discussed above) that a resistive termination be employed to terminate the signal and to complete the loop as shown in Figure 3. AC or unterminated configurations are not allowed. The 3.4mA loop current will develop a differential voltage of 340mV across the 100Ω termination resistor which the receiver detects with a 240mV minimum differential noise margin neglecting resistive line losses (driven signal minus receiver threshold (340mV - 100mV = 240mV)). The signal is centered around +1.2V (Driver Offset, V OS) with respect to ground as shown in Figure 4. Note: The steady-state voltage (V SS) peak-to-peak swing is twice the differential voltage (VOD) and is typically 680mV. 2 The current mode driver provides substantial benefits over voltage mode drivers, such as an RS-422 driver. Its quiescent current remains relatively flat versus switching frequency. Whereas the RS-422 voltage mode driver increases exponentially in most cases between 20 MHz - 50 MHz. This is due to the overlap current that flows between the rails of the device when the internal gates switch. Whereas the current mode driver switches a fixed current between its output without any substantial overlap current. This is similar to some ECL and PECL devices, but without the heavy static I CC requirements of the ECL/PECL design. LVDS requires 80% less current than similar PECL devices. AC specifications for the driver are a tenfold improvement over other existing RS-422 drivers. 3V DIN 0V DOUT- VOH VOS V0D SINGLE-ENDED VOL DOUT+ +VOD 0V (DIFF.) 0V VSS -VOD The Three-State function allows the driver outputs to be disabled, thus obtaining an even lower power state when the transmission of data is not required. DOUT+ - DOUTDIFFERENTIAL OUTPUT Note: The footprint of the UT54LVDSC031 is the same as the industry standard Quad Differential (RS-422) Driver. Figure 4. Driver Output Levels 3 ABSOLUTE MAXIMUM RATINGS 1 (Referenced to V SS) SYMBOL PARAMETER LIMITS VDD DC supply voltage -0.3 to 6.0V VI/O Voltage on any pin -0.3 to (VDD + 0.3V) TSTG Storage temperature -65 to +150°C PD Maximum power dissipation 1.25 W TJ Maximum junction temperature2 +150°C Thermal resistance, junction-to-case 3 10°C/W DC input current ±10mA ΘJC II Notes: 1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability and performance. 2. Maximum junction temperature may be increased to +175°C during burn-in and steady-static life. 3. Test per MIL-STD-883, Method 1012. RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER LIMITS VDD Positive supply voltage 4.5 to 5.5V TC Case temperature range -55 to +125°C VIN DC input voltage 0V to VDD 4 DC ELECTRICAL CHARACTERISTICS1, 2 (VDD = 5.0V +10%; -55°C < TC < +125°C) SYMBOL PARAMETER CONDITION MIN MAX UNIT VIH High-level input voltage (TTL) 2.0 VDD V VIL Low-level input voltage (TTL) V SS 0.8 V VOL Low-level output voltage RL = 100Ω 0.90 VOH High-level output voltage RL = 100Ω IIN4 Input leakage current VIN = VDD ICSOUT VOD1 ∆VOD1 VOS V 1.60 V -10 +10 µA Cold Spare Leakage LVDS Outputs VIN=5.5V, VDD=VSS -10 +10 µΑ Differential Output Voltage RL = 100Ω(figure 5) 250 400 mV Change in Magnitude of VOD for Complementary Output States RL = 100Ω(figure 5) 10 mV Offset Voltage + Vol- RL = 100Ω, Vos = Voh ------------------------- 1.375 V 1.125 2 ∆VOS Change in Magnitude of VOS for Complementary Output States RL = 100Ω(figure 5) 25 mV VCL3 Input clamp voltage ICL = -18mA -1.5 V IOS3 Output Short Circuit Current VOUT = 0V2 5.0 mA IOZ4 Output Three-State Current EN = 0.8V and EN = 2.0 V, VOUT = 0V or VDD +10 µΑ ICCL4 Loaded supply current drivers enabled RL = 100Ω all channels Loaded supply current drivers disabled DIN = VDD or VSS ICCZ4 VIN = VDD or VSS(all inputs) EN = VSS, EN = VDD -10 mA 25.0 mA 10.0 Notes: 1. Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground except differential voltages. 2. Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only. 3. Guaranteed by characterization. 4. Devices are tested @ VDD = 5.5V only. 5 DOUT+ 20pF DIN D Generator RL = 100Ω 50Ω Driver Enabled 20pF DOUT- Figure 5. Driver V OD and VOS Test Circuit or Equivalent Circuit 6 VOD AC SWITCHING CHARACTERISTICS 1, 2, 3, 4 (VDD = +5.0V + 10%, T A = -55 °C to +125 °C) SYMBOL PARAMETER MIN MAX UNIT tPHLD Differential Propagation Delay High to Low (figures 6 and 7) 0.5 5.0 ns tPLHD Differential Propagation Delay Low to High (figures 6 and 7) 0.5 5.0 ns tSKD4 Differential Skew (tPHLD - tPLHD) (figures 6 and 7) 0 3.0 ns tSK14 Channel-to-Channel Skew1 (figures 6 and 7) 0 3.0 ns tSK24 Chip-to-Chip Skew 5 (figure 6 and 7) 4.5 ns tTLH4 Rise Time (figures 6 and 7) 2.0 ns tTHL4 Fall Time (figures 6 and 7) 2.0 ns tPHZ4 Disable Time High to Z (figures 8 and 9) 10 ns tPLZ4 Disable Time Low to Z (figures 8 and 9) 10 ns tPZH4 Enable Time Z to High (figures 8 and 9) 10 ns tPZL4 Enable Time Z to Low (figures 8 and 9) 10 ns Notes: 1. Channel-to-Channel Skew is defined as the difference between the propagation delay of the channel and the other channels in the same chip with an event on the inputs. 2. Generator waveform for all tests unless otherwise specified: f = 1 MHz, Z O = 50, t r < 6 ns, and tf < 6 ns. 3. CL includes probe and jig capacitance. 4. Guaranteed by characterization 5. Chip to Chip Skew is defined as the difference between the minimum and maximum specified differential propagation delays. 7 DOUT+ 20pF DIN D Generator RL = 100Ω 50Ω Driver Enabled 20pF DOUT- Figure 6. Driver Propagation Delay and Transition Time Test Circuit or Equivalant Circuit VDD 1.25V DIN 1.25V 0V DOUT- tPLHD tPHLD VOH 0V (Differential) VOL DOUT+ 80% 80% V DIFF = D OUT+ - DOUT- 0V 0V VDIFF 20% 20% tTHL tTLH Figure 7. Driver Propagation Delay and Transition Time Waveforms 8 DOUT+ 20pF VDD DIN 50Ω D VSS +1.2V 50Ω EN DOUT- 20pF Generator 50Ω EN Figure 8. Driver Three-State Delay Test Circuit or Equivalant Circuit EN when EN = VDD 1.25V VDD 1.25V 0V or VDD 1.25V 1.25V EN when EN = V SS DOUT+ when D IN =VDD DOUT- when DIN = VSS 0V tPHZ tPZH VOH 50% 1.2V 1.2V 50% 50% DOUT+ when DIN = V SS DOUT- when DIN = VDD VOL tPZL tPLZ Figure 9. Driver Three-State Delay Waveform 9 PACKAGING Notes: 1. All exposed metalized areas are gold plated over electroplated nickel per MIL-PRF-38535. 2. The lid is electrically connected to VSS. 3. Lead finishes are in accordance to MIL-PRF-38535. 4. Package dimensions and symbols are similar to MIL-STD-1835 variation F-5A. 5. Lead position and coplanarity are not measured. 6. ID mark symbol is vendor option. 7. With solder, increase maximum by 0.003. Figure 10. 16-pin Ceramic Flatpack 10 ORDERING INFORMATION UT54LVDSC031 QUAD DRIVER: UT54LVDSC031 - * * * * * Lead Finish: (A) = Hot solder dipped (C) = Gold (X) = Factory option (gold or solder) Screening: (C) = Military Temperature Range flow (P) = Prototype flow Package Type: (U) = 16-lead Flatpack (dual-in-line) Access Time: Not applicable Device Type: UT54LVDSC031 LVDS Driver Notes: 1. Lead finish (A,C, or X) must be specified. 2. If an “X” is specified when ordering, then the part marking will match the lead finish and will be either “A” (solder) or “C” (gold). 3. Prototype flow per UTMC Manufacturing Flows Document. Tested at 25°C only. Lead finish is GOLD ONLY. Radiation neither tested nor guaranteed. 4. Military Temperature Range flow per UTMC Manufacturing Flows Document. Devices are tested at -55°C, room temp, and 125 °C. Radiation neither tested nor guaranteed. 11 UT54LVDSC031 QUAD DRIVER: SMD 5962 - 95833 ** * * * Lead Finish: (A) = Hot solder dipped (C) = Gold (X) = Factory Option (gold or solder) Case Outline: (X) = 16 lead Flatpack (dual-in-line) Class Designator: (Q) = QML Class Q (V) = QML Class V Device Type 03 = LVDS Driver Drawing Number: 95833 Total Dose (R) = 1E5 rad(Si) (F) = 3E5 rad(Si) Federal Stock Class Designator: No Options Notes: 1.Lead finish (A,C, or X) must be specified. 2.If an “X” is specified when ordering, part marking will match the lead finish and will be either “A” (solder) or “C” (gold). 3.Total dose radiation must be specified when ordering. QML Q and QML V not available without radiation hardening. 12