3 V LVDS Quad CMOS Differential Line Driver ADN4667 ±15 kV ESD protection on output pins 400 Mbps (200 MHz) switching rates Flow-through pinout simplifies PCB layout 300 ps typical differential skew 400 ps maximum differential skew 1.7 ns maximum propagation delay 3.3 V power supply ±310 mV differential signaling Low power dissipation (10 mW typical) Interoperable with existing 5 V LVDS receivers High impedance on LVDS outputs on power-down Conforms to TIA/EIA-644 LVDS standard Industrial operating temperature range: −40°C to +85°C Available in low profile TSSOP package APPLICATIONS FUNCTIONAL BLOCK DIAGRAM VCC ADN4667 DIN1 D1 DIN2 D2 DIN3 D3 DIN4 D4 DOUT1+ DOUT1– DOUT2+ DOUT2– DOUT3+ DOUT3– DOUT4+ DOUT4– EN EN GND 07032-001 FEATURES Figure 1. Backplane data transmission Cable data transmission Clock distribution GENERAL DESCRIPTION The ADN4667 is a quad, CMOS, low voltage differential signaling (LVDS) line driver offering data rates of over 400 Mbps (200 MHz) and ultralow power consumption. It features a flow-through pinout for easy PCB layout and separation of input and output signals. The device accepts low voltage TTL/CMOS logic signals and converts them to a differential current output of typically ±3.1 mA for driving a transmission medium such as a twisted pair cable. The transmitted signal develops a differential voltage of typically ±310 mV across a termination resistor at the receiving end. This is converted back to a TTL/CMOS logic level by an LVDS receiver. The ADN4667 also offers active high and active low enable/ disable inputs (EN and EN). These inputs control all four drivers and turn off the current outputs in the disabled state to reduce the quiescent power consumption to typically 10 mW. The ADN4667 and a companion LVDS receiver offer a new solution to high speed, point-to-point data transmission, and a low power alternative to emitter-coupled logic (ECL) or positive emitter-coupled logic (PECL). Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2008 Analog Devices, Inc. All rights reserved. ADN4667 TABLE OF CONTENTS Features .............................................................................................. 1 ESD Caution...................................................................................6 Applications ....................................................................................... 1 Pin Configuration and Function Descriptions..............................7 Functional Block Diagram .............................................................. 1 Typical Performance Characteristics ..............................................8 General Description ......................................................................... 1 Theory of Operation ...................................................................... 11 Revision History ............................................................................... 2 Enable Inputs .............................................................................. 11 Specifications..................................................................................... 3 Applications Information .......................................................... 11 AC Characteristics........................................................................ 4 Outline Dimensions ....................................................................... 12 Test Circuits ....................................................................................... 5 Ordering Guide .......................................................................... 12 Absolute Maximum Ratings............................................................ 6 REVISION HISTORY 1/08—Revision 0: Initial Version Rev. 0 | Page 2 of 12 ADN4667 SPECIFICATIONS VCC = 3.0 V to 3.6 V; RL = 100 Ω; CL = 15 pF to GND; all specifications TMIN to TMAX, unless otherwise noted.1 Table 1. Parameter Min Typ Max Unit Conditions/Comments2, 3 250 310 1 1.17 1 1.33 1.02 450 35 1.375 25 1.6 mV |mV| V |mV| V V See Figure 2 and Figure 4 See Figure 2 and Figure 4 See Figure 2 and Figure 4 See Figure 2 and Figure 4 See Figure 2 and Figure 4 See Figure 2 and Figure 4 VCC 0.8 +10 +10 V V μA μA V VIN = VCC or 2.5 V VIN = GND or 0.4 V ICL = −18 mA LVDS OUTPUTS (DOUT+, DOUT−) Differential Output Voltage, VOD Change in Magnitude of VOD for Complementary Output States, ΔVOD Offset Voltage, VOS Change in Magnitude of VOS for Complementary Output States, ΔVOS Output High Voltage, VOH Output Low Voltage, VOL 1.125 0.90 INPUTS (DIN, EN, EN) Input High Voltage, VIH Input Low Voltage, VIL Input High Current, IIH Input Low Current, IIL Input Clamp Voltage, VCL 2.0 GND −10 −10 −1.5 +2 +2 −0.8 LVDS OUTPUT PROTECTION (DOUT+, DOUT−) Output Short-Circuit Current, IOS4 −4.2 −9.0 mA Differential Output Short-Circuit Current, IOSD4 −4.2 −9.0 mA ±1 ±1 +20 +10 μA μA VOUT = 0 V or 3.6 V, VCC = 0 V or open EN = 0.8 V and EN = 2.0 V, VOUT = 0 V or VCC No Load Supply Current, Drivers Enabled, ICC Loaded Supply Current, Drivers Enabled, ICCL 4.0 20 8.0 30 mA mA No Load Supply Current, Drivers Disabled, ICCZ 2.2 6.0 mA DIN = VCC or GND RL = 100 Ω all channels, DIN = VCC or GND (all inputs) DIN = VCC or GND, EN = GND, EN = VCC kV kV Human body model Human body model Enabled, DIN = VCC, DOUT+ = 0 V or DIN = GND, DOUT− = 0 V Enabled, VOD = 0 V LVDS OUTPUT LEAKAGE (DOUT+, DOUT−) Power-Off Leakage, IOFF Output Three-State Current, IOZ −20 −10 POWER SUPPLY ESD PROTECTION DOUT+, DOUT− Pins All Pins Except DOUT+, DOUT− ±15 ±4 1 All typical values are given for VCC = +3.3 V, TA = +25°C. Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground except VOD ΔVOD, and ΔVOS. 3 The ADN4667 is a current-mode device and functions within data sheet specifications only when a resistive load is applied to the driver outputs. Typical range is 90 Ω to 110 Ω. 4 Output short-circuit current (IOS) is specified as magnitude only; minus sign indicates direction only. 2 Rev. 0 | Page 3 of 12 ADN4667 AC CHARACTERISTICS 1 VCC = 3.0 V to 3.6 V; RL = 100 Ω; CL 2 = 15 pF to GND; all specifications TMIN to TMAX, unless otherwise noted. 3 Table 2. Parameter Differential Propagation Delay, High to Low, tPHLD Differential Propagation Delay, Low to High, tPLHD Differential Pulse Skew |tPHLD − tPLHD|, tSKD1 6 Channel-to-Channel Skew, tSKD2 7 Differential Part-to-Part Skew, tSKD3 8 Differential Part-to-Part Skew, tSKD4 9 Rise Time, tTLH Fall Time, tTHL Disable Time High to Inactive, tPHZ Disable Time Low to Inactive, tPLZ Enable Time Inactive to High, tPZH Enable Time Inactive to Low, tPZL Maximum Operating Frequency, fMAX 10 Min 0.5 0.5 0 0 0 0 200 Typ 0.9 1.2 0.3 0.4 0.5 0.5 2 2 3 3 250 1 Max 1.7 1.7 0.4 0.5 1.0 1.2 1.5 1.5 5 5 7 7 Unit ns ns ns ns ns ns ns ns ns ns ns ns MHz Conditions/Comments 4, 5 See Figure 3 and Figure 4 See Figure 3 and Figure 4 See Figure 3 and Figure 4 See Figure 3 and Figure 4 See Figure 3 and Figure 4 See Figure 3 and Figure 4 See Figure 3 and Figure 4 See Figure 3 and Figure 4 See Figure 5 and Figure 6 See Figure 5 and Figure 6 See Figure 5 and Figure 6 See Figure 5 and Figure 6 See Figure 5 and Figure 6 AC parameters are guaranteed by design and characterization. CL includes probe and jig capacitance. All typical values are given for VCC = +3.3 V, TA = +25°C. 4 Generator waveform for all tests unless otherwise specified: f = 50 MHz, ZO = 50 Ω, tr ≤ 1 ns, and tf ≤ 1 ns. 5 All input voltages are for one channel unless otherwise specified. Other inputs are set to GND. 6 tSKD1 = |tPHLD − tPLHD| is the magnitude difference in differential propagation delay time between the positive going edge and the negative going edge of the same channel. 7 tSKD2 is the differential channel-to-channel skew of any event on the same device. 8 tSKD3, differential part-to-part skew, is defined as the difference between the minimum and maximum specified differential propagation delays. This specification applies to devices at the same VCC and within 5°C of each other within the operating temperature range. 9 tSKD4, part-to-part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices over recommended operating temperature and voltage ranges, and across process distribution. tSKD4 is defined as |Max − Min| differential propagation delay. 10 fMAX generator input conditions: tr = tf < 1 ns (0% to 100%), 50% duty cycle, 0 V to 3 V. Output criteria: duty cycle = 45%/55%, VOD > 250 mV, all channels switching. 2 3 Rev. 0 | Page 4 of 12 ADN4667 TEST CIRCUITS VCC V VOS V VOD 07032-002 DRIVER IS ENABLED DOUT– NOTES 1. CL INCLUDES LOAD AND TEST JIG CAPACITANCE. Figure 2. Test Circuit for Driver VOD and VOS Figure 3. Test Circuit for Driver Propagation Delay and Transition Time 3V DIN 1.5V 0V tPLHD tPHLD VOD DOUT– VOH 0V (DIFFERENTIAL) VOL DOUT+ 80% 0V VDIFF VDIFF = DOUT+ – DOUT– tTLH 20% tTHL Figure 4. Driver Propagation Delay and Transition Time Waveforms DOUT+ CL 50Ω VCC 1.2V 50Ω DIN DOUT– CL 50Ω 07032-005 EN SIGNAL GENERATOR 07032-003 CL RL/2 DRIVER IS ENABLED DOUT– 50Ω EN Figure 5. Test Circuit for Driver Three-State Delay 3V EN WITH EN = GND OR OPEN-CIRCUIT 1.5V 0V 3V EN WITH EN = VCC 1.5V 0V tPHZ tPZH DOUT+ WITH DIN = VCC OR DOUT– WITH DIN = GND VOH 50% 1.2V 1.2V 50% DOUT+ WITH DIN = GND OR DOUT– WITH DIN = VCC tPLZ Figure 6. Driver Three-State Delay Waveforms Rev. 0 | Page 5 of 12 tPZL VOL 07032-006 DIN DIN SIGNAL GENERATOR RL/2 07032-004 VCC DOUT+ CL DOUT+ ADN4667 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 3. Parameter VCC to GND Input Voltage (DIN) to GND Enable Input Voltage (EN, EN) to GND Output Voltage (DOUT+, DOUT−) to GND Short-Circuit Duration (DOUT+, DOUT−) to GND Operating Temperature Range Industrial Storage Temperature Range Junction Temperature (TJ max) Power Dissipation TSSOP Package θJA Thermal Impedance Reflow Soldering Peak Temperature (10 sec) Rating −0.3 V to +4 V −0.3 V to VCC + 0.3 V −0.3 V to VCC + 0.3 V −0.3 V to VCC + 0.3 V Continuous −40°C to +85°C −65°C to +150°C 150°C (TJ max − TA)/θJA Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION 150.4°C/W 260°C max Rev. 0 | Page 6 of 12 ADN4667 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 16 DOUT1– 15 DOUT1+ DIN2 3 ADN4667 14 DOUT2+ VCC 4 TOP VIEW (Not to Scale) 13 DOUT2– GND 5 12 DOUT3– DIN3 6 11 DOUT3+ DIN4 7 10 DOUT4+ EN 8 9 DOUT4– NC = NO CONNECT 07032-007 EN 1 DIN1 2 Figure 7. Pin Configuration Table 4. Pin Function Descriptions Pin No. 1 Mnemonic EN 2 3 4 DIN1 DIN2 VCC 5 6 7 8 GND DIN3 DIN4 EN 9 DOUT4− 10 DOUT4+ 11 DOUT3+ 12 DOUT3− 13 DOUT2− 14 DOUT2+ 15 DOUT1+ 16 DOUT1− Description Active High Enable and Power-Down Input (3 V TTL/CMOS). If EN is held low or open-circuit, EN enables the drivers when high and disables the drivers when low. Driver Channel 1 Logic Input. Driver Channel 2 Logic Input. Power Supply Input. These parts can be operated from 3.0 V to 3.6 V; and the supply should be decoupled with a 10 μF solid tantalum capacitor in parallel with a 0.1 μF capacitor to GND. Ground Reference Point for All Circuitry on the Part. Driver Channel 3 Logic Input. Driver Channel 4 Logic Input. Active Low Enable and Power-Down Input with Pull-Down (3 V TTL/CMOS). If EN is held high, EN enables the drivers when low or open-circuit and disables the drivers and powers down the device when high. Channel 4 Inverting Output Current Driver. When DIN4 is high, current flows into DOUT4−; when DIN4 is low, current flows out of DOUT4−. Channel 4 Noninverting Output Current Driver. When DIN4 is high, current flows out of DOUT4+; when DIN4 is low, current flows into DOUT4+. Channel 3 Noninverting Output Current Driver. When DIN3 is high, current flows out of DOUT3+; when DIN3 is low, current flows into DOUT3+. Channel 3 Inverting Output Current Driver. When DIN3 is high, current flows into DOUT3−; when DIN3 is low, current flows out of DOUT3−. Channel 2 Inverting Output Current Driver. When DIN2 is high, current flows into DOUT2−; when DIN2 is low, current flows out of DOUT2−. Channel 2 Noninverting Output Current Driver. When DIN2 is high, current flows out of DOUT2+; when DIN2 is low, current flows into DOUT2+. Channel 1 Noninverting Output Current Driver. When DIN1 is high, current flows out of DOUT1+; when DIN1 is low, current flows into DOUT1+. Channel 1 Inverting Output Current Driver. When DIN1 is high, current flows into DOUT1−; when DIN1 is low, current flows out of DOUT1−. Rev. 0 | Page 7 of 12 ADN4667 TYPICAL PERFORMANCE CHARACTERISTICS 440 1.414 1.412 3.0 07032-008 1.413 3.1 3.2 3.3 3.4 3.5 TA = 25°C VIN = GND OR VCC 420 400 380 360 07032-011 TA = 25°C RL = 100Ω OUTPUT THREE-STATE CURRENT, IOZ (pA) OUTPUT HIGH VOLTAGE, VOH (V) 1.415 340 3.0 3.6 3.1 POWER SUPPLY VOLTAGE, VCC (V) 07032-009 1.088 3.2 3.3 3.4 3.5 DIFFERENTIAL OUTPUT VOLTAGE, VOD (mV) OUTPUT LOW VOLTAGE, VOL (V) 325.0 1.089 3.1 324.6 324.4 324.2 3.1 3.4 3.5 3.4 3.5 3.6 450 400 350 300 250 90 3.6 POWER SUPPLY VOLTAGE, VCC (V) TA = 25°C VCC = 3.3V 07032-013 DIFFERENTIAL OUTPUT VOLTAGE, VOD (mV) 07032-010 SHORT-CIRCUIT CURRENT, I OS (mA) 500 –4.1 3.3 3.3 Figure 12. Differential Output Voltage vs. Power Supply Voltage –4.0 3.2 3.2 POWER SUPPLY VOLTAGE, VCC (V) TA = 25°C VIN = GND OR VCC VOUT = 0V 3.1 3.6 324.8 324.0 3.0 3.6 Figure 9. Output Low Voltage vs. Power Supply Voltage –4.2 3.0 3.5 TA = 25°C RL = 100Ω POWER SUPPLY VOLTAGE, VCC (V) –3.9 3.4 Figure 11. Output Three-State Current vs. Power Supply Voltage TA = 25°C RL = 100Ω 1.087 3.0 3.3 07032-012 Figure 8. Output High Voltage vs. Power Supply Voltage 1.090 3.2 POWER SUPPLY VOLTAGE, VCC (V) 100 110 120 130 140 LOAD RESISTOR, RL (Ω) Figure 10. Output Short-Circuit Current vs. Power Supply Voltage Figure 13. Differential Output Voltage vs. Load Resistor Rev. 0 | Page 8 of 12 150 ADN4667 14.92 1.251 1.249 3.0 07032-014 1.250 3.1 3.2 3.3 3.4 3.5 14.91 14.90 VCC = 3.3V f = 1MHz CL = 15pF VIN = 0V TO 3V RL = 100Ω PER DRIVER 14.89 14.88 –40 3.6 –20 POWER SUPPLY VOLTAGE, VCC (V) 1200 22 ALL CHANNELS SWITCHING 20 18 16 ONE CHANNEL SWITCHING 1 10 100 1100 tPLHD 1000 3.1 3.4 3.5 3.4 3.5 3.6 3.6 VCC = 3.3V f = 1MHz CL = 15pF RL = 100Ω PER DRIVER tPLHD 1100 tPHLD 1000 900 –40 07032-019 DIFFERENTIAL PROPAGATION DELAY (ns) 14.915 07032-016 POWER SUPPLY CURRENT, ICC (mA) 1200 3.3 3.3 Figure 18. Differential Propagation Delay vs. Power Supply Voltage 14.920 3.2 3.2 POWER SUPPLY VOLTAGE, VCC (V) TA = 25°C f = 1MHz CL = 15pF VIN = 0V TO 3V RL = 100Ω PER DRIVER 3.1 100 tPHLD 900 3.0 500 Figure 15.Power Supply Current vs. Switching Frequency 14.910 3.0 80 TA = 25°C f = 1MHz CL = 15pF RL = 100Ω PER DRIVER SWITCHING FREQUENCY, f (MHz) 14.925 60 07032-018 DIFFERENTIAL PROPAGATION DELAY (ns) TA = 25°C CL = 15pF VCC = 3.3V VIN = 0V TO 3V RL = 100Ω PER DRIVER 14 0.1 40 Figure 17. Power Supply Current vs. Ambient Temperature 07032-015 POWER SUPPLY CURRENT, ICC (mA) 24 20 AMBIENT TEMPERATURE, TA (°C) Figure 14. Offset Voltage vs. Power Supply Voltage 26 0 07032-017 TA = 25°C RL = 100Ω POWER SUPPLY CURRENT, ICC (mA) OFFSET VOLTAGE, VOS (mV) 1.252 –20 0 20 40 60 80 100 AMBIENT TEMPERATURE, TA (°C) POWER SUPPLY VOLTAGE, VCC (V) Figure 19. Differential Propagation Delay vs. Ambient Temperature Figure 16. Power Supply Current vs. Power Supply Voltage Rev. 0 | Page 9 of 12 ADN4667 400 TRANSITION TIME (ps) 80 60 40 20 0 3.0 3.1 3.2 3.3 3.4 3.5 TA = 25°C f = 1MHz CL = 15pF RL = 100Ω PER DRIVER 380 tTLH 360 tTHL 340 320 3.0 3.6 07032-022 TA = 25°C f = 1MHz CL = 15pF RL = 100Ω PER DRIVER 07032-020 DIFFERENTIAL SKEW, tSKD (ps) 100 3.1 POWER SUPPLY VOLTAGE, VCC (V) Figure 20. Differential Skew vs. Supply Voltage 400 VCC = 3.3V f = 1MHz CL = 15pF RL = 100Ω PER DRIVER TRANSITION TIME (ps) 40 3.3 3.4 3.5 3.6 Figure 22. Transition Time vs. Supply Voltage 30 20 VCC = 3.3V f = 1MHz CL = 15pF RL = 100Ω PER DRIVER 380 tTLH 360 tTHL 0 –40 –20 0 20 40 60 80 320 –40 100 AMBIENT TEMPERATURE, TA (°C) 07032-023 340 10 07032-021 DIFFERENTIAL SKEW, tSKD (ps) 50 3.2 POWER SUPPLY VOLTAGE, VCC (V) –20 0 20 40 60 80 AMBIENT TEMPERATURE, TA (°C) Figure 21. Differential Skew vs. Ambient Temperature Figure 23. Transition Time vs. Ambient Temperature Rev. 0 | Page 10 of 12 100 ADN4667 THEORY OF OPERATION The ADN4667 is a quad line driver for low voltage differential signaling. It takes a single-ended 3 V logic signal and converts it to a differential current output. The data can then be transmitted for considerable distances, over media such as a twisted pair cable or PCB backplane, to an LVDS receiver, where it develops a voltage across a terminating resistor, RT. This resistor is chosen to match the characteristic impedance of the medium, typically around 100 Ω. The differential voltage is detected by the receiver and converted back into a single-ended logic signal. as internal gates switch between high and low, which causes currents to flow from the device power supply to ground. When DIN is high (Logic 1), current flows out of the DOUT+ pin (current source) through RT and back into the DOUT− pin (current sink). At the receiver, this current develops a positive differential voltage across RT (with respect to the inverting input) and gives a Logic 1 at the receiver output. When DIN is low, DOUT+ sinks current and DOUT− sources current; a negative differential voltage across RT gives a Logic 0 at the receiver output. The ADN4667 has active high and active low enable inputs, which deactivate all the current drivers when in the disabled state. This also powers down the device and reduces the current consumption from typically 20 mA to typically 2.2 mA. A truth table for the enable inputs is shown in Table 5. The output drive current is between ±2.5 mA and ±4.5 mA (typically ±3.1 mA), developing between ±250 mV and ±450 mV across a 100 Ω termination resistor. The received voltage is centered around the receiver offset of 1.2 V. In other words, the noninverting receiver input is typically (1.2 V + [310 mV/2]) = 1.355 V, and the inverting receiver input is (1.2 V − [310 mV/2]) = 1.045 V for Logic 1. For Logic 0, the inverting and noninverting output voltages are reversed. Note that because the differential voltage reverses polarity, the peak-to-peak voltage swing across RT is twice the differential voltage. A current-mode device simply reverses a constant current between its two outputs, with no significant overlap currents. This is similar to emitter-coupled logic (ECL) and positive emitter-coupled logic (PECL), but without the high quiescent current of ECL and PECL. ENABLE INPUTS Table 5. Enable Inputs Truth Table EN EN H L or open H L or open Any other combination of EN and EN DIN DOUT+ DOUT− L H X ISINK ISOURCE Inactive ISOURCE ISINK Inactive APPLICATIONS INFORMATION Figure 24 shows a typical application for point-to-point data transmission. Current-mode drivers offer considerable advantages over voltage-mode drivers such as RS-422 drivers. The operating current remains fairly constant with increased switching frequency, whereas that of voltage-mode drivers increases exponentially in most cases. This is caused by the overlap 1/4 ADN4667 EN EN RT 100Ω RECEIVER DOUT 07032-024 DIN Figure 24. Typical Application Circuit Rev. 0 | Page 11 of 12 ADN4667 OUTLINE DIMENSIONS 5.10 5.00 4.90 16 9 4.50 4.40 4.30 6.40 BSC 1 8 PIN 1 1.20 MAX 0.15 0.05 0.20 0.09 0.30 0.19 0.65 BSC COPLANARITY 0.10 SEATING PLANE 8° 0° 0.75 0.60 0.45 COMPLIANT TO JEDEC STANDARDS MO-153-AB Figure 25. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16) Dimensions shown in millimeters ORDERING GUIDE Model ADN4667ARUZ1 ADN4667ARUZ-REEL71 1 Temperature Range −40°C to +85°C −40°C to +85°C Package Description 16-Lead Thin Shrink Small Outline Package [TSSOP] 16-Lead Thin Shrink Small Outline Package [TSSOP] Z = RoHS Compliant Part. ©2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07032-0-1/08(0) Rev. 0 | Page 12 of 12 Package Option RU-16 RU-16