REV 0.1 2002/04/23 Sigma-Delta Voice CODEC COD0419X GENERAL DESCRIPTION FEATURES The COD0419X is Sigma-Delta CODEC for speech and telephony applications. The product contains both digital IIR/FIR filter and smoothing filter. The normal input and output channels have µ/A law format with 38dB signal to distortion ratio. The input and output of this device is compressed form(A-law, µ-law) and 14bit linear which can be easily determined by control select pins An on-chip voltage reference circuit is included to allow the single supply operation - Single chip voice line Codec (A/D, D/A converter included) - Oversampled Sigma Delta modulator/ Demodulator - Input/Output format : 8bit µ-law/A-law and linear 14bit * These three types are easily selectible by control pins * When serial interface mode, the 14bit linear data has 16bit format with two don't care bits from LSB - Sigma Delta ADC. * 256X Oversampling * On chip Decimation Filter * On chip Smoothing Filter - Sigma Delta DAC. * 256X Oversampling * On chip 256X Interpolation Filter * On chip Analog Post Filter - Single ended Input and Output. - Sampling Rate of 8~11KHz - On chip voltage reference circuitry - Single +2.5V Power Supply - 1.6Vpp In, Output signal swing - Power Consumption * Operating Mode : 7.5mW Typ(2.5V) * Powerdown Mode : 25µW Typ(2.5V) TYPICAL APPLICATIONS - Speech Processing (Recognition, Synthesis, Compression etc.) - Telephony - Modem FUNCTIONAL BLOCK DIAGRAM WITH INPUT/OUPUT APPLICATION ALOOP MUTE TPOST TDECI REFL SINPO<1:0> SDECI<1:0> ADHPB DAHPB AINFB Analog Input Voltage Reference Output - + AMODIN Analog ∆Σ Modulator VREFOUT APOSTOUT IREF Serial Interface 1. 14bit Linear PCM in 16bit format 2. µ-law 3. A-law SDIN DAC Serial Interface Voltage Reference Analog Postfilter Analog Output Current Reference Output Decimation filter SDOUT ADC Serial Output Differential to Single circuit + Smoothing filter Digital ∆Σ Modulator Interpolation filter DADS LCS Selectible powerdown circuit CPSEL X256FS BCK SYNC SAMSUNG ELECTRONICS Co. LTD RST VDD25AD1 VSS25AD1 VDD25AA1 VSS25AA1 ADPWD DAPWD COD0419X Sigma-Delta voice CODEC CORE PIN DESCRIPTION I/O I/O PAD TYPE NAME PIN DESCRIPTION VDD25AA1 AP vdd1t_abb Analog Power (+2.5V) VSS25AA1 AG vss1t_abb Analog Ground (0.0V) IREF AO poa_abb Current Reference Output REFL AG vss1t_abb Analog Reference Ground (0.0V) AMODIN AI pia_abb MUTE DI picc_abb Analog Mute select (High active) ALOOP DI picc_abb Analog loop back select (High active) VREFOUT AO poa_abb Vref output AINFB AB poa_abb Analog Input Gain control APOSTOUT AO poa_abb DAC Analog output ADPWD DI picc_abb ADC Power Down (High active) DAPWD DI picc_abb DAC Power Down (High active) RST DI picc_abb Digital Reset (High active) X256FS DI picc_abb 256*Sampling Freq.(FS) Clock SYNC DI picc_abb Sampling Freq.(FS) Clock SDECI<1:0> DI picc_abb ADC Digital Filter input select TDECI DI picc_abb ADC Digital Filter Test input SINPO<1:0> DI picc_abb DAC Post Filter input select SDIN DI picc_abb Serial Data Input TPOST DI picc_abb DAC Post Filter Test input LCS DI picc_abb Linear/Compand data select (Low/High) CPSEL DI picc_abb µ-law/A-law select (Low/High) VSS25AD1 DG vss1t_abb Digital Ground VDD25AD1 DP vdd1t_abb Digital Power Supply SDOUT DO pot2_abb Serial Data Output BCK DI picc_abb Bit Clock DADS DO pot2_abb DAC Modulator output ADHPB DI picc_abb ADC High Pass Filter Enable (Low Active) DAHPB DI picc_abb DAC High Pass Filter Enable (Low Active) ADC Analog input I/O TYPE ABBR. - AI : Analog Input DI : Digital Input AO : Analog Output DO : Digital Output AB : Analog Bidirectional DB : Digital Bidirectional AP : Analog Power AG : Analog Ground DP : Digital Power DG : Digital Ground NOTES 1. This pin description is not fixed, but recommended. 2. The Power pin(VDD25AA1,VDD25AD1) must be connected by DIODE_SLOT2. 3. The Ground pin (VSS25AA1, VSS25AD1) must be connected bye DIODE_SLOT2. 4. SDECI<1:0>, TDECI -> Decimation Filter Block test pin. 5. SINPO<1:0>, TPOST -> Post Filter Block test pin. SEC ASIC 2/13 ANALOG COD0419X Sigma-Delta voice CODEC CORE CONFIGURATION RST SYNC TPOST DADS TDECI SDOUT DAPWD ADPWD LCS CPSEL IREF SDIN VREFOUT X256FS cod0419x ALOOP APOSTOUT MUTE SINPO<1:0> SDECI<1:0> VDD25AD1 BCK ADHPB VSS25AD1 DAHPB VDD25AA1 AINFB VSS25AA1 AMODIN REFL SEC ASIC 3/13 ANALOG COD0419X Sigma-Delta voice CODEC ABSOLUTE MAXIMUM RATINGS Characteristic Symbol Value Unit VDD25AD1 3.3 V Digital Input Voltage DIN VSS25AD1 to VDD25AD1 V Storage Temperature Range Tstg -45 to 125 °C Operating Temperature Range Topr 0 to 70 °C Supply Voltage NOTES 1. ABSOLUTE MAXIMUM RATING specifies the values beyond which the device may be damaged permanently. Exposure to ABSOLUTE MAXIMUM RATING conditions for extended periods may affect reliability. Each condition value is applied with the other values kept within the following operating conditions and function operations under any of these conditions is not implied. 2. All voltages are measured with respect to VSS(VSS25AA1 or VSS25AD1) unless otherwise specified. RECOMMENDED OPERATING CONDITIONS Characteristics Symbol Min Typ Max Unit Supply Voltage VDD25AA1 • VSS25AA1 VDD25AD1 • VSS25AD1 2.375 2.5 2.625 V Supply Voltage Difference VDD25AA1 • VDD25AD1 0.1 0.0 0.1 V Digital Input Voltage Range 2.25 2.5 2.75 V Analog Input Voltage Range - 1.6 - Vpp NOTES It is strongly recommended that all the supply pins (VDD25AA1, VDD25AD1) be powered from the same source to avoid power latch up. DIGITAL FILTER CHARACTERISTICS Characteristics Filter Passband Filter Passband ripple Filter Stopband Filter Stopband attenuation SEC ASIC Ratio Value (Fs = 8KHz) Conditions 0 ~ 0.4Fs 0 ~ 3.2KHz high pass filter off 0.0375Fs ~ 0.4Fs 300Hz ~ 3.2KHz high pass filter on ±0.5dB ±0.5dB - 0.6Fs over 4.8KHz over high pass filter off 0.0375Fs under, 0.6Fs over 300Hz under 4.8KHz over high pass filter on -1.2dB(0.425Fs) -40dB (0.6Fs over) -1.2dB(3.4KHz) -40dB(4.8KHz over) high pass filter off -1.2dB(0.425Fs) -40dB (0.6Fs over) -8dB(0.0075Fs) -25dB (0Fs) -1.2dB(3.4KHz) -40dB(4.8KHz over) -8dB(60Hz) -25dB(0Hz) high pass filter on 4/13 ANALOG COD0419X Sigma-Delta voice CODEC AC ELECTRICAL CHARACTERISTICS (Measurement Bandwidth is 20Hz - 4KHz. Full scale input sine wave 1KHz, FS=8KHz, @VDD25AA1,VDD25AD1=2.5V, Ta=25°C ,Unless otherwise specified.) Min Typ Max Unit Resolution - 14 - Bits Sampling rate - 8 - KHz Characteristics Symbol Conditions - ADC Analog Input Characteristics * Signal to Distortion Ratio 35 38 - dB 0dB Input : µ/A Law compand 70 75 - dB 0dB Input : Linear - dB - dB -40dB Input : µ-Law compand 29.5 28 29 -45dB Input : µ-Law compand 25 23 24 -40dB Input : A-Law compand -45dB Input : A-Law compand Offset Error - - ±20 mV - Input Voltage Range - 1.6 - Vpp - DAC Analog Input Characteristics * Signal to Distortion Ratio 35 38 - dB 70 75 − dB 30 33.5 − dB − dB 29 32 25 30 0dB Input : µ/A Law compand 0dB Input : Linear -40dB Input : µ-Law compand -40dB Input : A-Law compand -45dB Input : µ-Law compand 24 27 -45dB Input : A-Law compand Offset Error − − ±20 mV - Output Voltage Range − 1.6 − Vp-p - - Power Supply Power comsumption (2.5v Operating Mode) Analog Digital - 2.5 0.5 3 0.7 mA Power comsumption (2.5v Powerdown Mode) - 10 - µA SEC ASIC 5/13 ANALOG COD0419X Sigma-Delta voice CODEC CORE LAYOUT GUIDE N-WELL Guardring P+ Guardring VDD25AD1 VSS25AD1 VABB DIGITAL BLOCK Analog Input ANALOG BLOCK VSS25AA1 VABB Guardring Analog Output VDD25AA1 NOTE 1. The layout of cod0419x consists of digital part and analog part. The digital part and the analog part must be divided. 2. The substrate of digital and analog part is seperated from digital and analog ground so that it can minimize noise through substrate. 3. It is recommended that you use thick analog power metal. when connecting to PAD, and the path should be kept as short as possible. 4. Digital power and analog power are used separately. 5. When the core block is connected to other blocks, it must be double guardring using N-well and P+active to remove the substrate and coupling noise. In that case, the power metal should be connected to PAD directly. 6. Digital input signal lines must be same length to reduce the difference of delay. SEC ASIC 6/13 ANALOG COD0419X Sigma-Delta voice CODEC CORE EVALUATION GUIDE VDD25AD1 + C3 + VDD25AA1 C4 C4 + C3 + VSS25AD1 MUTE VSS25AA1 ALOOP ADPWD Analog Input - + RST R1 AMODIN X256FS C1 SYNC R1 AINFB Analog Output R1 SDECI<1:0> COD0419X APOSTOUT C2 + 2 TDECI DAPWD SINPO<1:0> 2 DSP Controller SDIN VREFOUT TPOST + C5+ C6 LCS CPSEL IREF SDOUT REFL DADS BCK ADHPB DAHPB LOCATION DESCRIPTION C6,C4 10µF CERAMIC CAPACITOR C1 0.33µF TANTALUM CAPACITOR C2 75pF CERAMIC CAPACITOR R1, R2 50kΩ RESISTOR R3 200kΩ RESISTOR C5,C3 0.1µF TANTALUM CAPACITOR <The Connection User Guide Line for Embedded Core Test> NOTES 1. If SDOUT is externally shorted with SDIN, The CODEC is achieved to loop-back test mode(ADC->DAC). 2. If end users want to test CODEC in integrated chip, The above pin must be extracted to the PAD. 3. The analog power/ground must be separated from digital power/ground. 4. CPSEL = 1 ;A-law select, 0 ;µ-law select 5. I/O TYPE PP and PG denote PAD Power and PAD Ground respectively. 6. Power typical value : VDD25AA1 = VDD25AD1 = 2.5V, VSS25AA1 = VSS25AD1 = 0.0V SEC ASIC 7 /13 ANALOG COD0419X Sigma-Delta voice CODEC CONTROL CLOCKS CHARACTERISTICS Characteristics Symbol Min Typ Max Unit X256FS Frequency Fmck - 2.048 - MHz BCK Frequency Fbck - 256 - KHz SYNC Frequency Fsync - 8 - KHz X256FS Duty cycle (H:L) MCDuty 40:60 50:50 60:40 % BCK Duty cycle (H:L) BCDuty 40:60 50:50 60:40 % SYNC Duty cycle (H:L) SYDuty 40:60 50:50 60:40 % X256FS Falling and BCK Edge Delay(Hold) Tdbck 5 10 15 ns X256FS Falling and SYNC Edge Delay(Hold) Tdsync 5 10 15 ns BCK Falling and SDOUT Delay Tdsdout 5 10 15 ns BCK Rising and SDIN Setup Tsetup 10 15 20 ns BCK Rising and SDIN Hold Thold 10 15 20 ns X256FS 0.5 VDD25AD1 SYNC 0.5 VDD25AD1 BCK 1/Fmck 0.5 VDD25AD1 1/Fbck X256FS 0.5 VDD25AD1 1/Fsync "H" "L" MCDuty BCK 0.5 VDD25AD1 "H" "L" SYNC 0.5 VDD25AD1 BCDuty "H" "L" SYDuty 0.5 BCK VDD25AD1 BCK 0.5 VDD25AD1 X256FS 0.5 VDD25AD1 X256FS0.5 VDD25AD1 Tdsync Tdbck Thold SDOUT 0.5 VDD25AD1 SDIN 0.5 VDD25AD1 BCK 0.5 VDD25AD1 BCK 0.5 VDD25AD1 Tsetup Tdsdout *Notes : BCK rising edge must NOT occur at the same time as SYNC edge. SEC ASIC 8 /13 ANALOG COD0419X Sigma-Delta voice CODEC TIMING DIAGRAM The frame of sync clock(SYNC) transitions determine the start of the serial data. Input data * All input data are clocked in by the falling edge of BCK. * 14bit, 2's complement or 8bit A-law, µ-law data format. Output data *All output data are clocked out by the falling edge of BCK. * 14bit, 2's complement or 8bit A-law, µ-law data format. Notes 1. SYNC clock is at sampling frequency, Fs 2. 14bit linear data has 16bit serial data format, this is accomplished by 16FS ( = Fs clock x 16 ) and two don't care bits are added from LSB, to fit into 16bit format. Fs Clock SYNC 16Fs 13 12 10 9 8 7 6 5 4 3 2 1 0 X X X : Non-valid data (0 insetion) X X X X X X X X : Non-valid data (0 insetion) 4 3 2 1 0 X X X : Don't care data X X X X X X X X : Don't care data SDOUT[ADC output](Linear data) 13 ; MSB, 0 ; LSB 7 6 7 ; MSB, 0 ; LSB 5 4 3 2 1 0 X SDOUT[ADC output](Compressed data) 13 12 13 ; MSB, 0 ; LSB 11 10 9 8 7 6 5 SDIN [DAC input](Linear data) 7 7 ; MSB, 0 ; LSB 11 BCK 6 5 4 3 2 1 0 X SDIN [DAC input](Compressed data) Codec serial interface timing diagram Fs SYNC 16Fs BCK 256Fs X256FS Codec clock interface timing diagram SEC ASIC 9 /13 ANALOG COD0419X Sigma-Delta voice CODEC INPUT/OUTPUT APPLICATION GUIDE 1. Input stage application guide R1 AINFB R1 C1 - + AMODIN Analog Input + Typical value of R1 and C1 R1 > 50KΩ C1 = 0.33µF 2. Output stage application guide R3 Speaker Driver Amp APOSTOUT C2 Ground How to determine the value of R3 and C2. C2 = 1.5*10-5/R3 For example : If you choose R3 as 200KΩ, then the value of C3 is 75pF. 3. VREFOUT port application guide VREFOUT C1 C2 Ground C1 = 0.1µF, C2 = 10µF * Note : The user should dispose the C1 and C2 as the order shown above and dispose the capacitors to VREFOUT pin as close as possibe. SEC ASIC 10/13 ANALOG COD0419X Sigma-Delta voice CODEC PHANTOM CELL INFORMATION VDD25AA1:P VSS25AA1:G ALOOP MUTE DADS VSS25AA1:G VSS25AD1:G VDD25AD1;P TPOST APOSTOUT VSS25AA1:G VSS25AA1:G VSS25AA1:G VSS25AA1:G VSS25AA1:G VSS25AA1:G SINPO[0] VSS25AA1:G VSS25AA1:G VSS25AA1:G SINPO[1] RST DAPWD VDD25AA1::P ADPWD ADHPB cod0419x DAHPB VDD25AA1::P VDD25AA1::P VDD25AA1::P VDD25AA1::P VDD25AA1::P VDD25AA1::P X256FS LCS VDD25AA1::P VDD25AA1::P REFL SDIN CPSEL IREF VREFOUT: VREFOUT: SYNC BCK VREFOUT: VREFOUT: SDOUT SDECI[1] AMODIN AINFB SDECI[0] TDECI SEC ASIC 11 /13 ANALOG COD0419X Sigma-Delta voice CODEC LAYOUT GUIDE ANALOG POWER:P ANALOG POWER:P ANALOG POWER:P PAD ANALOG POWER:P ANALOG GROUND:G PAD ANALOG GROUND:G ANALOG GROUND:G ANALOG GROUND:G SAME NAME PORT: SAME NAME PORT: SAME NAME PORT: SAME NAME PORT: Correct Examples : Each Same Name Port Should be Connected to PAD, Respectively. PAD ANALOG POWER:P ANALOG GROUND:G ANALOG GROUND:G ANALOG POWER:P PAD SAME NAME PORT: PAD PAD SAME NAME PORT: Wrong Examples : Each Same Name Port Merged together around GDS, and connected to together to PAD Analog Pads should be Placed as short as possible To GDS Analog Ports Digital Ports At least 50um Space recommended Digital Logics At least 50um Space recommended SEC ASIC • Digital Lines should not cross Analog lines 12 /13 ANALOG COD0419X Sigma-Delta voice CODEC FEEDBACK REQUEST It should be quite helpful to our CODEC core development if you specify your system requirements on CODEC in the following characteristic checking table and fill out the additional questions. We appreciate your interest in our products. Thank you very much. - Could you explain external/internal pin configurations as required? Specially requested function list : 1. What is your signal band to use, 3.6KHz? 4KHz? or 4.8KHz? 2. What is your analog in/output signal voltage swing? and what kind of format do your want as analog signal in/ouput: single or differential format? If you can, Please let us know, what is your exact in/output signal spec. 3. What is your minimum S/N+D spec? 4. Do you want linear phase characteristic or you don't care on digital filter spec? 5. Could you give us exact design spec of speech codec? (For example, A-law, µ-law and so on.) Datasheet Revision History Version Date 0.1 2002.04.23 SEC ASIC Modified Items Comments p11 : Phantom Cell Information added p12 : Layout Guide added 13/13 ANALOG