54AC299 • 54ACT299 8-Input Universal Shift/Storage Register with Common Parallel I/O Pins General Description The ’AC/’ACT299 is an 8-bit universal shift/storage register with TRI-STATE ® outputs. Four modes of operation are possible: hold (store), shift left, shift right and load data. The parallel load inputs and flip-flop outputs are multiplexed to reduce the total number of package pins. Additional outputs are provided for flip-flops Q0, Q7 to allow easy serial cascading. A separate active LOW Master Reset is used to reset the register. n Common parallel I/O for reduced pin count n Additional serial inputs and outputs for expansion n Four operating modes: shift left, shift right, load and store n TRI-STATE outputs for bus-oriented applications n Outputs source/sink 24 mA n ’ACT299 has TTL-compatible inputs n Standard Microcircuit Drawing (SMD) ’AC299: 5962-88754 ’ACT299: 5962-88771 Features n ICC and IOZ reduced by 50% Ordering Code: Logic Symbols Connection Diagrams Pin Assignment for DIP and Flatpak DS100252-1 IEEE/IEC DS100252-2 Pin Assignment for LCC DS100252-3 DS100252-4 TRI-STATE ® is a registered trademark of National Semiconductor Corporation. FACT ® is a registered trademark of Fairchild Semiconductor Corporation. © 1998 National Semiconductor Corporation DS100252 www.national.com 54ACC299 • 54ACT299 8-Input Universal Shift/Storage Register with Common Parallel I/O Pins September 1998 Connection Diagrams Pin Names (Continued) Description CP Clock Pulse Input DS0 Serial Data Input for Right Shift DS7 Serial Data Input for Left Shift S0, S1 Mode Select Inputs MR Asynchronous Master Reset OE1, OE2 TRI-STATE Output Enable Inputs I/O0–I/O7 Parallel Data Inputs or TRI-STATE Parallel Outputs Q0, Q7 Serial Outputs Functional Description Truth Table The ’AC/’ACT299 contains eight edge-triggered D-type flip-flops and the interstage logic necessary to perform synchronous shift left, shift right, parallel load and hold operations. The type of operation is determined by S0 and S1, as shown in the Truth Table. All flip-flop outputs are brought out through TRI-STATE buffers to separate I/O pins that also serve as data inputs in the parallel load mode. Q0 and Q7 are also brought out on other pins for expansion in serial shifting of longer words. A LOW signal on MR overrides the Select and CP inputs and resets the flip-flops. All other state changes are initiated by the rising edge of the clock. Inputs can change when the clock is in either state provided only that the recommended setup and hold times, relative to the rising edge of CP, are observed. A HIGH signal on either OE1 or OE2 disables the TRI-STATE buffers and puts the I/O pins in the high impedance state. In this condition the shift, hold, load and reset operations can still occur. The TRI-STATE buffers are also disabled by HIGH signals on both S0 and S1 in preparation for a parallel load operation. www.national.com Inputs Response MR S1 S0 CP L X X X Asynchronous Reset; Q0–Q7 = LOW H H H N H L H N Parallel Load; I/On → Qn Shift Right; DS0 → Q0, H H L N Shift Left, DS7 → Q7, Q7 → Q6, etc. H L L X Hold Q0 → Q1, etc. H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial N = LOW-to-HIGH Transition 2 Logic Diagram DS100252-5 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 3 www.national.com Absolute Maximum Ratings (Note 1) Recommended Operating Conditions If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VCC) DC Input Diode Current (IIK) VI = −0.5V VI = VCC +0.5V DC Input Voltage (VI) DC Output Diode Current (IOK) VO = −0.5V VO = VCC +0.5V DC Output Voltage (VO) DC Output Source or Sink Current (IO) DC VCC or Ground Current Per Output Pin (ICC or IGND) Storage Temperature (TSTG) Junction Temperature (TJ) CDIP Supply Voltage (VCC) (Unless Otherwise Specified) ’AC ’ACT Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) 54AC/ACT Minimum Input Edge Rate (∆V/∆t) ’AC Devices VIN from 30% to 70% of VCC VCC @ 3.3V, 4.5V, 5.5V Minimum Input Edge Rate (∆V/∆t) ’ACT Devices VIN from 0.8V to 2.0V VCC @ 4.5V, 5.5V −0.5V to +7.0V −20 mA +20 mA −0.5V to VCC +0.5V −20 mA +20 mA −0.5V to VCC +0.5V ± 50 mA ± 50 mA −65˚C to +150˚C 2.0V to 6.0V 4.5V to 5.0V 0V to VCC 0V to VCC −55˚C to +125˚C 125 mV/ns 125 mV/ns Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. Obviously the databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. National does not recommend operation of FACT ® circuits outside databook specifications. 175˚C DC Electrical Characteristics For ’AC Family Devices Symbol Parameter VCC 54AC TA = (V) −55˚C to +125˚C Units Conditions Guaranteed Limits VIH VIL VOH VOL IIN Minimum High Level 3.0 2.1 Input Voltage 4.5 3.15 5.5 3.85 Maximum Low Level 3.0 0.9 Input Voltage 4.5 1.35 5.5 1.65 Minimum High Level 3.0 2.9 Output Voltage 4.5 4.4 5.5 5.4 3.0 2.4 4.5 3.7 5.5 4.7 Maximum Low Level 3.0 0.1 Output Voltage 4.5 0.1 5.5 0.1 Maximum Input 3.0 0.50 4.5 0.50 5.5 0.50 5.5 ± 1.0 Leakage Current Note 2: All outputs loaded; threshold on input associated with output under test. www.national.com 4 VOUT = 0.1V V or VCC − 0.1V V or VCC − 0.1V VOUT = 0.1V IOUT = −50 µA V V (Note 2) VIN = VIL or VIH IOH = −12 mA IOH = −24 mA IOH = −24 mA IOUT = 50 µA V (Note 2) VIN = VIL or VIH IOH = 12 mA V µA IOH = 24 mA IOH = 24 mA VI = VCC, GND DC Electrical Characteristics For ’AC Family Devices Symbol Parameter VCC 54AC TA = (V) −55˚C to +125˚C Units Conditions Guaranteed Limits (Note 4) IOLD Minimum Dynamic 5.5 50 mA IOHD Output Current 5.5 −50 mA ICC Maximum Quiescent 5.5 80.0 µA VOLD = 1.65V Max VOHD = 3.85V Min VIN = VCC µA or GND VI(OE) = VIL, VIH VI = VCC, GND Supply Current IOZT Maximum I/O Leakage Current ± 5.5 5.5 VO = VCC, GND Note 3: All outputs loaded; threshold on input associated with output under test. Note 4: Maximum test duration 20 ms, one output loaded at a time. Note 5: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC. ICC for 54AC @ 25˚C is identical to 74AC @ 25˚C. DC Electrical Characteristics For ’ACT Family Devices Symbol Parameter VCC 54ACT TA = (V) −55˚C to +125˚C Units Conditions Guaranteed Limits VIH VIL VOH VOL IIN Minimum High Level 4.5 2.0 Input Voltage 5.5 2.0 Maximum Low Level 3.0 0.8 Input Voltage 4.5 0.8 Minimum High Level 4.5 4.4 5.5 5.4 4.5 3.70 5.5 4.70 Maximum Low Level 4.5 0.1 Output Voltage 5.5 0.1 Maximum Input V VOUT = 0.1V or VCC − 0.1V VOUT = 0.1V V or VCC − 0.1V IOUT = −50 µA V (Note 7) VIN = VIL or VIH IOH = −24 mA V IOH = −24 mA IOUT = 50 µA V (Note 7) VIN = VIL or VIH IOL = 24 mA 4.5 0.50 5.5 0.50 5.5 ± 1.0 µA IOL = 24 mA VI = VCC, GND 5.5 1.6 mA VI = VCC − 2.1V Leakage Current ICCT Maximum ICC/Input (Note 8) IOLD Minimum Dynamic 5.5 50 mA IOHD Output Current 5.5 −50 mA ICC Maximum Quiescent 5.5 80.0 µA VOLD = 1.65V Max VOHD = 3.85V Min VIN = VCC µA or GND VI(OE) = VIL, VIH VI = VCC, GND Supply Current IOZT Maximum I/O Leakage Current ± 5.0 5.5 VO = VCC, GND 5 www.national.com DC Electrical Characteristics (Continued) Note 6: ICC limit for 54ACT @ 25˚C is identical to 74ACT @ 25˚C. Note 7: All outputs loaded; thresholds on input associated with output under test. Note 8: Maximum test duration 2.0 ms, one output loaded at a time. Capacitance Symbol CIN CPD Typ Units Input Capacitance Parameter 4.5 pF Power Dissipation 170 pF Conditions VCC = 5.0V VCC = 5.5V Capacitance AC Electrical Characteristics 54AC TA = −55˚C VCC Symbol Parameter (V) to +125˚C CL = 50 pF (Note 9) Min fmax tPLH Maximum Input 3.3 70 Frequency 5.0 80 Fig. Units Max MHz Propagation Delay 3.3 1.0 25.5 CP to Q0 or Q7 5.0 1.0 17.5 ns (Shift Left or Right) tPHL Propagation Delay 3.3 1.0 26.5 CP to Q0 or Q7 5.0 1.0 18.0 ns ns (Shift Left or Right) tPLH tPHL tPHL tPHL tPZH tPZL tPHZ tPLZ Propagation Delay 3.3 1.0 24.5 CP to I/On 5.0 1.0 17.0 Propagation Delay 3.3 1.0 26.5 CP to I/On 5.0 1.0 18.5 Propagation Delay 3.3 1.0 27.0 MR to Q0 or Q7 5.0 1.0 18.5 Propagation Delay 3.3 1.0 26.5 MR to I/On 5.0 1.0 18.0 Output Enable Time 3.3 1.0 22.0 OE to I/On 5.0 1.0 15.0 Output Enable Time 3.3 1.0 23.5 OE to I/On 5.0 1.0 16.0 Output Disable Time 3.3 1.0 22.5 OE to I/On 5.0 1.0 17.0 Output Disable Time 3.3 1.0 21.5 OE to I/On 5.0 1.0 16.0 Note 9: Voltage Range 3.3 is 3.3V ± 0.3V. Voltage Range 5.0 is 5.0V ± 0.5V. www.national.com 6 ns ns ns ns ns ns ns No. AC Operating Requirements 54AC TA = −55˚C VCC Symbol Parameter (V) to +125˚C CL = 50 pF (Note 10) Fig. Units No. Guaranteed Minimum ts th ts th ts th tw tw trec Setup Time, HIGH or LOW 3.3 9.5 S0 or S1 to CP 5.0 7.0 Hold Time, HIGH or LOW 3.3 2.0 S0 or S1 to CP 5.0 2.5 Setup Time, HIGH or LOW 3.3 6.0 I/On to CP 5.0 4.0 Hold Time, HIGH or LOW 3.3 1.5 I/On to CP 5.0 2.0 Setup Time, HIGH or LOW 3.3 7.5 DS0 or DS7 to CP 5.0 5.0 Hold Time, HIGH or LOW 3.3 1.5 DS0 or DS7 to CP 5.0 1.5 CP Pulse Width, LOW 3.3 5.5 5.0 5.0 3.3 5.5 5.0 5.0 MR Pulse Width, LOW Recovery Time 3.3 2.5 MR to CP 5.0 2.5 ns ns ns ns ns ns ns ns ns Note 10: Voltage Range 3.3 is 3.3V ± 0.3V Voltage Range 5.0 is 5.0V ± 0.5V AC Electrical Characteristics 54ACT TA = −55˚C VCC Symbol Parameter (V) to +125˚C CL = 50 pF (Note 11) Min fmax Maximum Input Fig. Units No. Max 5.0 70 MHz 5.0 1.0 15.5 ns 5.0 1.0 16.0 ns 5.0 1.0 15.0 ns 5.0 1.0 18.0 ns 5.0 1.0 18.0 ns 5.0 1.0 17.5 ns Frequency tPLH Propagation Delay CP to Q0 or Q7 (Shift Left or Right) tPHL Propagation Delay CP to Q0 or Q7 (Shift Left or Right) tPLH Propagation Delay CP to I/On tPHL Propagation Delay CP to I/On tPHL Propagation Delay MR to Q0 or Q7 tPHL Propagation Delay MR to I/On 7 www.national.com AC Electrical Characteristics (Continued) 54ACT TA = −55˚C VCC Symbol Parameter (V) to +125˚C CL = 50 pF (Note 11) tPZH Output Enable Time Fig. Units Min Max 5.0 1.0 14.0 ns 5.0 1.0 14.5 ns 5.0 1.0 14.5 ns 5.0 1.0 14.0 ns No. OE to I/On tPZL Output Enable Time OE to I/On tPHZ Output Disable Time OE to I/On tPLZ Output Disable Time OE to I/On Note 11: Voltage Range 5.0 is 5.0V ± 0.5V AC Operating Requirements VCC Symbol Parameter (V) (Note 12) 54ACT TA = −55˚C to +125˚C CL = 50 pF Fig. Units Guaranteed Minimum ts Setup Time, HIGH or LOW 5.0 6.5 ns 5.0 1.5 ns 5.0 4.5 ns 5.0 1.5 ns 5.0 5.5 ns 5.0 1.5 ns 5.0 5.0 ns S0 or S1 to CP th Hold Time, HIGH or LOW S0 or S1 to CP ts Setup Time, HIGH or LOW I/On to CP th Hold Time, HIGH or LOW I/On to CP ts Setup Time, HIGH or LOW DS0 or DS7 to CP th Hold Time, HIGH or LOW DS0 or DS7 to CP tw CP Pulse Width HIGH or LOW tw MR Pulse Width, LOW 5.0 5.0 ns trec Recovery Time 5.0 1.5 ns MR to CP Note 12: Voltage Range 5.0 is 5.0V ± 0.5V. www.national.com 8 No. Physical Dimensions inches (millimeters) unless otherwise noted 20 Terminal Ceramic Leadless Chip Carrier (LCC) NS Package Number E20A 20 Lead Ceramic Dual-In-Line Package (J) NS Package Number J20A 9 www.national.com 54ACC299 • 54ACT299 8-Input Universal Shift/Storage Register with Common Parallel I/O Pins Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20 Lead Ceramic FLATPAK NS Package Number W20A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or sysdevice or system whose failure to perform can be reatems which, (a) are intended for surgical implant into sonably expected to cause the failure of the life support the body, or (b) support or sustain life, and whose faildevice or system, or to affect its safety or effectiveness. ure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 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