DS90C032B LVDS Quad CMOS Differential Line Receiver General Description Features TheDS90C032B is a quad CMOS differential line receiver designed for applications requiring ultra low power dissipation and high data rates. The device is designed to support data rates in excess of 155.5 Mbps (77.7 MHz) utilizing Low Voltage Differential Signaling (LVDS) technology. TheDS90C032B accepts low voltage (350 mV) differential input signals and translates them to CMOS (TTL compatible) output levels. The receiver supports a TRI-STATE ® function that may be used to multiplex outputs. The receiver also supports OPEN Failsafe and terminated (100Ω) input Failsafe with the addition of external failsafe biasing. Receiver output will be HIGH for both Failsafe conditions. The DS90C032Bprovides power-off high impedance LVDS inputs. This feature assures minimal loading effect on the LVDS bus lines when VCC is not present. The DS90C032Band companion line driver (DS90C031B) provide a new alternative to high power pseudo-ECL devices for high speed point-to-point interface applications. > 155.5 Mbps (77.7 MHz) switching rates Accepts small swing (350 mV) differential signal levels High Impedance LVDS inputs with power down Ultra low power dissipation 600 ps maximum differential skew (5V, 25˚C) 6.0 ns maximum propagation delay Industrial operating temperature range Available in surface mount packaging (SOIC) Pin compatible with DS26C32A, MB570 (PECL) and 41LF (PECL) n Supports OPEN and terminated input failsafe n Conforms to ANSI/TIA/EIA-644 LVDS standard Connection Diagram Functional Diagram n n n n n n n n n Dual-In-Line 10099001 Order Number DS90C032BTM See NS Package Number M16A 10099002 Receiver Truth Table INPUTS OUTPUT EN ENABLES EN* RIN+ − RIN− ROUT L H X Z VID ≥ 0.1V H VID ≤ −0.1V L Failsafe OPEN H All other combinations of ENABLE inputs or Terminated TRI-STATE ® is a registered trademark of National Semiconductor Corporation. © 2003 National Semiconductor Corporation DS100990 www.national.com DS90C032BLVDS Quad CMOS Differential Line Receiver September 2003 DS90C032B Absolute Maximum Ratings ESD Rating (Note 7) (Note 1) Supply Voltage (VCC) (EIAJ, 0 Ω, 200 pF) −0.3V to +6V Input Voltage (RIN+, RIN−) −0.3V to (VCC + 0.3V) Output Voltage (ROUT) −0.3V to (VCC + 0.3V) Maximum Package Power Dissipation @ +25˚C M Package 1025 mW Derate M Package Storage Temperature Range 8.2 mW/˚C above +25˚C Min Typ Max Units Supply Voltage (VCC) +4.5 +5.0 +5.5 V Receiver Input Voltage GND 2.4 V +85 ˚C Operating Free Air Temperature (TA) −65˚C to +150˚C DS90C032BT Lead Temperature Range Soldering (4 sec.) +260˚C Maximum Junction Temperature +150˚C ≥ 250V Recommended Operating Conditions −0.3V to +5.8V Enable Input Voltage (EN, EN*) ≥ 2kV (HBM, 1.5 kΩ, 100 pF) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. −40 +25 Electrical Characteristics Over Supply Voltage and Operating Temperature ranges, unless otherwise specified. (Notes 2, 3) Symbol Parameter VTH Differential Input High Threshold VTL Differential Input Low Threshold IIN Input Current Conditions VCM = +1.2V VIN = +2.4V Pin RIN+, RIN− VCC = 5.5V or 0V Output High Voltage IOH = −0.4 mA, VID = +200 mV VOL Output Low Voltage IOL = 2 mA, VID = −200 mV IOS Output Short Circuit Current Enabled, VOUT = 0V (Note 8) IOZ Output TRI-STATE Current Disabled, VOUT = 0V or VCC VIH Input High Voltage VIL Input Low Voltage II Input Current VCL Input Clamp Voltage ICL = −18 mA ICC No Load Supply Current EN, EN* = VCC or GND, Inputs Open Receivers Enabled No Load Supply Current Receivers Disabled ROUT IOH = −0.4 mA, Input terminated ICCZ www.national.com Max −100 Units mV mV −10 ±1 ±1 3.8 4.9 3.8 EN, EN* Typ +100 −10 VIN = 0V VOH Min +10 µA +10 µA V 4.9 V 0.07 0.3 V −15 −60 −100 mA −10 ±1 +10 µA 2.0 V 0.8 V +10 µA 3.5 10 mA EN, EN* = 2.4 or 0.5, Inputs Open 3.7 11 mA EN = GND, EN* = VCC, Inputs Open 3.5 10 mA 2 VCC −10 ±1 −1.5 −0.8 V VCC = +5.0V, TA = +25˚C (Notes 3, 4, 9) Min Typ Max Units tPHLD Symbol Differential Propagation Delay High to Low Parameter CL = 5 pF Conditions 1.5 3.40 5.0 ns tPLHD Differential Propagation Delay Low to High VID = 200 mV 1.5 3.48 5.0 ns tSKD Differential Skew |tPHLD − tPLHD| 0 80 600 ps tSK1 Channel-to-Channel Skew (Note 5) 0 0.6 1.0 ns tTLH Rise Time 0.5 2.0 ns tTHL Fall Time 0.5 2.0 ns tPHZ Disable Time High to Z RL = 2 kΩ 10 15 ns tPLZ Disable Time Low to Z CL = 10 pF 10 15 ns tPZH Enable Time Z to High tPZL Enable Time Z to Low (Figure 1 and Figure 2) (Figure 3 and Figure 4) 4 10 ns 4 10 ns Units Switching Characteristics VCC = +5.0V ± 10%, TA = −40˚C to +85˚C (Notes 3, 4, 9) Min Typ Max tPHLD Symbol Differential Propagation Delay High to Low Parameter CL = 5 pF 1.0 3.40 6.0 ns tPLHD Differential Propagation Delay Low to High VID = 200 mV 1.0 3.48 6.0 ns tSKD Differential Skew |tPHLD − tPLHD| 0 0.08 1.2 ns tSK1 Channel-to-Channel Skew (Note 5) 0 0.6 1.5 ns tSK2 Chip to Chip Skew (Note 6) 5.0 ns tTLH Rise Time 0.5 2.5 ns tTHL Fall Time 0.5 2.5 ns tPHZ Disable Time High to Z RL = 2 kΩ 10 20 ns CL = 10 pF 10 20 ns 4 15 ns 4 15 ns tPLZ Disable Time Low to Z tPZH Enable Time Z to High tPZL Enable Time Z to Low Conditions (Figure 1 and Figure 2) (Figure 3 and Figure 4) Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation. Note 2: Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground unless otherwise specified. Note 3: All typicals are given for: VCC = +5.0V, TA = +25˚C. Note 4: Generator waveform for all tests unless otherwise specified: f = 1 MHz, ZO = 50Ω, tr and tf (0%–100%) ≤ 1 ns for RIN and tr and tf ≤ 6 ns for EN or EN*. Note 5: Channel-to-Channel Skew is defined as the difference between the propagation delay of one channel and that of the others on the same chip with an event on the inputs. Note 6: Chip to Chip Skew is defined as the difference between the minimum and maximum specified differential propagation delays. Note 7: ESD Rating: HBM (1.5 kΩ, 100 pF) ≥ 2kV EIAJ (0Ω, 200 pF) ≥ 250V Note 8: Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only. Only one output should be shorted at a time, do not exceed maximum junction temperature specification. Note 9: CL includes probe and jig capacitance. Parameter Measurement Information 10099003 FIGURE 1. Receiver Propagation Delay and Transition Time Test Circuit 3 www.national.com DS90C032B Switching Characteristics DS90C032B Parameter Measurement Information (Continued) 10099004 FIGURE 2. Receiver Propagation Delay and Transition Time Waveforms 10099005 CL includes load and test jig capacitance. S1 = VCC for tPZL and tPLZ measurements. S1 = GND for tPZH and tPHZ measurements. FIGURE 3. Receiver TRI-STATE Delay Test Circuit 10099006 FIGURE 4. Receiver TRI-STATE Delay Waveforms www.national.com 4 DS90C032B Typical Application 10099007 FIGURE 5. Point-to-Point Application HIGH, stable output state for open inputs. 2. Terminated Input. TheDS90C032B requires external failsafe biasing for terminated input failsafe. Terminated input failsafe is the case of a receiver that has a 100Ω termination across its inputs and the driver is in the following situations. Unplugged from the bus, or the driver output is in TRI-STATE or in power-off condition. The use of external biasing resistors provide a small bias to set the differential input voltage while the line is un-driven, and therefore the receiver output will be in HIGH state. If the driver is removed from the bus but the cable is still present and floating, the unplugged cable can become a floating antenna that can pick up noise. The LVDS receiver is designed to detect very small amplitude and width signals and recover them to standard logic levels. Thus, if the cable picks up more than 10mV of differential noise, the receiver may respond. To insure that any noise is seen as commonmode and not differential, a balanced interconnect and twisted pair cables is recommended, as they help to ensure that noise is coupled common to both lines and rejected by the receivers. Applications Information LVDS drivers and receivers are intended to be primarily used in an uncomplicated point-to-point configuration as is shown in Figure 5. This configuration provides a clean signaling environment for the quick edge rates of the drivers. The receiver is connected to the driver through a balanced media which may be a standard twisted pair cable, a parallel pair cable, or simply PCB traces. Typically the characteristic impedance of the media is in the range of 100Ω. A termination resistor of 100Ω should be selected to match the media, and is located as close to the receiver input pins as possible. The termination resistor converts the current sourced by the driver into a voltage that is detected by the receiver. Other configurations are possible such as a multi-receiver configuration, but the effects of a mid-stream connector(s), cable stub(s), and other impedance discontinuities as well as ground shifting, noise margin limits, and total termination loading must be taken into account. TheDS90C032B differential line receiver is capable of detecting signals as low as 100 mV, over a ± 1V common-mode range centered around +1.2V. This is related to the driver offset voltage which is typically +1.2V. The driven signal is centered around this voltage and may shift ± 1V around this center point. The ± 1V shifting may be the result of a ground potential difference between the driver’s ground reference and the receiver’s ground reference, the common-mode effects of coupled noise, or a combination of the two. Both receiver input pins should honor their specified operating input voltage range of 0V to +2.4V (measured from each pin to ground), exceeding these limits may turn on the ESD protection circuitry which will clamp the bus voltages. 3. Operation in environment with greater than 10mV differential noise. National recommends external failsafe biasing on its LVDS receivers for a number of system level and signal quality reasons. First, only an application that requires failsafe biasing needs to employ it. Second, the amount of failsafe biasing is now an application design parameter and can be custom tailored for the specific application. In applications in low noise environments, they may choose to use a very small bias if any. For applications with less balanced interconnects and/or in high noise environments they may choose to boost failsafe further. Nationals "LVDS Owner’s Manual provides detailed calculations for selecting the proper failsafe biasing resistors. Third, the common-mode voltage is biased by the resistors during the un-driven state. This is selected to be close to the nominal driver offset voltage (VOS). Thus when switching between driven and un-driven states, the common-mode modulation on the bus is held to a minimum. For additional Failsafe Biasing information, please refer to Application Note AN-1194 for more detail. RECEIVER FAILSAFE The LVDS receiver is a high gain, high speed device that amplifies a small differential signal (20mV) to CMOS logic levels. Due to the high gain and tight threshold of the receiver, care should be taken to prevent noise from appearing as a valid signal. The receiver’s internal failsafe circuitry is designed to source/sink a small amount of current, providing failsafe protection (a stable known state of HIGH output voltage) for floating and terminated (100Ω) receiver inputs in low noise environment (differential noise < 10mV). 1. Open Input Pins. TheDS90C032B is a quad receiver device, and if an application requires only 1, 2 or 3 receivers, the unused channel(s) inputs should be left OPEN. Do not tie unused receiver inputs to ground or any other voltages. The input is biased by internal high value pull up and pull down resistors to set the output to a HIGH state. This internal circuitry will guarantee a The footprint of theDS90C032B is the same as the industry standard 26LS32 Quad Differential (RS-422) Receiver. For additional LVDS application information, please refer to National’s LVDS Owner’s Manual available through National’s website www.national.com/appinfo/lvds. 5 www.national.com DS90C032B Pin Descriptions Pin No. Name Description 2, 6, 10, 14 RIN+ Non-inverting receiver input pin 1, 7, 9, 15 RIN− Inverting receiver input pin 3, 5, 11, 13 ROUT Receiver output pin 4 EN Active high enable pin, OR-ed with EN* 12 EN* Active low enable pin, OR-ed with EN 16 VCC Power supply pin, +5V ± 10% 8 GND Ground pin Ordering Information Operating Package Type/ Temperature Number −40˚C to +85˚C SOP/M16A Order Number DS90C032BTM Typical Performance Characteristics Output High Voltage vs Power Supply Voltage Output High Voltage vs Ambient Temperature 10099008 10099009 Output Low Voltage vs Power Supply Voltage Output Low Voltage vs Ambient Temperature 10099010 www.national.com 10099011 6 DS90C032B Typical Performance Characteristics (Continued) Output Short Circuit Current vs Power Supply Voltage Output Short Circuit Current vs Ambient Temperature 10099012 10099013 Differential Propagation Delay vs Power Supply Voltage Differential Propagation Delay vs Ambient Temperature 10099014 10099015 Differential Skew vs Power Supply Voltage Differential Skew vs Ambient Temperature 10099017 10099016 7 www.national.com DS90C032B Typical Performance Characteristics (Continued) Transition Time vs Power Supply Voltage Transition Time vs Ambient Temperature 10099018 www.national.com 10099019 8 DS90C032BLVDS Quad CMOS Differential Line Receiver Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead (0.150" Wide) Molded Small Outline Package, JEDEC Order Number DS90C032BTM NS Package Number M16A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. 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