NSTB60ADW1T1 PNP General Purpose and NPN Bias Resistor Transistor Combination • • • • • Simplifies Circuit Design Reduces Board Space Reduces Component Count Available in 8 mm, 7 inch/3000 Unit Tape and Reel ESD Rating – Human Body Model: Class 1B ESD Rating – Machine Model: Class B http://onsemi.com (3) (2) (1) R1 R2 Q1 Q2 MAXIMUM RATINGS (TA = 25°C unless otherwise noted, common for Q1 and Q2) Rating Symbol Q1 Q2 Unit Collector-Emitter Voltage VCEO –50 50 Vdc Collector-Base Voltage VCBO –50 50 Vdc Emitter–Base Voltage VEBO –6.0 5.0 Vdc IC –150 150 mAdc Collector Current – Continuous (4) (5) 5 4 6 1 THERMAL CHARACTERISTICS Characteristic (One Junction Heated) Symbol Max Unit PD 187 (Note 1) 256 (Note 2) 1.5 (Note 1) 2.0 (Note 2) mW Total Device Dissipation TA = 25°C Derate above 25°C Thermal Resistance – Junction-to-Ambient Characteristic (Both Junctions Heated) RθJA 670 (Note 1) 490 (Note 2) 2 3 SOT–363 CASE 419B STYLE 1 mW/°C MARKING DIAGRAM °C/W 70d Symbol Max Unit PD 250 (Note 1) 385 (Note 2) 2.0 (Note 1) 3.0 (Note 2) mW Total Device Dissipation TA = 25°C Derate above 25°C mW/°C Thermal Resistance – Junction-to-Ambient RθJA 493 (Note 1) 325 (Note 2) °C/W Thermal Resistance – Junction-to-Lead RθJL 188 (Note 1) 208 (Note 2) °C/W TJ, Tstg –55 to +150 °C Junction and Storage Temperature (6) 70 = Specific Device Code d = Date Code ORDERING INFORMATION Device Package Shipping NSTB60ADW1T1 SOT–363 3000/Tape & Reel 1. FR–4 @ Minimum Pad 2. FR–4 @ 1.0 x 1.0 inch Pad Semiconductor Components Industries, LLC, 2002 March, 2002 – Rev. 1 1 Publication Order Number: NSTB60ADW1T1/D NSTB60ADW1T1 ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted) Characteristic Symbol Min Typ Max Unit Collector-Base Breakdown Voltage (IC = –50 µAdc, IE = 0) V(BR)CBO –50 – – Vdc Collector-Emitter Breakdown Voltage (IC = –1.0 mAdc, IB = 0) V(BR)CEO –50 – – Vdc Emitter–Base Breakdown Voltage (IE = –50 Adc, IE = 0) V(BR)EBO –6.0 – – Vdc Collector–Base Cutoff Current (VCB = –50 Vdc, IE = 0) ICBO – – –0.1 A Emitter–Base Cutoff Current (VEB = –6.0 Vdc, IB = 0) IEBO – – –0.1 A VCE(sat) – – –0.5 Vdc hFE 120 – 560 – fT – 140 – MHz COB – 3.5 – pF Collector-Base Breakdown Voltage (IC = 50 µA, IE = 0) V(BR)CBO 50 – – Vdc Collector-Emitter Breakdown Voltage (IC = 1.0 mA, IB = 0) (Note 3) V(BR)CEO 50 – – Vdc Collector–Base Cutoff Current (VCB = 50 V, IE = 0) ICBO – – 100 nAdc Collector–Emitter Cutoff Current (VCE = 50 V, IB = 0) ICEO – – 500 nAdc Emitter–Base Cutoff Current (VEB = 6.0 V, IC = 0) IEBO – – 0.15 mAdc VCE(sat) – – 0.25 Vdc hFE 40 – – Q1 Collector-Emitter Saturation Voltage (IC = –50 mAdc, IB = –5.0 mAdc) (Note 3) DC Current Gain (VCE = –10 V, IC = –5.0 mA) (Note 3) Transition Frequency (VCE = –12 Vdc, IC = –2.0 mAdc, f = 100 MHz) Output Capacitance (VCB = –12 Vdc, IE = 0 Adc, f = 1.0 MHz) Q2 Collector-Emitter Saturation Voltage (IC = 10 mA, IB = 5.0 mA) (Note 3) DC Current Gain (VCE = 10 V, IC = 5.0 mA) (Note 3) Output Voltage (on) (VCC = 5.0 V, VB = 4.0 V, RL = 1.0 k) (Note 3) VOL – – 0.2 Vdc Output Voltage (off) (VCC = 5.0 V, VB = 0.25 V, RL = 1.0 k) (Note 3) VOH 4.9 – – Vdc Input Resistor (Note 3) R1 32.9 47 61.1 kΩ Resistor Ratio (Note 3) R1/R2 3.76 4.7 5.64 3. Pulse Test: Pulse Width < 300 µs, Duty Cycle < 2.0% http://onsemi.com 2 NSTB60ADW1T1 Typical Electrical Characteristics – PNP Transistor -1.0 VCE = -10 V TA = 25°C 1.5 -0.9 1.0 0.7 0.5 -0.7 VBE(on) @ VCE = -10 V -0.6 -0.5 -0.4 -0.3 VCE(sat) @ IC/IB = 10 -0.1 0 -0.1 -0.2 -0.5 -1.0 -2.0 -5.0 -10 -20 -50 -100 -200 IC, COLLECTOR CURRENT (mAdc) Figure 1. Normalized DC Current Gain 10 400 300 200 VCE = -10 V TA = 25°C 100 80 -50 -100 Cib 7.0 150 -0.5 -1.0 -2.0 -5.0 -10 -20 IC, COLLECTOR CURRENT (mAdc) Figure 2. “Saturation” and “On” Voltages C, CAPACITANCE (pF) f T, CURRENT-GAIN BANDWIDTH PRODUCT (MHz) VBE(sat) @ IC/IB = 10 -0.2 0.3 0.2 -0.2 60 40 5.0 TA = 25°C 3.0 Cob 2.0 30 20 -0.5 -1.0 -2.0 -3.0 -5.0 -10 -20 -30 IC, COLLECTOR CURRENT (mAdc) 1.0 -0.4 -0.6 -50 Figure 3. Current–Gain – Bandwidth Product 0.3 r b′, BASE SPREADING RESISTANCE (OHMS) 0.5 VCE = -10 V f = 1.0 kHz TA = 25°C 0.1 0.05 0.03 0.01 -0.1 -0.2 -0.5 -1.0 -2.0 -5.0 IC, COLLECTOR CURRENT (mAdc) -1.0 -2.0 -4.0 -6.0 -10 -20 -30 -40 VR, REVERSE VOLTAGE (VOLTS) Figure 4. Capacitances 1.0 hob, OUTPUT ADMITTANCE (OHMS) TA = 25°C -0.8 V, VOLTAGE (VOLTS) hFE, NORMALIZED DC CURRENT GAIN 2.0 -10 150 140 130 VCE = -10 V f = 1.0 kHz TA = 25°C 120 110 100 -0.1 Figure 5. Output Admittance -0.2 -0.3 -0.5 -1.0 -2.0 -3.0 -5.0 IC, COLLECTOR CURRENT (mAdc) Figure 6. Base Spreading Resistance http://onsemi.com 3 -10 NSTB60ADW1T1 1000 100 hFE, DC CURRENT GAIN VCE(sat), MAXIMUM COLLECTOR VOLTAGE (V) Typical Electrical Characteristics – NPN BRT TA = –40°C 10 25°C 85°C 1 0.1 TA = 85°C 25°C IC/IB = 10 0.01 0 10 30 40 50 60 20 IC, COLLECTOR CURRENT (mA) 70 –40°C 100 10 80 VCE = 10 V 10 IC, COLLECTOR CURRENT (mA) 1 Figure 7. Maximum Collector Voltage versus Collector Current Figure 8. DC Current Gain 3 100 Vin, INPUT VOLTAGE (V) f = 1 MHz TA = 25°C 2.5 2 1.5 1 TA = –40°C 25°C 85°C 10 0.5 1 0 0 10 20 30 40 VR, REVERSE VOLTAGE (V) 50 0 60 Figure 9. Output Capacitance 10 20 30 40 50 IC, COLLECTOR CURRENT (mA) TA = –40°C 85°C 10 25°C Vo = 0.2 V 1 0 10 60 Figure 10. Input Voltage versus Output Voltage 100 Vin, INPUT VOLTAGE (V) Cob, CAPACITANCE (pF) 100 20 30 40 50 IC, COLLECTOR CURRENT (mA) 60 Figure 11. Input Voltage versus Output Current http://onsemi.com 4 NSTB60ADW1T1 INFORMATION FOR USING THE SOT–363 SURFACE MOUNT PACKAGE MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to insure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will self align when subjected to a solder reflow process. ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ 0.65 mm 0.65 mm 0.4 mm (min) 0.5 mm (min) 1.9 mm SOT–363 SOT–363 POWER DISSIPATION SOLDERING PRECAUTIONS The power dissipation of the SOT–363 is a function of the pad size. This can vary from the minimum pad size for soldering to a pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RθJA, the thermal resistance from the device junction to ambient, and the operating temperature, TA. Using the values provided on the data sheet for the SOT–363 package, PD can be calculated as follows: PD = The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. • Always preheat the device. • The delta temperature between the preheat and soldering should be 100°C or less.* • When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10°C. • The soldering temperature and time shall not exceed 260°C for more than 10 seconds. • When shifting from preheating to soldering, the maximum temperature gradient shall be 5°C or less. • After soldering has been completed, the device should be allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. • Mechanical stress or shock should not be applied during cooling. TJ(max) – TA RθJA The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into the equation for an ambient temperature TA of 25°C, one can calculate the power dissipation of the device which in this case is 256 milliwatts. PD = 150°C – 25°C 490°C/W = 256 milliwatts The 490°C/W for the SOT–363 package assumes the use of the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 256 milliwatts. There are other alternatives to achieving higher power dissipation from the SOT–363 package. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Clad. Using a board material such as Thermal Clad, an aluminum core board, the power dissipation can be doubled using the same footprint. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. http://onsemi.com 5 NSTB60ADW1T1 SOLDER STENCIL GUIDELINES The stencil opening size for the surface mounted package should be the same as the pad size on the printed circuit board, i.e., a 1:1 registration. Prior to placing surface mount components onto a printed circuit board, solder paste must be applied to the pads. A solder stencil is required to screen the optimum amount of solder paste onto the footprint. The stencil is made of brass or stainless steel with a typical thickness of 0.008 inches. TYPICAL SOLDER HEATING PROFILE The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177–189°C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints. For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones, and a figure for belt speed. Taken together, these control settings make up a heating “profile” for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 12 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. STEP 1 PREHEAT ZONE 1 RAMP" 200°C 150°C STEP 5 STEP 4 HEATING HEATING ZONES 3 & 6 ZONES 4 & 7 SPIKE" SOAK" STEP 2 STEP 3 VENT HEATING SOAK" ZONES 2 & 5 RAMP" DESIRED CURVE FOR HIGH MASS ASSEMBLIES 205° TO 219°C PEAK AT SOLDER JOINT 170°C 160°C 150°C 140°C 100°C 100°C 50°C STEP 6 STEP 7 VENT COOLING SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY) DESIRED CURVE FOR LOW MASS ASSEMBLIES TIME (3 TO 7 MINUTES TOTAL) TMAX Figure 12. Typical Solder Heating Profile http://onsemi.com 6 NSTB60ADW1T1 PACKAGE DIMENSIONS SOT–363 CASE 419B–02 ISSUE J A NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. G 6 5 4 1 2 3 DIM A B C D G H J K N S –B– S D 6 PL 0.2 (0.008) M B M N J C H K http://onsemi.com 7 INCHES MIN MAX 0.071 0.087 0.045 0.053 0.031 0.043 0.004 0.012 0.026 BSC --0.004 0.004 0.010 0.004 0.012 0.008 REF 0.079 0.087 STYLE 1: PIN 1. 2. 3. 4. 5. 6. EMITTER 2 BASE 2 COLLECTOR 1 EMITTER 1 BASE 1 COLLECTOR 2 MILLIMETERS MIN MAX 1.80 2.20 1.15 1.35 0.80 1.10 0.10 0.30 0.65 BSC --0.10 0.10 0.25 0.10 0.30 0.20 REF 2.00 2.20 NSTB60ADW1T1 Thermal Clad is a registered trademark of the Bergquist Company. ON Semiconductor is a trademark and is a registered trademark of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. PUBLICATION ORDERING INFORMATION Literature Fulfillment: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303–675–2175 or 800–344–3860 Toll Free USA/Canada Fax: 303–675–2176 or 800–344–3867 Toll Free USA/Canada Email: [email protected] JAPAN: ON Semiconductor, Japan Customer Focus Center 4–32–1 Nishi–Gotanda, Shinagawa–ku, Tokyo, Japan 141–0031 Phone: 81–3–5740–2700 Email: [email protected] ON Semiconductor Website: http://onsemi.com For additional information, please contact your local Sales Representative. N. American Technical Support: 800–282–9855 Toll Free USA/Canada http://onsemi.com 8 NSTB60ADW1T1/D