PRODUCT SPECIFICATIONS
®
Integrated Circuits Group
LH28F160S5T-L70A
Flash Memory
16M (2MB × 8/1MB × 16)
(Model No.: LHF16KA9)
Spec No.: EL127112A
Issue Date: August 29, 2000
SHARF’
LHF16KA9
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l Handle this document carefully for it contains material protected by international copyright
law. Any reproduction, full or in part, of this material is prohibited without the express
written permission of the company.
l When using the products covered herein, please observe the conditions written herein
and the precautions outlined in the following paragraphs. In no event shall the company
be liable for any damages resulting from failure to strictly adhere to these conditions and
precautions.
(1) The products covered herein are designed and manufactured for the following
application areas. When using the products covered herein for the equipment listed
in Paragraph (2), even for the following application areas, be sure to observe the
precautions given in Paragraph (2). Never use the products for the equipment listed
in Paragraph (3).
4 *Office electronics
l instrumentation and measuring equipment
*Machine tools
l Audiovisual equipment
l Home appliance
*Communication equipment other than for trunk lines
(2) Those contemplating using the products covered herein for the following equipment
which demands high reliability, should first contact a sales representative of the
company and then accept responsibility for incorporating into the design fail-safe
operation, redundancy, and other appropriate measures for ensuring reliability and
safety of the equipment and the overall system.
+ntrol
and safety devices for airplanes, trains, automobiles, and other
transportation equipment
*Mainframe computers
iraff ic control systems
@Gasleak detectors and automatic cutoff devices
oRescue and security equipment
l Other safety devices and safety equipment, etc.
l
(3) Do not use the products covered herein for the following equipment which demands
extremely high performance in terms of functionality, reliability, or accuracy.
*Aerospace equipment
*Communications equipment for trunk lines
aControl equipment for the nuclear power industry
*Medical equipment related to life support, etc.
(4) Please direct all queries and comments regarding the interpretation of the above
three Paragraphs to a sales representative of the company.
l Please direct all queries regarding the products covered herein to a sales representative
of the company.
Rev.1.9
SHARP
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LHFlGKA9
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CONTENTS
PAGE
.....................................................
3
1.l Product Overview ................................................
3
2 PRINCIPLES OF OPERATION.. ..............................
2.1 Data Protection ...................................................
6
7
3 BUS OPERATION ....................................................
3.1 Read ...................................................................
3.2 O&put Disable ....................................................
3.3 Standby.. .............................................................
3.4 Deep Power-Down ..............................................
3.5 Read Identifier Codes Operation.. ......... . .............
3.6 Query Operation ..................................................
7
I INTRODUCTION.
3.7 Write ....................................................................
1 COMMAND DEFINITIONS.. .....................................
4.1 Read Array Command.. .....................................
4.2 Read Identifier Codes Command.. ....................
4.3 Read Status Register Command.. .....................
4.4 Clear Status Register Command.. .....................
4.5 Query Command, ...............................................
4.51 Block Status Register ..................................
4.5.2 CFI CIuery Identification Stiing.. ...................
7
7
7
7
8
8
8
8
11
11
11
11
12
12
13
4.5.3 System Interface Information.. .....................
4.5.4 Device Geometry Definition .........................
13
14
4.5.5 SCS OEM Specific Extended Query Table..
4.6 Block Erase Command ......................................
4.7 Full Chip Erase Command ................................
4.8 Word/Byte Write Command.. .............................
4.9 Multi Word/Byte Write Command.. ....................
4.10 Block Erase Suspend Command.. ...................
14
15
15
16
16
17
4.11 (Multi) Word/Byte Write Suspend Command ...
4.12 Set Block Lock-Bit Command.. ........................
4.13 Clear Block Lock-Bits Command.. ...................
4.14 STS Configuration Command .........................
17
18
18
19
PAGE
5 DESIGN CONSIDERATIONS
................................
.30
5.1 Three-Line Output Control ................................ .30
5.2 STS and Block Erase, Full Chip Erase, (Multi)
Word/Byte Write and Block Lock-Bit Configuration
Polling.. .............................................................
.30
5.3 Power Supply Decoupling.. ............................... .30
5.4 V,, Trace on Printed Circuit Boards.. ............... .30
5.5 V,,, V,,, RP# Transitions.. .............................. .31
5.6 Power-Up/Down Protection.. ............................. .31
5.7 Power Dissipation .............................................
6 ELECTRICAL
SPECIFICATIONS..
........................
6.1 Absolute Maximum Ratings ..............................
6.2 Operating Conditions ........................................
6.2.1 Capacitance ................................................
6.2.2 AC Input/Output Test Conditions.. ...............
.31
.32
.32
.32
.32
.33
6.2.3 DC Characteristics.. .....................................
.34
6.2.4 AC Characteristics - Read-Only Operations .36
6.2.5
6.2.6
6.2.7
6.2.8
AC Characteristics - Write Operations.. .......
Alternative CE#-Controlled Writes.. .............
Reset Operations ........................................
Block Erase, Full Chip Erase, (Multi)
Word/Byte Write and Block Lock-Bit
Configuration Performance.. ........................
7 ADDITIONAL INFORMATION ...............................
7.1 Ordering Information .........................................
.39
.41
.43
.44
.45
.45
Rev. 1.9
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LH28F160S5T-L70A
1 GM-BIT (2MBx8/1 MBxl6)
Smart 5 Flash MEMORY
n Smart 5 Technology
- 5v vcc
- 5v vpp
n
Enhanced Data Protection Features
- Absolute Protection with Vpp=GND
- Flexible Block Locking
- Erase/Write Lockout during Power
Transitions
n
Extended Cycling Capability
- 100,000 Block Erase Cycles
- 3.2 Million Block Erase Cycles/Chip
n
Low Power Management
- Deep Power-Down Mode
- Automatic Power Savings Mode
Decreases ICC in Static Mode
n Common Flash Interface (CFI)
- Universal & Upgradable Interface
I
Scalable Command Set (SCS)
I
High Speed Write Performance
- 32 Bytes x 2 plane Page Buffer
- 2ps/Byte Write Transfer Rate
n High Speed Read Performance
- 70ns(5V*0.25V), 80ns(5V*0.5V)
n Operating Temperature
- 0°C to +7O”C
I
Enhanced Automated Suspend Options
- Write Suspend to Read
- Block Erase Suspend to Write
- Block Erase Suspend to Read
n High-Density Symmetrically-Blocked
Architecture
- Thirty-two 64K-byte Erasable Blocks
n Automated Write and Erase
- Command User Interface
- Status Register
n Industry-Standard Packaging
- 56-Lead TSOP
n ETOXrM* V Nonvolatile
Technology
Flash
l
I
SRAM-Compatible
Write Interface
I
User-Configurable
x8 or x16 Operation
n CMOS Process
(P-type silicon substrate)
n
Not designed or rated as radiation
hardened
SHARP’s LH28F160S5T-L70A
Flash memory with Smart 5 technology is a high-density, low-cost, nonvolatile,
,ead/write storage solution for a wide range of applications. Its symmetrically-blocked architecture, flexible voltage
and extended cycling provide for highly flexible component suitable for resident flash arrays, SlMMs and memory
:ards. Its enhanced suspend capabilities provide for an ideal solution for code + data storage applications. For
secure code storage applications, such as networking, where code is either directly executed out of flash or
downloaded to DRAM, the LH28F160S5T-L70A
offers three levels of protection: absolute protection with V,, at
3ND, selective hardware block locking, or flexible software block locking. These alternatives give designers
Jltimate control of their code security needs.
The LH28F160S5T-L70A is conformed to the flash Scalable Command Set (SCS) and the Common Flash Interface
CFI) specification which enable universal and upgradable interface, enable the highest system/device data transfer
*ates and minimize device and system-level implementation costs.
The LH28F160S5T-L70A
is manufactured on SHARP’s 0.35um ETOX TM* V process technology.
ndustry-standard package: the 56-Lead TSOP, ideal for board constrained applications.
It come in
‘ETOX is a trademark of Intel Corporation.
Rev.1.9
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1 INTRODUCTION
execute code from any other flash memory
location.
LH28F160S5T-L70A
This
datasheet
contains
specifications. Section 1 provides a flash memory
overview. Sections 2, 3, 4, and 5 describe the
memory organization and functionality. Section 6
covers electrical specifications.
1.1 Product Overview
The LH28F160S&T-L70A is a high-performance 16Mbit Smart
5 Flash memory
organized
as
2MBx8/1 MBxl6. The 2MB of data is arranged in
thirty-two 64K-byte blocks which are individually
erasable, lockable, and unlockable in-system. The
memory map is shown in Figure 3.
i
Smart 5 technology provides a choice of V,, and
V,, combinations, as shown in Table 1, to meet
system performance and power expectations. 5V V,,
provides the highest read performance. V,, at 5V
eliminates the need for a separate 12V converter,
while
V,,=5V
maximizes
erase
and
write
performance.
In addition to flexible erase and
program voltages, the dedicated V,, pin gives
complete data protection when V,+V,,Lk.
I
Table 1. Vcc.and VP, Voltage Combinations
Offered by Smart 5 Technology
Vcr: Voltage
Vpp Voltage
5v
5v
Internal
detection
Circuitry
VCC. and
VW
automatically configures the device for optimized
read and writeoperations.
A Command User Interface (CUI) serves as the
interface between the system processor and internal
operation of the device. A valid command sequence
written to the CUI initiates device automation. An
internal Write State Machine (WSM) automatically
executes the algorithms and timings necessary for
block erase, full chip erase, (multi) word/byte write
and block lock-bit configuration operations.
A block erase operation erases one of the device’s
64K-byte blocks typically within 0.34s (5V Voo, 5V
V,,) independent of other blocks. Each block can be
independently
erased 100,000 times (3.2 million
block erases per device). Block erase suspend mode
allows system software to suspend block erase to
read or write data from any other block.
A word/byte write is performed in byte increments
typically within 9.24us (5V Vcc, 5V Vpp). A multi
word/byte write has high speed write performance of
2uslbyte (5V Vcc, 5V V,,). (Multi) Word/byte write
suspend mode enables the system to read data or
,
1
arrayI
Individual block locking uses a combination of bit:
and WP#, Thirty-two block lock-bits, to lock ant
unlock blocks. Block lock-bits gate block erase, ful
chip erase and (multi) word/byte write operations
Block lock-bit configuration operations (Set BlocE
Lock-Bit and Clear Block Lock-Bits commands) se
and cleared block lock-bits.
The status register indicates when the WSM’s block
erase, full chip erase, (multi) word/byte write or block
lock-bit configuration operation is finished.
The STS output gives an additional indicator of WSM
activity by providing both a hardware signal of status
(versus software
polling) and status masking
(interrupt masking for background block erase, for
example). Status polling using STS minimizes both
CPU overhead and system power consumption. STS
pin can be configured to different states using the
Configuration command. The STS pin defaults tc
RY/BY# operation. When low, STS indicates that the
WSM is performing a block erase, full chip erase,
(multi) word/byte write or block lock-bit configuration.
STS-High Z indicates that the WSM is ready for a
new command, block erase is suspended and (multi)
word/byte write are inactive, (multi) word/byte write
are suspended, or the device is in deep power-down
mode. The other 3 alternate configurations are all
pulse mode for use as a system interrupt.
The access time is 70ns (tAvQv) over the commercial
temperature range (0% to +7O”C) and Vc, supply
voltage range of 4.75V-5.25V. At lower Voc voltage,
the access time is 80ns (45V-55V).
The Automatic
Power Savings (APS) feature
substantially reduces active current when the device
is in static mode (addresses not switching). In APS
m-ode, the typical lCCR current is 1 mA at 5V V,,.
When either CE,# or CE,#, and RP# pins are at Vcc,
the I,, CMOS standby mode is enabled. When the
RP# pin is at GND, deep power-down mode is
enabled which minimizes power consumption and
provides write protection during reset. A reset time
(tPHav) is required from RP# switching high until
outputs are valid. Likewise, the device has a wake
time (tpHEL) from RP#-high until writes to the CUI are
recognized. With RP# at GND, the WSM is reset and
the status register is cleared.
The device is available in 56-Lead TSOP (Thin Small
Outline Package, 1.2 mm thick). Pinout is shown in
Figure 2.
Rev. 1.9
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LHFlGKA9
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CE#
WEW
OE#
RP#
WP#
STS
VW
+L kc
+-
GND
Figure 1. Block Diagram
VPP
RP#
Ail
40
2
GND
A7
%
A5
6
‘7
8
9
10
11
12
13
14
15
16
17
18
20
19
56 LEAD TSOP
STANDARD PINOUT
14mm x 20mm
TOP VIEW
21
22
23
24
2
26
25
A2
Al
Iz:
56
55
54
53
52
51
50 b
49
48
47
46
45
44
43
42
41 b
WP#
WE#
OE#
STS
DQts
DC27
Da;,
DQ,
VCC
GND
DQII
39
40
38
37
:::.
36
35
34
33
32
31
30
29
Ei:
DQ,
DQ2
vcc
DQo
43
BYTE#
NC
NC
Figure 2. TSOP 56-Lead Pinout (Normal Bend)
J
Rev.
1.9
SHARI=
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r
Symbol
*o-*20
Type
INPUT
XJo-DQ,
INPUT/
OUTPUT
CE,#,
CE,#
INPUT
RP#
INPUT
OE#
INPUT
WE#
INPUT
STS
OPEN
DRAIN
OUTPUT
WP#
INPUT
BYTE#
INPUT
“PP
SUPPLY
“cc
SUPPLY
GND
NC
SUPPLY
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LHFlGKA9
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Table 2. Pin Descriptions
Name and Function
ADDRESS INPUTS: Inputs for addresses during read and write operations. Addresses are
internally latched during a write cycle.
Ao: Byte Select Address. Not used in x16 mode(can be floated).
AI-AK Column Address. Selects 1 of 16 bit lines.
As-At!% Row Address. Selects 1 of 2048 word lines.
A16420
: Block Address.
DATA INPUT/OUTPUTS:
DQo-DC&Inputs data and commands during CUI write cycles; outputs data during memory
array, status register, query, and identifier code read cycles. Data pins float to highimpedance when the chip is deselected or outputs are disabled. Data is internally latched
during a write cycle.
DQs-DQ15:lnputs data during CUI write cycles in x16 mode; outputs data during memory
array read cycles in xl 6 mode; not used for status register, query and identifier code read
mode. Data pins float to high-impedance when the chip is deselected, outputs are
disabled, or in x8 mode(Byte#=V,, ). Data is internally latched during a write cycle.
CHIP ENABLE: Activates the device’s control logic, input buffers decoders, and sense
amplifiers. Either CEO# or CE,# VIH deselects the device and reduces power consumption
to standby levels. Both CEn# and CE,# must be VII to select the devices.
RESET/DEEP POWER-DOWN: Puts the device in deep power-down mode and resets
internal automation. RP# VI, enables normal operation. When driven V,,, RP# inhibits
write operations which provides data protection during power transitions. Exit from deep
power-down sets the device to read array mode.
OUTPUT ENABLE: Gates the device’s outputs during a read cycle.
WRITE ENABLE: Controls writes to the CUI and array blocks. Addresses and data are
latched on the rising edge of the WE# pulse.
STS (RY/BY#): Indicates the status of the internal WSM. When configured in level mode
(default mode), it acts as a RY/BY# pin. When low, the WSM is performing an internal
operation (block erase, full chip erase, (multi) word/byte write or block lock-bit
configuration). STS High Z indicates that the WSM is ready for new commands, block
erase is suspended, and (multi) word/byte write is inactive, (multi) word/byte write is
suspended or the device is in deep power-down mode. For alternate configurations of the
STATUS pin, see the Configuration command.
WRITE PROTECT: Master control for block locking. When VI,, Locked blocks can not be
erased and programmed, and block lock-bits can not be set and reset.
BYTE ENABLE: BYTE# V,, places device in x8 mode. All data is then input or output on
DQO-,, and DQ8-t5 float. BYTE# V,, places the device in x16 mode , and turns off the Ac
input buffer.
BLOCK ERASE, FULL CHIP ERASE, (MULTI) WORD/BYTE WRITE. BLOCK LOCKBIT CONFIGURATION POWER SUPPLY: For erasing array blocks, writing bytes or
configuring block lock-bits. With Vpp<V+pLK, memory contents cannot be altered. Block
erase, full chip erase, (multi) word/byte write and block lock-bit configuration with an invalid
Vpp (see DC Characteristics) produce spurious results and should not be attempted.
DEVICE POWER SUPPLY: Internal detection configures the device for 5V operation. Do
notfloat any power pins. With VCCIVLKO, all write attempts to the flash memory are
inhibited. Device operations at invalid Vcc voltage (see DC Characteristics) produce
spurious results and should not be attempted.
GROUND: Do not float any ground pins.
NO CONNECT: Lead is not internal connected; it may be driven or floated.
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2 PRINCIPLES &OPERATION
The LH28F160S5T-L70A
Flash memory includes an
on-chip WSM to manage block erase, full chip erase,
write
and
block
lock-bit
(multi)
word/byte
configuration functions. It allows for: 100% TTL-level
control inputs, fixed power supplies during block
erase, full chip erase, (multi) word/byte write and
block lock-bit configuration, and minimal processor
overhead with RAM-Like interface timings.
After initial device power-up or return from deep
power-down mode (see Bus Operations), the device
defaults to read array mode. Manipulation of external
memory control pins allow array read, standby, and
output disable operations.
Status bgister, query structure and identifier codes
can be accessed through the CUI independent of the
VP, voltage. High voltage on VP, enables successful
block erase, full chip erase, (multi) word/byte write
and block lock-bit configuration.
All functions
associated with altering memory contents--block
erase, full chip erase, (multi) word/byte write and
block lock-bit configuration,
status, query and
identifier codes-are
accessed via the CUI and
verified through the status register.
written
standard
Commands
are
using
microprocessor write timings. The CUI contents serve
as input to the WSM, which controls the block erase,
full chip erase, (multi) word/byte write and block lockbit configuration.
The internal algorithms
are
regulated by the WSM, including pulse repetition,
and mar ining of data.
internal
verification,
Addresses and data are internally 91atch during write
cycles. Writing the appropriate command outputs
array data, accesses the identifier codes, outputs
query structure or outputs status register data.
Interface software that initiates and polls progress of
block erase, full chip erase, (multi) word/byte write
and block lock-bit configuration can be stored in any
block. This code is copied to and executed from
system RAM during flash memory updates. After
successful completion, reads are again possible via
the Read Array command. Block erase suspend
allows system software to suspend a block erase to
*cad or write data from any other block. Write
suspend allows system software to suspend a (multi)
Nerd/byte write to read data from any other flash
nemory array location.
Figure 3. Memory Map
Rev. 1.9
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2.1 Data Protection
3.2 Output Disable
Depending on the application, the system designer
may choose to make the V,,
power supply
switchable (available only when block erase, full chip
erase, (multi) word/byte write and block lock-bit
configuration are required) or hardwired to V,,,,.
The device accommodates either design practice and
encourages optimization of the processor-memory
interface.
With OE# at a logic-high level (VI,), the device
outputs are disabled. Output pins DQo-DQ,, are
placed in a high-impedance state.
When Vpp~VppLK,memory
contents cannot be
altered. The CUI, with multi-step block erase, full chip
erase, (multi) word/byte write and block lock-bit
sequences,
provides
configuration
command
protection from unwanted operations even when high
voltage ,is applied to V,,. All write functions are
disabled when V,, is below the write lockout voltage
VLKO or when RP# is at V,,. The device’s block
locking capability provides additional protection from
inadvertent code or data alteration by gating block
erase, full chip erase and (multi) word/byte write
operations.
3 BUS OPERATION
The local CPU reads and writes flash memory insystem. All bus cycles to or from the flash memory
conform to standard microprocessor bus cycles.
3.1 Read
Information can be read from any block, identifier
codes, query structure;gr status register independent
of the V,, voltyge. RP# must be at V,,.
The first task is to write the appropriate read mode
command (Read Array, Read Identifier Codes, Query
or Read Status Register) to the CUI. Upon initial
device power-up or after exit from deep power-down
mode, the device automatically resets to read array
mode. Five control pins dictate the data flow in and
out of the component: CE# (CEo#, CE,#), OE#, WE#,
RP# and WP#. CE,#, CE,# and OE# must be driven
active to obtain data at the outputs. CE,#, CE,# is
ihe device selection control, and when active enables
the selected memory device. OE# is the data output
(DQo-DQ,,) control and when active drives the
selected memory data onto the I/O bus. WE# and
SP# must be at VI,. Figure 17, 18 illustrates a read
:ycle.
3.3 Standby
Either CE,# or CE,# at a logic-high level (V,,) place:
the device in standby mode which substantial!
reduces device power consumption.
DQo-DQ,
outputs are placed in a high-impedance
state
independent of OE#. If deselected during bloc1
erase, full chip erase, (multi) word/byte write am
block lock-bit configuration, the device continue:
functioning, and consuming active power until the
operation completes.
3.4 Deep Power-Down
RP# at V,, initiates the deep power-down mode.
In read modes, RP#-low deselects the memory
places output drivers in a high-impedance state ant
turns off all internal circuits. RP# must be held low fo
a minimum of 100 ns. Time tpHQv is required afte,
return from power-down until initial memory access
outputs are valid. After this wake-up interval, norma
operation is restored. The CUI is reset to read arra)
mode and status register is set to 80H.
During block erase, full chip erase, (multi) word/byte
write or block lock-bit configuration modes, RP#-Ion
will abort the operation. STS remains low until the
reset operation is complete. Memory contents beins
altered are no longer valid; the data may be partialI]
erased or written. Time t,,,,
is required after RP#I
goes to logic-high (V,,) before another command car
be written.
As with any automated device, it is important tc
a$sert RP# during system reset. When the system
comes out of reset, it expects to read from the flash
memory. Automated flash memories provide status
information when accessed during block erase, full
chip erase, (multi) word/byte write and block lock-bii
configuration. If a CPU reset occurs with no flash
memory reset, proper CPU initialization may not
occur because the flash memory may be providing
status information instead of array data. SHARP’s
flash memories allow proper CPU initialization
following a system reset through the use of the RP#
input. In this application, RP# is controlled by the
same RESET# signal that resets the system CPU.
Rev. 1.9
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3.5 Read Identifier Codes Operation
3.6 Query Operation
The read identifier codes operation outputs the
manufacturer code, device code, block status codes
for each block (see Figure 4). Using the manufacturer
and device codes, the system CPU can automatically
match the device with its proper algorithms. The
block status codes identify locked or unlocked block
setting and erase completed or erase uncompleted
condition.
The query operation outputs the query structure
Query database is stored in the 48Byte ROM. Quer)
structure allows system software to gain critica
information
for controlling the flash component
Query structure are always presented on the lowest.
order data output (DQo-DQ,) only.
,.,..
::.
. .:. .
:
.
&&tied f&
.. :
:
: :
-.Ftiu~etmpiementaiion
4 :j /
,:
lFoC&” -ir.i-i----------------------------lFOCQ5
Block
IF0004
,Fooo3 :;-----_-------------
,Fo(JJ(;
IEFFFF; :
:
:
020000~
OlFFFF.1.
31 Status Code
----- - ----
Reserved for ;
‘. Future lmplemehation
. : .’
.,
.”
: (Blq&s 2thrtigh
., ... ‘.’
--
:
Bfock.41;
i
3?I,) : ; ) ,;
.*.
.’ Resewed’for
Ftiuie iinpteb3ntation
” .’
01~ ----L
i
I,..\
---^: L*----------------.L--------01ooo5
,,,
Block
1
Status
dode
010004
o,ooo3 T---------------------------------..
., .. I&serve&for
OOFFFF
:
:
:.
.~
.
..
: ;
Reserved for
Future Implement&ion
c4)0(& -___ -_--___-- -___ -_-_----_----_----___
ooooO5
OmOO4
000003
000002
OOOOOl
The Block Erase command requires appropriate
command data and an address within the block to be
erased. The Word/byte Write command requires the
command and address of the location to be written.
Set Block Lock-Bit command requires the command
and block address within the device (Block Lock) to
be locked. The Clear Block Lock-Bits command
requires the command and address within the device.
4 COMMAND DEFINITIONS
I-nylemg&ftion. I. :.,
.; Future.
,j.
.BlQckl~
o,m;..‘,.
Writing commands to the CUI enable reading 01
device data and identifier codes. They also contra,
inspection and clearing of the status register. When
Vcc=Vcc1,2 and VPP=VPPH1, the CUI additionally
controls block erase, full chip erase, (multi) word/byte
write and block lock-bit configuration.
The CUI does not occupy an addressable memory
location. It is written when WE# and CE# are active.
The address and data needed to execute a command
are latched on the rising edge of WE# or CE#
(whichever goes high first). Standard microprocessor
write timings are used. Figures 19 and 20 illustrate
WE# and CE#-controlled write operations.
:
:,:
.,
3.7 Write
When the VP, voltage I V,,,,, Read operations from
the status register, identifier codes, query, or blocks
are enabled.
Placing VP,+, on V,,
enables
successful block erase, full chip erase, (multi)
word/byte write and block lock-bit configuration
operations.
Device operations are selected by writing specific
commands into the CUI. Table 4 defines these
commands.
Block 0 Status Code
Device Code
_------------------------------------Manufacturer Code
Figure 4. Device Identifier
Block 0
Code Memory Map
:
Rev. 1.9
SHARI=
LHFlGKA9
. -
9
-Mode
Read
Output Disable
Standby
Table 3. Bus Operations(BYTE#=V,,)
1 Notes 1 RP# 1 CEd 1 CEd 1 OE# I WE#
1 1 r&3,9
1
vlH
I
VII
I
VII
3
V,,-,
V,,
V,,
3
VI,
VI,
$H
VI,
VI,
II
X
V,H
X
I
VII
!
VIH
V,,-,
V,H
X
X
X
X
Deep Power-Down
Read Identifier
Codes
4
V,,
9
VI,
VI,
VI,
VI,
vlH
Query
9
vlH
VI,
VI,
VI,
vlH
Write
3,7,&g
v,H
V,,
V,,
v,H
V,,
Notes
1,2,3,9
3
Table
RP#
v,,,
V,M
Mode
Read .
Outputbisable
Standby
3
vlH
3.1. Bus Operations(BYTE#=V
CEn#
CE,#
OE#
WE#
V,,
V,,
V,,
v,,,
V,,
V,,-j
v,,
V,H
VI,
vlH
vlH
VI,
v,,,
X
I Address
X
!
X
1 VP,,
I DQ,,,li
1
b-ml
X
I STS
X
X
High Z
X
X
X
High Z
X
X
See
Figure 4
See Table
7-11
X
X
High Z
High Z
Note 5
High Z
Note 6
High Z
D,N
X
,)
Address
X
X
’
x
X
VP,,
X
X
DQ&,
DolIT
HighZ
STS
X
X
X
X
X
X
High Z
X
X
X
X
See
Figure 4
See Table
7-11
X
X
High Z
High Z
Note 5
High Z
Note 6
High Z
Deep Power-Down
Read Identifier
Codes
4
v,,
v,,
X
9
‘1,
YL
YL
YL
‘1,
Query
9
VI,
VI,
VI,
VI,
vlH
’
x
Write
3,7,&g
v,H
V,,
V,,
v,,,
V,,
X
D,N
X
NOTES:
1. Refer to DC Characteristics. When VpplVppLK, memory contents can be read, but not altered.
2. X can be VIL or V,H for control pins and addresses, and VP,,, or VP,,+, for V,,. See DC Characteristics for
VP,,, and VP,,, voltages.
3. STS is VoL (if configured to RY/BY# mode) when the WSM is executing internal block erase, full chip erase,
(multi) word/byte write or block lock-bit configuration algorithms. It isfloated during when the WSM is not busy,
in block erase suspend mode with (multi) word/byte write inactive, (multi) word/byte write suspend mode, or
deep power;down mode.
4. RP# at GNDlt0.2V ensures the lowest deep power-down current.
5. See Section 4.2 for read identifier code data.
6. See Section 4.5 for query data.
7. Command writes involving block erase, full chip erase, (multi) word/byte write or block lock-bit configuration are
reliably executed when VPP=VPr+,1 and Vcc=Vcc,,2.
8. Refer to Table 4 for valid D,, during a write operation.
9. Don’t use the timing both OE# and WE# are VI,.
Rev. 1.9
SHAM=
_-
LHFlGKA9
_-
10
Command
Table 4. Command Definition@)
Bus Cycles Notes
First Bus Cycle
Req’d
Oper(‘) Addr(*)
Data(“)
Read Array/Reset
Read Identifier Codes
1
22
Level-Mode for Erase and Write
(RY/BY# Mode)
STS Configuration
Pulse-Mode for Erase
STS Confiauration
Pulse-Mod< for Write
STS Configuration
Pulse-Mode for Erase and Write
2
4
kdOTES:
1. BUS operations are defined in Table 3 and Table 3.1.
Write
Write
1 Write
1
Write
Write
Write
t
Second Bus Cycle
Ope#)
Addr(*)
Data@)
X
X
FFH
90H
Read
X
1 B8H
1 Write
X
B8H
Write
X
OlH
X
B8H
Write
X
02H
X
03H
IA
1
X
ID
1 OOH
1 t3
X
i
B8H
2I. X=Any valid address within the device.
lA=ldentifief. Code Address: see Figure 4.
QA=Query Offset Address.
BA=Address within the block being erased or locked.
WA=Address of memory location to be written.
3‘. SRD=Data read from status register. See Table 14 for a description of the status register bits.
WD=Data to be written at location WA. Data is latched on the rising edge of WE# or CE# (whichever goes high
first).
ID=Data read from identifier codes.
QD=Data read from query database.
4 . Following the Read Identifier Codes command, read operations access manufacturer, device and block status
codes. See Section 4.2 for read identifier code data.
5 . If the block is locked, WP# must be at VI, to enable block erase or (multi) word/byte write operations. Attempts
to issue a block erase or (multi) word/byte write to a locked block while RP# is V,,.
6 . Either 40H or 10H are recognized by the WSM as the byte write setup.
7 . A block lock-bit can be set while WP# is VI,.
a . WP# must be at VI, to clear block lock-bits. The clear block lock-bits operation simultaneously clears nil hlnck
lock-bits.
9 . Following the Third Bus Cycle, inputs the write address and write data of ‘N’ times. Finally, input the confirm
command ‘DOH’.
110. Commands other than those shown above are reserved by SHARP for future device implementations and
should not be used.
Rev. 1.9
SHARP
LHF16KA9
-
.-
11
-
4.1 Read Array Command
4.3 Read Status Register Command
Upon initial device power-up and after exit from deep
power-down mode, the device defaults to read array
mode. This operation is also initiated by writing the
Read Array command. The device remains enabled
For reads until another command is written. Once the
internal WSM has started a block erase, full chip
erase, (multi) word/byte write or block lock-bit
configuration, the device will not recognize the Read
Array command
until the WSM completes its
operation unless the WSM is suspended via an Erase
Suspend and (Multi) Word/byte Write Suspend
command. The Read Array command functions
independently of the V,, voltage and RP# must be
The status register may be read to determine when 2
block erase, full chip erase, (multi) word/byte write OI
block lock-bit configuration is complete and whethel
the operation completed successfully(see Table 14)
It may be read at any time by writing the Read Statu:
Register command. After writing this command, al
subsequent read operations output data from the
status register until another valid command is written
The status register contents are latched on the falling
edge of OE# or CE#(Either CE,# or CE,#),
whichever occurs. OE# or CE#(Either CEo# or CE,#;
must toggle to VI, before further reads to update the
status register latch. The Read Status Register
command functions independently of the V,, voltage.
RP# must be VI,.
VI,.
4.2 &ad
Identifier Codes Command
The identifier code operation is initiated by writing the
Read Identifier Codes command.
Following the
:ommand write, read cycles from addresses shown in
=igure 4 retrieve the manufacturer, device, block lock
zonfiguration and block erase status (see Table 5 for
dentifier code values). To terminate the operation,
Nrite another valid command. Like the Read Array
zommand, the Read Identifier Codes command
‘unctions independently of the V,, voltage and RP#
nust be Vi,. Following the Read Identifier Codes
:ommand, the following information can be read:
Table 5. Identifier Codes
1 Address 1
Code
Data
*Block is Unlocked
DC&,=0
*Block is Locked
DC&= 1
l Last erase operation
DQ, =0
completed successfully
*Last erase operation did
DC+1
not completed successfully
*Reserved for Future Use
DQ2-,
MOTE:
1. X selects the specific block status code to be
read. See Figure 4 for the device identifier code
memory map.
1
The extended status register may be read tc
determine multi word/byte write availability(see Table
14.1). The extended status register may be read al
any time by writing the Multi Word/Byte Write
command. After writing this command, all subsequeni
read operations output data from the extended status
register, until another valid command is written. Multi
Word/Byte Write command must be re-issued to
update the extended status register latch.
4.4 Clear Status Register Command
Status register bits SR.5, SR.4, SR.3 and SR.1 are
set to “1”s by the WSM and can only be reset by the
Clear Status Register command. These bits indicate
various failure conditions (see Table 14). By allowing
system software to reset these bits, several
operations (such as cumulatively erasing or locking
multiple blocks or writing several bytes in sequence)
may be performed. The status register may be polled
to determine if an error occurs during the sequence.
To clear the status register, the Clear Status Register
command (50H) is written. It functions independently
of the applied V,, Voltage. RP# must be V,,. This
command is not functional during block erase, full
chip erase, (multi) word/byte write block lock-bit
configuration,
block erase suspend
or (multi)
word/byte write suspend modes.
Rev. 1.9
SHARI=
LHF16KA9
12
Table 6. Example of Query Structure Output
Oute Nit
1 Mode
1 Offset Address
1
4.5 Query Command
IQuery
database can be read by writing Query
command (98H). Following the command write, read
cycle from address shown in Table 7-l 1 retrieve the
critical information to write, erase and otherwise
control the flash component. Ac of query offset
address is ignored when X8 mode (BYTE#=V,,).
Query data are always presented on the low-byte
data output (DC&,-DQ,). In x16 mode, high-byte
:DQs-DQ,,) outputs OOH. The bytes not assigned to
xty information or reserved for future use are set to
‘0”. This command functions independently of the
L/P,,voltage. RP# must be V,,.
A,, A,, A,, A,, A,, A,
X8 mode
X16mode
1 , 0 , 0 , 0 , 0 , 0 (20H)
1 , 0 , 0 , 0 , 0 , 1 (21H)
1, O,O,O,l
,0(22H)
1 , 0 , 0 , 0 , 1 , 1 (23H)
A,, A,, A,, A,, A,
1 ,O,O,O,O
(10H)
1 ,O,O,O,l
(11H)
DQ,c;-j-, DQ,-,
High Z
High Z
HighZ
High Z
OOH
OOH
"Q"
"Q"
"I?"
"Fl"
"Q"
"R" -1
1.5.1 Block Status Register
rhis field provides lock configuration and erase status for the specified block. These informations are only available
when device is ready (SR.7=1). If block erase or full chip erase operation is finished irregulary, block erase status
Iit will be set to “1”. If bit 1 is “l”, this block is invalid.
Table 7. Query Block Status Register
Offset
(Word Address)
(BA+2)H
./
Description
Length
OlH
Block Status Register
bit0 Block Lock Configuration
O=Block is unlocked
1=Block is Locked
bit1 Block Erase Status
O=Last erase operation completed successfully
,
1=Last erase operation not completed successfully
bit2-7 reserved for future use
Mote:
1. BA=The beginning of a-Block Address.
Rev. 1.9
SHARP
LHFlGKA9
4.5.2 CFI Query Identification
13
String
The Identification String provides verification that the component
supports the Common Flash interface
specification. Additionally, it indicates which version of the spec and which Vendor-specified command set(s) is(are)
supported.
Table 8. CFI Query Identification
String
Description
13H,14H
02H
15H,16H
02H
17H,18H
02H
Primary Vendor Command Set and Control Interface ID Code
01 H,OOH (SCS ID Code)
Address for Primary Algorithm Extended Query Table
31 H,OOH (SCS Extended Query Table Offset)
Alternate Vendor Command Set and Control Interface ID Code
OOOOH(OOOOHmeans that no alternate exists)
Address for Alternate Algorithm Extended Query Table
OOOOH(OOOOHmeans that no alternate exists)
4.5.3 System Interface Information
The following device information can be useful in optimizing system interface software.
Table 9. System Information
String
Description
\
I
1FH
.OlH
20H
OlH
21H
OlH
22H
OlH
23H
01H
24H
OlH
25H
OlH
26H
OlH
V,, Logic Supply Minimum Write/Erase voltage
27H 12.7V)
Vcc Logic Supply Maximum Write/Erase voltage
55H (5.5V)
V,, Programming Supply Minimum-Write/Erase voltage
27H (2.7V)
Vpp Programming Supply Maximum Write/Erase voltage
55H (5.5V)
Typical Timeout per Single Byte/Word Write
03H (23=8us)
Typical Timeout for Maximum Size Buffer Write (32 Bytes)
06H (26=64us)
Typical Timeout per Individual Block Erase
OAH (OAH=lO, 210=1024ms)Typical Timeout for Full Chip Erase
OFH (OFH=15, 215=32768ms)
Maximum Timeout per Single Byte/Word Write, 2N times of typical.
04H (24=1 6, 8usxl6=128us)
Maximum Timeout Maximum Size Buffer Write, 2N times of typical.
04H (24=1 6, 64usxl6=1024us)
Maximum Timeout per Individual Block Erase, 2N times of typical.
04H (24=1 6, 1024msxl6=16384ms)
Maximum Timeout for Full Chip Erase, 2N times of typical.
04H (24=1 6,32768msxl6=524288ms)
Rev. 1.9
SHARI=
LHF16KA9
--
1.5.4 Device Geometry Definition
rhis field provides critical details of the flash device geometry.
Table 10. Device Geometry
Offset
(Word Address)
27H
Length
01H
28H,29H
02H
2AH,2BH
02H
2CH
OlH
2DH,2EH
i
2FH,30H
02H
02H
Definition
Description
Device Size
15H (15H=21, 221=2097152=2M Bytes)
Flash Device Interface description
02H,OOH (x8/x1 6 supports x8 and xl 6 via BYTE#)
Maximum Number of Bytes in Multi word/byte write
05H,OOH (25=32 Bytes )
Number of Erase Block Regions within device
01 H (symmetrically blocked)
The Number of Erase Blocks
1 FH,OOH (1 FH=31 ==> 31+1=32 Blocks)
The Number of “256 Bytes” cluster in a Erase block
OOH,OlH (OlOOH=256 ==>256 Bytes x 256= 64K Bytes in a Erase Block)
$55 SCS OEM Specific Extended Query Table
Zertain flash features and commands may be optional in a vendor-specific algorithm specification. The optional
rendor-specific Query table(s) may be used to specify this and other types of information. These structures are
defined solely by the flash vendor(s).
Table 11. SCS OEM Specific Extended
Offset
(Word Address)
31 H,32H,33H
34H
35H
36H,37H,
38H,39H
Query Table
Length
Description
03H
PRI
50H,52H,49H
31 H (1) Major Version Number , ASCII
30H (0) Minor Version Number, ASCII
QFH,OOH,OOH,OOH
Optional Command Support
bitO=l : Chip Erase Supported
bitl=l : Suspend Erase Supported
bit2=1 : Suspend Write Supported
bit3=1 : Lock/Unlock Supported
bit4=0 : Queued Erase Not Supported
bit5-31 =O : reserved for-future use
OlH
Supported Functions after Suspend
bitO=l : Write Supported after Erase Suspend
bit1 -7=O : reserved for future use
03H,OOH
Block Status Register Mask
bitO=l : Block Status Register Lock Bit [BSR.O] active
bitl=l : Block Status Register Valid Bit [BSR.l] active
bit2-l5=0 : reserved for future use
Vcc Logic Supply Optimum Write/Erase voltage(highest performance)
50H(5.OV)
Vpp Programming Supply Optimum Write/Erase voltage(highest performance)
50H@OV)
Reserved for future versions of the SCS Specification
OlH
OlH
04H
”
3AH
OlH
3BH,3CH
02H
3DH
OlH
3EH
OlH
3FH
reserved
Rev. 1.9
SHARP
..~
LHFlGKA9
4.6 Block Erase Command
Block erase is executed one block at a time and
initiated by a two-cycle command. A block erase
setup is first written, followed by an block erase
confirm.
This
command
sequence
requires
appropriate sequencing and an address within the
block to be erased (erase changes all block data to
FFH). Block preconditioning, erase and verify are
handled internally by the WSM (invisible to the
system). After the two-cycle block erase sequence is
written, the device automatically
outputs status
register data when read (see Figure 5). The CPU can
detect block erase completion by analyzing the
output data of the STS pin or status register bit SR.7.
When the block erase is complete, status register bit
SR.5 should be checked. If a block erase error is
detected, the status register should be cleared before
system software attempts corrective actions. The CUI
remains in read status register mode until a new
command is issued.
This two-step command sequence of set-up followed
by execution ensures that block contents are not
accidentally erased. An invalid Block Erase command
sequence will result in both status register bits SR.4
and SK5 being set to “1 ‘I. Also, reliable block erasure
San only occur when Vcc=Vcc1,2 and VPP=VPPH,. In
the absence of this high voltage, block contents are
orotected against erasure. If block erase is attempted
SR.3 and SR.5 will be set to “1 ‘I.
while V&l,,,,,
Successful
block
erase
requires
that
the
:orresponding block lock-bit be cleared or if set, that
tiP#=V,,.
If Flock erase is attempted when the
:orrespondincj’ block lock-bit is set and WP#=V,,,
SR.l and SR.5 will be set.to “1”.
15
erase setup is first written, followed by a full chil )I
erase confirm. After a confirm command is written
device erases the all unlocked blocks from block 0 tc
Block 31 block by block. This command sequenct
requires
appropriate
sequencing.
Bloc1
preconditioning,
erase and verify are handle<
internally by the WSM (invisible to the system). Afte
the two-cycle full chip erase sequence is written, thf
device automatically outputs status register da&
when read (see Figure 6). The CPU can detect ful
chip erase completion by analyzing the output data o
the STS pin or status register bit SR.7.
When the full chip erase is complete, status registe; r
bit SR.5 should be checked. If erase error i:
detected, the status register should be cleared before
system software attempts corrective actions. The CU
remains in read status register mode until a ne\n
command is issued. If error is detected on a blocE
during full chip erase operation, WSM stops erasing
Reading the block valid status by issuing Read IC
Codes command or Query command informs whict
blocks failed to its erase.
This two-step command sequence of set-up followec
by execution ensures that block contents are no’
accidentally erased. An invalid Full Chip Erase
command sequence will result in both status register
bits SR.4 and SR.5 being set to “1”. Also, reliable ful
chip erasure can only occur when Vcc=Vcc,,2 ant
VPP=VPPHI. In the absence of this high voltage, block
contents are protected against erasure. If full chip
erase is attempted while V,,IV,,,,,
SR.3 and SR.5
will be set to “1”. When WP#=V,,, all blocks are
erased. independent of block lock-bits status. When
WP#=V,,, only unlocked blocks are erased. In this
case, SR.l and SR.5 will not be set to “1“. Full chip
erase can not be suspended.
4.7 Full Chip Erase Command
rhis command followed by a confirm command
:DOH) erases all of the unlocked blocks. A full chip
Rev. 1.9
I
SHARP
.-
;
LHFlGKA9
4.8 Word/Byte Write Command
Word/byte write is executed by a two-cycle command
sequence. Word/Byte Write setup (standard 40H or
alternate 10H) is written, followed by a second write
that specifies the address and data (latched on the
rising edge of WE#). The WSM then takes over,
controlling the word/byte write and write verify
algorithms internally. After the word/byte
write
sequence is written, the device automatically outputs
status register data when read (see Figure 7). The
CPU can detect the completion of the word/byte write
event by analyzing the STS pin or status register bit
SR.7.
When word/byte write is complete, status register bit
SR.4 should be checked. If word/byte write error is
detected, the status register should be cleared. The
internal WSM verify only detects errors for “1”s that
do not successfully write to “0”s. The CUI remains in
read status register mode until it receives another
command.
Reliable word/byte writes can only occur when
Vcc=Vcc,,2 and VPP=VPPH1. In the absence of this
high voltage, memory contents are protected against
word/byte writes. If word/byte write is attempted while
V,,&V,,,,,
status register bits SR.3 and SR.4 will be
set to “1”. Successful word/byte write requires that
the corresponding block lock-bit be cleared or, if set,
that WP#=V,,. If word/byte write is attempted when
the corresponding block lock-bit is set and WP#=V,L,
SR.l and SR.4 will be set to “1”. Word/byte write
operations with V,,<WP#<V,,
produce spurious
results and should not be attempted,
4.9 Multi Word/Byte. Write Command
Vlulti word/byte write is executed by at least fourcycle or up to 35-cycle command sequence. Up to
32 bytes in x8 mode (16 words in x16 mode) can be
oaded into the buffer and written to the Flash Array.
?rst, multi word/byte write setup (E8H) is written with
:he write address. At this point, the device
automatically outputs extended status register data
:XSR) when read (see Figure 8, 9). If extended
status register bit XSR.7 is 0, no Multi Word/Byte
iNrite command is available and multi word/byte write
setup which just has been written is ignored. To retry,
16
continue monitoring XSR.7 by writing multi word/bytt
write setup with write address until XSR.7 transition:
to 1. When XSR.7 transitions to 1, the device is read)
for loading the data to the buffer. A word/byte coun
(N)-1 is written with write address. After writing ;
word/byte count(N)-1, the device automatically turm
back to output status register data. The word/byte
count (N)-1 must be less than or equal to 1FH in xE
mode (OFH in x16 mode). On the next write, device
start address is written with buffer data. Subsequen,
writes provide additional device address and data
depending on the count. All subsequent address
must lie within the start address plus the count. After
the final buffer data is written, write confirm (DOH;
must be written. This initiates WSM to begin copying
the buffer data to the Flash Array. An invalid Mult
Word/Byte Write command sequence will result ir
both status register bits SR.4 and SR.5 being set tc
“1”. For additional multi word/byte write, write another
multi word/byte write setup and check XSR.7. The
Multi Word/Byte Write command can be queuec
while WSM is busy as long as XSR.7 indicates “1”1
because LH28F160S5T-L70A
has two buffers. If an
error occurs while writing, the device will stop writing
and flush next multi word/byte write command loaded
in multi word/byte write command. Status register bit
SR.4 will be set to “1 ‘I. No multi word/byte write
command is available if either SR.4 or SR.5 are sei
to “1”. SR.4 and SR.5 should be cleared before
issuing multi word/byte write command. If a multi
word/byte write command is attempted past an erase
block boundary, the device will write the data to Flash
Array up. to an erase block boundary and then stop
writing. Status register bits SR.4 and SR.5 will be se1
to “1 ‘I.
Reliable multi byte writes can only occur when
Vcc=Vcc1,2 and VPP=VPPHI. In the absence of this
high voltage, memory contents are protected against
multi word/byte writes. If multi word/byte write is
attempted while V,+V,,,k,
status register bits SR.3
and SR.4 will be set to “1”. Successful multi
word/byte write requires that the corresponding block
lock-bit be cleared or, if set, that WP#=V,,. If multi
byte write is attempted when the corresponding block
lock-bit is set and WP#=V,L, SR.l and SR.4 will be
set to “1 I’.
Rev. 1.9
SHARP
LHFlGKA9
. -
17
-
1.10 Block Erase Suspend Command
The Block Erase Suspend command allows blockerase interruption to read or (multi) word/byte-write
data in another block of memory. Once the blockxase process starts, writing the Block Erase
Suspend command requests that the WSM suspend
:he block erase sequence at a predetermined point in
:he algorithm. The device outputs status register data
,vhen read after the Block Erase Suspend command
s written. Polling status register bits SR.7 and SR.6
xn determine when the block erase operation has
Deen suspended (both will be set to “1”). STS will
also transition to High Z. Specification twHRH2 defines
:he block erase suspend latency.
At this Qoint, a Read Array command can be written
to read data from blocks other than that which is
suspended. A (Multi) Word/Byte Write command
sequence can also be issued during erase suspend
to program data in other blocks. Using the (Multi)
word/Byte Write Suspend command (see Section
4.1 l), a (multi) word/byte write operation can also be
suspended. During a (multi) word/byte write operation
with block erase suspended, status register bit SR.7
will return to “0” and the STS (if set to RY/BY#)
Dutput will transition to VOL. However, SR.6 will
remain “1’ to indicate block erase suspend status.
The only other valid commands while block erase is
suspended are Read Status Register and Block
Erase Resume. After a Block Erase Resume
command is written to the flash memory, the WSM
inrillcontinue the block erase process. Status register
oits SR.6 and SR.7 will automatica!ly clear and STS
nil1 return to V&. After the Erase Resume command
is written, the device automatically outputs status
register data when read ‘(see Figure 10). V,, must
remain at VppH1 (the same V,, level used for block
erase) while block erase is suspended. RP# must
also remain at VI,. Block erase cannot resume until
(multi) word/byte write operations initiated
block erase suspend have completed.
4.11
(Multi) Word/Byte
Command
Write
during
Suspend
The (Multi) Word/Byte Write Suspend command
allows (multi) word/byte write interruption to read data
in other flash memory locations. Once the (multi)
word/byte write process starts, writing the (Multi)
Word/Byte Write Suspend command requests that
the WSM suspend the (multi) word/byte write
sequence at a predetermined point in the algorithm.
The device continues to output status register data
when read after the (Multi) Word/Byte Write Suspend
command is written. Polling status register bits SR.7
and SR.2 can determine when the (multi) word/byte
write operation has been suspended (both will be set
to “1”). STS will also transition to High Z.
Specification twHRHl defines the (multi) word/byte
write suspend latency.
At this point, a Read Array command can be written
to read data from locations other than that which is
suspended. The only other valid commands while
(multi) word/byte write is suspended are Read Status
Register and (Multi) Word/Byte Write Resume. After
(Multi) Word/Byte Write Resume command is written
to the flash memory, the WSM will continue the
(multi) word/byte write process. Status register bits
SR.2 and SR.7 will automatically clear and STS will
return to V,,. After the (Multi) Word/Byte Write
command is written, the device automatically outputs
status register data when read (see Figure 11). V,,
must remain at V,,,,
(the same V,, level used for
(multi) word/byte write) while in (multi) word/byte
write suspend mode. WP# must also remain at V,, or
YL*
Rev. 1.9
SHARP
.-
LHFlGKA9
4.12 Set Block Lock-Bit Command
A flexible block locking and unlocking scheme is
enabled via block lock-bits. The block lock-bits gate
program and erase operations With WP#=V,,,
individual block lock-bits can be set using the Set
Block Lock-Bit command.
See Table 13 for a
summary of hardware and software write protection
options.
Set block lock-bit is executed by a two-cycle
command sequence. The set block lock-bit setup
along with appropriate block or device address is
written followed by either the set block lock-bit
confirm (and an address within the block to be
locked). The WSM then controls the set block lock-bit
algorithp. After the sequence is written, the device
automatically outputs status register data when read
(see Figure 12). The CPU can detect the completion
of the set block lock-bit event by analyzing the STS
pin output or status register bit SR.7.
When the set block lock-bit operation is complete,
status register bit SR.4 should be checked. If an error
is detected, the status register should be cleared.
The CUI will remain in read status register mode until
a new command is issued.
This two-step sequence of set-up followed by
execution ensures that block lock-bits are not
accidentally set. An invalid Set Block Lock-Bit
command will result in status register bits SR.4 and
SR.5 being set to “1”. Also, reliable operations occur
only when Vcc=Vccv2 and VPP=VPPHI. In the
absence of this high voltage, block* lock-bit contents
are protected against alteration.
A successful set block ‘lock-bit operation requires
WP#=V,,. If it is attempted with WP#=V,,, SR.l and
SR.4 will be set to “1” and the operation will fail. Set
block lock-bit operations with WP#<V,, produce
spurious results and should not be attempted.
18
block lock-bits can be cleared using only the Cleal
Block Lock-Bits command. See Table 13 for s
summary of hardware and software write protectior
options.
Clear block lock-bits operation is executed by a two.
cycle command sequence. A clear block lock-bits
setup is first written. After the command is written, the
device automatically outputs status register data
when read (see Figure 13). The CPU can deteci
completion of the clear block lock-bits event by
analyzing the STS Pin output or status register bii
SR.7.
When the operation is complete, status register bii
SR.5 should be checked. If a clear block lock-bit error
is detected, the status register should be cleared.
The CUI will remain in read status register mode until
another command is issued.
This two-step sequence of set-up followed by
execution ensures that block lock-bits are not
accidentally cleared. An invalid Clear Block Lock-Bits
command sequence will result in status register bits
SR.4 and SR.5 being set to “1”. Also, a reliable clear
block lock-bits operation can only occur when
Vcc=Vcc1,2 and VPP=VPPH1. If a clear block lock-bits
operation is attempted while V,,IV,,,k,
SR.3 and
SR.5 will be set to “1 I’. In the absence of this high
voltage, the block lock-bits content are protected
against alteration. A successful clear block lock-bits
operation requires WP#=V,,. If it is attempted with
WP#=V,,, SR.l and SR.5 will be set to “1” and the
operation will fail. Clear block lock-bits operations
with V,,,<RP# produce spurious results and should
not be attempted.
If a clear block lock-bits operation is aborted due to
V,, or Voo transitioning out of valid range or RP#
active transition, block lock-bit values are left in an
undetermined state. A repeat of clear block lock-bits
is required to initialize block lock-bit contents to
known values.
4.13 Clear Block Lock-Bits Command
All set block lock-bits are cleared in parallel via the
Clear Block Lock-Bits command. With WP#=V,,,
Rev. 1.9
SHARP
LHFlGKA9
4.14 STS Configuration
Command
The Status (STS) pin can be configured to different
states using the STS Configuration command. Once
the STS pin has been configured, it remains in that
configuration until another configuration command is
issued, the device is powered down or RP# is set to
V,,. Upon initial device power-up and after exit from
deep power-down mode, the STS pin defaults to
RY/BY# operation where STS low indicates that the
WSM is busy. STS High Z indicates that the WSM is
ready for a new operation.
To reconfigure the STS pin to other modes, the STS
Configuration is issued followed by the appropriate
configuration code. The three alternate configurations
are all pulse mode for use as a system interrupt. The
STS Configuration command functions independently
of the Vpp voltage and RP# must be VI,+.
Table 12. STS Configuration
Coding Description
Configuration
Effects
Bits
Set STS pin to default level mode
(RY/BY#). RY/BY# in the default
OOH
level-mode of operation will indicate ~
WSM status condition.
Set STS pin to pulsed output signal
for specific erase operation. In this
mode, STS provides low pulse at
OlH
the completion of BLock Erase,
Full Chip Erase and Clear Block
Lock-bits operations.
Set STS pin to pulsed output signal
for a specific write operation. In this
02H
mode, STS provides low pulse at
the completion of (Multi) Byte Write
and Set Block Lock-bit operation.
Set STS pin to pulsed output signal
for specific write and erase
operation. STS provides low pulse
03H
at the completion of Block Erase,
Full Chip Erase, (Multi) Word/Byte
Write and Block Lock-bit
Configuration operations.
Table 13. Write Protection
Operation
Block Erase, .
(Multi) Word/Byte
Write
./
Block
Lock-Bit
0
,
WP#
VI, or VI,.,
,
VI,
VI,
Full Chip Erase
Set Block Lock-Bit
Clear Block Lock-Bits
091
X
X
X
V,,
vp ,
V,,
V,H
V,,
V,w
Alternatives
Effect
Block Erase and (Multi) Word/Byte Write Enabled
Block is Locked. Block Erase and (Multi) Word/Byte Write
Disabled
Block Lock-Bit Override. Block Erase and (Multi) Word/Byte
Write Enabled
All unlocked blocks are erased, locked blocks are not erased
All blocks are erased
Set Block Lock-Bit Disabled
Set Block Lock-Bit Enabled
Clear Block Lock-Bits Disabled
Clear Block Lock-Bits Enabled
Rev. 1.9
SHARP
LHFlGKA9
_-
20
.WSMS
7
j
BESS
6
Table 14. Status Register Definition
wss
1 ECBLBS 1 WSBLBS 1 VPPS
I
5
4
3
2
DPS
R
1
0
NOTES:
SR.7 = WRITE STATE MACHINE STATUS
1 = Ready
0 = Busy
Check STS or SR.7 to determine block erase, full chip
erase, (multi) word/byte write or block lock-bit
configuration completion.
SR.6-0 are invalid while SR.7=“0”.
SR.6 = BLOCK ERASE SUSPEND STATUS
1 = Block Erase Suspended
0 = Block Erase in Progress/Completed
SR.5 = ERASE AND CLEAR BLOCK LOCK-BITS
STATUS
1 = Error in Erase or Clear Bloc1 Lock-Bits
0 = Successful Erase or Clear Block Lock-Bits
4
SR.4 = WRITE AND SET BLOCK LOCK-BIT STATUS
1 = Error in Write or Set Block Lock-Bit
0 = Successful Write or Set Block Lock-Bit
SR.3 = V,, STATUS
1 = V,, Low Detect, Operation Abort
O=V,,OK
If both SR.5 and SR.4 are “1”s after a block erase, full
chip erase, (multi) word/byte write, block lock-bit
configuration or STS configuration attempt, an improper
command sequence was entered.
SR.3 does not provide a continuous indication of V,,
level. The WSM interrogates and indicates the V,, level
only after block erase, full chip erase, (multi) word/byte
write or block lock-bit configuration command
sequences. SR.3 is not guaranteed to reports accurate
feedback only when V,p&/,p,,
.
SR.l does not provide a continuous indication of block
lock-bit values. The WSM interrogates block lock-bit,
and WP# only after block erase, full chip erase, (multi)
word/byte write or block lock-bit configuration command
sequences. It informs the system, depending on the
attempted operation, if the block lock-bit is set and/or
WP# is not V,,. Reading the block lock configuration
codes after writing the Read Identifier Codes command
indicates block lock-bit status.
SR.2 = WRITE SUSPEND STATUS
1 = Write Suspended
0 = Write in Progress/Completed
SR.l = DEVICE PROTECT STATUS
1 = Block Lock-Bit and/or WP# Lock Detected,
Operation Abort
0 = Unlock -
SR.0 is reserved for future use and should be masked
out when polling the status register.
SR.0 = RESERVED FOR FUTURE*ENHANCEMENTS
SMS
R
7
6
Table 14.1. Extended Status Register Definition
R
R
R
R
5
4
3
2
R
R
1
0
NOTES:
XSR.7 = STATE MACHINE STATUS
1 = Multi Word/Byte Write available
0 = Multi Word/Byte Write not available
After issue a Multi Word/Byte Write command: XSR.7
indicates that a next Multi Word/Byte Write command is
available.
XSR.G-O=RESERVED FOR FUTURE ENHANCEMENTS
XSR.G-0 is reserved for future use and should be
masked out when polling the extended status register.
Rev. 1.9
SHARP
.-
~.
LHFIGKAS
Bus
OpOWlOtl
write
21
Commrnd
Read Status
Rsgister
Data-70H
Addr-X
Status Ragistar Data
Read
Check SR.7
l-WSM Ready
(bWSM Busy
Standby
Block Address
Comments
Write
Etaso setup
Data&UH
Adds-Within Block to be Erased
Writ.3
Erase
confirm
Data-DOH
Adds-Within Block to be Erased
Status Register Data
Read
Check SR.7
1-WSM Ready
O=WSM Busy
Standby
Repeat for subsequent block erasures.
Full status check can be dona after each block erase or after a sequence of
block erasures.
Write FFH after the last operation to place device in read away mode.
Check if Desired
FULL STATUS CHECK PROCEDURE
(C)
BUS
Operalion
Comma”d
Comments
Standby
Check SR.3
lxVpp Error Detect
standby
Check SR. 1
I-Device Protect Detect
WP#~VIL,Blo& Lock-Bit is Set
Only required for systems
implementing lock-bit configuration
Standby
Check SR.4.5
Soti l=Command Sequence Enw
Standby
Check SR.5
l=Elock Erase Error
Dewce Protect Error
%t.5,SR.4,SR.3 and SR.1 are onb cleared by the Clear Status
Register Command in causes where multiple blocks are emsed
before full status is checked.
f error IS detected. clear the Status Register before attempting
ratly or other error raCO”wy.
Figure 5. Automated
Block Erase Flowchart
LRev. 1.9
SHARF=
LHF16KA9
.-
22
--
I
Read
Status Register Data
I
:uII stabs check can be done after each full chip erase.
Wit0 FFH after tie last opera(ion to place device in mad array mode.
Check if Desired
FULL STATUS CHECK PROCEDURE
Read Status Register
Data(Sae Above)
/ O:~c”1 GrnrnMd
/
Comments
Standby
Check SR.3
l=Vpp Error Detect
Standby
Chedc SR.4.5
Both l=Command Sequence Error
Check SR.5
l-Full Chip Erase Error
SR.S.SR.4.SR.3 and SR.1 are only dewed by the Clear Status
Register Command in cases where multiple blocks are erased
before full status is chedwd.
If error is detected. clear the Status Register before attempting
retry or other error ?-eccNery.
Full Chip Erase
Successful
Figure 6. Automated
Full Chip Erase Flowchart
J
Rev. 1.9
SHARI=
LHFIGKAS
_-
23
.i
c- stall \
Command
Write
Read status
Register
Read
0
SR.7=
Data-70H
Add,=X
Status Register Data
Check SR.7
l-W%
Ready
OIWSM Busy
standby
0
,
Comments
Wlite
Setup Word/Byte
wlite
Datw4OH or 10H
Addr-Locabon to Be Written
write
Word/Byte Write
Data-Data to Be Written
Addr-Location to Be Written
Status Register Data
Read
Check SR.7
1=WSM Reacfy
o.wsM Busy
standby
Repeat for subsequent word/byte writes.
SR full stah~s check can be done after each worn
write. or after a sequence of
wordbyte writes.
Write FFH after the last wotdibyte write operabn to place device in
mad anay mode.
FULL STATUS CHECK PROCEDURE
(5zyttz?]
.. .
,
BUS
Op~tiOn
Command
Comments
Standby
Check SR.3
l.Vpp Error Detect
Standby
Check SR.1
I-Devise Pmtect Detect
WPY-V#o&
Lock-Bit is Set
Only required for systems
implementing lock-bit configuration
Standby
Check SR.4
l-Data Write Error
Device Protect Enw
SR.4,SR.3 and SR.1 are only dearud by the Clear Status Register
command in cases where multiple locations are witten before
full status is checked.
If em)r is detected, clear the Status Regster before attempting
retry or other error recovery.
Figure 7. Automated
Word/byte
Write Flowchart
Rev. 1.9
LHFlGKA9
_-
24
r
Bus
Opsration
write
Command
StiP
Multi WordByte write
Comments
DataPEBH
Add&tart Address
t
Read
Extended Status Register Data
standby
Check XSR.7
l-Multi Word/Byte Write Ready
O-Multi woldmyte writ0 Buoy
write
4
Write Buffer Data,
Start Address
(N&l)
Data-Word or Byte Count (N)-1
Addr-Start Address
Write
(N&2,3)
DataPBuffer Data
Add&tart Address
Data-Buffer Data
Addr-Device Address
Data-DOH
Addr=X
-I----Read
Standby
\
Write Buffer Data,
Device Address
Wlite DOH
Abort
I
Status Register Data
Check SR.7
1=WSM Ready
0s.WSM Busy
1, Byte or word count values on DC!,,., are loaded into the count register.
2. Write Buffer contents will be programmed at the start address.
3. Align the start address on a Write Buffer boundary for maximum
programming perfonance.
4.The device aborts the Multi Word/Byte Write command if the current address is
outside of theprfginal block address.
B.The Status Register indicates an ‘improper command sequence’ if the Multi
WordByte command is aborted. Follow this with a Clear Status Register command.
SR full status check can be done after each multi wov9byte write,
or after Q sequence of multi wotiyte
writes.
Write FFH after the last multi wordbyte write operation to place device in
read array mode.
Read Status
Register
I
Figure 8. Automated
Multi Word/Byte
Write Flowchart
LRev. 1.9
SHARP
LHFIGKAS
FULLSTATUSCHECKPROCEWRE
FOR
MULTI WORD/BYTE WRITE OPERATION
Read status Register
Command
Comments
Check SR.3
t=Vpp Ermr Detect
stsndby
Check SR.1
l=Dovlce Protect Detect
WPwPV,L,Bfock Lock-Bit is Set
Only mquimd for systems
implementing lock-bit contigumtion
Standby
Check SFt.4.5
Both 1Gommand
Standby
Check SR.4
l-Data Write Ermr
Device Protect Enor
Sequence Error
SRS.SR.4.SR.3 and SR.1 are only deamd by the Clear Status Register
command in casas where multiple locations are written before
full status is dmcked.
If ermr is detected. clear the Status Register before attempting
retry oroUw error recovery.
Figure 9. Full Status Check Procedure
for Automated
Multi Word/Byte
Write
Rev. 1.9
SHARP
_-
LHFlGKA9
*-
26
--
I
Bus
OpeMiOll
Command
Check SR.7
1-WSM Ready
ONWSM Bury
Standby
SR.7=
Comments
0
Chock SR.6
l-Block Erase Suspended
Standby
O-Block Erase Completed
1
Write
EtWe
ReSUllS
Data&OH
Addr-X
(Multi) wofd/Byte write Loop
I
Figure 10. Block Erase Suspend/Resume
Flowchart
Rev. 1.9
SHARP
.-
_-
LHFlGKA9
27
.i
(Multi) WodSyte
,*,
I
Write
Suspend
I
Data&H
AddhX
I
Status Register Data
Addr=X
Read
Chock SR.7
l-WSM Ready
0a.Ws.M Busy
SR.7-
+-
0
1
Chech 533.2
b(Mul6) Word’eyte Write
SUSpended
O-(Multi) Word/Byte Write
Completed
Standby
(MUlli)
worvsvtowrite\
Compk ied
/
DatarFFH
Write
AddhX
Read Array locatbns other
than that being written.
Write FFH
Write
(Multi) Word/Byte Write
Resume
Data-DOH
Addr-X
Read Army Data
Figure 11. (Multi) Word/Byte
Write Suspend/Resume
Flowchart
Rev. 1.9
SHARP
.-
_-
LHFlGKA9
Command
I
Writ.3
Block Address
Set Block
Lock-Bit Setup
Data-6Ol-l
Add&lock
Address
Block Address
0
SR.7=
+4
1
Check if Desired
Repeat for subsequent block lock-bit set operations.
Full status chsck can be done after each block l&-bit set operation
or after a sequence of block lock-bit set operations.
Write FFH after the last block lo&-bit set operation to place device in
read army mode.
FULL STATUS CHECK PROCEDURE
(T)
Command
Comments
I
Standby
Check SR.3
I-Vpp Error Detect
Standby
Check SR.4
l&at Block Lock-Bit Error
I
SRS,SR.4,SR.3 and SR.l am only cleared by tfw Clear Status
Register command in cases where multiple Mock lock-bits are set before
full stahis is checked.
If error 1sd&tad.
clear the Status Register before attempting
retry or other error recovery.
Figure 12. Set Block Lock-Bit Flowchart
Rev. 1.9
SHARP
LHF16KA9
Stall
Command
q---Q&y
Wnto 60H
x
Clear Blodc
Lock-Sits Confirm
Writ9
I
Data&OH
Add-X
Data=DOH
Addr-X
I
I
Read
chak SR.7
l=WSM Ready
OIWSM Busy
Standby
I
0
SR.74c?-
Write FFH after the Clear Block Lock-Sib operation to
place device in read array mode.
1
Check if Desired
FULL STATUS CHECK PROCEDURE
Read Status Register
Data(See Above)
Command
I
Chedc SR.3
I+,,
Error Detect
Standby
Standby
Check SR.5
l-Clear Block Lock-Bits Error
Standby
SR.S,SR.4,SR.3 and SR.1 am only deared by the Clear Status
Register command.
IIf error is detected. clear the Status Register before attempting
retry or other ermr mcovely.
Clear Block Lock-Bits
SUCCeSSfUl
Figure 13. Clear Block Lock-Bits
Flowchart
L-
Rev. 1.9
LHFlGKA9
30
--
5 DESIGN CONSIDERATIONS
5.1 Three-Line Output Control
The device will often be used in large memory arrays.
inputs
to
SHARP
provides
three
control
accommodate multiple memory connections. ThreeLine control provides for:
a. Lowest possible memory power dissipation.
b. Complete assurance that data bus contention will
not occur.
To use these control inputs efficiently, an address
decoder should enable CE# while OE# should be
connected to all memory devices and the system’s
READ#Qontrol line. This assures that only selected
memory
devices
have
active outputs
while
deselected memory devices are in standby mode.
RP# should
be connected
to the system
POWERGOOD signal to prevent unintended writes
during system power transitions. POWERGOOD
should also toggle during system reset.
5.2 STS and Block Erase, Full Chip
Erase, (Multi) Word/Byte Write and
Block Lock-Bit Configuration Polling
STS is an open drain output that should be
connected to Vcc b y a pullup resistor to provide a
hardware method of detecting block erase, full chip
erase, (multi) .word/byte write and block lock-bit
configuration
completion.
In default
mode,
it
transitions low after block erase,, full chip erase,
(multi) word/byte write or block lock-bit configuration
commands and returns to V,, when the WSM has
finished executing
the’ internal algorithm.
For
alternate
STS
pin configurations,
see
the
Configuration command.
STS, in default mode, is also High Z when the device
is in block erase suspend (with (multi) word/byte write
inactive), (multi) word/byte write suspend or deep
power-down modes.
5.3 Power Supply Decoupling
Flash memory power switching characteristics require
careful device decoupling. System designers are
interested in three supply current issues; standby
current levels, active current levels and transient
peaks produced by falling and rising edges of CE#
and OE#. Transient current magnitudes depend on
the device outputs’ capacitive and inductive loading.
Two-line control and proper decoupling capacitor
selection will suppress transient voltage peaks. Each
device should have a O.luF ceramic capacitor
connected between its Vcc and GND and between its
V,, and GND. These high-frequency, low inductance
capacitors should be placed as close as possible to
package leads. Additionally, for every eight devices,
a 4.7uF electrolytic capacitor should be placed at the
array’s power supply connection between Vcc and
GND. The bulk capacitor will overcome voltage
slumps caused by PC board trace inductance.
5.4 Vpp Trace on Printed Circuit Boards
Updating flash memories that reside in the target
system requires that the printed circuit board
designer pay attention to the V,, Power supply trace.
The V,, pin supplies the memory cell current for
block erase, full chip erase, (multi) word/byte write
and block lock-bit configuration. Use similar trace
widths and layout considerations given to the V,,
power bus. Adequate
V,,
supply traces and
decoupling will decrease V,, voltage spikes and
overshoots.
STS can be connected to an interrupt input of the
system CPU or controller. It is active at all times.
Rev. 1.9
SHARP
LHFlGKA9
. -
5.5 VCC, Vpp, RP# Transitions
Block erase, full chip erase, (multi) word/byte write
and block lock-bit configuration are not guaranteed if
V,, falls outside of a valid V,,,,
range, Voo falls
outside of a valid VCCIR range, or RP#=V,,. If V,,X
error is detected, status register bit SR.3 is set to “1”
along with SR.4 or SR.5, depending on the attempted
operation. If RP# transitions to V,, during block
erase, full chip erase, (multi) word/byte write or block
lock-bit configuration, STS(if set to RY/BY# mode)
will remain low until the reset operation is complete.
Then, the operation will abort and the device will
enter deep power-down. The aborted operation may
leave data partially altered. Therefore, the command
sequence must be repeated after normal operation is
restored. Device power-off or RP# transitions to V,,
clear the status register.
The CUI latches commands issued by system
software and is not altered by V,, or CE# transitions
or WSM actions. Its state is read array mode upon
power-up, after exit from deep power-down or after
Voc transitions below VLko.
After block erase, full chip erase, (multi) word/byte
write or block lock-bit configuration, even after V,,
transitions down to V,,,,, the CUI must be placed in
read array mode via the Read Array command if
subsequent access to the memory array is desired.
5.6 Power-Up/Down
Protection
The device is designed to offer protection against
accidental block and- full chip , erasure, (multi)
word/byte writfhg or block lock-bit configuration during
power transitions. Upon. power-up, the device is
indifferent as to which power supply (V,, or Vc,)
31
powers-up first. Internal circuitry resets the CUI tc
read array mode at power-up.
A system designer must guard against spuriou:
writes for Voo voltages above VLKo when V,, i!
active. Since both WE# and CE# must be low for :
command write, driving either to V,, will inhibit writes
The CUl’s two-step command sequence architecturt
provides added level of protection against dat:
alteration.
In-system block lock and unlock capability prevent:
inadvertent data alteration. The device is disablec
while RP#=VIL regardless of its control inputs state.
5.7 Power Dissipation
When designing portable systems, designers mus
consider battery power consumption not only durin!
device operation, but also for data retention durin!
system idle time. Flash memory’s nonvolatiliQ
increases usable battery life because data is retainec
when system power is removed.
In addition,
deep power-down
mode ensure:
extremely low power consumption even when systen
power is applied. For example, portable computin{
products and other power sensitive applications tha
use an array of devices for solid-state storage car
consume negligible power by lowering RP# to V,,
standby or sleep modes. If access is again needed
the devices can be read following the tPHQV ant
t,,,,
wake-up cycles required after RP# is firs
raised to V,,. See AC CharacteristicsRead OnI)
and Write Operations and Figures 17, 18, 19, 20 foi
more information.
Rev. 1.9
SHARI=
_-
-
LHFIGKAS
32
.-
6 ELECTRICAL
6.1 Absolute
SPECIFICATIONS
Maximum
*WARNING:
Stressing the device beyond
th
“Absolute Maximum Ratings” may cause permaner
damage. These are stress ratings only. Operatio,
beyond
the
“Operating
Conditions”
is nc
recommended and extended exposure beyond th,
“Operating Conditions” may affect device reliability.
Ratings*
Operating Temperature
During Read, Erase, Write and
Block Lock-Bit Configuration .. . .. ...O”C to +70”C(1)
Temperature under Bias .. .. . .. .. .. . .. . -10°C to +8O”C
NOTES:
1. Operating
temperature
is for
commercia
temperature product defined by this specification.
2. All specified voltages are with respect to GND
Minimum DC voltage is -0SV on input/output pin
and -0.2V on Vco and V,,
pins. Durin!
transitions, this level may undershoot to -2.OV fo
periods
<20ns.
Maximum
DC voltage
OI
input/output pins and Vcc is Vc,+O.5V which
during transitions, may overshoot to Voc+2.OV fo
periods e20ns.
3. Output shorted for no more than one second. Nc
more than one output shorted at a time.
Storage Temperature . .. .. . .. .. . .. .. .. . .. .. .. -65°C to +125X
Voltage On Any Pin
(except Voo, V,,) . . .. . .. .. .. .. . . -0.5V to Voo+O5V(*)
Voc Suply Voltage . .. . .. .. . .. . .. .. .. . .. .. . .. .. -0.2v to +7.ov(*)
V,, Update Voltage during
Erase, Write and
Block Lock-Bit Configuration . .. ...-0.2V to +7.OV(*)
Output Short Circuit Current . .. .. . .. .. .. . .. .. .. .. . .. lOOmA
6.2 Operating Conditions
6.2.1 CAPACITAN’CE(‘)
.I’
T,=+25”C,
Symbol
C,N
cn, ,T
Parameter
Input Capacitance
Output Capacitance
Typ.
7
9
f=l MHz
Max.
Unit
10
12
pF
pF
Condition
v,,=o.ov
‘Jr-,,,r=O.OV
NOTE:
1. Sampled, not 100% tested.
Rev. 1.9
SHARP
LHF16KA9
6.2.2 AC INPUTiiJTPUT
TEST CONDITIONS
AC test inputs are driven at 3.OV for a Logic “1” and O.OV for a Logic
Input rise and fall times (10% to 90%) cl0 ns.
“0.” Input timing
begins,
and output
timing
en&,
at 1.5V.
I
Figure 14. Transient
Input/Output
Reference Waveform
(High Speed Testing Configuration)
for Vcc=5V~0.25V
AC test inputs are driven at VOH (2.4 Vm) for a Logic “1” and VOL (0.45 VTTL) for a Logic “0.” Input timing begins
(2.0 Vm) and VIL (0.8 Vm).
Output timing ends at VIH and VIL. Input rise and fall times (10% to 90%) <lo ns.
Figure 15. Transient
Input/Output
Reference Waveform
(Standard Testing Configuration)
at VIH
for Vcc=5V+0.5V
1.3v
lN914
r
$
RL=3.3kR
-tCL Includes Jig
Capacitance
-I-
T
CL
I
Figure 16. Transient Equivalent
Load Circuit
Testing
Rev. 1.9
SHARP
LHFlGKA9
5.2.3 DC CHARACTERISTICS
Symbol
‘Ll
Parameter
Input Load Current
‘LO
Output Leakage Current
‘cc,
Vcc Standby Current
Vcc Deep Power-Down
’ Current
Vcc Read Current
‘CCR
‘CC0
DC Characteristics
v(-c=sv
Notes
Max.
TYP.
1
*l
1
*lO
Unit
PA
lJA
1,396
25
100
CIA
2
4
mA
15
CIA
50
mA
65
mA
1
1A6
,
Test
Conditions
Vcc=VccMax.
V,,=V,c or GND
Vcc=V&lax.
VCllIT=VCC or GND
CMOS Inputs
V,,=V,,Max.
CE#=RP#=Vcc’0.2V
TTL Inputs
Vcc=VccMax.
CE#=RP#=V,,
RP#=GND*O.2V
I,,,,(STS)=OmA
CMOS Inputs
Vcc=VccMax.
CE#=GND
f=8MHz, louT=OmA
TTL Inputs
Vcc=VccMax., CE#=V,,
f=8MHz, 10,,T=OmA
B Write or Set Block
Rev. 1.9
SHARP
LHFlGKA9
DC Characteristics
(Continued)
VOTES:
I. All currents are in RMS unless otherwise noted. Typical values at nominal V,, voltage and TA=+25”C.
!* ‘CC,, and ‘CCESare specified with the device de-selected. If read or byte written while in erase suspend mode,
the device’s current draw is the sum of lccws or lCCESand I,,, or I,,,,
respectively.
3. Includes STS.
1. Block erases, full chip erases, (multi) word/byte writes and block lock-bit configurations are inhibited when
V#I,,Lk,
and not guaranteed in the range between V,,Lk(max.) and V,,,,(min.)
and above VppH,(max.).
5. Automatic Power Savings (APS) reduces typical ICC, to 1 mA at 5V Vcc in static operation.
j. CMOS inputs are either Vcc+0.2V or GNDk0.2V. TTL inputs are either V,, or V,,.
7. Sampled, not 100% tested.
SHARI=
_-
LHFlGKA9
6.2.4 AC CHARA-iTERlSTlCS
- READ-ONLY OPERATIONS(‘)
36
Vcc=5V+0.5V, 5Vt0.25V, T,pO ‘C to +7O”C
Vcc=5V*0.25V) LH28F :16OS5-L70@)
__ _ _ _ .
,1
vcc=5v*o.5v
1
1 LH28F16OS5-L80@)
fF, n,
tELFL
BYTE# to Output in High Z
CE# Low to BYTE# High or Low
3
25
30
ns
3
5
5
ns
tF, FH
NOTES:
1. See AC Input/Output Reference Waveform for maximum allowable input slew rate.
2. OE# may be delayed up to t,Lav-bLov after the falling edge of CE# without impact on tELQV.
3. Sampled, not 100% tested.
4. See Ordering Information for device speeds (valid operational combinations).
5. See Transient Input/Output Reference Waveform and Transient Equivalent Testing Load Circuit (High Speed
Configuration) for testing characteristics.
6. See Transient Input/Output Reference Waveform and Transient Equivalent Testing Load Circuit (Standard
Configuration) for testing characteristics.
Rev. 1.9
SHARP
_-
.-
LHF16KA9
Device
Address
Selection
Address
37
Data Valid
11.1.1111.
Stable
hi
CE#(E)
VIH
OE#(G)
ML
.*1..,,,.,
VH
WE#(W)
WL
VOH
DATA(D/Q)
VOL
tPHoV
“““““7
..
NOTE:
CE# iddefined
as the latter
of &,$I
and CE#
going
Low or the first of CEo# or CE,#
going
High.
Figure 17. AC Waveform for Read Operations
Rev. 1.9
.,,
SHARP
RELATED DOCUtiENi
INFORMATIONAL
Document No.
Document Name
AP-00 I-SD-E
Flash Memoq Family So&are
Drivers
AP-006~FT-E
Data Protection Method of SHARP Flash Memoq~
RP#, Vpp Electric Potential Switching Circuit
AP-OOTSW-E
NOTE :
I. lmemational customers should contact their local SHARP or distribution sales office.
SHARI=
b PFIEUMINARY1
AMEi TSOPS6-P-1420 1 LE4D FINISH ! PLATING NOTE Phstic body dimens ions do not include
of resin.
1 *fc
;
DRA9fINGNO. i Ml115
1 UNIT 1 mm
1
burr