74AC843 # 74ACT843 9-Bit Transparent Latch General Description Features The ’AC/’ACT843 bus interface latch is designed to eliminate the extra packages required to buffer existing latches and provide extra data width for wider address/data paths. The ’AC/’ACT843 is functionally and pin compatible with AMD’s Am29843. Y Logic Symbols Y ’ACT843 has TTL-compatible inputs TRI-STATEÉ outputs for bus interfacing Connection Diagram Pin Assignment for DIP and SOIC TL/F/9800 – 1 IEEE/IEC TL/F/9800 – 2 TL/F/9800 – 3 Pin Names D0 – D8 O0 – O8 OE LE CLR PRE Description Data Inputs Data Outputs Output Enable Latch Enable Clear Preset TRI-STATEÉ is a registered trademark of National Semiconductor Corporation FACTTM is a trademark of National Semiconductor Corporation C1995 National Semiconductor Corporation TL/F/9800 RRD-B30M75/Printed in U. S. A. 74AC843 # 74ACT843 9-Bit Transparent Latch April 1993 Functional Description addition to the LE and OE pins, the ’AC/’ACT843 has a Clear (CLR) pin and a Preset (PRE) pin. These pins are ideal for parity bus interfacing in high performance systems. When CLR is LOW, the outputs are LOW if OE is LOW. When CLR is HIGH, data can be entered into the latch. When PRE is LOW, the outputs are HIGH if OE is LOW. Preset overrides CLR. The ’AC/’ACT843 consists of nine D-type latches with TRI-STATE outputs. The flip-flops appear transparent to the data when Latch Enable (LE) is HIGH. This allows asynchronous operation, as the output transition follows the data in transition. On the LE HIGH-to-LOW transition, the data that meets the setup times is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH, the bus output is in the high impedance state. In Function Tables Internal Outputs CLR PRE Inputs OE LE D Q O H H H H H H H L L L H H H H H H H L H L H L H H H L L L L L L H H H H L H H L X X X L L L H X L H X X X X X X L H NC L H NC H L H L H Z Z Z L H NC H L H Z Z Function High Z High Z Latched Transparent Transparent Latched Preset Clear Preset Clear/High Z Preset/High Z H e HIGH Voltage Level L e LOW Voltage Level X e Immaterial Z e High Impedance NC e No Change Logic Diagram TL/F/9800 – 5 2 Absolute Maximum Ratings (Note 1) Recommended Operating Conditions If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage (VCC) DC Input Diode Current (IIK) VI e b0.5V VI e VCC a 0.5V DC Input Voltage (VI) DC Output Diode Current (IOK) VO e b0.5V VO e VCC a 0.5V DC Output Voltage (VO) DC Output Source or Sink Current (IO) DC VCC or Ground Current per Output Pin (ICC or IGND) Storage Temperature (TSTG) Junction Temperature (TJ) PDIP Supply Voltage (VCC) ’AC ’ACT Input Voltage (VI) b 0.5V to a 7.0V b 20 mA a 20 mA 2.0V to 6.0V 4.5V to 5.5V 0V to VCC 0V to VCC Output Voltage (VO) Operating Temperature (TA) 74AC/ACT b 0.5V to VCC a 0.5V b 40§ C to a 85§ C Minimum Input Edge Rate (DV/Dt) ’AC Devices VIN from 30% to 70% of VCC VCC @ 3.3V, 4.5V, 5.5V Minimum Input Edge Rate (DV/Dt) ’ACT Devices VIN from 0.8V to 2.0V VCC @ 4.5V, 5.5V b 20 mA a 20 mA b 0.5V to VCC a 0.5V g 50 mA g 50 mA 125 mV/ns 125 mV/ns b 65§ C to a 150§ C 140§ C Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. National does not recommend operation of FACT TM circuits outside databook specifications. DC Electrical Characteristics for ’AC Family Devices Symbol Parameter VCC (V) 74AC 74AC TA e a 25§ C TA e b 40§ C to a 85§ C Typ VIH VIL VOH IIN Conditions Guaranteed Limits Minimum High Level Input Voltage 3.0 4.5 5.5 1.5 2.25 2.75 2.1 3.15 3.85 2.1 3.15 3.85 V VOUT e 0.1V or VCC b 0.1V Maximum Low Level Input Voltage 3.0 4.5 5.5 1.5 2.25 2.75 0.9 1.35 1.65 0.9 1.35 1.65 V VOUT e 0.1V or VCC b 0.1V Minimum High Level Output Voltage 3.0 4.5 5.5 2.99 4.49 5.49 2.9 4.4 5.4 2.9 4.4 5.4 V 2.56 3.86 4.86 2.46 3.76 4.76 V 0.1 0.1 0.1 0.1 0.1 0.1 V 3.0 4.5 5.5 0.36 0.36 0.36 0.44 0.44 0.44 V 5.5 g 0.1 g 1.0 mA 3.0 4.5 5.5 VOL Units Maximum Low Level Output Voltage Maximum Input Leakage Current 3.0 4.5 5.5 0.002 0.001 0.001 *All outputs loaded; thresholds on input associated with output under test. 3 IOUT e b50 mA *VIN e VIL or VIH b 12 mA b 24 mA IOH b 24 mA IOUT e 50 mA *VIN e VIL or VIH 12 mA 24 mA IOL 24 mA VI e VCC, GND DC Electrical Characteristics for ’AC Family Devices (Continued) Symbol Parameter VCC (V) 74AC 74AC TA e a 25§ C TA e b 40§ C to a 85§ C Units Conditions g 5.0 mA VI (OE) e VIL, VIH VI e VCC, GND VO e VCC, GND 5.5 75 mA VOLD e 1.65V Max 5.5 b 75 mA VOHD e 3.85V Min 80.0 mA VIN e VCC or GND Typ IOZ IOLD IOHD ICC Maximum TRI-STATE Leakage Current ² Minimum Dynamic Output Current Maximum Quiescent Supply Current Guaranteed Limits 5.5 g 0.5 5.5 8.0 ² Maximum test duration 2.0 ms, one output loaded at a time. Note: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC. DC Electrical Characteristics for ’ACT Family Devices Symbol Parameter VCC (V) 74ACT 74ACT TA e a 25§ C TA e b 40§ C to a 85§ C Typ Units Conditions Guaranteed Limits VIH Minimum High Level Input Voltage 4.5 5.5 1.5 1.5 2.0 2.0 2.0 2.0 V VOUT e 0.1V or VCC b 0.1V VIL Maximum Low Level Input Voltage 4.5 5.5 1.5 1.5 0.8 0.8 0.8 0.8 V VOUT e 0.1V or VCC b 0.1V VOH Minimum High Level Output Voltage 4.5 5.5 4.49 5.49 4.4 5.4 4.4 5.4 V 3.86 4.86 3.76 4.76 V 0.1 0.1 0.1 0.1 V 4.5 5.5 0.36 0.36 0.44 0.44 V 4.5 5.5 VOL Maximum Low Level Output Voltage 4.5 5.5 0.001 0.001 IIN Maximum Input Leakage Current 5.5 g 0.1 g 1.0 mA IOZ Maximum TRI-STATE Leakage Current 5.5 g 0.5 g 5.0 mA ICCT Maximum ICC/Input 5.5 1.5 mA IOLD ² Minimum Dynamic Output Current IOHD ICC Maximum Quiescent Supply Current 0.6 IOUT e b50 mA *VIN e VIL or VIH b 24 mA IOH b 24 mA IOUT e 50 mA *VIN e VIL or VIH 24 mA IOL 24 mA VI e VCC, GND VI e VIL, VIH VO e VCC, GND VI e VCC b 2.1V 5.5 75 mA VOLD e 1.65V Max 5.5 b 75 mA VOHD e 3.85V Min 80.0 mA VIN e VCC or GND 5.5 8.0 *All outputs loaded; thresholds on input associated with output under test. ² Maximum test duration 2.0 ms, one output loaded at a time. 4 AC Electrical Characteristics Symbol Parameter VCC* (V) 74AC 74AC TA e a 25§ C CL e 50 pF TA e b40§ C to a 85§ C CL e 50 pF Units Min Typ Max Min Max tPLH Propagation Delay Dn to On 3.3 5.0 3.5 2.0 6.5 4.5 12.0 8.5 2.5 1.5 13.0 9.0 ns tPHL Propagation Delay Dn to On 3.3 5.0 4.0 2.5 7.0 5.0 12.0 8.5 3.0 1.5 13.0 9.0 ns tPLH Propagation Delay LE to On 3.3 5.0 3.5 2.0 6.5 4.5 12.0 8.5 13.0 1.5 2.5 9.0 ns tPHL Propagation Delay LE to On 3.3 5.0 4.0 2.5 7.0 5.0 12.0 8.5 3.0 1.5 13.0 9.0 ns tPLH Propagation Delay PRE to On 3.3 5.0 5.5 3.5 8.5 6.0 19.0 13.0 4.5 2.5 21.5 14.5 ns tPHL Propagation Delay CLR to On 3.3 5.0 7.5 5.0 11.0 7.5 21.5 15.0 6.0 4.0 24.0 17.0 ns tPZH Output Enable Time OE to On 3.3 5.0 3.5 2.0 6.0 4.5 11.0 8.0 3.0 1.5 12.0 9.0 ns tPZL Output Enable Time OE to On 3.3 5.0 4.0 2.0 6.5 5.0 11.0 8.0 2.5 1.5 12.0 9.0 ns tPHZ Output Disable Time OE to On 3.3 5.0 4.0 3.0 6.5 5.0 10.5 8.0 3.5 2.5 11.0 8.5 ns tPLZ Output Disable Time OE to On 3.3 5.0 3.0 2.0 6.0 4.5 10.5 8.0 2.5 1.5 11.0 8.5 ns tPHL Propagation Delay PRE to On 3.3 5.0 4.5 3.0 7.0 5.0 12.5 9.0 3.5 2.0 13.5 9.5 ns tPLH Propagation Delay CLR to On 3.3 5.0 4.5 3.0 7.0 5.0 12.5 9.0 3.5 2.0 13.5 9.5 ns *Voltage Range 3.3 is 3.3V g 0.3V *Voltage Range 5.0 is 5.0V g 0.5V 5 AC Operating Requirements 74AC 74AC TA e a 25§ C CL e 50 pF TA e b40§ C to a 85§ C CL e 50 pF Parameter VCC* (V) ts Setup Time, HIGH or LOW Dn to LE 3.3 5.0 0 b 0.5 3.0 1.5 3.5 2.0 ns th Hold Time, HIGH or LOW Dn to LE 3.3 5.0 b 0.5 2.0 2.5 2.0 2.5 ns tw LE Pulse Width, HIGH 3.3 5.0 1.5 1.5 3.0 3.0 3.0 3.0 ns tw PRE Pulse Width, LOW 3.3 5.0 5.0 3.0 12.0 8.5 14.5 10.0 ns tw CLR Pulse Width, LOW 3.3 5.0 5.5 4.0 14.0 10.0 16.5 12.0 ns trec PRE Recovery Time 3.3 5.0 1.0 0 3.0 1.5 3.0 1.5 ns trec CLR Recovery Time 3.3 5.0 0 b 0.5 1.5 0.5 1.5 0.5 ns Symbol Typ *Voltage Range 3.3 is 3.3V g 0.3V *Voltage Range 5.0 is 5.0V g 0.5V 6 Units Guaranteed Minimum AC Electrical Characteristics Symbol Parameter VCC* (V) 74ACT 74ACT TA e a 25§ C CL e 50 pF TA e b40§ C to a 85§ C CL e 50 pF Units Min Typ Max Min Max 5.0 2.5 5.5 9.5 2.0 10.0 ns Propagation Delay Dn to On 5.0 2.5 5.5 9.5 2.0 10.0 ns tPLH Propagation Delay LE to On 5.0 2.5 5.5 9.0 2.0 10.0 ns tPHL Propagation Delay LE to On 5.0 2.5 5.5 9.0 2.0 10.0 ns tPLH Propagation Delay PRE to On 5.0 2.5 6.5 14.0 2.0 16.0 ns tPHL Propagation Delay CLR to On 5.0 2.5 7.5 15.5 2.0 17.5 ns tPZH Output Enable Time OE to On 5.0 2.5 5.5 9.5 2.0 10.5 ns tPZL Output Enable Time OE to On 5.0 2.5 5.5 9.5 2.0 10.5 ns tPHZ Output Disable Time OE to On 5.0 2.5 6.0 10.5 2.0 11.0 ns tPLZ Output Disable Time OE to On 5.0 2.5 6.0 10.5 2.0 11.0 ns tPHL Propagation Delay PRE to On 5.0 2.5 6.0 10.5 2.0 11.0 ns tPLH Propagation Delay CLR to On 5.0 2.5 5.5 9.5 2.0 10.5 ns tPLH Propagation Delay Dn to On tPHL *Voltage Range 5.0 is 5.0V g 0.5V AC Operating Requirements Symbol Parameter VCC* (V) Typ 74AC 74AC TA e a 25§ C CL e 50 pF TA e b40§ C to a 85§ C CL e 50 pF Units Guaranteed Minimum ts Setup Time, HIGH or LOW Dn to LE 5.0 b 0.5 0.5 1.0 ns th Hold Time, HIGH or LOW Dn to LE 5.0 0.5 2.0 2.0 ns tw LE Pulse Width, HIGH 5.0 2.0 3.5 3.5 ns tw PRE Pulse Width, LOW 5.0 5.0 8.5 10.0 ns tw CLR Pulse Width, LOW 5.0 5.5 9.5 11.0 ns trec PRE Recovery Time 5.0 0.5 2.0 2.0 ns trec CLR Recovery Time 5.0 b 0.5 1.0 1.0 ns *Voltage Range 5.0 is 5.0V g 0.5V 7 Capacitance Typ Units Conditions CIN Symbol Input Capacitance Parameter 4.5 pF VCC e OPEN CPD Power Dissipation Capacitance 44 pF VCC e 5.0V Ordering Information The device number is used to form part of a simplified purchasing code where a package type and temperature range are defined as follows: 74AC 843 P Temperature Range Family 74AC e Commercial 74ACT e Commercial TTL-Compatible C QR Special Variations X e Devices shipped in 13× reels QR e Commercial grade device with burn-in Device Type Package Code SP e Slim Plastic DIP S e Small Outline (SOIC) Temperature Range C e Commercial (b40§ C to a 85§ C) 8 Physical Dimensions inches (millimeters) 24-Lead Small Outline Integrated Circuit (S) NS Package Number M24B 9 74AC843 # 74ACT843 9-Bit Transparent Latch Physical Dimensions inches (millimeters) (Continued) Lit. Ý 114638 24-Lead Slim (0.300× Wide) Plastic Dual-In-Line Package (SP) NS Package Number N24C LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. National Semiconductor Corporation 2900 Semiconductor Drive P.O. Box 58090 Santa Clara, CA 95052-8090 Tel: 1(800) 272-9959 TWX: (910) 339-9240 National Semiconductor GmbH Livry-Gargan-Str. 10 D-82256 F4urstenfeldbruck Germany Tel: (81-41) 35-0 Telex: 527649 Fax: (81-41) 35-1 National Semiconductor Japan Ltd. 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