ONSEMI NTP75N03R

NTB75N03R, NTP75N03R
Power MOSFET
75 Amps, 25 Volts
N−Channel D2PAK, TO−220
Features
•
•
•
•
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Planar HD3e Process for Fast Switching Performance
Low RDS(on) to Minimize Conduction Loss
Low Ciss to Minimize Driver Loss
Low Gate Charge
75 AMPERES
25 VOLTS
RDS(on) = 5.6 mΩ (Typ)
MAXIMUM RATINGS (TJ = 25°C Unless otherwise specified)
Parameter
4
Symbol
Value
Unit
Drain−to−Source Voltage
VDSS
25
Vdc
Gate−to−Source Voltage − Continuous
VGS
±20
Vdc
Thermal Resistance − Junction−to−Case
Total Power Dissipation @ TC = 25°C
Drain Current
− Continuous @ TC = 25°C
− Single Pulse (tp = 10 s)
RJC
PD
1.68
74.4
°C/W
W
ID
IDM
75
225
A
A
Thermal Resistance − Junction−to−Ambient
(Note 1)
Total Power Dissipation @ TA = 25°C
Drain Current − Continuous @ TA = 25°C
RJA
60
°C/W
PD
ID
2.08
12.6
W
A
Thermal Resistance − Junction−to−Ambient
(Note 2)
Total Power Dissipation @ TA = 25°C
Drain Current − Continuous @ TA = 25°C
RJA
100
°C/W
PD
ID
1.25
9.7
W
A
Operating and Storage Temperature Range
TJ, Tstg
−55 to
150
°C
Single Pulse Drain−to−Source Avalanche
Energy − Starting TJ = 25°C
(VDD = 30 Vdc, VGS = 10 Vdc, IL = 12 Apk,
L = 1 mH, RG = 25 )
EAS
71.7
mJ
Maximum Lead Temperature for Soldering
Purposes, 1/8″ from Case for 10 Seconds
TL
4
1
3
1
°C
1. When surface mounted to an FR4 board using 1 inch pad size,
(Cu Area 1.127 in2).
2. When surface mounted to an FR4 board using minimum recommended pad
size, (Cu Area 0.412 in2).
D2PAK
CASE 418AA
STYLE 2
TO−220AB
CASE 221A
STYLE 5
2
3
MARKING DIAGRAMS
& PIN ASSIGNMENTS
4
Drain
4
Drain
75N03R
YWW
P75N03R
YWW
1
Gate
260
2
3
Source
2
Drain
1
Gate
75N03
Y
WW
2
Drain
3
Source
= Device Code
= Year
= Work Week
ORDERING INFORMATION
Package
Shipping†
NTP75N03R
TO−220AB
50 Units/Rail
NTB75N03R
D2PAK
50 Units/Rail
NTB75N03RT4
D2PAK
800/Tape & Reel
Device
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
 Semiconductor Components Industries, LLC, 2003
October, 2003 − Rev. 2
1
Publication Order Number:
NTB75N03R/D
NTB75N03R, NTP75N03R
ELECTRICAL CHARACTERISTICS (TJ = 25°C Unless otherwise specified)
Characteristics
Symbol
Min
Typ
Max
25
−
28
20.5
−
−
−
−
−
−
1.0
10
−
−
±100
1.0
−
1.5
4.0
2.0
−
−
−
8.1
5.6
13
8.0
−
27
−
Ciss
−
1333
−
Coss
−
600
−
Crss
−
218
−
td(on)
−
6.9
−
tr
−
1.3
−
td(off)
−
18.4
−
tf
−
5.5
−
QT
−
13.2
−
Q1
−
3.3
−
Q2
−
6.2
−
−
−
0.86
0 73
0.73
1.2
−
trr
−
15.6
−
ta
−
13.8
−
tb
−
1.78
−
QRR
−
0.004
−
Unit
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage (Note 3)
(VGS = 0 Vdc, ID = 250 Adc)
Temperature Coefficient (Positive)
V(br)DSS
Zero Gate Voltage Drain Current
(VDS = 20 Vdc, VGS = 0 Vdc)
(VDS = 20 Vdc, VGS = 0 Vdc, TJ = 150°C)
IDSS
Gate−Body Leakage Current
(VGS = ±20 Vdc, VDS = 0 Vdc)
IGSS
Vdc
mV/°C
Adc
nAdc
ON CHARACTERISTICS (Note 3)
Gate Threshold Voltage (Note 3)
(VDS = VGS, ID = 250 Adc)
Threshold Temperature Coefficient (Negative)
VGS(th)
Static Drain−to−Source On−Resistance (Note 3)
(VGS = 4.5 Vdc, ID = 20 Adc)
(VGS = 10 Vdc, ID = 20 Adc)
RDS(on)
Forward Transconductance (Note 3)
(VDS = 10 Vdc, ID = 15 Adc)
Vdc
mV/°C
m
gFS
Mhos
DYNAMIC CHARACTERISTICS
Input Capacitance
(VDS = 20 Vdc, VGS = 0 V,
f = 1 MHz)
Output Capacitance
Transfer Capacitance
pF
SWITCHING CHARACTERISTICS (Note 4)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
(VGS = 10 Vdc, VDD = 10 Vdc,
ID = 30 Adc, RG = 3)
Fall Time
Gate Charge
(VGS = 5 Vdc, ID = 30 Adc,
VDS = 10 Vdc) (Note 3)
ns
nC
SOURCE−DRAIN DIODE CHARACTERISTICS
Forward On−Voltage
VSD
((IS = 20 Adc, VGS = 0 Vdc) ((Note 3))
(IS = 20 Adc, VGS = 0 Vdc, TJ = 125°C)
Reverse Recovery Time
(IS = 35 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/s) (Note 3)
Reverse Recovery Stored Charge
3. Pulse Test: Pulse Width = 300 s, Duty Cycle = 2%.
4. Switching characteristics are independent of operating junction temperatures.
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2
Vdc
ns
C
NTB75N03R, NTP75N03R
10 V
140
5V
120
8V
6V
100
VDS ≥ 10 V
4.5 V
ID, DRAIN CURRENT (AMPS)
ID, DRAIN CURRENT (AMPS)
140
4V
80
3.5 V
60
3V
40
20
VGS = 2.5 V
0
2
6
4
80
60
TJ = 25°C
40
TJ = 125°C
20
10
8
TJ = −55°C
0
4
3
5
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
RDS(on), DRAIN−TO−SOURCE RESISTANCE (Ω)
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)
0.022
VGS = 10 V
0.018
0.014
TJ = 150°C
0.010
TJ = 125°C
0.006
TJ = 25°C
TJ = −55°C
0.002
20
0
2
1
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
40
80
60
100
120
140
6
0.022
VGS = 4.5 V
TJ = 150°C
0.018
0.014
TJ = 125°C
0.010
TJ = 25°C
0.006
TJ = −55°C
0.002
0
20
40
60
80
100
120
140
ID, DRAIN CURRENT (AMPS)
ID, DRAIN CURRENT (AMPS)
Figure 3. On−Resistance versus Drain Current
and Temperature
Figure 4. On−Resistance versus Drain Current
and Temperature
100,000
1.8
1.6
VGS = 0 V
ID = 30 A
VGS = 10 V
IDSS, LEAKAGE (nA)
RDS(on), DRAIN−TO−SOURCE RESISTANCE (Ω)
100
0
0
RDS(on), DRAIN−TO−SOURCE RESISTANCE
(NORMALIZED)
120
TJ = 150°C
10,000
1.4
1.2
1.0
TJ = 125°C
1000
0.8
0.6
−50
100
−25
0
25
50
75
100
125
150
0
5
10
15
20
TJ, JUNCTION TEMPERATURE (°C)
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
versus Voltage
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3
25
NTB75N03R, NTP75N03R
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (∆t)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The published capacitance data is difficult to use for
calculating rise and fall because drain−gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
average input current (IG(AV)) can be made from a
rudimentary analysis of the drive circuit so that
t = Q/IG(AV)
The capacitance (Ciss) is read from the capacitance curve at
a voltage corresponding to the off−state condition when
calculating td(on) and is read at a voltage corresponding to the
on−state when calculating td(off).
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate
resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
components. Most power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
approximates an optimally snubbed inductive load. Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.
During the rise and fall time interval when switching a
resistive load, VGS remains virtually constant at a level
known as the plateau voltage, VSGP. Therefore, rise and fall
times may be approximated by the following:
tr = Q2 x RG/(VGG − VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turn−on and turn−off delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG − VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
2400
TJ = 25°C
Ciss
C, CAPACITANCE (pF)
2000
1600
Crss
Ciss
1200
800
Coss
400
Crss
VDS = 0 V VGS = 0 V
0
10
0
5
VGS
5
10
15
20
VDS
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
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4
8
1000
6
VGS
t, TIME (ns)
VGS , GATE−TO−SOURCE VOLTAGE (VOLTS)
NTB75N03R, NTP75N03R
QT
4
Q1
Q2
100
td(off)
10
td(on)
2
0
tr
1
0
4
8
12
QG, TOTAL GATE CHARGE (nC)
VDS = 10 V
ID = 35 A
VGS = 10 V
tf
ID = 35 A
TJ = 25°C
16
1
Figure 8. Gate−To−Source and Drain−To−Source
Voltage versus Total Charge
10
RG, GATE RESISTANCE (OHMS)
100
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
DRAIN−TO−SOURCE DIODE CHARACTERISTICS
IS, SOURCE CURRENT (AMPS)
70
VGS = 0 V
60
50
40
30
TJ = 150°C
20
10
TJ = 25°C
0
0
0.6
0.8
0.2
0.4
VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
1.0
Figure 10. Diode Forward Voltage versus Current
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain−to−source voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
junction temperature and a case temperature (TC) of 25°C.
Peak repetitive pulsed power limits are determined by using
the thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance −
General Data and Its Use.”
Switching between the off−state and the on−state may
traverse any load line provided neither rated peak current
(IDM) nor rated voltage (VDSS) is exceeded and the
transition time (tr,tf) do not exceed 10 µs. In addition the total
power averaged over a complete switching cycle must not
exceed (TJ(MAX) − TC)/(RθJC).
A Power MOSFET designated E−FET can be safely used
in switching circuits with unclamped inductive loads. For
reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and adjusted for operating conditions
differing from those specified. Although industry practice is
to rate in terms of energy, avalanche energy capability is not
a constant. The energy rating decreases non−linearly with an
increase of peak current in avalanche and peak junction
temperature.
Although many E−FETs can withstand the stress of
drain−to−source avalanche at currents up to rated pulsed
current (IDM), the energy rating is specified at rated
continuous current (ID), in accordance with industry custom.
The energy rating must be derated for temperature as shown
in the accompanying graph (Figure 12). Maximum energy at
currents below rated continuous ID can safely be assumed to
equal the values indicated.
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5
NTB75N03R, NTP75N03R
SAFE OPERATING AREA
I D, DRAIN CURRENT (AMPS)
1000
VGS = 20 V
SINGLE PULSE
TC = 25°C
100
10 µs
100 µs
10
1 ms
10 ms
dc
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
1
10
1
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
0.1
100
r(t), EFFECTIVE TRANSIENT THERMAL
RESISTANCE (NORMALIZED)
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
1
D = 0.5
0.2
P(pk)
0.1
0.05
t1
0.01
t2
DUTY CYCLE, D = t1/t2
SINGLE PULSE
0.1
0.0001
0.001
0.01
0.1
t, TIME (s)
Figure 12. Thermal Response
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6
RθJC(t) = r(t) RθJC
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) − TC = P(pk) RθJC(t)
1
10
NTB75N03R, NTP75N03R
PACKAGE DIMENSIONS
D2PAK
CASE 418AA−01
ISSUE O
C
NOTES:
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
E
V
W
−B−
4
DIM
A
B
C
D
E
F
G
J
K
M
S
V
A
1
2
S
3
−T−
SEATING
PLANE
K
W
J
G
D
STYLE 2:
PIN 1.
2.
3.
4.
3 PL
0.13 (0.005)
T B
M
M
VARIABLE
CONFIGURATION
ZONE
U
M
INCHES
MIN
MAX
0.340 0.380
0.380 0.405
0.160 0.190
0.020 0.036
0.045 0.055
0.310
−−−
0.100 BSC
0.018 0.025
0.090
0.110
0.280
−−−
0.575 0.625
0.045 0.055
M
M
F
F
F
VIEW W−W
1
VIEW W−W
2
VIEW W−W
3
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7
GATE
DRAIN
SOURCE
DRAIN
MILLIMETERS
MIN
MAX
8.64
9.65
9.65 10.29
4.06
4.83
0.51
0.92
1.14
1.40
7.87
−−−
2.54 BSC
0.46
0.64
2.29
2.79
7.11
−−−
14.60 15.88
1.14
1.40
NTB75N03R, NTP75N03R
PACKAGE DIMENSIONS
TO−220
CASE 221A−09
ISSUE AA
SEATING
PLANE
−T−
B
C
F
T
S
4
DIM
A
B
C
D
F
G
H
J
K
L
N
Q
R
S
T
U
V
Z
A
Q
1 2 3
U
H
K
Z
L
R
V
J
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION Z DEFINES A ZONE WHERE ALL
BODY AND LEAD IRREGULARITIES ARE
ALLOWED.
G
D
N
INCHES
MIN
MAX
0.570
0.620
0.380
0.405
0.160
0.190
0.025
0.035
0.142
0.147
0.095
0.105
0.110
0.155
0.018
0.025
0.500
0.562
0.045
0.060
0.190
0.210
0.100
0.120
0.080
0.110
0.045
0.055
0.235
0.255
0.000
0.050
0.045
−−−
−−−
0.080
STYLE 5:
PIN 1.
2.
3.
4.
MILLIMETERS
MIN
MAX
14.48
15.75
9.66
10.28
4.07
4.82
0.64
0.88
3.61
3.73
2.42
2.66
2.80
3.93
0.46
0.64
12.70
14.27
1.15
1.52
4.83
5.33
2.54
3.04
2.04
2.79
1.15
1.39
5.97
6.47
0.00
1.27
1.15
−−−
−−−
2.04
GATE
DRAIN
SOURCE
DRAIN
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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8
For additional information, please contact your
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NTB75N03R/D