STEL-2060C/CR Data Sheet STEL-2060C/CR 45 Mbps Viterbi Decoder R Powered by ICminer.com Electronic-Library Service CopyRight 2003 FUNCTIONAL DESCRIPTION FEATURES ■ 45 Mbps Operating Rate ■ Constraint Length K = 7 G1 = 1718 Convolutional encoding and Viterbi decoding are used to provide forward error correction (FEC) which improves digital communication performance over a noisy link. The STEL-2060C is a specialized product designed to perform this specific communications related function. At the encoder a stream of symbols is created which introduces a high degree of redundancy. This enables accurate decoding of the information despite a high symbol error rate resulting from an impaired communications link. G2 = 1338 ■ Multiple Rates: Rate 1/2 as well as Punctured codes at Rates 2/3 through 7/8 ■ Internal Depuncturing Capability at Rates 2 /3, 3/4 and 7/8 ■ Multiple Devices can be Multiplexed to Give Higher Data Rates ■ Optimized Interface to Operate with BPSK and QPSK Demodulators ■ ■ ■ ■ Auto Node Sync Capability ■ ■ ■ 5.2 dB Coding Gain @10-5 BER (R = 1/2) The STEL-2060C contains a K = 7 Viterbi Decoder. The data inputs can be in offset binary or offset signed-magnitude formats, with 3-bit soft decision. Auto node sync is provided for applications where symbol uncertainty can occur. Rate 2 /3, 3/4, 4/5, 5/6, 6/7 and 7/8 punctured signals can be decoded, as well as non-punctured, Rate 1/2, signals. The polynomials and puncturing patterns used are industry standards. Depuncturing logic is incorporated into the decoder to provide automatic depuncturing of received data at rates 2/3, 3/4 and 7/8 when the puncturing patterns supported by the device are used. A BER monitor is also provided in the device, along with a circuit for computing the mean value of the BER over an extended period. These circuits operate with punctured codes as well as unpunctured. The STEL-2060C incorporates a descrambler for signals scrambled with the “Invert G2” algorithm. (With this method the G2 symbols are logically inverted at the encoder. This provides a very effective level of scrambling for the purpose of avoiding long strings of ones or zeroes in the transmitted signal using BPSK modulation.) Differential Decoder “Invert G2” Descrambler Internal BER Monitor and BER Measurement Circuit 100-pin PQFP Package 0.5 Micron CMOS Technology BLOCK DIAGRAM DSCRAM OBIN PARL LDG2 G1 G2 SYMBOL ALIGNMENT AND DEPUNCTURING CIRCUIT 3 3 2 PNCG1/G2 BRANCH METRIC ASSIGNMENT VITERBI DECODER (ACS) TRACEBACK MEMORY SYMCKIN DCLKIN SYNC RATE EXTSEL THRES H COUNT NODE SYNC CONTROL 3 OOS TIMING AND CONTROL 8 8 DATO DIFFERENTIAL DECODER DDIF DATA ADDR WR AUTO ODCLK 8 3 µP INTERFACE BER MONITOR AND COUNTER RD CSEL RESET TO ALL REGISTERS STEL-2060C Powered by ICminer.com Electronic-Library Service CopyRight 2003 2 BERR G1ERR G2ERR INT PIN CONFIGURATION Package: 100-pin HQFP Thermal coefficient, θja = 30° C/W 0.941" ± 0.010" 0.742" ±0.005" 80 81 51 50 Top View 0.487" ±0.003" 0.705" ± 0.010" 0.11" nom. 0.009" ± 0.005" Pin 1 Identifier 31 100 1 0.031" ± 0.005" 30 Detail of pins 0.0256" ±0.002" Notes: (1) (2) (3) (4) 0.014" ± 0.002" 0.122" max. Tolerances on pin spacing are not cumulative Dimensions shown are at seating plane I.C. denotes Internal Connection. This pin must be left unconnected. Do not use for vias. N.C. denotes No Connection. These pins can be used for vias. PIN CONNECTIONS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 VDD N.C. N.C. G10 G11 G12 G20 G21 G22 N.C. OBIN N.C. VSS SYMCKIN N.C. VSS DCLKIN N.C. VSS RESET 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 VSS N.C. PNCG1 PNCG2 DSCRAM SYNC LDG2 N.C. N.C. VDD VDD COUNT0 COUNT1 COUNT2 COUNT3 COUNT4 COUNT5 COUNT6 COUNT7 VDD 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 VSS VDD PARL READ VSS ADDR2 ADDR1 ADDR0 WRITE CSEL VDD VDD N.C. DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 3 Powered by ICminer.com Electronic-Library Service CopyRight 2003 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 DATA0 N.C. INT N.C. VSS ODCLK N.C. VSS DATO N.C. OOS AUTO N.C. I.C. N.C. BERR G1ERR G2ERR VDD VDD 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 THR0 THR1 THR2 THR3 THR4 THR5 THR6 THR7 EXTSEL VSS VSS VSS VDD VSS DDIF VSS RATE2 RATE1 RATE0 VDD STEL-2060C INPUT SIGNALS RESET inputs are accepted sequentially, using the G12-0 pins for both symbols. The sequential input is most suited for BPSK data, and the parallel input is most suited for QPSK data. The auto node sync sequence will operate on the assumption that the signal is BPSK modulated when PARL is set low and QPSK modulated when it is set high. Setting PARL low adds two cycles of ODCLK to the pipeline delay. Reset. A logic low on this asynchronous input will completely reset all registers in the decoder to an initial condition within 20 nsec. Normal operation will commence after RESET goes high. This will not affect the values stored in the decision path memory but will reset the node sync state to the initial condition. DCLKIN OBIN Decoder clock input. It is the reference clock for all internal synchronous functions in the decoder when operating in the Internal Puncturing mode. It should nominally be a square wave with a maximum frequency of 45 MHz, corresponding to a decoded data rate of 45 Mbps. When operating at Rate 1 /2 and in the External Puncturing mode this clock will be generated internally from SYMCKIN, and DCLKIN should be connected to ground. The STEL-2060CCC can accept the soft-decision input data in either offset binary or offset signed-magnitude formats. When the OBIN input is set high, the format expected will be offset binary; when it is set low it will be offset signedmagnitude. The meanings of the 3-bit values for these two codes is shown in the following table: SYMCKIN Symbol clock input. This is the reference clock for all internal synchronous functions in the symbol alignment and depuncturing circuits. It should nominally be a square wave with a maximum frequency of 90 MHz. Its frequency should be equal to f DCLKIN/2R in the parallel input mode (PARL = 1) and equal to fDCLKIN/R in the sequential input mode (PARL = 0), where R is the decoding rate when using internal depuncturing. Please refer to the section on Punctured Mode Operation for more detailed information. OBIN = 1 OBIN = 0 Value 111 110 111 110 Most confident + (Data = 1) 101 100 101 100 Least confident + 011 010 000 001 Least confident – 001 000 010 011 (Data = 0) Most confident – When using the STEL-2060CCC with hard-decision data, the symbols should be loaded into the G12 and G22 pins. The other symbol inputs should be set to a logic high level and OBIN should be set low. G12-0, G22-0 The G12-0 and G22-0 signals are the 3-bit soft decision input symbols to the decoder. They are presented to the decoder either sequentially or in parallel depending on the states of the PARL and RATE2-0 inputs. In the parallel mode (PARL = 1) the symbols are clocked into the device on the rising edges of SYMCKIN when RATE2-0 = 0 (Rate 1/2 and External Depuncturing) and on both edges of SYMCKIN when RATE2-0 ≠ 0 (Internal Depuncturing). In the sequential mode (PARL␣ = 0) in which theG22-0 inputs are not used, both the G1 and G2 symbols are loaded via the G12-0 pins. The G1 symbols are then latched in on the rising edges of SYMCKIN when LDG2 is low and the G2 symbols are latched in on the rising edges of SYMCKIN when LDG2 is high. RATE2-0 These signals select the decoding rate for unpunctured operation (Rate 1/2) and internally supported depuncturing patterns (Rates 2/3, 3/4 and 7/8). These patterns are shown in the following table, where a 0 in the pattern indicates a punctured symbol: RATE2-0 Rate Pattern 0 0 0 1 /2 N.A. 0 0 1 2 /3 G1: 10 G2: 11 1 0 0 3 /4 G1: 101 G2: 110 0 1 0 7 /8 G1: 1000101 LDG2 When this signal is high during a rising edge of SYMCKIN the symbol loaded into the G12-0 pins will be G2. This function is only active when PARL is set low (sequential input mode) and RATE2-0 is set to 000 (Rate 1/2 operation or External Puncturing mode). If auto node sync is used, the LDG2 signal can be derived by dividing the SYMCKIN signal by two. The auto node sync will then compensate for the phase ambiguity. Other puncturing patterns can be implemented externally using the PNCG1 and PNCG2 inputs. PARL DDIF When this signal is high, the input symbols are accepted in parallel by the chip, using the G12-0 pins for the G1 symbols and the G22-0 pins for the G2 symbols. When it is set low, the When this input is set high, it causes the data out of the Viterbi decoder to be differentially decoded. This adds one cycle of ODCLK to the pipeline delay. STEL-2060C Powered by ICminer.com Electronic-Library Service CopyRight 2003 G2: 1111010 4 OUTPUT SIGNALS DSCRAM ODCLK When this input is set high, it causes the G2 symbols to be inverted before they enter the Viterbi decoder, thereby reversing the effect of the G2 inversion if an "Invert G2" scrambler is implemented at the encoder. Output data clock. All outputs change on the rising edge of this clock. The falling edge of ODCLK can be used as a strobe for DATO output, which is guaranteed to be valid on this edge. PNCG1, PNCG2 DATO The PNCG1 and PNCG2 signals are used to control the STEL-2060CCC when operating in punctured modes not supported by the internal puncturing logic. In normal operation (Rate 1/2 and when using internal puncturing) these pins should be set low. In the external depuncturing mode, the PNCG1 signal must be set high to indicate that the G1 symbol is punctured and the PNCG2 signal must be set high to indicate that the G2 symbol is punctured. A symbol will be depunctured when the PNCG1 or PNCG2 signals are high during the rising edge of SYMCKIN which latches the corresponding symbol in to the decoder. RATE2-0 should be set to 000 when operating in external depuncturing mode. Zero value metrics will be substituted internally for the actual metrics corresponding to the signals present on the G12-0 and G22-0 pins at that time. Internal depuncturing can be selected by the use of the RATE inputs. Decoded data output. This is the output of the Viterbi decoder. This signal changes on the rising edges of ODCLK. In Rate 1/2 operation there will be a pipeline delay of 526 cycles of ODCLK from the G12-0/G22-0 inputs to the DATO output when DDIF is set low and PARL is set high. Setting DDIF high adds one cycle to this value and setting PARL low adds two cycles. OOS This output pin serves as a flag for the out-of-sync condition. When it goes high it signifies that the renormalization count in the internal node sync circuit has exceeded the threshold value set by the THR7-0 signal, declaring an out-of-sync condition. It will remain high until this condition ceases to exist. i.e., until the next time the threshold is not exceeded during a complete count period. AUTO SYNC When the SYNC input is set high during the rising edge of SYMCKIN the internal symbol synchronization will be changed. When auto node sync is not desired this pin should be set low. It should be connected to the AUTO output to use the auto node sync capability of the STEL-2060CCC. The state of this circuit will always be set to normal after a reset. This is the feedback signal from the internal node sync correction circuit. It will pulse high for one cycle of DCLKIN each time the renormalization count in the internal node sync circuit has exceeded the threshold value set by the THR7-0 signal and the out-of-sync condition is declared. It should be connected to the SYNC input when using the internal node sync facility. COUNT7-0 BERR The 8-bit COUNT7-0 input defines the period (number of bits) used in the node synchronization circuit when EXTSEL is set high. The 8-bit number N is used to set up a period of (256N + 256) bits internally, where N is the value of COUNT7-0. An out-of-sync condition is declared (i.e., the output pin OOS is set high and AUTO pulses high) if the renormalization count exceeds the threshold value during a period of this number of bits. The Bit Error output indicates that an error has been detected in either the G1 or G2 symbols corresponding to the current output bit. G1ERR The G1 Error output indicates that an error has been detected in the G1 symbol corresponding to the current output bit. G2ERR The G2 Error output indicates that an error has been detected in the G2 symbol corresponding to the current output bit. Note: The BERR, G1ERR and G2ERR signals are in NRZ format, i.e., the signals will not return to zero between two consecutive errors. To generate pulsed outputs, the signals can be gated with the ODCLK signal. THR7-0 The 8-bit THR7-0 input defines the threshold for node synchronization when EXTSEL is set high. The 8-bit number N is used to set up a threshold value of (8N + 6) internally, where N is the value of THR7-0. An out-of-sync condition is declared (i.e., the output pin OOS is set high and AUTO pulses high) if the renormalization count exceeds this threshold value. MICROPROCESSOR INTERFACE DATA7-0 EXTSEL All I/O and control functions can be accessed via the DATA7-0 bus with the associated control signals. The STEL-2060CCC is used as a memory or I/O mapped peripheral to the host processor. When the EXTSEL input is set high, the COUNT7-0 and THR7-0 information is derived from the COUNT7-0 and THR7-0 input pins. When it is set low, this information is derived from the data written into addresses 0 and 1. 5 Powered by ICminer.com Electronic-Library Service CopyRight 2003 STEL-2060C ADDR2-0 Since the default (reset) value of the BPER23-0 register is FF FF FFH a potential problem occurs if the desired value is not written into this register before the value of the counter has already incremented past this value. If this is not done the equality will not be detected until after the counter overflows and increments to the desired value once again. Even at the maximum rate of 45 Mbps this will take over 6 minutes and, at a more modest data rate, such as 1 Mbps, it will take over 41/2 hours! In any case, the user can easily be misled into believing that the circuit is not operating correctly since the interrupts will not be generated as expected. It is therefore imperative that the BPER23-0 value be written into the STEL-2060CCC as soon as possible after a reset to ensure that this condition does not take place. The maximum time allowable is just less than the desired interrupt period itself, since the counter begins counting right after the reset is released. e.g., if the desired interrupt period is one second, the BPER23-0 value must be written within one second of the reset. At a data rate of 1 Mbps the period would correspond to 106 bits and the correct BPER23-0 value would be 103, or 00 03 E8H. If, for some reason, it is not possible to do this, a dummy value should first be written into the STEL-2060CCC. This should be large enough so that, at the time of writing, the bit counter will not have exceeded the dummy value. In this way the first interrupt will be generated within a reasonable period of time and the dummy value can then be overwritten with the desired value. Again, care must be taken to ensure that the BPER 23-0 value written is greater than the instantaneous counter value, otherwise the same problem will occur. e.g., in the above example, if it is not possible to write the BPER23-0 value until 5 seconds after the reset, then a dummy BPER23-0 value corresponding to >5 seconds, e.g., 6 seconds, or 00 17 70H should first be written. The desired value of 00 03 E8H must then be written within one second of an interrupt generated by the STEL-2060CCC, thereby ensuring that the counter has not exceeded the new value at that time. The 3-bit address bus is used to access the various I/O functions, as shown in the Memory Map table, below. Note that some addresses contain both Read and Write registers. These read and write mode registers are separate and contain different data. WRITE The Write input is used to write data to the microprocessor data bus. It is active low and is normally connected to the write line of the host processor. READ The Read input is used to read data from the microprocessor data bus. It is active low and is normally connected to the read line of the host processor. CSEL The Chip Select input can be used to selectively enable the microprocessor data bus. It is active low. INT The Interrupt output indicates when the Period Counter in the BER Monitor has completed a count period, and that a new value of BERCT is ready to be read from addresses 0H and 1H, when INT will go high for one symbol period. INPUT (WRITE) FUNCTIONS COUNT7-0 The 8-bit COUNT7-0 data defines the period (i.e., the number of bits) used in the node synchronization circuit. The 8-bit number N is used to set up a period of (256N + 256) internally, where N is the value of COUNT7-0. If the renormalization count exceeds the threshold value during a period of this number of bits then an out-of-sync condition is declared (i.e., the output pin OOS is set high and AUTO pulses high). Reset value 00H. THR7-0 The 8-bit THR7-0 data defines the threshold for node synchronization when EXTSEL is set low. The function is identical to that of the THR7-0 input signal. Reset value 00H. BPER23-0 OUTPUT (READ) FUNCTIONS The 24-bit BER Period data is used to set the period (number of data bits) over which the mean BER is measured by the BER Monitor. The period used is 1000 times the value of BPER23-0. Reset value FFFFFFH. Note: The BER Count function incorporated in the STEL-2060CCC uses a counter to count the number of thousands of bits received. When the value of this counter is equal to the value written into BPER23-0 the number of errors counted is dumped into the BERCT15-0 output register and can be read from read addresses 0-1H. Simultaneously, both the error and bit counters are reset and the process is restarted, and an interrupt (INT) is generated to indicate that the new value is ready to be read. STEL-2060C Powered by ICminer.com Electronic-Library Service CopyRight 2003 BERCT15-0 The 16-bit Bit Error Count data represents the mean Bit Error Rate over the period determined by the BER Period data BPER23-0. The actual BER is given by: BER = 8 x BERCT15-0 1000 x BPER23-0 The value will be updated each time the period counter completes its count. Completion is indicated by the INT output going high for one clock cycle. If the accumulator overflows during a measurement period its output will be caused to saturate at a value of FFFFH. 6 MICROPROCESSOR INTERFACE MEMORY MAP WRITE MODE REGISTERS ADDR2-0 DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 0 1 COUNT7 THR7 COUNT6 THR6 COUNT5 THR5 COUNT4 THR4 COUNT3 THR3 COUNT2 THR2 COUNT1 THR1 COUNT0 THR0 2 3 BPER7 BPER6 BPER5 BPER4 BPER3 BPER2 BPER1 BPER0 4 5 BPER15 BPER23 BPER14 BPER22 BPER13 BPER21 BPER12 BPER20 BPER11 BPER19 BPER10 BPER18 BPER9 BPER17 BPER8 BPER16 READ MODE REGISTERS ADDR2-0 0 1 DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 BERCT7 BERCT15 BERCT6 BERCT14 BERCT5 BERCT13 BERCT4 BERCT12 BERCT3 BERCT11 BERCT2 BERCT10 BERCT1 BERCT9 BERCT0 BERCT8 PUNCTURED MODE OPERATION CONCEPT OF PUNCTURING USING INTERNAL DEPUNCTURING In punctured codes some of the symbols generated by the convolutional encoder are deleted, or punctured, from the transmitted sequence. For example, in a rate 1 / 2 (unpunctured) sequence, four symbols are transmitted for every two data bits. If one symbol out of every group of four was punctured from the sequence then only three symbols would be transmitted for every two data bits. This would result in a rate 2/3 code. The coding gain is significantly less than that for unpunctured operation, but this is the trade-off for the reduced bandwidth required to transmit the information. The STEL-2060CC decoder is designed to operate with punctured codes as well as rate 1 /2 code. Two methods are provided for depuncturing the symbols. The external method can be used for all rates and patterns up to rate 7/8 by indicating which symbols were punctured at the encoder (and then reinserted prior to decoding) with the PNCG1 and PNCG2 signals. When one of these signals is set high the input data at the corresponding symbol input is ignored, and the internally generated metric for the symbol pair (G1 and G2) assigns a zero weight to the punctured symbol in the pair. This is done because the Viterbi decoder has no way of knowing what the punctured symbol should have been. The recommended puncturing sequences for the various (N-1)/ N rates of punctured operation are shown in the tables. The portions shown in boldface are the basic sequences, which are then repeated. The use of the PNCG1 and PNCG2 signals for rate 3/4 is shown in the External Puncturing timing diagrams. The sequence for rate 3/4 is G1 G2 P G2 G1 P, and the punctured symbols are marked with asterisks in the timing diagrams. The internal depuncturing method supports Rates 2/3, 3/4 and 7/8 using the puncturing sequences specified in the tables, and the node sync process will automatically find the correct places to reinsert the punctured symbols. The puncturing sequences used for the rates supported are shown in the tables, along with the speeds of the two input clocks, SYMCKIN and DCLKIN. The portions shown in boldface are the basic sequences, which are then repeated. The symbol sequence for rate 2/3 is shown in the Internal Puncturing timing diagrams. The sequence is G1 G2 P G2; only G1 symbols are punctured in this particular sequence. The SYMCKIN and DCLKIN clocks are used to clock in the symbols and to clock out the data bits. The speeds of these two clocks vary according to the modes and rate in use. When operating in the External Depuncturing modes the DCLKIN signal is not used and the SYMCKIN speed will be equal to the data rate (D) in the parallel mode (PARL = 1) and be equal to twice the data rate (2D) in the sequential mode (PARL = 0). In the Internal Depuncturing modes, however, DCLKIN is used and the speed of SYMCKIN will be as shown in the tables. The depuncturing circuit in the STEL-2060CC takes symbols synchronized to the SYMCKIN signal and depunctures them, i.e., inserts dummy symbols into the signal stream at the appropriate positions. To do this the circuit handles the symbols as a group of up to four pairs, depending on the code rate. This circuit operates at the SYMCKIN rate and, at this point, the group of depunctured symbols is transferred into another set of registers clocked with DCLKIN. There is an internal timing requirement that the falling edge of DCLKIN 7 Powered by ICminer.com Electronic-Library Service CopyRight 2003 STEL-2060C must follow the rising edge of SYMCKIN by a minimum of 8 nsec. at this instant, otherwise the handover will not occur correctly. This occurs once every 4 cycles of DCLKIN at rate 7 /8, every 2 cycles at rate 3/4 and every 3 cycles at rate 2/3, the number of cycles of SYMCKIN depending on whether the parallel or sequential input mode is used, as well as the code rate. Two examples of clock phasing for rate 3/4 parallel operation are shown below. Here, the timing is such that the falling edges of DCLKIN only coincide with falling edges of SYMCKIN, never with rising edges. In this case the timing violation never occurs at any speed, since the non-coincident falling edges of DCLKIN will trail the rising edges of SYMCKIN by approximately 8 nsec. at a speed of 45 Mbps. Again, the same caveat regarding jitter must be observed. However, the symbol signal setup and hold requirements, shown in page 11 of the data sheet make it necessary for SYMCKIN to have a minimum low time of 12 nsec. to satisfy these requirements, so that it is not possible for this signal to be a square wave above 40 MHz for this reason. Since the method for eliminating the clock timing violation presented here relies on the use of square waves (50% mark-space ratio), it cannot be used above 40 MHz because of the setup and hold time requirements. Again, a similar condition exists for rate 7/8 operation, as shown below. SYMCKIN Good Bad DCLKIN In the first example the falling edges of DCLKIN never coincide with the rising edges of SYMCKIN. Thus the timing violation will never occur provided that the delay from the non-coincident rising edges of SYMCKIN to the following falling edge of DCLKIN (shown by the arrows) exceeds 8 nsec. In the second case the falling edge of DCLKIN coincides with the rising edge of SYMCKIN once every two cycles of DCLKIN, resulting in a 50% probability that this may be the point at which the handover occurs, creating the problem discussed above. There are several ways to satisfy the timing requirement, depending on the code rate. One effective way which works at all rates is to generate SYMCKIN from DCLKIN by puncturing the clock to reduce its frequency while keeping all the edges synchronized; this will require the use of a small FIFO to buffer the input symbols to cope with the punctured clock. The rate 3/4 timing is shown below as an example. SYMCKIN DCLKIN However, in this case the timing violation will begin to occur at speeds over 15 Mbps, so that this method of solving the timing problem is less useful for rate 7/8 operation. Note that for sequential mode operation (PARL = 0) the frequency of the SYMCKIN signal will be doubled in every case. This presents a problem with the synchronized clock method presented here since it will not be possible to generate the necessary waveforms with the correct mutual phasing guaranteed because of the phase ambiguity of the SYMCKIN signal itself relative to the internal handover process. In this case it will be necessary to use either the punctured clock approach or the synchronized reset approach. The third method, which, while having the disadvantage that it is susceptible to loss of sync from disturbances, is easier to implement than clock puncturing and provides a lot more margin than simple clock phase synchronization. It consists of a synchronized reset generator used in conjunction with clock phase synchronization. This is shown below for rate 7/8. SYMCKIN DCLKIN For rate 3/4 operation it is possible to generate the two clocks with a mutual phase relationship that can exclude the timing violation, as was shown in the first figure. As previously stated, provided the two clocks can be generated as shown in the first example, where only the rising edges of DCLKIN coincide with the edges of SYMCKIN, the timing violation will never occur provided that the delay from the noncoincident rising edges of SYMCKIN to the following falling edge of DCLKIN (shown by the arrows) exceeds 8 nsec. In the example shown this will be true at data rates up to 30 Mbps. Care must be taken to ensure that jitter between the clocks is kept low enough to avoid the timing violation condition. A similar condition exists for rate 2/3 operation, as shown below. SYMCKIN ➀ ➁ ➂ ➃ ➄ ➅ ➆ ➇ ➀ DCLKIN 15 nsec. min. RESET SYMCKIN This ensures that the STEL-2060CC starts up during the optimum phase of the SYMCKIN/DCLKIN repetition cycle, i.e., the phase with the maximum separation between the rising edge of SYMCKIN and the next falling edge of DCLKIN; DCLKIN STEL-2060C Powered by ICminer.com Electronic-Library Service CopyRight 2003 8 separation between the rising edge of SYMCKIN and the following falling edge of DCLKIN the same situation will occur again every four cycles of DCLKIN, which is precisely where the timing sensitivity occurs, as shown in the figure. This method ensures good timing margins for stable operation at all data rates up to 40 Mbps, this limit again being set by the symbol setup and hold time requirements and need to use square waves for the clocks. the decoder will then continue to operate correctly provided that nothing occurs to upset this cycle. This method exploits the fact that not all falling edges of DCLKIN have a timing sensitivity relative to the rising edges of SYMCKIN, as was discussed earlier. For example, in rate 7/8 operation only every fourth falling edge of DCLKIN is critical, starting with the fourth one after the reset is released. By timing the rising edge of the reset at a point in the cycle where there is good ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS Warning: Stresses greater than those shown below may cause permanent damage to the device. Exposure of the device to these conditions for extended periods may also affect device reliability. Symbol Parameter Range Units Tstg Storage Temperature –65 to +150 °C Ta Operating Temperature (Ambient) –40 to +85 °C VDDmax Max. voltage between VDD and VSS +7 to –0.7 volts VI/O(max) Max. voltage on any input or output pin VDD + 0.3 volts VI/O(min) Min. voltage on any input or output pin VSS – 0.3 volts RECOMMENDED OPERATING CONDITIONS Symbol Parameter Range Units VDD Supply Voltage +5 ± 10% volts Ta Operating Temperature (Ambient) 0 to +70 °C D.C. CHARACTERISTICS Symbol (Operating Conditions: VDD = 5.0 ± 5% volts, Ta = 0° to 70° C) Parameter Min. Typ. Max. 1.0 Units Conditions mA Static, no clock mA/Mbps @ 45 Mbps (fDATA) volts Guaranteed Logic '1' volts Guaranteed Logic '0' volts IO = –4.0 mA IDD(Q) Supply Current, Quiescent IDD Supply Current, Operational VIH(min) Min. High Level Input Voltage VIL(max) Max. Low Level Input Voltage VOH(min) Min. High Level Output Voltage VOL(max) Max. Low Level Output Voltage 0.4 volts IO = +4.0 mA IIH(max) Max. High Level Input Current 10 µA VIN = +5.0 volts IIL(max) Max. Low Level Input Current –10 µA VIN = 0 volts 8 2.0 0.8 2.4 9 Powered by ICminer.com Electronic-Library Service CopyRight 2003 STEL-2060C RATE 1/2 AND EXTERNAL DEPUNCTURING TIMING. (a) PARALLEL INPUT MODE (PARL = 1) SYMCKIN tSU tSHPE tHD SYMB. N+1 SYMB. N G1/2 tSLPE SYMB. N+2 PNCG1/G2 tSO ODCLK tOD DATO (b) SEQUENTIAL INPUT MODE (PARL = 0) SYMCKIN tSHS tHD tSU tSLS LDG2 G1/2 G1 G2 G1 G2 G1 PNCG1 PNCG2 tSO ODCLK tOD DATO STEL-2060C Powered by ICminer.com Electronic-Library Service CopyRight 2003 10 G2 G1 G2 A.C. CHARACTERISTICS Symbol fDAT (Operating Conditions: VDD = 5.0 ±5% volts, Ta = 0° to 70° C) Parameter Min. Data speed, Parallel input mode (PARL = 1), Max. 45 Units Conditions Mbps PARL = 1 and all rates when not using Internal Depuncturing fDAT RATE2-0 = 0 Data speed, Sequential input mode (PARL = 0), Rate 1/2 45 Mbps PARL = 0 or RATE2-0 ≠ 0 and all rates and modes when using Internal Depuncturing tSU G1, G2, PNCG1 or PCNG2, LDG2 to SYMCKIN Setup 3 nsecs. PARL = 0 or tHD G1, G2, PNCG1 or PCNG2, LDG2 to SYMCKIN Hold 5 nsecs. RATE2-0 = 0 tSUI G1, G2, PNCG1 or PCNG2, LDG2 to SYMCKIN Setup 6 nsecs. PARL = 1 and tHDI G1, G2, PNCG1 or PCNG2, LDG2 to SYMCKIN Hold 6 nsecs. RATE2-0 ≠ 0 10 nsecs. PARL = 1 and tSHPE, tSLPE SYMCKIN Pulse width (high or low), Parallel input mode, RATE2-0 = 0 all rates when not using Internal Depuncturing tSHPI, tSLPI SYMCKIN Pulse width (high or low), Parallel input mode, 12 nsecs. RATE2-0 ≠ 0 all rates when using Internal Depuncturing tSHS, tSLS PARL = 1 and SYMCKIN Pulse width (high or low), Serial input mode 6 tSO SYMCKIN to ODCLK stable delay (RATE2-0 = 000) 3 8 nsecs. tDO DCLKIN to ODCLK stable delay (RATE2-0 ≠ 000) 3 8 nsecs. Load = 15 pF tOD ODCLK to output stable delay, all other outputs 1 3 nsecs. Load = 15 pF 11 Powered by ICminer.com Electronic-Library Service CopyRight 2003 nsecs. } } } } } } PARL = 0 STEL-2060C PUNCTURED SYMBOL SEQUENCES RATE 1/2 AND EXTERNAL DEPUNCTURING - SEQUENTIAL INPUTS (PARL = 0) 1. Rate Symbol sequence (suffix is symbol number in sequence, all at G12-0 input) 1 /2 G11 G21 G12 G22 G13 G23 2 /3 G11 G21 P2 G22 G13 G23 P4 G24 G15 G25 P6 G26 3 /4 G11 G21 P2 G22 G13 P3 G14 G24 P5 G25 G16 P6 G17 4 /5 G11 G21 P2 G22 P3 G23 P4 G24 G15 G25 P6 P6 5 /6 G11 G21 P2 G22 G13 P3 P4 G24 G15 P5 G16 6 /7 G11 G21 P2 G22 P3 G23 G14 P4 P5 G25 7 /8 G11 G21 P2 G22 P3 G23 P4 G24 G15 P5 SYMCKIN DCLKIN (Not Punctured) 2D 0 2D 0 G27 2D 0 G27 P7 2D 0 G26 P7 G27 2D 0 G16 P6 G17 G27 2D 0 P6 G26 G17 P7 2D 0 2. RATE 1/2 AND EXTERNAL DEPUNCTURING - PARALLEL INPUTS (PARL = 1) Rate Input Symbol sequence (suffix is symbol number in sequence) 1 /2 G12-0 G11 G22-0 G21 G12 G22 G13 G23 G14 G24 G15 G25 G16 G26 2 /3 G12-0 G11 G22-0 G21 P2 G22 G13 G23 P4 G24 G15 G25 P6 G26 G17 G27 P8 G28 G19 G29 3 /4 G12-0 G11 G22-0 G21 P2 G22 G13 P3 G14 G24 P5 G25 G16 P6 G17 G27 P8 G28 4 /5 G12-0 G11 G22-0 G21 P2 G22 P3 G23 P4 G24 G15 G25 P6 G26 P7 G27 5 /6 G12-0 G11 G22-0 G21 P2 G22 G13 P3 P4 G24 G15 P5 G16 G26 6 /7 G12-0 G11 G22-0 G21 P2 G22 P3 G23 G14 P4 P5 G25 7 /8 G12-0 G11 G22-0 G21 P2 G22 P3 G23 P4 G24 G15 P5 3. SYMCKIN DCLKIN (Not Punctured) D 0 P10 G210 D 0 G19 P9 G110 G210 D 0 P8 G28 G19 G29 P10 G210 D 0 P7 G27 G18 P8 P9 G29 G110 P10 D 0 G16 P6 G17 G17 P8 G28 P9 P9 G110 G210 D 0 P6 G26 G17 P7 G18 G28 P9 G29 P10 G210 D 0 INTERNAL DEPUNCTURING - SEQUENTIAL INPUTS (PARL = 0) Rate 1 2 3 7 4. /2 /3 /4 /8 Symbol sequence (suffix is symbol number in sequence, all at G12-0 input) G11 G11 G11 G11 G21 G21 G21 G21 G12 G22 G22 G22 G22 G13 G13 G23 G13 G23 G14 G24 G23 G24 G24 G15 G14 G24 G15 G25 G25 G16 G26 G17 G15 G26 G17 G18 SYMCKIN DCLKIN (Not Punctured) G17 G27 G28 G27 G28 G29 2D 0 G28 3 /2 D D G19 4 /3 D D G210 8 /7 D D INTERNAL DEPUNCTURING - PARALLEL INPUTS (PARL = 1) Rate Input Symbol sequence (suffix is symbol number in sequence) 1 /2 G12-0 G22-0 G11 G21 G12 G22 G13 G23 G14 G24 G15 G25 G16 G26 G17 G27 2 /3 G12-0 G22-0 G11 G21 G22 G13 G23 G24 G15 G25 G26 G17 G27 G28 G19 G29 G210 G111 G211 G212 3 /4 G12-0 G22-0 G11 G21 G22 G13 G14 G24 G25 G16 G17 G27 G28 G19 G110 G210 G211 G112 G113 G213 7 /8 G12-0 G22-0 G11 G21 G22 G23 G24 G15 G26 G17 G18 G28 G29 G210 G211 G112 G113 G214 G115 G215 STEL-2060C Powered by ICminer.com Electronic-Library Service CopyRight 2003 12 SYMCKIN DCLKIN (Not Punctured) D 0 3 /4 D D G214 G115 2 /3 D D G216 G117 4 /7 D D INTERNAL DEPUNCTURING TIMING. (a) RATE 2/3 SHOWN PARALLEL INPUT MODE (PARL = 1) SYMCKIN * t SUI tSHPI t HDI G2 N+1** G1 N G1 tSLPI G2 N+2 G1 N+4 G2 N+3*** G2 N+4 Basic Pattern G2 N G2 G1 N+2 DCLKIN tDO ODCLK tOD DATO ** G1 N+1 Punctured * (b) *** G1 N+3 Punctured Within each symbol period, rising edge of SYMCLKIN must precede falling edge, as shown SEQUENTIAL INPUT MODE (PARL = 0) SYMCKIN tSUI tSHS tHDI tSLS Basic Pattern G1/2 G1 N G2 N G2 N+1 ** G1 N+2 G2 N+2 G2 N+3 *** G1 N+4 G2 N+4 DCLKIN tDO ODCLK tOD DATO ** G1 N+1 Punctured 13 Powered by ICminer.com Electronic-Library Service CopyRight 2003 *** G1 N+3 Punctured STEL-2060C RATE 3/4 SHOWN EXTERNAL DEPUNCTURING TIMING. (a) PARALLEL INPUT MODE (PARL = 1) SYMCKIN tSU G1 tHD * * G2 * * * PNCG1 PNCG2 ODCLK DATO * Indicates Punctured Symbols (b) SEQUENTIAL INPUT MODE (PARL = 0) SYMCKIN tSU tHD LDG2 G1/2 G2 G1 * G2 G1 G2 * G1 G2 G1 * G2 G1 G2 * G1 G2 G1 PNCG1 PNCG2 ODCLK DATO * Indicates Punctured Symbols STEL-2060C Powered by ICminer.com Electronic-Library Service CopyRight 2003 14 * G2 MICROPROCESSOR INTERFACE TIMING 1. WRITE MODE CSEL ADDR2-0 DON'T CARE DATA 7-0 DON'T CARE tSM tHM tWW WRITE 2. READ MODE CSEL ADDR2-0 DON'T CARE DON'T CARE tSM tHM READ tVZ tZV DATA 7-0 A.C. CHARACTERISTICS (Operating Conditions: VDD = 5.0 ±5% volts, Ta = 0° to 70° C) Symbol Parameter Min. Max. Units tSM CSEL, ADDR2-0 or DATA7-0 to WRITE or READ Setup 10 nsecs. tHM CSEL, ADDR2-0 or DATA7-0 to WRITE or READ Hold 5 nsecs. tWW WRITE Pulse width 5 nsecs. tZV READ (low) to DATA7-0 Valid 10 nsecs. tVZ READ (high) to DATA7-0 High-Impedance 10 nsecs. 15 Powered by ICminer.com Electronic-Library Service CopyRight 2003 STEL-2060C NODE SYNCHRONIZATION assumed that the data was modulated using QPSK. The appropriate synchronization sequences will be invoked, as shown in the node sync sequence tables. Note that the pipeline delay through the device will be affected by the node sync state. If multiple devices are used in parallel to achieve higher data rates, it is necessary for the all devices to have the same node sync state to equalize their pipeline delays. It will be necessary to reset the devices together to achieve this state In a communication system using Viterbi decoding the decoder will only operate correctly when the symbols G1 and G2 are loaded into the decoder in the correct order. Identifying which symbol is G1 and which one is G2 is referred to as node synchronization. The STEL-2060C contains a circuit designed to carry out the node synchronization function automatically. It uses the internally generated metrics of the received sequence to do this. These constantly changing parameters are periodically renormalized to keep them within bounds. If renormalization occurs too frequently it is a good indication that the system is not converging, most likely due to lack of node synchronization. The renormalization rate at which the system will decide to change the node sync is determined by the threshold parameter. This is an 8-bit number which is set by the THR7-0 inputs. When the renormalization count exceeds this value, the OOS output will go high and the AUTO output will pulse high for one clock cycle, as shown during Count Window N in the timing diagram below. The counter is reset after a number of bits determined by the number set by the COUNT7-0 inputs, so that the threshold must be exceeded somewhere in that period for resynchronization to take place. OOS will be reset if the counter then counts through an entire window and the threshold is not exceeded, as shown during Count Window N + 1 in the timing diagram below. The most suitable threshold setting will depend on the value of Eb/N0, the coding rate, and the signal level at the G1 and G2 inputs. For full scale inputs, i.e., the peak signal values almost saturate the digital inputs, suitable starting values for the threshold will be 1% for Rate 1/2, 0.5% for Rates 2/3 to 6 /7, and 0.1% for Rate 7/8. e.g., for Rate 1/2, if the number of bits over which the measure is made is set to 512 (COUNT7-0 = 01H) the threshold should be set to 5. Setting THR7-0 = 0 gives a value of 6, which is adequately close. More reliable results will be obtained by counting over a longer period to improve the averaging process, but this increases the time taken to make a decision and hence to acquire node sync. Thus, starting with a low count period and then increasing it (and adjusting the threshold accordingly to maintain a value of 1%) when OOS goes low will result in a faster acquisition of correct node sync with a lower probability of accidental loss of node sync once correct sync has been achieved. To use the internal node sync the AUTO output must be connected to the SYNC input. The synchronization sequence depends on the setting of the PARL input. When PARL is set low it is assumed that the data was modulated using BPSK, and when it is set high it is When internal depuncturing is used, additional node sync states exist because of the uncertainty of the current symbol position in the puncture sequence. In this case the node sync circuit will also search through the sequence by adding delays in the depuncturing process to precess through the sequence. In the sequential input mode (PARL = 0) this is simply an extension of the node sync process, since the alternate state is achieved by delaying the symbols. In the parallel input mode, however, this is different from the "invert G2 and swap" process, and in this sync sequence "invert G2 and swap" precedes the delay addition, so that the system goes through both the initial and alternate states for each delay addition tried. This is shown for the Rate 2 /3 case. In each case the symbols are read into the depuncturing circuit in groups of three (in the BPSK mode) or six (in the QPSK mode) and attempts are made to reinsert the punctured symbol in all of the possible insertion positions. The positions of the punctured symbols in the sequences are shown by the asterisks (*). The resulting groups of four or eight symbols are then decoded in pairs, resulting in two decoded bits in the BPSK mode and four bits in the QPSK mode. For higher rates the sequences will be extensions of this procedure. When external depuncturing is used, the determination of which symbols were punctured, and need to be reinserted into the symbol sequence, is part of the node sync process. This is because the acquisition of correct node sync cannot be completed until the punctured symbols are reinserted correctly. The AUTO and OOS outputs of the STEL-2060C can be used as indicators of the operation of the internal node sync process; OOS will remain high as long as node sync has not been achieved and AUTO will pulse each time a new node sync state is being tried. Since there are only two possible internal node sync states, alternate pulses on the AUTO output can be used as an indication that the depuncturing is incorrect and a new depuncturing sequence should be tried externally. NODE SYNC TIMING Count Window N Count Window N+1 ODCLK AUTO OOS STEL-2060C Powered by ICminer.com Electronic-Library Service CopyRight 2003 16 NODE SYNC SEQUENCES 1. RATE 1/2 PARL 0 Input Initial State 2. RATE 2/3, PARL = 0 (BPSK MODE) Alternate State G1 G1n G2 N.A. N.A. G1 G1n G2n G2 G2n G1n G2n G2n Input Initial State G1n+1 G1 2 G1n G2n* G2n+1 G2n* G2n+1 G1n+2 G2n+1 G1n+2 G2n+2* (No delay) 1 Alternate States 1 (One symbol delay) (Two symbol delay) 3. RATE 2/3, PARL = 1 (QPSK MODE) Input Initial State 1 Alternate States 3 2 4 5 G1 G1n G2n+1 G2n+2* G2n* G1n+2 G2n+3 G2 G2n* G1n+2 G2n+3 G1n G2n+1 G2n+2* G2n+1 G2n+2* G1n+4 G2n* G1n+2 G2n+3 G1n+2 G2n+3 G2n+4 G2n+1 G2n+2*G1n+4 (No Invert/Swap (Invert/Swap No delay) No delay) G2n* G1n+2 G2n+3 G2n+1 G2n+2* G1n+4 *G2n+1 G2n+2*G1n+4 G1n+2 G2n+3 G2n+4* (No Invert/Swap (Invert/Swap (No Invert/Swap One symb. delay) One symb. delay) Two symb. delay) (Invert/Swap Two symb. delay) BER PERFORMANCE 10–1 10–2 R = 1/2 –3 BER 10 R = 2/3 R = 3/4 10–4 R = 7/8 10–5 Uncoded 10–6 10–7 2 3 4 5 6 7 Eb/No 8 The coding gain obtained by the use of Convolutional coding and Viterbi decoding is extremely dependent on many parameters. Not surprisingly, the code rate is a primary factor, but so are the bit error rate (BER) and amplitude of the input signal. The BER affects the coding gain because the error correction capability of the Viterbi decoder is dependent on the statistics of the errors, specifically the clustering of errors. As the BER of the input signal increases, so does the clustering, causing a reduction in the error correcting capability of the device, along with the coding gain. The signal amplitude is important because of the weighting given to the signal amplitude as an indication of the likelihood of an error in a given symbol pair. 10 11 Consequently it is important to maintain the signal amplitude at an optimum level in order to maximize the performance. The performance curves shown above were measured using a digital link simulator with the signal level set at one half of full scale; i.e., the signal amplitude without noise ranged from 101 to 001 in signed magnitude format, or 101 to 010 in offset binary format. The coding gain under these conditions is about 0.2 dB less than that under optimum signal level conditions. The performance of the STEL-2060C is shown here for unpunctured operation (Rate 1/2) as well as punctured operation at the rates for which internal depuncturing is supported (Rates 2/3, 3/4 and 7/8). The error rate for uncoded data is shown for comparison. 17 Powered by ICminer.com Electronic-Library Service CopyRight 2003 9 STEL-2060C APPLICATION INFORMATION The STEL-2060C can be used in a variety of different environments. One example of a system using a convolutional encoder with the STEL-2060C Viterbi decoder is illustrated here. The STEL-2060C cannot be used as a common decoder in multi-channel applications because of the memory incorporated on the chip which is dedicated to a single channel. The system modulates a data stream of rate 45 Mbps using binary PSK (BPSK) or quaternary PSK (QPSK). To be able to use convolutional coding, the system must either have available the additional bandwidth needed to transmit symbols at a higher rate or must be able to make use of higher levels of modulation. e.g., by changing from BPSK to QPSK modulation, the data can be encoded at Rate 1/2 without requiring any additional bandwidth. The performance improvement that can be expected is shown in the graph below. The STEL-2060C is designed to accept symbols synchronously. SYMCKIN is supplied by the user to clock in the symbols. The maximum data rate is 45 Mbps, using a SYMCKIN frequency of 45 MHz (when PARL is set high) or 90 MHz (when PARL is set low) at rate 1/2, corresponding to 90 MSymbols per sec. 10–1 6 3 2 10–2 I Tx DATA 45 Mbps RATE 1/2 CONV. ENCODER 6 QPSK MODULATOR Q 3 2 CHANNEL BW=90 MHz CODED DATA @ 90 Mbps 45 Mbps RATE 1/2 VITERBI DECODER Q 6 BER 3 2 Coded Uncoded 10–4 6 3 2 I Rx DATA 10–3 Coding Gain 10–5 QPSK DEMOD. 6 3 2 10–6 6 CODED DATA @ 90 Mbps 3 2 10–7 2 3 4 5 6 7 8 Eb/N 0 dB QPSK Communication System Using Convolutional Encoding and Viterbi Decoding. Rate = 1/2 STEL-2060C Powered by ICminer.com Electronic-Library Service CopyRight 2003 18 9 10 11 12 Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intels Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel® products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. For Further Information Call or Write INTEL CORPORATION Cable Network Operation 350 E. Plumeria Drive, San Jose, CA 95134 Customer Service Telephone: (408) 545-9700 Technical Support Telephone: (408) 545-9799 FAX: (408) 545-9888 Copyright © Intel Corporation, December 15, 1999. All rights reserved Powered by ICminer.com Electronic-Library Service CopyRight 2003