STEL-2040A Data Sheet STEL-2040A Convolutional Encoder Viterbi Decoder R Powered by ICminer.com Electronic-Library Service CopyRight 2003 FEATURES ■ Constraint Length 7 ■ Coding Gain of 5.2 dB (@ 10-5 BER, Rate 1/2) ■ Rates 1/3 , 1/2 , 2/3* and 3/4* (*Punctured) ■ Industry Standard Polynomials ■ Built in BER Monitor G1=1718, G2=1338, G3=1458, ■ Microprocessor Interface ■ Programmable Scrambler: V.35 (CCITT or IESS) ■ Low Power Consumption ■ Differential Encoder and Decoder ■ 68-pin PLCC and CLDCC Packages ■ Three Bit Soft Decision Inputs in Signed ■ Commercial and Military Temperature Magnitude or 2's Complement Formats Ranges Available ■ Up to 256 Kbps Data Rate (0° to 70° C) BLOCK DIAGRAM OSYMB DATACLK CONVOLUTIONAL ENCODER DIFFERENTIAL ENCODER AND V.35 SCRAMBLERS DATAIN ERATE ENLATCH 2 2 READ, WRITE ADDR 3:1 MUX Q LATCH ENCODER SECTION 2 SEL A, B MODE D SELECT MICROPROCESSOR INTERFACE, MODE SELECT AND CONTROL 4 8 DATA µPDIS RESET SCRAM1-0 OCLK ICLK (TO ALL REGS.) 2 DECODER SECTION ADDRESS SEQUENCER AND CONTROL LOGIC DRDY ACK STATE-METRIC RAM G2D2-0 G3D2-0 ADDR DO DI 3 3 3 BERR G1ERR DRATE SYNC0 SYNC1 G1D2-0 TRELLIS RAM BER G2ERR MONITOR G3ERR DATA DESCRAMBLER, BUFFER REG. & MUX. B RANCH METRIC AND ADD-COMPARESELECT LOGIC PATH HISTORY AND AUTO NODE-SYNC LOGIC DIFFERENTIAL DECODER AND V.35 DESCRAMBLERS DOUT PNCG1 SYNC PNCG2 SM2C SST0 MIS THRESH SST1 3 STEL-2040A Powered by ICminer.com Electronic-Library Service CopyRight 2003 2 FUNCTIONAL DESCRIPTION Convolutional Encoding and Viterbi Decoding are used to provide forward error correction (FEC) which improves digital communication performance over a noisy link. In satellite communication systems where transmitter power is limited, FEC techniques can reduce the required transmission power. The STEL2040A is a specialized product designed to perform this specific communications related function. rate resulting from a noisy link. The coding overhead can be reduced at the expense of the coding gain by puncturing (deleting) some of the symbols. The STEL-2040A is designed to operate in this way at Rate 3 /4. In this case 4 symbols are transmitted for every 3 bits encoded. The resulting bandwidth overhead is just 33% in this case, compared with 100% at Rate 1/2. The STEL-2040A incorporates all the memories required to perform these functions. In addition, the STEL-2040A incorporates a differential encoder and decoder, two scrambling algorithms, a BER monitor and a microprocessor interface. The STEL-2040A is available in a 68-pin PLCC (plastic leaded chip carrier) and also in a ceramic leaded chip carrier (J-bend leads). The encoder creates a stream of symbols which are transmitted at 2 (Rate 1/2) or 3 (Rate 1/3) times the information rate. This encoding introduces a high degree of redundancy which enables accurate decoding of information despite a high symbol error PIN CONFIGURATION Package: 68 pin CLDCC Thermal coefficient, θja = 34°C/W Package: 68 pin PLCC Thermal coefficient, θja = 36°C/W 6 6 6 6 6 6 6 6 9 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 TOP VIEW 0.145" max. 6 6 6 6 6 6 6 6 9 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 0.017" ± 0.004" ** **At seating plane 0.990" ±0.005" 0.05" * *Tolerance not cumulative 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 2 2 2 3 3 3 3 3 3 3 3 3 3 4 4 4 4 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 60 59 58 57 56 55 54 53 0.990" 52 51 ± 0.010" 50 49 48 47 46 45 44 2 2 2 3 3 3 3 3 3 3 3 3 3 4 4 4 4 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 0.200" max. 0.954" ± 0.004" 0.035" nomina 0.951" ± 0.009" Notes: (1) Tolerances on pin spacing are not cumulative. (2) Dimensions apply at seating plane. (3) PLCC and CLDCC packages have different corners and may not fit into sockets designed for the other type. Universal sockets are available without alignment locators. PIN CONNECTIONS 1 2 3 4 5 6 7 8 9 10 11 12 SYNC VSS ACK DATACLK DRDY DATAIN MODE SEL A SEL B G3D2 G3D1 G3D0 13 14 15 16 17 18 19 20 21 22 23 24 PNCG2 G2D2 G2D1 G2D0 PNCG1 G1D2 G1D1 G1D0 DIFEN BERR VSS G1ERR 25 26 27 28 29 30 31 32 33 34 35 36 G2ERR G3ERR ADDR3 ADDR2 ADDR1 ADDR0 VSS VSS WRITE READ VDD DATA7 37 38 39 40 41 42 43 44 45 46 47 48 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 VSS I.C. DRATE THRESH0 THRESH1 49 50 51 52 53 54 55 56 57 58 59 60 THRESH2 MIS VSS RESET VDD SM2C µPDIS DOUT SST0 SYNC0 SST1 SYNC1 61 62 63 64 65 66 67 68 ERATE ENLATCH OSYMB VDD ICLK OCLK SCRAM1 SCRAM0 Notes: 1. I.C. denotes Internal Connection. These pins must be left unconnected. Do not use for vias. 2. Connect all unused inputs except READ to VSS, leave unused outputs unconnected. If the READ input is not used it should be connected to VDD. 3 Powered by ICminer.com Electronic-Library Service CopyRight 2003 STEL-2040A FUNCTION BLOCK DESCRIPTION ENCODER The convolutional coder is functionally independent of the decoder. A single data bit is clocked into the 7-bit shift register on the rising edge of DATA CLK. There are two modes of operation, controlled by the MODE input. When MODE is low the timing of the SEL␣ A, SEL␣ B and ENLATCH signals determine whether 2 or 3 symbol bits are generated for every data bit. When MODE is high the symbols are automatically generated sequentially every clock cycle. In this case, the state of ERATE determines whether the device generates symbols for Rate 1/2 or Rate 1/3 operation. The symbols G1, G2, and G3 are generated from the modulo-2 sum (exclusive-OR) of the inputs to the 3 generators from the taps on the shift register. The 3 polynomials are 1718 (G1), 1338 (G2), and 1458 (G3). Example inputs are shown in the timing diagram for both rate 1/2 and rate 1/3 operation. then the internal auto node sync circuit can be used to do this. This is accomplished by connecting the node sync outputs (SST0 and SST1) to the node sync inputs (SYNC0 and SYNC1). The threshold for determining the out of sync condition is user selectable by means of the THRESH2-0 inputs. Alternatively, the SYNC0 and SYNC1 pins can be used with an external algorithm to achieve the same result. Further information on the theory of operation of Viterbi decoders may be obtained from text books such as "Error-Correcting Codes", by Peterson and Weldon (MIT Press), or "Error Control Coding", by Lin and Costello (Prentice-Hall). An alternative source of information is the many papers on this subject that have appeared in the IEEE transactions, such as "Convolutional Codes and their Performance in Communication Systems", by Dr. A. J. Viterbi, IEEE Trans. on Communications Technology, October 1971. DECODER The STEL-2040A is designed to accept symbols either synchronously or in a handshake mode. Symbols are latched into the decoder input registers on the falling edge of the DRDY input. ACK is returned by the decoder to indicate that the symbols have been accepted. INPUT SIGNALS RESET Asynchronous master Reset. A logic low on this pin will clear all registers on the STEL-2040A in both the encoder and decoder sections of the chip. RESET should remain low for at least 3 cycles of ICLK. The RATE input determines whether the decoder will operate in Rate 1/2 or Rate 1/3 mode. When operating at Rate 1/2 the G3 symbol is ignored by the decoder. DATACLK This is the encoder Shift Register Clock. A rising edge on this clock latches DATAIN into the encoder shift register. This signal should nominally be a square wave with a maximum frequency of 256 KHz. For hard decision binary symbols the G1, G2, G3 symbol bits should be connected to pins G1D2, G2D2 and G3D2 respectively, and the other symbol input pins should be tied high (VDD). Three-bit soft decision symbols may be input in Signed Magnitude or Inverted Two’s Complement code, according to the setting of the code control pin, SM2C. The code should be set to Signed Magnitude when using hard decision data. DATAIN This is the encoder input. The data present at this pin is latched into the encoder shift register on the rising edge of DATACLK. This signal should be stable at the rising edge of DATACLK. A single decoded data bit is output for every set of input symbols. The data bit corresponding to a particular symbol set will be output after a delay of 71 symbols. Therefore, when using the STEL-2040A to decode blocks of data 71 additional dummy symbols and 71 DRDY signals need to be added to the data stream to flush the last 71 decoded data bits out of the decoder. MODE The state of the MODE input determines the method of symbol sequencing in the encoder. When MODE is set low the sequencing is generated externally under the control of the SEL A and SEL B inputs, and when MODE is set high it is generated automatically. Node synchronization (correctly grouping incoming symbols into G1, G2, and G3 sets) is inherent with many communication techniques such as TDMA and spread spectrum systems. If node synchronization is not an inherent property of the communications link STEL-2040A Powered by ICminer.com Electronic-Library Service CopyRight 2003 SEL A, SEL B When MODE is set low SEL A and SEL B select the encoded symbol, G1, G2 or G3, which will appear on the OSYMB pin on the next rising edge of ENLATCH according to the table: 4 SEL A SEL B SYMBOL POLYNOMIAL 0 1 G1 1718 (11110012) 1 0 G2 1338 (10110112) 0 0 G3 1458 (11001012) and the frequency of the ENLATCH signal should be 2 or 3 times the frequency of the DATACLK, depending on the rate selected. ICLK, OCLK System Clock. A crystal may be connected between ICLK and OCLK or a CMOS level clock may be fed into ICLK only. The clock frequency should be at least 70 times the data rate but no more than 18 MHz. When MODE is set high the symbol sequence is generated automatically and the SEL A and SEL B inputs are inactive. DRATE The Decoder Rate input selects whether the decoder will read two symbols (DRATE set high) or three symbols (DRATE set low)) for every data bit decoded. During Rate 1/2 operation the symbol G3 on inputs G3D2-0 is completely ignored by the decoder. DRATE should be set high for Rate 3/4 operation. ERATE When MODE is high the Encoder Rate input determines whether symbols for Rate 1/2 (ERATE=1) or Rate 1/3 (ERATE=0) operation are generated. When MODE is low this input is inactive. DIFEN When the DIFEN input is set high the differential encoder and decoder in the STEL-2040A are enabled. Differential encoding is done after V.35 scrambling (when used) but before Invert G2 scrambling (when used) in the encoder. The sequence is reversed in the decoder. Note that the BER monitor function will only operate correctly when DIFEN is set low. G1D2-0, G2D2-0, G3D2-0 The three 3-bit soft decision symbols are connected to these inputs and loaded into the input registers on the falling edge of DRDY. The order in which the symbols are entered into the decoder from the registers depends on the state of the SYNC0 and SYNC1 inputs. The decoder can make use of soft decision information, which includes both polarity information and a confidence measure, to improve the decoder performance. If hard decision (single bit) symbols are used the signals are connected to pins G1D2, G2D2 and G3D2 and the other inputs are connected to VDD. See SM2C for a description of the input data codes. SCRAM0, SCRAM1 The Scramble inputs are used to enable the two scrambler functions included in the STEL-2040A, as shown in the table below: SCRAM0 SCRAM1 FUNCTION 0 0 Scrambler disabled 0 1 V.35 (CCITT compatible) 1 1 V.35 (IESS compatible) SM2C The state of the Signed Magnitude/2's Complement input determines the format of the incoming softdecision symbols into the decoder. When SM2C is high the input code is Signed Magnitude, and when it is low the code is Two's Complement. The codes are shown in the following table: Two different "V.35" scrambler formats are provided since there are two versions of this standard in exixtence: the true CCITT version of the standard, and the IESS version, which has become a de facto standard through widespread use. In each case, the scrambling function is provided at the encoder and the descrambler is provided at the decoder. CODE CONTROL: ENLATCH This is the encoder Output Latch Enable. The new symbol is clocked into the output latch and appears on the OSYMB pin on the rising edge of ENLATCH. When MODE is low the symbol selected will depend on the states of the SEL A and SEL B lines, which should be stable on the rising edge of ENLATCH. When MODE is high the symbol selection is internal, SM2C=0 SYMBOL INPUT: GXD2-GXD0 GXD2-GXD0 Most Confident '+' level 0 1 1 0 1 1 Data = 0 0 1 0 0 1 0 0 0 1 0 0 1 Least Confident '+' level 0 0 0 0 0 0 Least Confident '–' level 1 0 0 1 1 1 Data = 1 1 0 1 1 1 0 1 1 0 1 0 1 1 1 1 1 0 0 Most Confident '–' level SM2C should be set high when using hard decision data. 5 Powered by ICminer.com Electronic-Library Service CopyRight 2003 SM2C=1 STEL-2040A DRDY The Data Ready signal is used to load symbols into the decoder. A new set of symbols is latched into the input registers on each falling edge of the DRDY input. Since the actual error rate obtained will depend on the signal to noise ratio (Eb/N0) in the signal, the optimum value of the threshold will also depend on Eb/N0 and should be set accordingly. The actual mismatch or renomalization count is stored in and can be read from the register at address EH. SYNC0, SYNC1 The Symbol Sync0 and Symbol Sync1 inputs are used for auto node sync operation. When using the internal auto node sync mode these two pins are connected to SST0 and SST1, respectively. The operation of the decoder is affected as shownin the following table: MIS Two algorithms for auto node-sync are incorporated into the STEL-2040A. When MIS is set high the Traceback Mismatch algorithm is selected, and when it is set low the Metric Renormalization algorithm is selected. Symbol entered into decoder during symbol period N DRATE SYNC0 SYNC1 G1 G2 G3 1 0 0 G1N G2N – 1 1 0 G2N-1 G1N – 1 0 1 G2N G1N – 1 1 1 Invalid state 0 0 0 G1N G2N G3N 0 1 0 G3N-1 G1N G2N 0 0 1 G2N-1 G3N-1 G1N 0 1 1 Invalid state PNCG1, PNCG2 The PNCG1 and PNCG2 signals are used to control the STEL-2040A when operating in punctured mode. In normal (Rate=1/2) operation these pins should be set low. In punctured mode the PNCG1 signal must be set high to indicate that the G1 symbol is punctured and the PNCG2 signal must be set high to indicate that the G2 symbol is punctured. A symbol will be punctured when the PNCG1 or PNCG2 signals are high during the falling edge of DRDY. Zero value metrics will be substituted internally for the actual metrics corresponding to the signals present on the G12-0 or G22-0 pins at that time. Note that whenever the states of the SYNC0 and SYNC1 inputs are changed there will be a delay of 71 bit periods before valid data starts appearing at DOUT. OUTPUT SIGNALS OSYMB Output Symbol from the Encoder. This output depends on the seven most recent data bits (DATAIN) clocked into the encoder shift register and on the select lines SEL A and SEL B. The individual symbols are formed by the modulo-2 sum of the inputs to the generators from the 7-bit shift register. THRESH 2-0 A counter is used to determine the number of either traceback mismatches or metric renormalizations per 256 bits in the auto node-sync circuit, and the threshold at which the counter triggers the SST0 and SST1 outputs to change states is set with the data on the THRESH2-0 inputs. The threshold values will be as shown in the following table. THRESH2-0 ACK A low level pulse on the Acknowledge pin indicates that the decoder has input the current set of two or three symbols. The signal will pulse low between 68 and 69 clock cycles after the falling edge of DRDY. Threshold value 0 1 1 2 2 4 3 8 4 16 5 32 6 64 7 128 STEL-2040A Powered by ICminer.com Electronic-Library Service CopyRight 2003 DOUT Decoded Data Out. The signal is latched into the output register on the falling edge of DRDY. There is a delay of 71 data bits from the time a set of symbols is input to the time the corresponding data bit is output. Consequently, in order to flush the last 71 bits of data out of the system at the end of a burst it is necessary to continue pulsing the DRDY line for 71 symbol periods after the last valid symbol has been entered. 6 MICROPROCESSOR INTERFACE µ PDIS The microprocessor interface is selected by setting the µPDisable input low. All I/O and control functions are then accessed via the DATA7-0 bus with the associated control signals. The STEL-2040A is then used as a memory or I/O mapped peripheral to the host processor. The RESET input must be set high, but all other inputs will be ignored and the outputs will be invalid. When this input is set high the microprocessor interface is disabled and all I/O and control functions are accessed via the corresponding pins. SST0, SST1 The Sync State 0 and Sync State 1 signals are the outputs of the internal auto node sync circuit. They should be connected to SYNC0 and SYNC1 respectively to use the internal auto node sync capability. They may also be used in conjunction with an external node sync algorithm implementation which can use the SST0 and SST1 outputs. SYNC The Sync output provides an indication of the status of the internal auto node sync circuit. When it is high it indicates that node sync has been lost, and when it is low it indicates that the system is assumed to be in sync, as determined by the error rate estimate. DATA7-0 When using the STEL-2040A in the microprocessor interface mode (µPDIS=0) all data I/O and control is done via this bus. G1ERR, G2ERR and G3ERR The G1 Error, G2 Error and G3 Error outputs indicates that an error has been detected in the G1, G2 or G3 symbols, respectively, corresponding to the current output bit. These outputs will only be valid when operating at Rates 1/2 and 1/3 with DIFEN = 0. ADDR3-0 The 4-bit address bus is used to access the various I/O functions in the microprocessor interface mode, as shown in the table below. WRITE The Write input is used to write data to the microprocessor data bus. Data will be latched into the STEL-2040A on the rising edge of this signal. BERR The Bit Error output indicates that an error has been detected in any of the symbols corresponding to the current output bit. This function is the logical OR of G1ERR, G2ERR, and (at Rate 1/3) G3ERR. This output will only be valid when operating at Rates 1/2 and 1/3 with DIFEN = 0. READ The Read input is used to read data from the microprocessor data bus; the DATA7-0 bus will be active in the output mode whenever this input is low. MICROPROCESSOR INTERFACE MEMORY MAP ADDR3-0 0 1 2 3 4 5 6 7 8 9 A B C D E DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 PNCG1 G1D2 G1D1 G1D0 PNCG2 DRATE SM2C SCRAM1 SCRAM0 MIS G2D2 G2D1 G3D2 G3D1 THRESH2 THRESH1 SYNC1 DIFEN MODE SEL A SEL B BERR* RNORM* G3ERR* MSMCH* G2ERR* SST1* G1ERR* SST0* DATA0 G2D0 G3D0 THRESH0 SYNC0 DATAIN ERATE RESET DRDY DATACLK ENLATCH DOUT* SYNC* OSYMB* COUNT7* COUNT6* COUNT5* COUNT4* COUNT3* COUNT2* COUNT1* COUNT0* * Indicates a read only function. 7 Powered by ICminer.com Electronic-Library Service CopyRight 2003 STEL-2040A ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS Warning: Stresses greater than those shown below may cause permanent damage to the device. Exposure of the device to these conditions for extended periods may also affect device reliability. All voltages are referenced to Vss. Symbol Parameter Range Units Tstg Storage Temperature –40 to +125 –65 to +150 °C (Plastic package) °C (Ceramic package) VDDmax Supply voltage on VDD –0.3 to + 7 volts VI(max) Input voltage –0.3 to VDD+0.3 volts Ii DC input current ± 10 mA RECOMMENDED OPERATING CONDITIONS Symbol VDD Ta Parameter Supply Voltage Operating Temperature (Ambient) Range Units +5 ± 5% +5 ± 10% Volts (Commercial grade) Volts (Military grade) 0 to +70 –55 to +125 °C (Commercial grade) °C (Military grade) D.C. CHARACTERISTICS (Operating Conditions: VDD= 5.0 V ±5%, VSS=0 V, Ta= 0° to 70° C, Commercial VDD= 5.0 V ±10%, VSS=0 V, Ta=–55° to 125° C, Military) Symbol Parameter Min. Typ. Max. Units IDD(Q) Supply Current, Quiescent 1.0 IDD Supply Current, Operational 2.0 VIH(min) High Level Input Voltage mA Conditions Static, no clock mA/MHz Standard Operating Conditions 2.0 volts Logic '1' Extended Operating Conditions 2.25 volts Logic '1' 0.8 volts Logic '0' VIL(max) Low Level Input Voltage IIH(min) High Level Input Current 10 35 110 µA DRDY, VIN = VDD IIL(max) Low Level Input Current –130 –45 –15 µA All other inputs, VIN = VSS VOH(min) High Level Output Voltage 2.4 4.5 VOL(max) Low Level Output Voltage IOS Output Short Circuit Current volts IO = –6.0 mA IO = +6.0 mA 0.2 0.4 volts 20 65 130 mA VOUT = VDD, VDD = max –10 –45 –130 mA VOUT = VSS, VDD = max CIN Input Capacitance 2 pF All inputs COUT Output Capacitance 4 pF All outputs STEL-2040A Powered by ICminer.com Electronic-Library Service CopyRight 2003 8 ENCODER TIMING. MODE=1 tDS DATAIN BIT 1 X BIT 2 tDH BIT3 X BIT4 X X DATACLK tDE RATE 1/2 OPERATION ENLATCH tEOD OSYMB G1 G2 FROM BIT 1 RATE 1 G1 G2 FROM BIT 2 G1 G2 G1 FROM BIT 3 G2 FROM BIT 4 /3 OPERATION ENLATCH OSYMB G1 G2 G3 FROM BIT 1 G1 G2 G3 FROM BIT 2 G1 G2 G3 G1 FROM BIT 3 G2 G3 FROM BIT 4 ENCODER ELECTRICAL CHARACTERISTICS A.C. CHARACTERISTICS (Operating Conditions: VDD= 5.0 V ±5%, VSS=0 V, Ta= 0° to 70° C, Commercial VDD= 5.0 V ±10%, VSS=0 V, Ta=–55° to 125° C, Military) Commercial Symbol Parameter Min. tSR RESET pulse width 3*tCLK tSR RESET to ICLK setup tDS Max. Military Min. Max. 3*tCLK Units nsec. 2 3 nsec. DATAIN to DATACLK setup 10 12 nsec. tDH DATAIN to DATACLK hold 10 12 nsec. tSS SEL A or SEL B to ENLATCH setup 10 12 nsec. tSH SEL A or SEL B to ENLATCH hold 5 8 nsec. tDE DATACLK to ENLATCH delay 10 12 nsec. tEOD ENLATCH to OSYMB stable delay 10 12 nsec. Notes: tCLK = Period of ICLK =(1/ fCLK). tSR is only relevant if operation is to commence during the first clock cycle after RESET goes high. 9 Powered by ICminer.com Electronic-Library Service CopyRight 2003 STEL-2040A ENCODER TIMING. RATE 1 MODE=0 (STEL-5268 EMULATION MODE) /2 OPERATION DATAIN BIT 1 X tDS BIT 2 X tDH BIT3 X BIT4 X DATACLK SEL A tSH SEL B tDE tSS ENLATCH tEOD G1 OSYMB G2 FROM BIT 1 RATE 1 G1 G2 FROM BIT 2 G1 G2 FROM BIT 3 G1 G2 FROM BIT 4 /3 OPERATION DATAIN BIT 1 X BIT 2 X BIT3 X BIT4 X DATACLK SEL A SEL B ENLATCH OSYMB G1 G2 G3 FROM BIT 1 G1 G2 G3 FROM BIT 2 G1 G2 G3 FROM BIT 3 RESET TIMING RESET tRS ICLK STEL-2040A Powered by ICminer.com Electronic-Library Service CopyRight 2003 10 tSR G1 G2 G3 FROM BIT 4 DECODER TIMING ENCODED SYMB 0 SYMBOLS G1D0-G3D2 tSS SYMB 1 SYMB 2 SYMB 3 SYMB 71 SYMB 72 tHD tSP DRDY tAD ACK tDA BIT -70 DOUT BIT -69 BIT -68 BIT -1 BIT 0 BIT 1 DRDY tWA ACK tDI tIA tCLK ICLK tDO DOUT DECODER ELECTRICAL CHARACTERISTICS A.C. CHARACTERISTICS (Operating Conditions: VDD= 5.0 V ±5%, VSS=0 V, Ta= 0° to 70° C, Commercial VDD= 5.0 V ±10%, VSS=0 V, Ta=–55° to 125° C, Military) Commercial Symbol Parameter Min. Max. 70*fDRDY 18 Military Min. Units 14 MHz fCLK ICLK Frequency tSS SYMBOL to DRDY setup 20 25 nsec. tHD SYMBOL to DRDY hold 5 8 nsec. tSP SYMBOL Period 3.9 5 µsec. tDA DRDY to ACK 35 + 68*tCLK tAD ACK to DRDY 2*tCLK 2*tCLK tWA ACK pulse width tCLK tCLK tDI DRDY to ICLK setup tIA ICLK to ACK 10 31 nsec. tDO ICLK to DOUT 10 35 nsec. tSR RESET to ICLK setup 30 + 69*tCLK 5 70*fDRDY Max. 35 + 68*tCLK nsec. nsec. nsec. 8 2 30 + 69*tCLK 3 nsec. nsec. Notes: fDRDY = Frequency of DRDY, tCLK = Period of ICLK =(1/ fCLK). tSR is only relevant if operation is to commence during the first clock cycle after RESET goes high. 11 Powered by ICminer.com Electronic-Library Service CopyRight 2003 STEL-2040A MICROPROCESSOR INTERFACE TIMING 1. WRITE OPERATIONS µPDIS ADDR 3-0 DON'T CARE DON'T CARE tAW WRITE tHD DATA 7-0 2. tW DON'T CARE DON'T CARE READ OPERATIONS µPDIS ADDR 3-0 DON'T CARE DON'T CARE tAW READ tHD tZV tVZ DATA7-0 MICROPROCESSOR INTERFACE ELECTRICAL CHARACTERISTICS A.C. CHARACTERISTICS (Operating Conditions: VDD= 5.0 V ±5%, VSS=0 V, Ta= 0° to 70° C, Commercial VDD= 5.0 V ±10%, VSS=0 V, Ta=–55° to 125° C, Military) Commercial Symbol Parameter Min. Max. Military Min. Max. Units tW WRITE pulse width 5 8 nsec. tAW ADDR to WRITE or READ setup 5 8 nsec. tWA WRITEor READ to ADDR hold 5 8 nsec. tZV DATA Hi-Z to valid 20 27 nsec. tSR DATA valid to Hi-Z 20 27 nsec. STEL-2040A Powered by ICminer.com Electronic-Library Service CopyRight 2003 12 PUNCTURED MODE OPERATION In punctured codes some of the symbols generated by the convolutional encoder are deleted, or punctured, from the transmitted sequence. For example, in an unpunctured Rate 1/2 sequence, four bits would be transmitted for every two data bits. If every fourth bit was punctured from the sequence then only three bits would be transmitted for every two data bits. This would result in a Rate 2/3 code. The STEL-2040A is designed to operate in punctured mode as well as normal, Rate 1/2, mode. This is easily accomplished by means of the PNCG1 and PNCG2 signals, which delete the symbol which would normally have been loaded into the device at the time when either of these signals is set high. The punctured symbols are replaced by zero metric values. Zero weight is given to Rate these values in the computations relative to the other symbols. The coding gain is significantly less than that for unpunctured operation, but this is the trade-off for the reduced bandwidth required to transmit the symbols. The recommended puncturing sequences for Rates 2/3 and 3/4 punctured operation are shown in the table. The sequences shown in boldface are the basic sequence, which are then repeated. The use of the PNCG1 and PNCG2 signals is shown below for Rate 3 /4. The punctured symbols are marked with asterisks. Rates higher than 3/4 are not recommended with the STEL-2040A. Note that the BER monitor will indicate an error each time a symbol is punctured, and consequently the BER monitor is not valid when operating in punctured mode. Symbol sequence 2 G1 G2 G1 P G1 G2 G1 P G1 G2 G1 P G1 G2 G1 P G1 G2 3 G1 G2 P G2 G1 P G1 G2 P G2 G1 P G1 G2 P G2 G1 P /3 /4 * Denotes punctured symbols G1 * G2 * * * * DRDY PNCG1 PNCG2 USING AUTOMATIC NODE SYNC SYMBOL INPUTS The automatic node sync circuit built into the STEL2040A can be used to provide node sync in applications where this is not intrinsic to the nature of the operation. The automatic node sync is enabled by connecting the SST1 and SST0 outputs to the SYNC1 and SYNC0 inputs, as shown below. The threshold should be set according to the expected signal to noise ratio of the input signal for optimum operation of the system. DOUT G3 SYNC STEL-2040A DATA OUT IN/OUT OF SYNC SYNC0 SYNC1 SST0 SST1 13 Powered by ICminer.com Electronic-Library Service CopyRight 2003 G1 G2 STEL-2040A BPSK COMMUNICATION SYSTEM USING CONVOLUTIONAL ENCODING AND VITERBI DECODING. RATE = 1/2 The STEL-2040A can be used in a variety of different environments. One example is shown below. It cannot be used as a common encoder or decoder in multichannel applications because of the memory incorporated on the chip which is dedicated to a single channel. the data rate. The performance improvement that can be expected is shown in the graph below. The convolutional encoder is functionally independent from the decoder. A single data bit is clocked into the 7 bit shift register on the rising edge of DATA CLK. The decoder portion of the STEL-2040A is designed to accept symbols synchronously. DRDY is supplied by the user to clock in the symbols. The maximum data rate is 256 Kbps, using a clock frequency of 18 MHz. This corresponds to 512 K symbols per second at rate 1/2 and 768 K symbols per second at rate 1/3. 18 MHz crystals are readily available, and this clock frequency can be used at all data rates, although the power consumption can be reduced by using lower clock frequencies. An example of a system using the convolutional coder and Viterbi decoder is illustrated here. The system modulates a data stream of rate 512 Kbps using binary PSK (BPSK). To be able to use convolutional coding/ decoding, the system must have available the additional bandwidth needed to transmit symbols at twice the data rate (for rate 1 / 2 encoding). Alternatively, the system could make use of two parallel channels to transmit two streams of symbols at 10–1 10–2 Tx DATA 256 Kbps RATE 1/2 CONV. ENCODER BPSK MODULATOR CHANNEL BW=1024 KHz CODED DATA @ 512 Kbps Rx DATA 256 Kbps RATE 1/ 2 VITERBI DECODER Uncoded 10–3 BER 10–4 Coded Coding Gain 10–5 BPSK DEMOD. 10–6 CODED DATA @ 512 Kbps 10–7 2 3 BPSK Communication System using Convolutional Encoding and Viterbi Decoding. Rate = 1/2 STEL-2040A Powered by ICminer.com Electronic-Library Service CopyRight 2003 14 4 5 6 7 8 9 Eb/N0 dB 10 11 Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intels Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel® products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. 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