ETC STEL-2070A/CC

STEL-2070A
Data Sheet
STEL-2070A
Dual Constraint
Length (K=7,9)
Convolutional Encoder
Viterbi Decoder
R
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FEATURES
■ Dual Constraint Length: 7 or 9
■ Coding Gain: 5.2 dB (@ 10-5 BER, K = 7)
■ Rate 1/2
6.0 dB (@ 10-5 BER, K = 9)
■ Three Bit Soft Decision Inputs in Signed
■ Auto node sync for BPSK, QPSK and
Magnitude or 2's Complement Formats
OQPSK input signals
■ Maximum data rates:
■ Built in BER Monitor with Error Counter
■ Programmable Scrambler/Descrambler:
86 Kbps (K = 9, –55° to 125° C)
V.35 (CCITT or IESS) or "Invert G2"
96 Kbps (K = 9, 0° to 70° C)
330 Kbps (K = 7, –55° to 125° C)
■ Differential Encoder and Decoder
360 Kbps (K = 7, 0° to 70° C)
■ Microprocessor Interface
■ Industry Standard Polynomials
■ Low Power Consumption
G1 = 1718, G2 = 1338 (K = 7)
■ 68-pin PLCC and CLDCC Packages
G1 = 7538, G2 = 5618 (K = 9)
■ Commercial and Military Temperature
■ 0.5 Micron CMOS Technology
Ranges Available
BLOCK DIAGRAM
DATAIN
V.35
SCRAMBLER
DIFFERENTIAL
ENCODER
EG1
K=7, 9 CONVOLUTIONAL
ENCODER
EG2
DATACLK
(TO ALL REGISTERS)
RESET
INT
V.35
DIFEN
EKSEL
INV G2
3
READ, WRSTB, CSEL
ADDR
DATA
4
BERCT 15-0
MICROPROCESSOR
INTERFACE,
MODE SELECT
AND CONTROL
8
BPER 23-0
BER
COUNTER
V.35
DIFEN
ADDRESS
SEQUENCER
AND
CONTROL LOGIC
OCLK
ICLK
IDVAL
STATE-METRIC
RAM
TRELLIS
RAM
ADDR
DELAY
SYNC0
SYNC1
DRDY
G1D 2-0
G2D 2-0
ERROR
MONITOR
DKSEL
INV G2
DO DI
V.35
DESCRAMBLER
DOUT
ODCLK
DATA
3
3
SYMBOL
ALIGNMENT
CIRCUIT
BRANCH METRIC
AND
ADD-COMPARESELECT LOGIC
DKSEL
MIS
THRESH
STEL-2070A
PATH HISTORY AND
AUTO NODE-SYNC
LOGIC
DIFFERENTIAL
DECODER
SYNC
SST0
3
SST1
2
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PRODUCT INFORMATION
FUNCTIONAL DESCRIPTION
Convolutional Encoding and Viterbi Decoding are
used to provide forward error correction (FEC) which
improves digital communication performance over a
noisy link. In satellite communication systems where
transmitter power is limited, FEC techniques can
reduce the required transmission power. The STEL2070A is a specialized product designed to perform
this specific communications related function.
The encoder generates a pair of symbols by the
convolution of the current data bit and a number of
previous data bits using two different polynomials;
the length of the convolution used determines the
constraint length of the code. The STEL-2070A is
designed to operate with both constraint length 7 and
constraint length 9 convolutional codes. This
encoding introduces a high degree of redundancy
which enables accurate decoding of information
despite a high symbol error rate resulting from a noisy
link.
The STEL-2070A incorporates all the memories
required to perform these functions. In addition, the
STEL-2070A incorporates a differential encoder and
decoder, three different scrambling algorithms, a BER
monitor and a microprocessor interface. The BER
monitor also includes a counter, allowing the average
BER over an extended number of bits (up to 1.6 x 1010)
to be computed. The STEL-2070A is available in a 68pin PLCC (plastic leaded chip carrier) and also in a
ceramic leaded chip carrier (J-bend leads).
PIN CONFIGURATION
Package: 68 pin PLCC
Thermal coefficient, θja = 36° C/W
Package: 68 pin CLDCC
Thermal coefficient, θja = 34° C/W
0.200"
max.
6 6 6 6 6 6 6 6
9 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
PLCC
TOP
VIEW
0.145"
max.
6 6 6 6 6 6 6 6
9 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1
0.017"
± 0.004" (2)
At seating
plane
0.990"
±0.005"
0.05"
± 0.005" (1)
Tolerance not
cumulative
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
0.035"
nominal
2 2 2 3 3 3 3 3 3 3 3 3 3 4 4 4 4
7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
CLDCC
TOP
VIEW
0.017"
± 0.004" (2)
At seating
plane
0.990"
± 0.010"
2 2 2 3 3 3 3 3 3 3 3 3 3 4 4 4 4
7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3
0.954"
± 0.004"
0.05"
± 0.005" (1)
Tolerance not
cumulative
0.035"
nominal
0.951"
± 0.009"
Notes: (1) Tolerances on pin spacing are not cumulative.
(2) Dimensions apply at seating plane.
(3) PLCC and CLDCC packages have different corners and may not fit into sockets designed
for the other type. Universal sockets are available without alignment locators.
PIN CONNECTIONS
1
2
3
4
5
6
7
8
9
10
11
12
VSS
VSS
DATACLK
DATAIN
EG1
EG2
I.C.
I.C.
VDD
VDD
IDVAL
VSS
13
14
15
16
17
18
19
20
21
22
23
24
RESET
VDD
OCLK
VSS
VDD
ICLK
VSS
G1D2
G1D1
G1D0
G2D2
G2D1
25
26
27
28
29
30
31
32
33
34
35
36
G2D0
VDD
VDD
WRITE
READ
ADDR3
ADDR2
ADDR1
ADDR0
VSS
DATA7
DATA6
37
38
39
40
41
42
43
44
45
46
47
48
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
VDD
VDD
CSEL
INT
VSS
ODCLK
49
50
51
52
53
54
55
56
57
58
59
60
VSS
DOUT
VSS
VSS
G2ERR
G1ERR
BERR
SST0
SYNC0
SST1
SYNC1
VDD
61
62
63
64
65
66
67
68
VDD
SYNC
BERSEL
VDD
I.C.
VSS
DRDY
VDD
Notes: 1. I.C. denotes Internal Connection. These pins must be left unconnected. Do not use for vias.
2. Connect all unused inputs except READ to VSS, leave unused outputs unconnected. If the
READ input is not used it should be connected to VDD.
PRODUCT INFORMATION
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3
STEL-2070A
FUNCTION BLOCK DESCRIPTION
INPUT SIGNALS
ENCODER
The convolutional coder is functionally independent of
the decoder. A single data bit is clocked into the 9-bit
shift register on the rising edge of DATACLK. The
symbols G1 and G2 are generated from the inputs to
one of two sets of two polynomial generators (modulo2 sum, or exclusive-OR) from selected taps on the shift
register. The first set of generators uses the constraint
length 7 polynomials 1718 (G1) and 1338 (G2), and the
second set of generators uses the constraint length 9
polynomials 7538 (G1) and 5618 (G2). In each case the
two symbols appear at the EG1 and EG2 outputs.
RESET
Asynchronous master Reset. A logic low on this pin
will clear all registers on the STEL-2070AA in both the
encoder and decoder sections of the chip.
DECODER
Received symbols are latched into the decoder input
registers on the falling edge of the DRDY input. At that
time a new data bit will be clocked out at the DOUT pin
with the output data clock, ODCLK.
The decoder is designed to operate with 3-bit softdecision input signals which may be in Signed
Magnitude or Inverted Two’s Complement code,
according to the setting of the code control pin, SM2C.
For hard decision binary symbols the input signals
should be connected to pins G1D2, and G2D2, and the
other symbol input pins should be tied high (VDD) and
the code set to Signed Magnitude.
A single decoded data bit is output for every pair of
input␣ symbols. The data bit corresponding to a
particular symbol set will be output after a delay of 54
symbols for constraint length 7 decoding and 56 symbols
for constraint length 9 decoding. Therefore, when
using the STEL-2070A to decode blocks of data 54 or 56
additional dummy symbols and 54 or 56 DRDY pulses
need to be added to the data stream to flush the last 54
or 56 decoded data bits out of the decoder.
Node synchronization (correctly grouping incoming
symbols into G1 and G2 pairs) is inherent with many
communication techniques such as TDMA and spread
spectrum systems. If node synchronization is not an
inherent property of the communications link then the
internal auto node sync circuit can be used to do this.
This is accomplished by connecting the node sync
outputs (SST0 and SST1) to the node sync inputs
(SYNC0 and SYNC1). Two algorithms are available for
determining node sync, Metric Renormalization and
BER Measurement, selected by the setting of bit 6 in
address 0H. The threshold for determining the out of
sync condition is user selectable by means of the
THRESH15-0 bits stored in addresses 1H and 2H; this
information is used in conjunction with the window
period information, WINDO15-0, stored in addresses 3H
and 4H. Alternatively, the SYNC0 and SYNC1 pins can
be used with an external algorithm to achieve the same
result.
STEL-2070A
4
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DATACLK
This is the encoder Shift Register Clock. A rising edge
on this clock latches DATAIN into the encoder shift
register. This signal should nominally be a square
wave with a maximum frequency of 360 KHz.
DATAIN
This is the encoder input. The data present at this pin
is latched into the encoder shift register on the rising
edge of DATACLK. This signal should be stable at the
rising edge of DATACLK.
ICLK, OCLK
System Clock. A crystal may be connected between
ICLK and OCLK or a CMOS level clock may be fed
into ICLK only. The clock frequency should be at least
68 times the data rate for constraint length 7 decoding
and at least 260 times the data rate for constraint length
9 decoding, but no more than 22.5 MHz for operation
over the military temperature range or 25 MHz for
operation of the commercial temperature range.
G1D2-0, G2D2-0
The two 3-bit soft decision symbols are connected to
these inputs and loaded into the input registers on the
falling edge of DRDY. The order in which the symbols
are entered into the decoder from the registers
depends on the state of the SYNC0 and SYNC1 inputs.
The decoder can make use of soft decision information,
which includes both polarity information and a
confidence measure, to improve the decoder
performance. If hard decision (single bit) symbols are
used the signals are connected to pins G1D2 and G2D2
and the other inputs are connected to VDD. Refer to
SM2C for a description of the input data codes.
DRDY
The Data Ready signal is used to load symbols into the
decoder. A new set of symbols is latched into the input
registers on each falling edge of the DRDY input. The
frequency of the DRDY signal will be the same as the
decoded data rate.
BERSEL
The BER Select signal is used to select the algorithm
used to compute the BER figure in the BER counter.
When BERSEL is set low the BER figure will be:
PRODUCT INFORMATION
BER =
BERCT15-0
BPER23-0 + 2
and when BERSEL is set high the BER figure will be:
BER =
8 x BERCT15-0
1000 x BPER23-0
SYNC0, SYNC1
The Symbol Sync0 and Symbol Sync1 inputs are used
for auto node sync operation. When using the internal
auto node sync mode these two pins are connected to
SST0 and SST1, respectively. The operation of the
decoder is affected as shown in the following table:
Symbol entered into
decoder during
symbol period N
SYNC0 SYNC1
G1
G2
0
0
G1N
G2N
1
0
G2N-1
G1N
0
1
G2N
G1N
1
1
G2N-1
G1N
Note that whenever the states of the SYNC0 and
SYNC1 inputs are changed there will be a delay of 54
symbols for constraint length 7 decoding and 56
symbols for constraint length 9 decoding before valid
data appears at the DOUT pin.
IDVAL
The Input Data Valid signal is used to control the
operation of the Viterbi decoder when operating with
burst data. IDVAL should be set high before and after
each data burst and set low for the duration of each
burst.
OUTPUT SIGNALS
EG1, EG2
Encoded output symbols G1 and G2. These outputs
depend on the seven or nine (depending on the state of
EKSEL, bit 3 in address 0H) most recent data bits
(DATAIN) clocked into the encoder shift register. The
individual symbols are formed by the modulo-2 sum
of the inputs to the polynomial generators from the
9-bit shift register. The symbols will appear at the EG1
and EG2 outputs 2 cycles of DATACLK after the
corresponding data bit was loaded into DATAIN.
PRODUCT INFORMATION
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DOUT
Decoded Data Out. The signal is latched into the
output register on the rising edge of ODCLK. There is
a delay of 54 data bits for constraint length 7 decoding
and 56 bits for constraint length 9 decoding from the
time a set of symbols is input to the time the
corresponding data bit is output. Consequently, in
order to flush the last 54 or 56 bits of data out of the
system at the end of a burst it is necessary to continue
pulsing the DRDY line for 54 or 56 symbol periods
after the last valid symbol has been entered.
ODCLK
Output Data Clock. The ODCLK output will pulse
high for one cycle of ICLK each time a new valid
output data bit is available at the DOUT output.
ODCLK will not pulse whenever the output data is
defined to be invalid, as defined by the state of the
IDVAL input at the time that the corresponding input
symbols entered the decoder.
SST0, SST1
The Sync State 0 and Sync State 1 signals are the
outputs of the internal auto node sync circuit. They
should be connected to SYNC0 and SYNC1
respectively to use the internal auto node sync
capability. They may also be used in conjunction with
an external node sync algorithm implementation
which can use the SST0 and SST1 or SYNC outputs.
SYNC
The Sync output provides an indication of the status of
the internal auto node sync circuit. This output will
pulse high for one symbol period if the
renormalization count exceeds the threshold value,
indicating that the node sync has been changed.
G1ERR, G2ERR
The G1 Error, G2 Error outputs indicates that an error
has been detected in the G1 or G2 symbols,
respectively, corresponding to the current output bit.
BERR
The Bit Error output indicates that an error has been
detected in any of the symbols corresponding to the
current output bit. This function is the logical OR of
G1ERR and G2ERR.
5
STEL-2070A
MICROPROCESSOR INTERFACE
DATA7-0
DATA7-0 is an 8-bit bidirectional data bus. All control
and status operations are performed via this bus.
ADDR3-0
The 4-bit address bus is used to access the various
control and status functions, as shown in the memory
map table.
WRITE
The Write input is used to write data to the
microprocessor data bus. Data will be latched into the
STEL-2070AA on the rising edge of this signal.
READ
The Read input is used to read data from the
microprocessor data bus; the DATA7-0 bus will be
active in the output mode whenever this input is low.
CSEL
The Chip Select input is used to selectively enable the
microprocessor data bus. It is active low. When this
input is high all data bus operations will be inhibited.
INT
The Interrupt output indicates when the Period
Counter in the BER Monitor has completed a count
period and that a new value of BERCT is ready to be
read from addresses 7H and 8H, at which time INT will
go high for one symbol period.
INPUT (WRITE) FUNCTIONS
ADDRESS 0H (Reset value = 00H)
Bits 1-0: SCRAM1, SCRAM0
The Scramble bits are used to enable the three different
scrambler functions included in the STEL-2070AA, as
shown in the table below:
SCRAM0 SCRAM1
the IESS version, which has become a de facto
standard through widespread use. In each case, the
scrambling function is provided at the encoder and the
descrambler is provided at the decoder.
Bit 2: DKSEL
When the DKSEL bit is set low the decoder section of
the STEL-2070AA is set to operate with the constraint
length 7 polynomials, 1338 and 1718. When DKSEL is
set high the decoder is set to operate with the
constraint length 9 polynomials, 7538 and 5618.
Bit 3: EKSEL
When the EKSEL bit is set low the encoder section of
the STEL-2070AA is set to operate with the constraint
length 7 polynomials, 1338 and 1718. When DKSEL is
set high the encoder is set to operate with the constraint
length 9 polynomials, 7538 and 5618.
Bit 4: DIFEN
When the DIFEN bit is set high the differential encoder
and decoder in the STEL-2070AA are enabled.
Differential encoding is done after V.35 scrambling
(when used) but before Invert G2 scrambling (when
used) in the encoder. The sequence is reversed in the
decoder.
Bit 5: SM2C
The state of the Signed Magnitude/2's Complement
bit determines the format of the incoming softdecision symbols into the decoder. When SM2C is
high the input code is Signed Magnitude, and when it
is low the code is Two's Complement. The codes are
shown in the following table:
CODE CONTROL:
SM2C = 1
SM2C = 0
SYMBOL INPUT:
GXD2-GXD0
GXD2-GXD0
FUNCTION
Most Confident '+' level
0 1 1
0 1 1
Data = 0
0 1 0
0 1 0
0 0 1
0 0 1
0
0
Scrambler disabled
1
0
Invert G2
0
1
V.35 (CCITT compatible)
Least Confident '+' level
0 0 0
0 0 0
1
1
V.35 (IESS compatible)
Least Confident '–' level
1 0 0
1 1 1
Data = 1
1 0 1
1 1 0
1 1 0
1 0 1
1 1 1
1 0 0
The "Invert G2" scrambler simply inverts the G2
symbols generated in the encoder. The decoder then
re-inverts the received G2 symbols before decoding.
Two different "V.35" scrambler formats are provided
since there are two versions of this standard in
existence: the true CCITT version of the standard, and
STEL-2070A
6
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Most Confident '–' level
SM2C should be set high when using hard decision
data.
PRODUCT INFORMATION
OUTPUT (READ) FUNCTIONS
Bit 6: RENORM
When the RENORM bit is set high the Metric
Renormalization algorithm is selected for node
synchronization and when it is set low the BER
Measurement algorithm is selected. The BER
Measurement algorithm is highly recommended and
is much more reliable than the Renormalization
algorithm under most operating conditions. The
recommended threshold setting is 30% of the window
setting.
Bit 7: UBYTE
Read address 7 is used to store the 16-bit data word
SCNT15-0. When the UBYTE bit is set high the upper
byte (bits 15-8) of this data will be read and when it is
set low the lower byte (bits 7-0) will be read.
ADDRESS 1H-2H (Reset value = 00 00H)
THRESH15-0
In the auto node-sync circuit the number of metric
renormalizations or error bits is counted over the
programmable window period WINDO 15-0,
determined by the data stored in addresses 3H-4H. The
threshold at which the counter triggers the SST0 and
SST1 outputs to change states is set with the
THRESH15-0 data. The threshold value will be equal to
the value of THRESH15-0. Since the actual error rate
obtained will depend on the signal to noise ratio
(Eb/N0) in the signal, the optimum value of the
threshold will also depend on Eb/N0 and should be set
accordingly. The actual error count is stored in and can
be read from the register at address 7H.
ADDRESS 3H-4H (Reset value = 00 00H)
WINDO15-0
In the auto node-sync circuit the number of metric
renormalizations or error bits is counted over the
programmable window period WINDO15-0. The
threshold at which the counter triggers the SST0 and
SST1 outputs to change states is set with
THRESH15-0, stored in addresses 3H-4H. The threshold
value will be equal to the value of THRESH15-0.
ADDRESSES 5H-7H (Reset value = FF FF FFH)
BPER23-0
The 24-bit BER Period data, BPER23-0, is used to set the
period (number of data bits) over which the mean BER
is measured by the BER Monitor. The period used is
the value of BPER23-0 + 2 when BERSEL is set low and
1000 times the value of BPER23-0 when BERSEL is set
high. BPER23-0 is stored as three bytes in addresses
2H-4H and should have a minimum value of 1H.
PRODUCT INFORMATION
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ADDRESSES 0H-1H
BERCT15-0
The 16-bit Bit Error Count data represents the mean Bit
Error Rate over the period determined by the BER
Period data BPER23-0. The algorithm used to compute
the BER figure depends on the setting of the BERSEL
input. When BERSEL is set low the BER figure will be:
BER =
BERCT15-0
BPER23-0 + 2
and when BERSEL is set high the BER figure will be:
BER =
8 x BERCT15-0
1000 x BPER23-0
The value will be updated each time the period counter
completes its count. This will be indicated by the INT
output going high for one clock cycle. If the accumulator
overflows during a measurement period its output
will be caused to saturate at a value of FFFFH.
ADDRESSES 2H-4H
CNT2423-0
The 24-bit BER Period data, BPER23-0, is used to set the
period (number of data bits) over which the mean BER
is measured by the BER Monitor. The current value of
the period counter (in thousands of bits counted when
BERSEL is set high), CNT2423-0, is stored as three bytes
in addresses 2H-4H.
ADDRESSES 5H-6H
Bits 2-0: CNT1615-0
The 16-bit BER Count data, CNT1615-0, is used to
generate the BERCT output at the end of the measuring
period by the BPER data written in write addresses
2H-4H. The current value of the error counter,
CNT1615-0, is stored as two bytes in addresses 5H-6H.
ADDRESS 7H
SCNT15-8/SCNT7-0
The 16-bit Sync Count data gives the current value of
the renormalization or error count which is used for
comparison with the threshold in the auto node sync
circuit. The current value can be read from address 7H.
The upper byte (bits 15-8) will be read when UBYTE
(bit 7 in address 0H) is set high and the lower byte (bits
7-0) will be read when UBYTE is set low.
ADDRESSES 8H-FH
The data written into write addresses 0H-7H can be
read out at addresses 8H-FH. i.e., by setting ADDR4
high, addresses 0H-7H translate to 8H-FH.
7
STEL-2070A
MICROPROCESSOR INTERFACE MEMORY MAP
WRITE MODE REGISTERS
ADDR3-0
0
1
2
3
4
5
6
7
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
UBYTE
THRESH7
THRESH15
WINDO7
WINDO15
BPER7
BPER15
BPER23
RENORM
THRESH6
THRESH14
WINDO6
WINDO14
BPER6
BPER14
BPER22
SM2C
THRESH5
THRESH13
WINDO5
WINDO13
BPER5
BPER13
BPER21
DIFEN
THRESH4
THRESH12
WINDO4
WINDO12
BPER4
BPER12
BPER20
EKSEL
THRESH3
THRESH11
WINDO3
WINDO11
BPER3
BPER11
BPER19
DKSEL
THRESH2
THRESH10
WINDO2
WINDO10
BPER2
BPER10
BPER18
SCRAM1
THRESH1
THRESH9
WINDO1
WINDO9
BPER1
BPER9
BPER17
SCRAM0
THRESH0
THRESH8
WINDO0
WINDO8
BPER0
BPER8
BPER16
READ MODE REGISTERS
ADDR3-0
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
BERCT7
BERCT15
CNT247
CNT2415
CNT2423
CNT167
CNT1615
SCNT15/7
UBYTE
THRESH7
THRESH15
WINDO7
WINDO15
BPER7
BPER15
BPER23
BERCT6
BERCT14
CNT246
CNT2414
CNT2422
CNT166
CNT1614
SCNT14/6
RENORM
THRESH6
THRESH14
WINDO6
WINDO14
BPER6
BPER14
BPER22
BERCT5
BERCT13
CNT245
CNT2413
CNT2421
CNT165
CNT1613
SCNT13/5
SM2C
THRESH5
THRESH13
WINDO5
WINDO13
BPER5
BPER13
BPER21
BERCT4
BERCT12
CNT244
CNT2412
CNT2420
CNT164
CNT1612
SCNT12/4
DIFEN
THRESH4
THRESH12
WINDO4
WINDO12
BPER4
BPER12
BPER20
BERCT3
BERCT11
CNT243
CNT2411
CNT2419
CNT163
CNT1611
SCNT11/3
EKSEL
THRESH3
THRESH11
WINDO3
WINDO11
BPER3
BPER11
BPER19
BERCT2
BERCT10
CNT242
CNT2410
CNT2418
CNT162
CNT1610
SCNT10/2
DKSEL
THRESH2
THRESH10
WINDO2
WINDO10
BPER2
BPER10
BPER18
BERCT1
BERCT9
CNT241
CNT249
CNT2417
CNT161
CNT169
SCNT9/1
SCRAM1
THRESH1
THRESH9
WINDO1
WINDO9
BPER1
BPER9
BPER17
BERCT0
BERCT8
CNT240
CNT248
CNT2416
CNT160
CNT168
SCNT8/0
SCRAM0
THRESH0
THRESH8
WINDO0
WINDO8
BPER0
BPER8
BPER16
STEL-2070A
8
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PRODUCT INFORMATION
ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS
Warning: Stresses greater than those shown below may cause permanent damage to the device. Exposure of the device to these conditions for extended periods
may also affect device reliability. All voltages are referenced to Vss.
Symbol
Parameter
Range
Units
Tstg
Storage Temperature
–40 to +125

–65 to +150
°C
(Plastic package)
°C
(Ceramic package)
volts
VDDmax
Supply voltage on VDD
–0.3 to + 7
VI(max)
Input voltage
–0.3 to VDD + 0.3 volts
Ii
DC input current
± 10
mA
RECOMMENDED OPERATING CONDITIONS
Symbol
VDD
Ta
Parameter
Range
Supply Voltage
Operating Temperature (Ambient)
Units
 +5 ± 5%

 +5 ± 10%
Volts (Commercial grade)
 0 to +70

 –55 to +125
°C
(Commercial grade)
°C
(Military grade)
Volts (Military grade)
D.C. CHARACTERISTICS (Operating Conditions: VDD= 5.0 V ±5%, VSS = 0 V, Ta= 0° to 70° C, Commercial
VDD= 5.0 V ±10%, VSS = 0 V, Ta = –55° to 125° C, Military)
Symbol
Parameter
IDD(Q)
Supply Current, Quiescent
IDD
Supply Current, Operational
VIH(min)
High Level Input Voltage
Commercial Operating Conditions
Military Operating Conditions
Min. Typ. Max. Units
1.0
mA
4.0
Conditions
Static, no clock
mA/MHz fICLK
2.0
volts
Logic '1'
2.25
volts
Logic '1'
0.8
volts
Logic '0'
VIL(max)
Low Level Input Voltage
IIH(min)
High Level Input Current
10
35
110
µA
DRDY, VIN = VDD
IIL(max)
Low Level Input Current
–15
–45
–130
µA
All other inputs, VIN = VSS
VOH(min)
High Level Output Voltage
2.4
4.5
VOL(max)
Low Level Output Voltage
IOS
Output Short Circuit Current
volts
IO = –6.0 mA
IO = +6.0 mA
0.2
0.4
volts
20
65
130
mA
VOUT = VDD, VDD = max
–10
–45
–130
mA
VOUT = VSS, VDD = max
CIN
Input Capacitance
2
pF
All inputs
COUT
Output Capacitance
4
pF
All outputs
PRODUCT INFORMATION
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9
STEL-2070A
RESET TIMING
RESET
tRS
t SR
ICLK
ENCODER TIMING
tDS
DATAIN
BIT 1
X
BIT 2
X
tDH
BIT3
BIT4
X
X
DATACLK
tDE
EG1, EG2
FROM BIT 1
FROM BIT 2
FROM BIT3
FROM BIT4
RESET AND ENCODER ELECTRICAL CHARACTERISTICS
A.C. CHARACTERISTICS (Operating Conditions:
VDD= 5.0 V ±5%, VSS = 0 V, Ta= 0° to 70° C, Commercial
VDD= 5.0 V ±10%, VSS = 0 V, Ta = -55° to 125° C, Military)
Cload = 20 pF
Commercial
Symbol
Parameter
tRS
RESET pulse width (low)
tSR
tDS
Min.
Max.
Military
Min.
Max.
Units
50
70
nsec.
RESET to DATACLK setup
5
5
nsec.
DATAIN to DATACLK setup
5
5
nsec.
tDH
DATAIN to DATACLK hold
5
5
nsec.
tDE
DATACLK to EG1 and EG2 stable delay
9
11
nsec.
Notes: tCLK = Period of ICLK =(1/fCLK).
tSR is only relevant if operation is to commence during the first clock cycle after RESET goes high.
STEL-2070A
10
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PRODUCT INFORMATION
DECODER TIMING
DRDY
ICLK
t DO
t CLK
ODCLK
tOD
DOUT
G1D 2-0
G2D 2-0
SYMB 0
SYMB 1
tHD
tSS
DRDY
IDVAL
ODCLK
DOUT
AA
AA
AA
AA
AA
AA
AA
AA
AA
SYMB 2
SYMB n
SYMB n-1
SYMB n+1
SYMB n+2
tSP
NOT VALID NOT VALID
NOT VALID
BIT 0
BIT 1
BIT 2
Note: N = 54 for constraint length 7 decoding and 56 for constraint length 9 decoding
DECODER ELECTRICAL CHARACTERISTICS
A.C. CHARACTERISTICS (Operating Conditions: VDD= 5.0 V ±5%, VSS = 0 V, Ta= 0° to 70° C, Commercial
VDD= 5.0 V ±10%, VSS = 0 V, Ta = -55° to 125° C, Military)
Cload = 20 pF
Commercial
Symbol
Parameter
Min.
Max.
Military
Min.
Max.
Units
fCLK
ICLK frequency, K = 7
68*fDRDY
25
68*fDRDY
22.5
MHz
fCLK
ICLK frequency, K = 9
260*fDRDY
25
260*fDRDY
22.5
MHz
tSS
G12-0 and G22-0 to DRDY setup
4
5
nsec.
tHD
G12-0 and G22-0 to DRDY hold
4
5
nsec.
fSYM
SYMBOL frequency, K = 7
360
330
kHz
fSYM
SYMBOL frequency, K = 9
96
86
kHz
tDO
ICLK to ODCLK
15
18
nsec.
tOD
ODCLK to DOUT
5
6
nsec.
tOD
ICLK to BERR, G1/2ERR, SST0/1, SYNC
15
18
nsec.
Notes: tCLK = Period of ICLK =(1/fCLK), tSP = Symbol period =( 1/fSYM).
PRODUCT INFORMATION
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11
STEL-2070A
MICROPROCESSOR INTERFACE TIMING
1. WRITE OPERATIONS
µPDIS
ADDR 3-0
DON'T CARE
DON'T CARE
tAW
WRITE
DATA 7-0
tHD
tW
DON'T CARE
DON'T CARE
2. READ OPERATIONS
µPDIS
ADDR 3-0
DON'T CARE
DON'T CARE
tAW
READ
tZV
tHD
tVZ
DATA7-0
MICROPROCESSOR INTERFACE ELECTRICAL CHARACTERISTICS
A.C. CHARACTERISTICS (Operating Conditions: VDD= 5.0 V ±5%, VSS = 0 V, Ta= 0° to 70° C, Commercial
VDD= 5.0 V ±10%, VSS = 0 V, Ta = -55° to 125° C, Military)
Commercial
Symbol
Parameter
Min.
Max.
Military
Min.
Max.
Units
tW
WRITE pulse width
5
8
nsec.
tAW
ADDR to WRITE or READ setup
5
8
nsec.
tWA
WRITE or READ to ADDR hold
5
8
nsec.
tZV
DATA Hi-Z to valid
20
27
nsec.
tVZ
DATA valid to Hi-Z
20
27
nsec.
STEL-2070A
12
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PRODUCT INFORMATION
USING AUTOMATIC NODE SYNC
The automatic node sync circuit built into the STEL2070A can be used to provide node sync in
applications where this is not intrinsic to the nature of
the operation. The automatic node sync is enabled by
connecting the SST1 and SST0 outputs to the SYNC1
and SYNC0 inputs, as shown below. The threshold
should be set according to the expected signal to noise
ratio of the input signal for optimum operation of the
system.
G1
G2
SYMBOL
INPUTS
DATA
OUT
IN/OUT
OF SYNC
DOUT
SYNC
STEL-2070
SYNC0
SST0
SST1
SYNC1
BPSK COMMUNICATION SYSTEM USING CONVOLUTIONAL
ENCODING AND VITERBI DECODING. RATE = 1/2
The STEL-2070A can be used in a variety of different
environments. One example is shown below.
An example of a system using the convolutional coder
and Viterbi decoder is illustrated here. The system
modulates a data stream of rate 512 Kbps using binary
PSK (BPSK). To be able to use convolutional coding/
decoding, the system must have available the
additional bandwidth needed to transmit symbols at
twice the data rate (for rate 1 / 2 encoding).
Alternatively, the system could make use of two
parallel channels to transmit two streams of symbols at
the data rate. The performance improvement that can
be expected is shown in the graph below. It shows a
coding gain of approximately 5.2 dB at a BER level of
10–5 for K = 7 and approximately 6.0 dB for K = 9.
10–1
6
3
Tx DATA
256 Kbps
RATE 1/2
CONV.
ENCODER
2
BPSK
MODULATOR
10–2
6
CHANNEL
BW=1024 KHz
3
2
CODED DATA @ 512 Kbps
10–3
6
BER
3
Uncoded
2
Rx DATA
256 Kbps
RATE 1/ 2
VITERBI
DECODER
10–4
BPSK
DEMOD.
6
3
2
Coding Gain
10–5
6
CODED DATA @ 512 Kbps
3
2
K=7
BPSK Communication System using
Convolutional Encoding and Viterbi
Decoding. Rate = 1/2
10–6
6
3
2
K=9
10–7 2
3
4
5
6
7
8
9
10
11
12
Eb /N0 dB
PRODUCT INFORMATION
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13
STEL-2070A
Information in this document is provided in connection with
Intel® products. No license, express or implied, by estoppel
or otherwise, to any intellectual property rights is granted by
this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability
whatsoever, and Intel disclaims any express or implied
warranty, relating to sale and/or use of Intel® products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent,
copyright or other intellectual property right. Intel products
are not intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
For Further Information Call or Write
INTEL CORPORATION
Cable Network Operation
350 E. Plumeria Drive, San Jose, CA 95134
Customer Service Telephone: (408) 545-9700
Technical Support Telephone: (408) 545-9799
FAX: (408) 545-9888
Copyright © Intel Corporation, December 15, 1999. All rights reserved
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