STEL-2050A Data Sheet STEL-2050A Convolutional Encoder Viterbi Decoder R Powered by ICminer.com Electronic-Library Service CopyRight 2003 FEATURES ■ Constraint Length 7 ■ Coding Gain of 5.2 dB (@ 10-5 BER, Rate 1/2) ■ Rates 1/3 , 1/2 , 2/3* and 3/4* (*Punctured) ■ Industry Standard Polynomials ■ Built in BER Monitor G1=1718, G2=1338, G3=1458, ■ All control and data I/O via Microprocessor ■ Programmable Scrambler: Interface V.35 (CCITT or IESS) or "Invert G2" ■ Differential Encoder and Decoder ■ Low Power Consumption ■ Three Bit Soft Decision Inputs in Signed ■ 28-pin PLCC and CLDCC Packages Magnitude or 2's Complement Formats ■ Commercial and Military Temperature ■ Up to 256 Kbps Data Rate (–40° to 85° C) Ranges Available ■ 0.6 Micron CMOS Technology BLOCK DIAGRAM DIFFERENTIAL ENCODER AND V.35 SCRAMBLERS DATACLK DATAIN RESET (TO ALL REGISTERS) CONVOLUTIONAL ENCODER "INV G2" SCRAMBLER ENCODER SECTION SCRAM1-0 2 G3OUT INT 3 READ, WRSTB, CSEL ADDR G2OUT 4 G1OUT 8 DATA MICROPROCESSOR INTERFACE, MODE SELECT AND CONTROL OCLK ADDRESS SEQUENCER AND CONTROL LOGIC ICLK DRATE STATE-METRIC RAM TRELLIS RAM SYNC 1-0 G3D 2-0 G1D 2-0 G2D 2-0 SM2C ADDR DO DI BER MONITOR DATA "INV G2" DESCRAMBLER BUFFER REGISTER & MUX BRANCH METRIC AND ADD-COMPARESELECT LOGIC PATH HISTORY AND AUTO NODE-SYNC LOGIC PNCG1 PNCG2 MIS THRESH DECODER SECTION DIFFERENTIAL DECODER AND V.35 DESCRAMBLERS SYNC SST0 SST1 3 STEL-2050A Powered by ICminer.com Electronic-Library Service CopyRight 2003 2 DOUT DRDY 2 BERR G1ERR 3 G2ERR G3ERR 3 3 FUNCTIONAL DESCRIPTION Convolutional Encoding and Viterbi Decoding are used to provide forward error correction (FEC) which improves digital communication performance over a noisy link. In satellite communication systems where transmitter power is limited, FEC techniques can reduce the required transmission power. The STEL-2050A is a specialized product designed to perform this specific communications related function. can be reduced at the expense of the coding gain by puncturing (deleting) some of the symbols. The STEL-2050A is designed to operate in this way at rates 2 /3 and 3/4, when 3 symbols are transmitted for every 2 bits encoded (rate 2/3) or 4 symbols are transmitted for every 3 bits encoded (rate 3/4). The resulting bandwidth overhead is just 50% and 33% respectively, compared with 100% at rate 1/2. The STEL-2050A incorporates all the memories required to perform these functions. In addition, the STEL-2050A incorporates a differential encoder and decoder, three different scrambling algorithms, a BER monitor and a microprocessor interface. The STEL2050A is available in a 28-pin PLCC (plastic leaded chip carrier) and also in a ceramic leaded chip carrier (J-bend leads). The encoder creates a stream of symbols which are transmitted at 2 (rate 1/2) or 3 (rate 1/3) times the information rate. This encoding introduces a high degree of redundancy which enables accurate decoding of information despite a high symbol error rate resulting from a noisy link. The coding overhead PIN CONFIGURATION Package: 28 pin PLCC (J-bend) Thermal coefficient, θja = 45°/W 2 2 2 4 3 2 1 8 7 6 5 6 7 8 9 10 11 25 24 23 22 21 20 19 Top View 0.492" ±.01" 0.05" (1) 1 1 1 1 1 1 1 2 3 4 5 6 7 8 0.450 ±.01" PIN CONNECTIONS 1 VSS 2 READ 3 CSEL 4 VDD 5 RESET 6 VSS 7 ICLK 8 9 10 11 12 13 14 0.175" max. 0.020" min. 0.018" ±.003" (2) Notes: 1 Tolerance not cumulative 2 Dimension at seating plane 15 16 17 18 19 20 21 VSS OCLK VDD ADDR3 ADDR2 ADDR1 ADDR0 VSS DATA7 DATA6 VDD DATA5 DATA4 DATA3 22 23 24 25 26 27 28 VSS DATA2 DATA1 DATA0 INT I.C. WRSTB Notes: 1. I.C. denotes Internal Connection. ThIs pin must be left unconnected. Do not use for a via. 2. Connect all unused inputs to VSS, leave unused outputs unconnected. 3 Powered by ICminer.com Electronic-Library Service CopyRight 2003 STEL-2050A FUNCTION BLOCK DESCRIPTION The convolutional coder is functionally independent of the decoder. Writing a new data bit into address 4H automatically clocks the data down the 7-bit shift register. The symbols G1, G2, and G3 are generated from the modulo-2 sum (exclusive-OR) of the inputs to the 3 generators from the taps on the shift register. The 3 polynomials are 1718 (G1), 1338 (G2), and 1458 (G3). The three symbols generated for each input data bit are written into the read mode register at address 5H. result with a delayed version of the input symbols. The error information is available in two ways. First, each time an error occurs the error bits in address 3H (read mode) are set high according to which symbol is found to be in error, and second a running count of the errors in a block of data is generated. The length of the block is determined by the 24-bit word BPER23-0 stored in addresses 6H-8H multiplied by 1000, i.e. At the decoder symbols are written into addresses 0H and (for rate 1/3 operation only) 1H. The DRATE bit in address 2H determines whether the decoder operates in rate 1/2 or rate 1/3 mode. When operating at rate 1 /2 the decoding process starts automatically as soon as data is written into address 0H and the G3 data is ignored by the decoder. When operating at rate 1/3 the G1 and G2 symbols must be written first, since the decoding process starts automatically as soon as data is written into address 1H. At least 70 cycles of ICLK must elapse between each write operation to address 0H. (rate 1/2) or 1H (rate 1/3) to allow the decoder to process each data bit. The number of errors in this period is divided by 8 and accumulated. If the accumulator overflows during this period its output will be caused to saturate at a value of FFFFH. At the end of the period the error divider (÷8) and the error and period accumulators are cleared and the error count is stored in addresses 7H and 8H (read mode) so that the actual Bit Error Rate over this period is: Block length = 1000 x BPER23-0 BER = Further information on the theory of operation of Viterbi decoders may be obtained from text books such as "Error-Correcting Codes", by Peterson and Weldon (MIT Press), or "Error Control Coding", by Lin and Costello (Prentice-Hall), or papers such as "Convolutional Codes and their Performance in Communication Systems", by Dr. A. J. Viterbi, IEEE Trans. on Communications, October 1971. A single decoded data bit, DOUT, is written into address 3H (read mode) for every set of input symbols. The data bit corresponding to a particular symbol set will be output after a delay of 71 symbol sets. Therefore, when using the STEL-2050A to decode blocks of data 71 additional dummy zero symbols (G1 and G2 for rate 1/3 or G3 for rate 1/3) must be written into address 0H or 1H to flush the last 71 decoded data bits out of the decoder. INPUT SIGNALS Node synchronization (correctly grouping incoming symbols into G1, G2, and G3 sets) is inherent with many communication techniques such as TDMA and spread spectrum systems. If node synchronization is not an inherent property of the communications link then the internal auto node sync circuit can be used to do this. This is accomplished by internally connecting the node sync outputs (SST0 and SST1) to the node sync inputs (SYNC0 and SYNC1) by setting the AUTONS bit in address 3H high. The threshold for determining the out of sync condition is user selectable by means of the THRESH2-0 bits in address 2H. RESET Asynchronous master Reset. A logic low on this pin will clear all registers on the STEL-2050AA in both the encoder and decoder sections of the chip. RESET should remain low for at least 3 cycles of ICLK to clear the decoder. A software reset is also effected by writing dummy data to address 5H. The address lines, WRITE and CSEL lines should generate a valid write state for at least 3 cycles of ICLK to clear the decoder. ICLK, OCLK System Clock. A crystal may be connected between ICLK and OCLK or a CMOS level clock may be fed into ICLK. The clock frequency should be at least 70 times the decoded data rate but no more than 18 MHz. A Bit Error Rate Monitor function is provided by reencoding the decoded data bits and comparing the STEL-2050A 1000 x BPER23-0 Note that the BER monitor will indicate an error each time an input symbol is punctured, so that the BER indicated by the BERCT15-0 output will not be valid when using punctured codes. In addition, the error divider truncates the error count since it takes 8 errors to increase the count by one, and this truncation can cause significant under-reporting of the error rate unless the value of BERCT15-0 is large enough to make the truncation insignificantly small. For hard decision binary symbols the symbol should be written into bits G1D2, G2D2 and G3D2 respectively, and the other symbol bits set high. Threebit soft decision symbols may be input in Signed Magnitude or Two’s Complement code, according to the setting of the code control bit, SM2C, in address 2H. The bit should be set high when using hard decision data. Powered by ICminer.com Electronic-Library Service CopyRight 2003 8 x BERCT15-0 4 MICROPROCESSOR INTERFACE DATA7-0 All I/O and control functions are accessed via the DATA7-0 bus with the associated control signals. The STEL-2050AA is used as a memory or I/O mapped peripheral to the host processor. PNCG1, PNCG2 The PNCG1 and PNCG2 bits are used to control the STEL-2050AA when operating in punctured mode and are written along with the symbol data. In unpunctured operation (rates 1/2 and 1/3) these bits should be set low. In punctured operation the PNCG1 bit must be set high to indicate that the G1 symbol is punctured and the PNCG2 bit must be set high to indicate that the G2 symbol is punctured. A symbol will be punctured when the PNCG1 or PNCG2 bits are high when the symbol data is written into address 0H. Zero value metrics will be substituted internally for the actual metrics corresponding to the G12-0 or G22-0 data at that time. ADDR3-0 The 4-bit address bus is used to access the various I/O functions, as shown in the table below. Note that some addresses contain both read and write registers, i.e., the read and write mode registers at these addresses are separate and contain different data. WRITE The Write input is used to write data to the microprocessor data bus. It is active low and is normally connected to the write line of the host processor. ADDRESS 2H THRESH2-0 A counter is used to determine the number of either traceback mismatches or metric renormalizations per 256 bits in the auto node-sync circuit, and the threshold at which the counter triggers the SST0 and SST1 bits to change states is set with the data on the THRESH2-0 bits. The threshold values will be as shown in the following table. READ The Read input is used to read data from the microprocessor data bus. It is active low and is normally connected to the read line of the host processor. CSEL The Chip Select input can be used to selectively enable the microprocessor data bus. It is active low. THRESH2-0 INT The Interrupt output indicates when the Period Counter in the BER Monitor has completed a count period and that a new value of BERCT is ready to be read from addresses 7H and 8H, when INT will go high for one symbol period. INPUT (WRITE) FUNCTIONS ADDRESSES 0H, 1H G1D2-0, G2D2-0, G3D2-0 The three 3-bit soft decision symbols are written into the registers at addresses 0H and 1H and the decoding process begins when the data has been written. When operating at rate 1/2 the operation will begin as soon as the G1D2-0 and G2D2-0 data is written into address 0H; when operating at rate 1/3 the operation begins when the G3D2-0 data is written into address 1H, so that it is necessary to write the G1D2-0 and G2D2-0 data first. The order in which the symbols are entered into the decoder from the registers depends on the state of the SYNC0 and SYNC1 bits. The decoder can make use of soft decision information, which includes both polarity information and a confidence measure, to improve the decoder performance. If hard decision (single bit) symbols are used the signals are written into bits G1D2, G2D2 and G3D2 and the other bits are set high. See SM2C for a description of the input data codes. 0 1 1 2 2 4 3 8 4 16 5 32 6 64 7 128 Since the actual error rate obtained will depend on the signal to noise ratio (Eb/No) in the signal, the optimum value of the threshold will also depend on Eb/No and should be set accordingly. The actual mismatch or renomalization count is stored in the read mode register at address 6H. MIS Two algorithms for auto node-sync are incorporated into the STEL-2050AA. When the MIS bit is set high the Traceback Mismatch algorithm is selected, and when this bit is set low the Metric Renormalization algorithm is selected. SCRAM0, SCRAM1 The Scramble bits are used to enable the three different scrambler functions included in the STEL-2050AA, as shown in the following table: 5 Powered by ICminer.com Electronic-Library Service CopyRight 2003 Threshold value STEL-2050A SCRAM0 SCRAM1 0 0 1 0 0 1 1 1 writing data into address 3H during the operation of the decoder to prevent manually overwriting the SYNC0 and SYNC1 bits, since this will affect the operation of the auto node sync circuit. The operation of the decoder is affected in the following way by the SYNC0 and SYNC1 inputs: FUNCTION Scrambler disabled Invert G2 V.35 (CCITT compatible) V.35 (IESS compatible) Symbol entered into decoder during symbol period N The "Invert G2" scrambler simply inverts the G2 symbols generated in the encoder. The decoder then re-inverts the received G2 symbols before decoding. Two different "V.35" scrambler formats are provided since there are two versions of this standard in existence: the true, CCITT version of the standard, and the IESS version, which has become a de facto standard through widespread use. In each case, the scrambling function is provided at the encoder and the descrambler is provided at the decoder. RATE SYNC0 SYNC1 1 1 1 1 0 0 0 0 SM2C The state of the Signed Magnitude/2's Complement bit determines the format of the incoming softdecision symbols into the decoder. When SM2C is set high the input code is Signed Magnitude, and when it is low the code is Two's Complement. The codes are shown in the following table: CODE CONTROL: SYMBOL INPUT: Most Confident '+' level Data = 0 Least Confident '+' level Least Confident '–' level Data = 1 Most Confident '–' level SM2C=1 SM2C=0 GXD2-GXD0 GXD2-GXD0 0 0 0 0 1 1 0 0 1 0 1 0 0 0 0 0 1 1 0 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 0 1 1 1 1 1 1 1 0 0 1 0 1 0 G3 G1N G2N-1 G2N G2N-1 G1N G3N-1 G2N-1 G2N – G1N – G1N – G1N – G2N G3N G1N G2N G3N-1 G1N Invalid state AUTONS When the AUTONS bit is set high it causes the SST0 and SST1 bits to overwrite the SYNC0 and SYNC1 bits respectively, thereby turning on the internal auto node sync function. DIFEN When the DIFEN bit is set high the differential encoder and decoder in the STEL-2050AA are enabled. Differential encoding is done after V.35 scrambling (when used) but before Invert G2 scrambling (when used) in the encoder. The sequence is reversed in the decoder. Note that the BER monitor function will only operate correctly when this bit is set low. ADDRESS 4H DATAIN The Encoder input data bit is written into the register at address 4H. A DATACLK signal is automatically generated internally each time data is written into this location, causing the data to be latched into the encoder shift register and generating a new set of encoded symbols. When the encoder is used in a burst application the encoder register should be flushed with seven dummy data bits (zeroes) at the end of the burst. DRATE The Decoder Rate bit selects whether the decoder will read two symbols (DRATE set high) or three symbols (DRATE set low) for every data bit decoded. During rate 1/2 operation the G3 symbol is completely ignored by the decoder. DRATE should be set high for rate 3 /4 operation. ADDRESS 3H SYNC0, SYNC1 The Symbol Sync0 and Symbol Sync1 bits are used for the node sync operation. When using the internal auto node sync mode these two bits are overwritten by SST0 and SST1, respectively by setting the AUTONS bit high. When this is done it is necessary to avoid STEL-2050A 0 0 1 1 0 0 1 1 G2 Note that whenever the states of the SYNC0 and SYNC1 inputs are changed there will be a delay of 71 bit periods before valid data starts appearing at the decoder output. The SM2C bit should be set high when using hard decision data. The polarity of the input signals is such that a constant + level on both G1 and G2 produces an output data stream of zeros. Powered by ICminer.com Electronic-Library Service CopyRight 2003 0 1 0 1 0 1 0 1 G1 ADDRESS 5H RESET A software reset is effected by writing dummy data to address 5H. The address lines, WRITE and CSEL lines 6 each time a traceback mismatch occurs and will stay low for one bit period. When using the Traceback Mismatch algorithm for automatic node sync the mismatch counter will be incremented at the same time. should generate a valid write state for at least 3 cycles of ICLK to clear the decoder. ADDRESSES 6H - 8H BPER23-0 The 24-bit BER Period data is used to set the period (number of data bits) over which the mean BER is measured by the BER Monitor. The period used is 1000 times the value of BPER23-0. RNORM The RENORM bit is normally set low. It will be set high each time the metrics are renormalized and will stay high for one bit period. When using the Metric Renormalization algorithm for automatic node sync the renormalization counter will be incremented at the same time. OUTPUT (READ) FUNCTIONS ADDRESS 3H DOUT Decoded Data Out. The signal is stored in the read register at address 3H when the next symbol data is written to start the decoding process for the next bit. There is a delay of 71 data bits from the time a set of symbols is written into the STEL-2050AA to the time the corresponding data bit is available. Consequently, in order to flush the last 71 bits of data out of the system at the end of a burst it is necessary to continue writing dummy input symbols and reading the output data for 71 symbol periods after the last valid symbol has been entered. ADDRESS 5H G1OUT, G2OUT, G3OUT These are the output Symbols from the Encoder. They depend on the seven most recent data bits (DATAIN) clocked into the encoder shift register and are formed by the modulo-2 sum of the inputs to the generators from the 7-bit shift register. They are stored in the read mode register at address 5H. ADDRESS 6H COUNT7-0 The 8-bit Count data gives the current value of the mismatch or renormalization count which is used for comparison with the threshold. G1ERR, G2ERR and G3ERR The G1 Error, G2 Error and G3 Error bits indicate that an error has been detected in the G1, G2 or G3 symbols, respectively, corresponding to the current output bit. These functions will only be valid when operating at rates 1/2 and 1/3 with the DIFEN bit set low. ADDRESSES 7H - 8H BERCT15-0 The 16-bit Bit Error Count data represents the mean Bit Error Rate over the period determined by the BER Period data BPER23-0. The actual BER is given by: BERR The Bit Error bit indicates that an error has been detected in any of the symbols corresponding to the current output bit. This function is the logical OR of G1ERR, G2ERR, and (at rate 1/3 only) G3ERR. This function will only be valid when operating at rates 1 /2 and 1/3 with the DIFEN bit set low. BER = 8 x BERCT15-0 1000 x BPER23-0 The value will be updated each time the period counter completes its count. This will be indicated by the INT output going high for one clock cycle. If the accumulator overflows during a measurement period its output will be caused to saturate at a value of FFFFH. Note that the BER monitor will indicate an error each time an input symbol is punctured, so that the BER indicated by the BERCT15-0 output will not be valid when using punctured codes unless the effect of the puncturing can be compensated externally. ADDRESS 4H SYNC The Sync bit provides an indication of the status of the internal auto node sync circuit. This bit will pulse high for one symbol period if the mismatch or renormalization count exceeds the threshold value, indicating that the node sync has been changed. SST0, SST1 The Sync State 0 and Sync State 1 signals are the outputs of the internal auto node sync circuit. They will overwrite the SYNC0 and SYNC1 bits respectively when AUTONS is set high. They may also be used in conjunction with an external node sync algorithm implementation which can use the SST0 and SST1 data. ADDRESS EH ACK Acknowledge. The signal is stored in the read register at address EH. This bit goes high when a new symbol set has been written into the decoder and the decoding process has started and goes low again 70 clock cycles later to indicate that a new data bit is ready to be read. MSMCH The MSMCH bit is normally set high. It will be set low 7 Powered by ICminer.com Electronic-Library Service CopyRight 2003 STEL-2050A MICROPROCESSOR INTERFACE MEMORY MAP WRITE MODE REGISTERS ADDR3-0 DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 0* 1* 2* 3 4 5 6 7 8 PNCG1 G1D2 G1D1 G1D0 PNCG2 DRATE SM2C SCRAM0 SCRAM1 MIS DIFEN G2D2 G3D2 THRESH2 AUTONS G2D1 G3D1 THRESH1 SYNC1 BPER7 BPER15 BPER23 BPER6 BPER14 BPER22 BPER5 BPER13 BPER21 BPER4 BPER12 BPER20 BPER3 BPER11 BPER19 BPER2 BPER10 BPER18 BPER1 BPER9 BPER17 G2D0 G3D0 THRESH0 SYNC0 DATAIN RESET BPER0 BPER8 BPER16 DATA4 DATA3 DATA2 DATA1 DATA0 BERR RNORM G3ERR MSMCH COUNT4 BERCT4 BERCT12 COUNT3 BERCT3 BERCT11 G2ERR SST1 G3OUT COUNT2 BERCT2 BERCT10 G1ERR SST0 G2OUT COUNT1 BERCT1 BERCT9 DOUT SYNC G1OUT COUNT0 BERCT0 BERCT8 * Indicates that these are also readable registers READ MODE REGISTERS ADDR3-0 3 4 5 6 7 8 E DATA7 COUNT7 BERCT7 BERCT15 ACK DATA6 COUNT6 BERCT6 BERCT14 DATA5 COUNT5 BERCT5 BERCT13 ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS Note: Stresses greater than those shown below may cause permanent damage to the device. Exposure of the device to these conditions for extended periods may also affect device reliability. All voltages are referenced to Vss. Symbol Parameter Range Tstg Storage Temperature –40 to +125 –65 to +150 Units °C (Plastic package) °C (Ceramic package) VDDmax Supply voltage on VDD –0.3 to + 7 VI(max) Input voltage –0.3 to VDD+0.3 volts Ii DC input current ± 10 STEL-2050A Powered by ICminer.com Electronic-Library Service CopyRight 2003 8 volts mA RECOMMENDED OPERATING CONDITIONS Symbol VDD Ta Parameter Supply Voltage Operating Temperature (Ambient) Range Units +5 ± 5% +5 ± 10% Volts (Commercial grade) Volts (Military grade) 0 to +70 –55 to +125 °C (Commercial grade) °C (Military grade) D.C. CHARACTERISTICS (Operating Conditions: VDD= 5.0 V ±5%, VSS=0 V, Ta= 0° to 70° C, Commercial VDD= 5.0 V ±10%, VSS=0 V, Ta=–55° to 125° C, Military) Symbol Parameter Min. Typ. Max. Units IDD(Q) Supply Current, Quiescent 1.0 IDD Supply Current, Operational 2.0 VIH(min) High Level Input Voltage Conditions mA Static, no clock mA/MHz Standard Operating Conditions 2.0 volts Logic '1' Extended Operating Conditions 2.25 volts Logic '1' 0.8 volts Logic '0' 110 µA VIL(max) Low Level Input Voltage IIH(min) High Level Input Current 10 35 VOH(min) High Level Output Voltage 2.4 4.5 VOL(max) Low Level Output Voltage IOS Output Short Circuit Current VIN = VDD volts IO = –6.0 mA IO = +6.0 mA 0.2 0.4 volts 20 65 130 mA VOUT = VDD, VDD = max –10 –45 –130 mA VOUT = VSS, VDD = max CIN Input Capacitance 2 pF All inputs COUT Output Capacitance 4 pF All outputs A.C. CHARACTERISTICS (Operating Conditions: VDD= 5.0 V ±5%, VSS=0 V, Ta= 0° to 70° C, Commercial VDD= 5.0 V ±10%, VSS=0 V, Ta=–55° to 125° C, Military) Symbol Parameter Min. Max. Units Conditions tRS RESET pulse Width 3*tICLK tSR RESET to ICLK Setup 2 nsec. tW WRITE Pulse Width 5 nsec. tCI ICLK to INT Delay 10 tSU CSEL, DATA or ADDR to WRITE or READ setup 5 nsec. tHD WRITE or READ to CSEL, DATA or ADDR hold 5 nsec. tZV DATA Hi-Z to valid 12 nsec. Load = 15 pF tVZ DATA valid to Hi-Z 12 nsec. Load = 15 pF 35 9 Powered by ICminer.com Electronic-Library Service CopyRight 2003 nsec. STEL-2050A RESET AND MICROPROCESSOR INTERFACE TIMING RESET (or CSEL/WRITE/ADDR 5H) tRS t SR ICLK t CI INT 1. WRITE OPERATONS CSEL ADDR3-0 DON'T CARE DON'T CARE tW WRITE tHD tSU DATA 7-0 DON'T CARE DON'T CARE 2. READ OPERATONS CSEL ADDR3-0 DON'T CARE DON'T CARE tSU READ t ZV t HD tVZ DATA7-0 STEL-2050A Powered by ICminer.com Electronic-Library Service CopyRight 2003 10 PUNCTURED MODE OPERATION In punctured codes some of the symbols generated by the convolutional encoder are deleted, or punctured, from the transmitted sequence. For example, in an unpunctured rate 1/2 sequence, four bits would be transmitted for every two data bits. If every fourth bit was punctured from the sequence then only three bits would be transmitted for every two data bits. This would result in a rate 2/3 code. The STEL-2050A is designed to operate in punctured mode as well as normal, rate 1/2, mode. This is easily accomplished by means of the PNCG1 and PNCG2 bits, which delete the symbol which would normally have been loaded into the decoder at the time when either of these bits is set high. The punctured symbols are replaced Rate internally by zero metric values. The Viterbi algorithm treats the zero value metrics by giving them zero weight in the computations relative to the other symbols. The coding gain is significantly less than that for unpunctured operation, but this is the trade-off for the reduced bandwidth required to transmit the symbols. The recommended puncturing sequences for rates 2/3 and 3/4 punctured operation are shown in the table. The sequences shown in boldface are the basic sequence, which are then repeated. The use of the PNCG1 and PNCG2 bits is shown below for rate 3 / 4. The punctured symbols are marked with asterisks. Rates higher than 3/4 are not recommended with the STEL-2050A. Symbol sequence 2 G1 G2 G1 P G1 G2 G1 P G1 G2 G1 P G1 G2 G1 P G1 G2 3 G1 G2 P G2 G1 P G1 G2 P G2 G1 P G1 G2 P G2 G1 P /3 /4 G1 * G2 * * * * DRDY** PNCG1 PNCG2 * Denotes punctured symbols. ** Denotes that DRDY is set high at these times. USING AUTOMATIC NODE SYNC The automatic node sync circuit built into the STEL-2050A can be used to provide node sync in applications where this is not intrinsic to the nature of the operation. The automatic node sync is enabled by setting the AUTONS bit high. The threshold should be set according to the expected signal to noise ratio of the input signal for optimum operation of the system. 11 Powered by ICminer.com Electronic-Library Service CopyRight 2003 STEL-2050A BPSK COMMUNICATION SYSTEM USING CONVOLUTIONAL ENCODING AND VITERBI DECODING. RATE = 1/2 The STEL-2050A can be used in a variety of different environments. One example is shown below. It cannot be used as a common encoder or decoder in multichannel applications because of the memory incorporated on the chip which is dedicated to a single channel. the data rate. The performance improvement that can be expected is shown in the graph below. The convolutional encoder is functionally independent from the decoder. A single data bit is clocked into the 7 bit shift register on the rising edge of DATA CLK. The decoder portion of the STEL-2050A is designed to accept symbols synchronously. DRDY is supplied by the user to clock in the symbols. The maximum data rate is 256 Kbps, using a clock frequency of 18 MHz. This corresponds to 512 K symbols per second at rate 1/2 and 768 K symbols per second at rate 1/3. 18 MHz crystals are readily available, and this clock frequency can be used at all data rates, although the power consumption can be reduced by using lower clock frequencies. An example of a system using the convolutional coder and Viterbi decoder is illustrated here. The system modulates a data stream of rate 512 Kbps using binary PSK (BPSK). To be able to use convolutional coding/ decoding, the system must have available the additional bandwidth needed to transmit symbols at twice the data rate (for rate 1 / 2 encoding). Alternatively, the system could make use of two parallel channels to transmit two streams of symbols at 10–1 10–2 Tx DATA 256 Kbps RATE 1/2 CONV. ENCODER BPSK MODULATOR Uncoded 10–3 CHANNEL BW=1024 KHz CODED DATA @ 512 Kbps BER 10–4 Coded Coding Gain 10–5 Rx DATA 256 Kbps 1/ 2 RATE VITERBI DECODER BPSK DEMOD. 10–6 CODED DATA @ 512 Kbps 10–7 2 3 BPSK Communication System using Convolutional Encoding and Viterbi Decoding. Rate = 1/2 STEL-2050A Powered by ICminer.com Electronic-Library Service CopyRight 2003 12 4 5 6 7 8 9 Eb/N0 dB 10 11 Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intels Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel® products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. For Further Information Call or Write INTEL CORPORATION Cable Network Operation 350 E. Plumeria Drive, San Jose, CA 95134 Customer Service Telephone: (408) 545-9700 Technical Support Telephone: (408) 545-9799 FAX: (408) 545-9888 Copyright © Intel Corporation, December 15, 1999. All rights reserved Powered by ICminer.com Electronic-Library Service CopyRight 2003