STEL-5269+512 Data Sheet STEL-5269+512 Convolutional Encoder Viterbi Decoder R Powered by ICminer.com Electronic-Library Service CopyRight 2003 FEATURES ■ CONSTRAINT LENGTH 7 ■ CODING RATES 1/2 AND 1/3 ■ THREE BIT SOFT-DECISION INPUTS IN ■ CODING GAIN OF 6.0 dB (AT 10–5 BER, RATE 1/3) ■ INDUSTRY STANDARD POLYNOMIALS G1 = 1718, G2 = 1338, G3 = 1458, SIGNED MAGNITUDE OR 2’s COMPLEMENT FORMAT ■ LOW POWER CONSUMPTION ■ 44 PIN PLCC AND CLDCC PACKAGES ■ AVAILABLE TO MIL-STD 883C ■ 512 Kbps DATA RATE (0° to 70° C) ■ CODING GAIN OF 5.2 dB (AT 10-5 BER, RATE 1/2) BLOCK DIAGRAM DATACLK ENCODER SECTION Q1 DATAIN 7-BIT SHIFT REGISTER Q2 Q3 Q4 Q5 Q6 Q7 OSY MB "INV G2" SCRAMBLER AND 3:1 MUX 2 SEL A, B MODE ERATE ENLATCH RESET (TO ALL REGS.) SCRAMBL OCLK ICLK DRDY ACK DRATE SYNC0 SYNC1 G1D 2-0 G2D 2-0 G3D 2-0 2 MODE SELECT AND CONTROL Q LATCH SELECT DECODER SECTION STATE-METRIC RAM ADDRESS SEQUENCER AND CONTROL LOGIC TRELLIS RAM ADDR 3 3 3 "INV G2" DESCRAMBLER, BUFFER REG. & MUX. DATA BRANCH METRIC AND ADD-COMPARESELECT LOGIC PATH HISTORY AND AUTO NODE-SYNC LOGIC SM2C MIS THRESH D DOUT SYNC SST0 3 STEL-5269+512 Powered by ICminer.com Electronic-Library Service CopyRight 2003 SST1 2 FUNCTIONAL DESCRIPTION ENCODER OPERATION Convolutional Encoding and Viterbi Decoding are used to provide forward error correction (FEC) which improves digital communication performance over a noisy link. In satellite communication systems where transmitter power is limited, FEC techniques can reduce the required transmission power. The STEL-5269+512 is a specialized product designed to perform this specific communications related function. The encoder creates a stream of symbols which are transmitted at 2 (Rate 1/2) or 3 (Rate 1/3) times the information rate. This encoding introduces a high degree of redundancy which enables accurate decoding of information despite a high symbol error rate resulting from a noisy link. The STEL-5269+512 incorporates all the memories required to perform these functions. The STEL5269+512 is available in a 44-pin PLCC (plastic leaded chip carrier) and also in a ceramic leaded chip carrier (J-bend leads). A 256 Kbps version, the STEL-5269, is also available at a lower cost. The convolutional coder is functionally independent of the decoder. A single data bit is clocked into the 7-bit shift register on the rising edge of DATACLK. There are two modes of operation, controlled by the MODE input. When MODE is low the timing of the SEL␣ A, SEL␣ B and ENLATCH signals determine whether 2 or 3 symbol bits are generated for every data bit. When MODE is high the symbols are automatically generated sequentially every clock cycle. In this case, the state of ENRATE determines whether the device generates symbols for Rate 1/2 or Rate 1/3 operation. The symbols G1, G2, and G3 are generated from the modulo-2 sum (exclusive-OR) of the inputs to the 3 generators from the taps on the shift register. The 3 polynomials are 1718 (G1), 1338 (G2), and 1458 (G3). Example inputs are shown in the timing diagram for both rate 1/2 and rate 1/3 operation. PIN CONFIGURATION Package: 44 pin CLDCC Thermal coefficient, θja = 50° C/W Package: 44 pin PLCC Thermal coefficient, θja = 40°C/W 7 8 9 10 11 12 13 14 15 16 17 0.14" max. 0.18" max. 4 4 4 4 4 6 5 4 3 2 1 4 3 2 1 0 39 38 37 36 35 0.690" 34 33 ± .005" 32 31 30 29 4 4 4 4 4 6 5 4 3 2 1 4 3 2 1 0 7 8 9 10 11 12 13 14 15 16 17 0.017" ± 0.004" (2) 0.05" nom. (1) 0.02" min. 1 1 2 2 22 2 2 2 2 2 8 9 0 1 23 4 5 6 7 8 0.653" ± 0.010" Top View 39 38 37 36 35 0.690" 34 33 ± .010" 32 31 30 29 0.016" ± 0.004" (2) 0.05" nom. (1) 0.045" nom. 1 1 2 2 22 2 2 2 2 2 8 9 0 1 23 4 5 6 7 8 0.653" ± 0.004" Notes: (1) Tolerances on pin spacing are not cumulative. (2) Dimensions apply at seating plane. (3) PLCC and CLDCC packages have different corners and may not fit into sockets designed for the other type. Universal sockets are available without alignment locators. PIN CONNECTIONS 1 SYNC 2 VSS 3 ACK 4 DATACLK 5 DRDY 6 DATAIN 7 G3D0 8 G3D1 9 G3D2 10 MODE 11 VSS 12 13 14 15 16 17 18 19 20 21 22 MIS DOUT OSYMB G2D0 G2D1 G2D2 G1D0 G1D1 G1D2 ENLATCH VDD 23 24 25 26 27 28 29 30 31 32 33 VSS THRESH0 THRESH1 RESET DRATE SEL A THRESH2 VDD VSS I.C. ERATE 34 35 36 37 38 39 40 41 42 43 44 VSS SST1 SYNC1 SST0 SYNC0 SEL B SM2C ICLK OCLK SCRAMBL I.C. Note: I.C. denotes Internal Connection. These pins must be left unconnected. Do not use for vias. 3 Powered by ICminer.com Electronic-Library Service CopyRight 2003 STEL-5269+512 DECODER OPERATION INPUT SIGNALS The STEL-5269+512 is designed to accept symbols either synchronously or in a handshake mode. Symbols are latched into the decoder input registers on the falling edge of the DRDY input. ACK is returned by the decoder to indicate that the symbols have been accepted. The RATE input determines whether the decoder will operate in Rate 1/2 or Rate 1/3 mode. When operating at Rate 1/2 the G3 symbol is ignored by the decoder. For hard decision binary symbols the G1, G2, G3 symbol bits should be connected to pins G1D2, G2D2 and G3D2 respectively, and the other symbol input pins should be tied high (VDD). Three-bit soft decision symbols may be input in Signed Magnitude or Inverted Two’s Complement code, according to the setting of the code control pin, SM2C. The code should be set to Signed Magnitude when using hard decision data. A single decoded data bit is output for every set of input symbols. The data bit corresponding to a particular symbol set will be output after a delay of 42 symbols. Therefore, when using the STEL-5269+512 to decode blocks of data 42 additional dummy symbols and 42 DRDY signals need to be added to the data stream to flush the last 42 decoded data bits out of the decoder. Node synchronization (correctly grouping incoming symbols into G1, G2, and G3 sets) is inherent with many communication techniques such as TDMA and spread spectrum systems. If node synchronization is not an inherent property of the communications link then the internal auto node sync circuit can be used to do this. This is accomplished by connecting the node sync outputs (SST0 and SST1) to the node sync inputs (SYNC0 and SYNC1). The threshold for determining the out of sync condition is user selectable by means of the THRESH2-0 inputs. Alternatively, the SYNC0 and SYNC1 pins can be used with an external algorithm to achieve the same result. Further information on the theory of operation of Viterbi decoders may be obtained from text books such as "Error-Correcting Codes", by Peterson and Weldon (MIT Press), or "Error Control Coding", by Lin and Costello (Prentice-Hall). An alternative source of information is the many papers on this subject that have appeared in the IEEE transactions, such as "Convolutional Codes and their Performance in Communication Systems", by Dr. A. J. Viterbi, IEEE Trans. on Communications Technology, October 1971. STEL-5269+512 Powered by ICminer.com Electronic-Library Service CopyRight 2003 RESET Asynchronous master Reset. A logic low on this pin will clear all registers on the STEL-5269+512 in both the encoder and decoder sections of the chip. RESET should remain low for at least 3 cycles of ICLK. DATACLK This is the encoder Shift Register Clock. A rising edge on this clock latches DATAIN into the encoder shift register. This signal should nominally be a square wave with a maximum frequency of 512 KHz. DATAIN This is the encoder input. The data present at this pin is latched into the encoder shift register on the rising edge of DATACLK. This signal should be stable at the rising edge of DATACLK. MODE The state of the MODE input determines the method of symbol sequencing in the encoder. When MODE is set low the sequencing is generated externally under the control of the SEL A and SEL B inputs, and when MODE is set high it is generated automatically. SEL A, SEL B When MODE is set low SEL A and SEL B select the encoded symbol, G1, G2 or G3, which will appear on the OSYMB pin on the next rising edge of ENLATCH according to the table: SEL A SEL B SYMBOL POLYNOMIAL 0 1 0 1 0 0 G1 G2 G3 1718 (11110012) 1338 (10110112) 1458 (11001012) When MODE is set high the symbol sequence is generated automatically and the SEL A and SEL B inputs are inactive. ERATE When MODE is high the Encoder Rate input determines whether symbols for Rate 1/2 (ERATE = 1) or Rate 1/3 (ERATE = 0) operation are generated. When MODE is low this input is inactive. SCRAMBL When the Scramble input is set high the G2 symbol generated at the encoder and the G2 symbol received at the decoder will be inverted. This ensures that the output symbol stream is not a string of zeroes when the input data stream is all zeroes, thereby making it easier for the demodulator to recover the clock information under these conditions. When SCRAMBL is set low the normal symbol stream is generated. 4 ENLATCH This is the encoder Output Latch Enable. The new symbol is clocked into the output latch and appears on the OSYMB pin on the rising edge of ENLATCH. When MODE is low the symbol selected will depend on the states of the SEL A and SEL B lines, which should be stable on the rising edge of ENLATCH. When MODE is high the symbol selection is internal, and the frequency of the ENLATCH signal should be 2 or 3 times the frequency of the DATACLK, depending on the rate selected. CODE CONTROL: SYMBOL INPUT: Most Confident '+' level Data = 0 Least Confident '+' level Least Confident '–' level Data = 1 ICLK, OCLK System Clock. A crystal may be connected between ICLK and OCLK or a CMOS level clock may be fed into ICLK only. The clock frequency should be at least 70 times the data rate but no more than 36 MHz. Most Confident '–' level SM2C = 0 GxD2-0 0 0 0 0 1 1 0 0 1 0 1 0 0 0 0 0 1 1 0 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 0 1 1 1 1 1 1 1 0 0 1 0 1 0 When using hard decision data, SM2C should be set high, the G12 and G22 input pins used for the symbol signals and G11-0 and G21-0 tied high. DRATE The Decoder Rate input selects whether the decoder will read two symbols (DRATE set high) or three symbols (DRATE set low)) for every data bit decoded. During rate 1/2 operation the symbol G3 on inputs G3D2-0 is completely ignored by the decoder. SYNC0, SYNC1 The Symbol Sync inputs are used for auto node sync operation. When using the internal auto node sync mode these two pins are connected to SST0 and SST1, respectively. The operation of the decoder is affected in the following way by the SYNC0 and SYNC1 inputs: G1D2-0, G2D2-0, G3D2-0 The three 3-bit soft decision symbols are connected to these inputs and loaded into the input registers on the falling edge of DRDY. The order in which the symbols are entered into the decoder from the registers depends on the state of the SYNC0 and SYNC1 inputs. The decoder can make use of soft decision information, which includes both polarity information and a confidence measure, to improve the decoder performance. If hard decision (single bit) symbols are used the signals are connected to pins G1D2, G2D2 and G3D2 and the other inputs are connected to VDD. See SM2C for a description of the input data codes. RATE SYNC0 SYNC1 1 1 1 1 0 0 0 0 DRDY The Data Ready signal is used to load symbols into the decoder. This signal is edge triggered and a new set of symbols is latched into the input registers on each falling edge of the DRDY input. 0 1 0 1 0 1 0 1 0 0 1 1 0 0 1 1 Symbol entered into decoder inputs during symbol period N G12-0 G22-0 G32-0 G1N G2N G2N–1 G1N G2N G1N Invalid state G1N G2N G3N–1 G1N G2N–1 G3N-1 Invalid state – – – G3N G2N G1N When RATE = 1 (rate 1/2 operation) only one possible alternative state exists in any given situation. This depends on whether the modulation format used was BPSK (sequential symbols) or QPSK (parallel symbol pairs). In this case the node sync process can be improved by only using the SYNC input applicable for the corresponding alternative sync state (i.e., SYNC0 for BPSK, SYNC1 for QPSK) and tying the other low to prevent the node sync circuit from inadvertently selecting the non-applicable state. When RATE = 0 (rate 1/3 operation) both alternative sync states correspond to those possible with BPSK modulation. SM2C The state of the Signed Magnitude/2's Complement input determines the format of the incoming softdecision symbols into the decoder. When SM2C is high the input code is Signed Magnitude, and when it is low the code is Two's Complement. The codes are shown in the following table: 5 Powered by ICminer.com Electronic-Library Service CopyRight 2003 SM2C = 1 GxD2-0 STEL-5269+512 OUTPUT SIGNALS OSYMB Output Symbol from the Encoder. This output depends on the seven most recent data bits (DATAIN) clocked into the encoder shift register and on the select lines SEL A and SEL B. The individual symbols are formed by the modulo-2 sum of the inputs to the generators from the 7-bit shift register. Note that whenever the states of the SYNC0 and SYNC1 inputs are changed there will be a delay of 42 bit periods before valid data starts appearing at DOUT. MIS Two algorithms for auto node-sync are incorporated into the STEL-5269+512. When MIS is set high the Traceback Mismatch algorithm is selected, and when MIS is set low the Metric Renormalization algorithm is selected. The Traceback Mismatch algorithm is recommended for most applications since it generates a better discrimination function between the in-sync and out-of-sync conditions, especially at high error rates (Eb/N0 ≤ 3 dB). ACK A low level pulse on the Acknowledge pin indicates that the decoder has input the current set of two or three symbols. The signal will pulse low between 68 and 69 clock cycles after the falling edge of DRDY. DOUT Decoded Data Out. The signal is latched into the output register on the falling edge of DRDY. There is a delay of 42 data bits from the time a set of symbols is input to the time the corresponding data bit is output. Consequently, in order to flush the last 42 bits of data out of the system at the end of a burst it is necessary to continue pulsing the DRDY line for 42 symbol periods after the last valid symbol has been entered. THRESH 2-0 A counter is used to determine the number of either traceback mismatches or metric renormalizations per 256 bits in the auto node-sync circuit, and the threshold at which the counter triggers the SST0 and SST1 outputs to change states is set with the data on the THRESH2-0 inputs. The threshold values will be as shown in the table below. THRESH2-0 0 1 2 3 4 5 6 7 SST0, SST1 The Sync State 0 and Sync State 1 signals are the outputs of the internal auto node sync circuit. They should be connected to SYNC0 and SYNC1 respectively to use the internal auto node sync capability. They may also be used in conjunction with an external node sync algorithm implementation which can use the SST0 and SST1 outputs. Threshold value 1 2 4 8 16 32 64 128 SYNC The Sync output provides an indication of the status of the internal auto node sync circuit. When it is high it indicates that node sync has been lost, and when it is low it indicates that the system is assumed to be in sync, as determined by the error rate estimate. Since the actual error rate obtained will depend on the signal to noise ratio (Eb/No) in the signal, the optimum value of the threshold will also depend on Eb/No and should be set accordingly. Suggested initial values for THRESH2-0 are 5 for the Mismatch algorithm and 3 for the Renormalization algorithm. STEL-5269+512 Powered by ICminer.com Electronic-Library Service CopyRight 2003 6 ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS Warning: Stresses greater than those shown below may cause permanent damage to the device. Exposure of the device to these conditions for extended periods may also affect device reliability. Symbol Ts Ta Parameter Range Storage Temperature –40 to +125 –55 to +125 °C (Plastic package) °C (Ceramic package) –40 to +85 –55 to +125 °C (Plastic package) °C (Ceramic package) Operating Temperature Units VDDmax Max. voltage between VDD and VSS +7 to –0.7 volts VI/O(max) Max. voltage on any input or output pin VDD + 0.3 volts VI/O(min) Min. voltage on any input or output pin VSS – 0.3 volts RECOMMENDED OPERATING CONDITIONS Symbol Ta VDD Parameter Operating Temperature (Ambient) Supply Voltage D.C. CHARACTERISTICS Symbol Range Units 0 to +70 –55 to +125 °C (Plastic package) °C (Ceramic package) +5 ± 5% +5 ± 5% volts (Commercial grade) volts (Military grade) (Standard Operating Conditions: VDD = 5.0 ± 5% volts,Ta = 0° to 70° C, Military Operating Conditions: VDD = 5.0 ± 5% volts, Ta = –55° to 125° C) Parameter Min. Typ. Max. Units 1.0 mA Conditions IDD(Q) Supply Current, Quiescent Static, no clock IDD Supply Current, Operational 2.0 mA/Mbps fCLK = 36 MHz IDD Supply Current, Operational 6 mA/Mbps All other modes VIH(min) Min. High Level Input Voltage Commercial Operating Cond. 2.0 volts Guaranteed Logic '1' Military Operating Cond. 2.25 volts Guaranteed Logic '1' volts Guaranteed Logic '0' volts IO = –4.0 mA volts IO = +4.0 mA VIL(max) Max. Low Level Input Voltage 0.8 VOH(min) Min. High Level Output Voltage VOL(max) Max. Low Level Output Voltage IIH(min) High Level Input Current 10 35 110 µA DRDY, VIN = VDD IIL(max) Low Level Input Current –15 –45 –130 µA All other inputs, VIN = VSS IOS Output Short Circuit Current 20 65 130 mA VOUT = VDD, VDD = max –10 –45 –130 mA VOUT = VSS, VDD = max 2.4 0.4 CIN Input Capacitance 2 pF All inputs COUT Output Capacitance 4 pF All outputs 7 Powered by ICminer.com Electronic-Library Service CopyRight 2003 STEL-5269+512 ENCODER TIMING. MODE = 1 tDH tDS DATAIN X BIT 1 X BIT 2 X BIT3 X BIT4 DATACLK RATE 1 tDE /2 OPERATION ENLATCH tEOD OSYMB G1 G2 G1 FROM BIT 1 RATE 1 G2 G1 FROM BIT 2 G2 FROM BIT 3 G1 G2 FROM BIT 4 /3 OPERATION ENLATCH OSYMB G1 G2 G3 G1 FROM BIT 1 G2 G3 FROM BIT 2 G1 G2 G3 FROM BIT 3 G1 G2 G3 FROM BIT 4 ENCODER ELECTRICAL CHARACTERISTICS A.C. CHARACTERISTICS (Standard Operating Conditions: VDD = 5.0 ± 5% volts,Ta = 0° to 70° C, Military Operating Conditions: VDD = 5.0 ± 5% volts, Ta = –55° to 125° C) Commercial Symbol Military Parameter Min. Max. tRS RESET pulse width 3*tCLK 3*tCLK nsec. tSR RESET to ICLK setup 2 3 nsec. tDS DATAIN to DATACLK setup 8 10 nsec. tDH DATAIN to DATACLK hold 8 10 nsec. tSS SEL A or SEL B to ENLATCH setup 8 10 nsec. tSH SEL A or SEL B to ENLATCH hold 4 6 nsec. tDE DATACLK to ENLATCH delay 8 10 nsec. tEOD ENLATCH to OSYMB stable delay 8 Min. Max. 10 Units nsec. Notes: tCLK = Period of ICLK =(1/ fCLK). tSR is only relevant if operation is to commence during the first clock cycle after RESET goes high. STEL-5269+512 Powered by ICminer.com Electronic-Library Service CopyRight 2003 8 ENCODER TIMING. MODE = 0 (STEL-5268 EMULATION MODE) RATE 1 tDH /2 OPERATION tDS DATAIN BIT 1 X BIT 2 X BIT3 X BIT4 X DATACLK SEL A tSH SEL B tDE tSS ENLATCH tEOD OSYMB G1 G2 FROM BIT 1 RATE 1 G1 G2 FROM BIT 2 G1 G2 FROM BIT 3 G1 G2 FROM BIT 4 /3 OPERATION DATAIN BIT 1 X BIT 2 X BIT3 X BIT4 X DATACLK SEL A SEL B ENLATCH OSYMB G1 G2 G3 FROM BIT 1 G1 G2 G3 FROM BIT 2 G1 G2 G3 FROM BIT 3 G1 G2 G3 FROM BIT 4 RESET TIMING RESET tRS t SR ICLK 9 Powered by ICminer.com Electronic-Library Service CopyRight 2003 STEL-5269+512 DECODER TIMING ENCODED SYMBOLS SYMB 0 G1D0-G3D2 tSS SYMB 1 SYMB 2 SYMB 3 SYMB 42 SYMB 43 tHD tSP DRDY tAD ACK tDA BIT -41 DOUT DRDY BIT -40 BIT -39 BIT -1 BIT 0 BIT 1 tWA ACK tDI tIA tCLK ICLK tDO DOUT DECODER ELECTRICAL CHARACTERISTICS A.C. CHARACTERISTICS (Standard Operating Conditions: VDD = 5.0 ± 5% volts,Ta = 0° to 70° C, Military Operating Conditions: VDD = 5.0 ± 5% volts, Ta = –55° to 125° C) Commercial Symbol Parameter Min. Max. 70*fDRDY 36 Military Min. 70*fDRDY Max. Units 28 MHz fCLK ICLK Frequency tSS SYMBOL to DRDY setup 16 tHD SYMBOL to DRDY hold tSP SYMBOL Period tDA DRDY to ACK tAD ACK to DRDY 2*tCLK 2*tCLK nsec. tWA ACK pulse width tCLK tCLK nsec. tDI DRDY to ICLK setup 4 tIA ICLK to ACK 8 26 12 32 nsec. tDO ICLK to DOUT 8 30 12 35 nsec. tSR RESET to ICLK setup 2 21 nsec. 4 6 nsec. 2 2.5 µsec. 30 + 68*tCLK 26 + 69*tCLK 30 + 68*tCLK 26 + 69*tCLK 6 3 nsec. nsec. nsec. Notes: fDRDY = Frequency of DRDY, tCLK = Period of ICLK =(1/ fCLK). tSR is only relevant if operation is to commence during the first clock cycle after RESET goes high. STEL-5269+512 Powered by ICminer.com Electronic-Library Service CopyRight 2003 10 APPLICATIONS INFORMATION USING AUTOMATIC NODE SYNC The automatic node sync circuit built into the STEL5269+512 can be used to provide node sync in applications where this is not intrinsic to the nature of the operation. The automatic node sync is enabled by connecting the SST1 and SST0 outputs to the SYNC1 and SYNC0 inputs, as shown below. The threshold should be set according to the expected signal to noise ratio of the input signal for optimum operation of the system (see page 6). When RATE = 1 (rate 1/2) only one possible alternative state exists in any given situation. This depends on whether the modulation format used was BPSK (sequential symbols) or QPSK (parallel symbol pairs). In this case the node sync process can be improved by only using the SYNC input applicable for the corresponding alternative sync state (i.e., SYNC0 G1 G2 3-bit Soft Decision Inputs Data Out DOUT G3 SYNC STEL-5269 SYNC0 SST0 SYNC1 SST1 In/Out of Sync for BPSK, SYNC1 for QPSK) and tying the other low to prevent the node sync circuit from inadvertently selecting the non-applicable state. When RATE = 0 (rate 1/3) both alternative sync states correspond to those possible with BPSK modulation. Note that whenever the states of the SYNC0 and SYNC1 inputs are changed there will be a delay of 42 bit periods before valid data starts appearing at DOUT. DECODER OPERATION WITH BPSK The Viterbi decoder is designed to operate with a QPSK demodulator, which provides the G1 and G2 symbols as parallel pairs from the I and Q channels. Operating the device with a BPSK demodulator, which provides the G1 and G2 symbols as sequential pairs, requires some external circuitry to convert the sequential pairs into parallel pairs. The circuit shown here assumes that the symbols are clocked out of the demodulator on the rising edges of the clock signal. The symbol rate clock is divided by 2 to generate a bit rate clock. One phase of the clock is used to latch alternate symbols into the upper 3-bit latch and the opposite phase latches the interleaving symbols into the lower 3-bit latch. The automatic node sync circuit in the STEL-5269 will take care of the symbol ambiguity which occurs in this system. A third clock phase provides the DRDY signal to the STEL-5269. Again, the phase ambiguity will be taken care of by the automatic node sync circuit. ENCODER OPERATION The encoder section requires a clock at twice the data rate when operating at rate 1/2. A suitable circuit is shown below. The input clock runs at twice the data rate and is divided to produce the data clock itself. The encoder produces serialized symbol pairs suitable for BPSK modulation directly. The optional circuit shown will convert these into parallel pairs suitable for QPSK modulation. Data Clock Data Clock Q Q Q D1 Q1 D2 Q2 D3 Q3 G2D 2 G2D 1 G2D 0 DRDY (All latches are 74HC74/175 type) BPSK Out D Q D Q Q Q G1 (I) DATACLK OSYMB D Q Q (All latches are 74HC74 type) 11 Powered by ICminer.com Electronic-Library Service CopyRight 2003 G1D 2 G1D 1 G1D 0 D Q ENLATCH D Q D1 Q1 D2 Q2 D3 Q3 D Q STEL-5269 DATAIN Data In 2X Data Clock 3-bit Soft Decision Input G2 (Q) Optional circuit for QPSK only STEL-5269+512 BPSK COMMUNICATION SYSTEM USING CONVOLUTIONAL ENCODING AND VITERBI DECODING. RATE = 1/2 The STEL-5269+512 can be used in a variety of different environments. One example is shown below. It cannot be used as a common encoder or decoder in multichannel applications because of the memory incorporated on the chip which is dedicated to a single channel. An example of a system using the convolutional coder and Viterbi decoder is illustrated here. The system modulates a data stream of rate 512 Kbps using binary PSK (BPSK). To be able to use convolutional coding/ decoding, the system must have available the additional bandwidth needed to transmit symbols at twice the data rate (for rate 1/2 encoding). Alternatively, the system could make use of two parallel channels to transmit two streams of symbols at the data rate. The performance improvement that can be expected is shown in the graph below. The convolutional encoder is functionally independent from the decoder. A single data bit is clocked into the 7-bit shift register on the rising edge of DATA CLK. The decoder portion of the STEL-5269+512 is designed to accept symbols synchronously. DRDY is supplied by the user to clock in the symbols. The maximum data rate is 512 Kbps, using a clock frequency of 36 MHz. This corresponds to 512 K symbols per second at rate 1 /2 and 768 K symbols per second at rate 1/3. 36 MHz crystals are readily available, and this clock frequency can be used at all data rates, although the power consumption can be reduced by using lower clock frequencies. 10–1 6 3 2 10–2 6 Tx DATA 512 Kbps RATE 1/2 CONV. ENCODER 3 2 BPSK MODULATOR 10–3 CHANNEL BW=2048 KHz 6 BER 3 2 Coded Uncoded 10–4 CODED DATA @ 1024 Kbps 6 3 2 Coding Gain 10–5 Rx DATA 512 Kbps RATE 1/2 VITERBI DECODER 6 BPSK DEMOD 3 2 10–6 6 3 2 CODED DATA @ 1024 Kbps 10–7 2 BPSK Communication System Using Convolutional Encoding and Viterbi Decoding. Rate = 1/2 STEL-5269+512 Powered by ICminer.com Electronic-Library Service CopyRight 2003 12 3 4 5 6 7 8 Eb/N 0 dB 9 10 11 12 Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intels Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel® products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. For Further Information Call or Write INTEL CORPORATION Cable Network Operation 350 E. Plumeria Drive, San Jose, CA 95134 Customer Service Telephone: (408) 545-9700 Technical Support Telephone: (408) 545-9799 FAX: (408) 545-9888 Copyright © Intel Corporation, December 15, 1999. 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