ETC STEL

STEL-1377Q/S
Data Sheet
STEL-1377Q
(Quadrature)
STEL-1377S
(Single Channel)
32-Bit Resolution FM & PM
Modulated Direct Digital
Frequency Synthesizer
R
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The STEL-1377Q is a complete Quadrature Direct
Digital Frequency Synthesizer (DDS) in a single DIL
package measuring only 3.75 x 1.6". The STEL-1377S
provides a single ended output only. The STEL-1377
makes it possible to use DDS technology in
applications requiring quadrature outputs as well as
frequency and phase modulation in a small package.
The STEL-1377 is a printed circuit unit using the STEL1177 PM and FM Numerically Controlled Oscillator
(NCO) chip driving two high-speed 10-bit DACs
(Sony CX20201A-1) to generate quadrature analog
output signals. Surface mount technology (SMT)
components are used throughout. The device is
guaranteed to operate at clock frequencies up to 60
MHz over the temperature range of 0-70°C, giving an
output frequency range of 0 to over 25 MHz, with a
frequency resolution of 14 milliHz at a clock frequency
of 60 MHz. In addition, the device features phase and
frequency modulation capabilities at extremely high
modulation rates, up to 25% of the clock frequency. For
more detailed information on the STEL-1177 NCO
please refer to the STEL-1177 data sheet. For more
information on the DAC please refer to the Sony
CX20201A-1 data sheet. The output frequency is
directly related to the clock frequency by the
following:
FEATURES
■ HIGH MAXIMUM CLOCK FREQUENCY
■
■
■
■
■
■
- UP TO 60 MHz
HIGH OUTPUT BANDWIDTH
- UP TO 25 MHz OUTPUT FREQUENCY
HIGH FREQUENCY–RESOLUTION
- 32 BITS, 14 milliHz @ 60 MHz
HIGH SPEED FREQUENCY HOPPING
OR MODULATION
- MAXIMUM UPDATE RATE 15 MHz
PRECISION PHASE MODULATION
- 12 BITS, 0.09° RESOLUTION
CAN BE USED FOR LINEAR PM OR
PULSE-SHAPED PSK AT UP TO 15 MHz
PRECISION FREQUENCY MODULATION
- 16 BITS RESOLUTION, CAN BE USED
FOR LINEAR FM OR PULSE-SHAPED FSK
SINE AND COSINE OUTPUTS
(STEL-1377Q) OR SINGLE ENDED
OUTPUT (STEL-1377S) FOR LOWER
POWER CONSUMPTION
HIGH-SPEED, LOW GLITCH ECL DACS
■
■ HIGH SPECTRAL PURITY
■
- –65 dBc SPURIOUS TYPICAL
3.75" BY 1.6" BY 0.4"
fo=
where:
and:
BLOCK DIAGRAM
DATA
8
ADDR
WRSTB
4
10
RESET
FMOD
16
FMAD
2
RATE
SIMLD
2
232
fo is the frequency of the output signal
fc is the clock frequency.
FMSYNC
FRLD
FRSEL
PHLD
PHSEL
fc x ∆-Phase
CMOS-ECL 10
TRANSLATORS
STEL1177
NCO
10
CMOS-ECL 10
TRANSLATORS
FMSUB
FMLD
CLOCK
ECL/CMOS LEVEL SHIFTER
VREF
STEL-1377Q/S
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2
SIN
10-BIT
DAC
OUT
COS
10-BIT
DAC
OUT
(STEL1377Q
ONLY)
PIN CONFIGURATION
Package: 63-pin DIP
63
62
61
60
59
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
0.4" max.
0.2" max.
58
57
Pin diameter: 0.018" ± .002"
56
55
54
53
52
51
50
49
48
47
46
45
0.1" ± .005"
C omp onent area, unencap sulated
3.75" ± .01"
44
43
42
41
40
39
38
37
36
35
34
33
32
1.5" ± .01"
1.6" ± .01"
PIN CONNECTIONS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CLOCK
VEE
RATE0
RATE1
FMLD
FMSUB
FMADDR0
FMADDR1
FMOD0
FMOD1
FMOD2
FMOD3
FMOD4
FMOD5
FMOD6
FMOD7
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
FMOD8
FMOD9
FMOD10
FMOD11
FMOD12
FMOD13
FMOD14
FMOD15
SIMLD
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
DATA7
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
3
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DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
ADDR0
ADDR1
ADDR2
ADDR3
FRSEL
FMSYNC
VSS
FRLD
RESET
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
PHLD
WRSTB
PHSEL
VDD
CSEL
VSS
CIN
VDD
DVEE (DAC)
AVEE (DAC)
VSS
OUT (SIN)
VEE
VREF
OUT (COS)
(STEL-1377Q only)
STEL-1377Q/S
CIRCUIT DESCRIPTION
The frequency of the NCO is determined by the
number stored in the ∆-Phase register which is
programmed from the interface bus. The number
stored in the ∆-Phase register is added to the current
contents of the accumulator every clock cycle to
generate a monotonically increasing phase angle. By
modulating this number the frequency of the NCO can
be modulated. The NCO generates digitized sine and
cosine functions by addressing sine and cosine lookup
tables with the phase accumulator. Phase modulation
data is added to the accumulator output before the
lookup tables. Please refer to the STEL-1177 data sheet
for information on programming the NCO.
corresponding to zero phase until new frequency or
modulation (either frequency or phase) data is loaded
with the FRLD, FMLD, or PHLD inputs after the
RESET returns high.
The NCO output is passed through CMOS to ECL level
translators and loaded synchronously into two highspeed 10-bit DACs. The full-scale outputs of the DACs
is determined by the voltage on the VREF input, and
this can be used to amplitude modulate the output
signals.
CSEL
The Chip Select input is used to control the writing of
data into the chip. It is active low. When this input is
high all data writing via the DATA7-0 bus is inhibited.
CLOCK
All synchronous functions performed within the NCO
are referenced to the rising edge of the CLOCK input.
The CLOCK signal should be a square wave or sine
wave at a maximum frequency of 60 MHz. A nonrepetitive CLOCK waveform is permissible as long as
the minimum duration positive or negative pulse on
the waveform is always greater than 5 nanoseconds.
DATA7 through DATA0
The 8-bit DATA7-0 bus is used to program the two 32bit ∆-Phase Registers and the two 12-bit Phase
Modulation Registers. DATA0 is the least significant
bit of the bus. The data programmed into the ∆-Phase
registers in this way determines the carrier frequency
of the NCO.
FUNCTION BLOCK DESCRIPTION
NCO BLOCK
The NCO block is the core of the STEL-1377 DDS. It
consists of a front-end which may be programmed
from the control inputs. The NCO is described fully in
the STEL-1177 data sheet. Please refer to this data sheet
for more detailed information.
ADDR3 through ADDR0
The four address lines ADDR3-0 control the use of the
DATA7-0 bus for writing frequency data to the ∆-Phase
Buffer Registers, and phase data to the Phase Buffer
Registers, as shown in the table:
LEVEL TRANSLATOR BLOCK
The outputs of the NCO block are CMOS level digital
signals. These are translated to ECL levels for
optimum operation of the DAC.
ADDR3 ADDR1 ADDR0 Register Field
CLOCK GENERATION BLOCK
The clock generation block generates the different
clocks required for the NCO and DAC blocks from the
incoming ECL or sinusoidal clock signal.
DAC BLOCK
The DAC block consists of the Sony CX20201A-1
digital to analog converters and the necessary
supporting circuitry.
INPUT SIGNALS
STEL-1377Q/S
0
0
∆-Phase Bits 0 (LSB)–7
0
0
1
∆-Phase Bits 8–15
0
1
0
∆-Phase Bits 16–23
0
1
1
∆-Phase Bits 24–31
1
0
0
Sine Bits 0(LSB)–3*
1
0
1
Sine Bits 4-11*
1
1
0
Cosine Bits 0(LSB)–3*
1
1
1
Cosine Bits 4-11*
ADDR3 ADDR2
RESET
The RESET input is asynchronous and active low, and
clears all the registers in the device. When RESET goes
low, all registers are cleared within 20 nsecs, and
normal operation will resume after this signal returns
high. The outputs will go to the zero level during the
reset, and thereafter will remain at the value
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0
Register Selected
0
0
∆-Phase Buffer Register 'A'
0
1
∆-Phase Buffer Register 'B'
1
X
Phase Buffer Registers
Note: The Phase Buffer Registers are 12-bit registers.
When the least significant bytes of these registers are
selected (ADDR3-0 =1XX0), DATA7-4 is written into
4
Bits 3–0 of the registers. In all cases, it is not necessary
to reload unchanged bytes, and the byte loading
sequence may be random.
Control Block must be valid during the clock cycle
following the falling edge of PHLD. The data is then
transferred during the subsequent cycle. The 12-bit
phase data is added to the 12 most significant bits of the
accumulator output, so that the MSB of the phase data
represents a 180° phase change. The source of this data
will be determined by the state of PHSEL. The phase
of the NCO output will change 12 clock cycles after the
PHLD command, due to pipelining delays.
WRSTB
The Write Strobe input is used to latch the data on the
DATA7-0 bus into the device. On the rising edge of the
WRSTB input, the information on the 8-bit data bus is
transferred to the buffer register selected by the
ADDR3-0 bus.
FMOD15 through FMOD0
The Frequency Modulation bus is a 16-bit bus on
which the FM data is loaded into the STEL-1177. The
data should be a 16-bit unsigned number.
FRSEL
The Frequency Register Select line is used to control
the mux which selects the ∆-Phase Buffer Register in
use. When this signal is high ∆-Phase Buffer Register
'A' is selected as the source for the ∆-Phase ALU, and
the frequency corresponding to the data stored in this
register will be generated by the NCO after the next
falling edge on the FRLD input. When this line is low,
∆-Phase Buffer Register 'B' is selected as the source.
FMSUB
The FM Subtract input controls the Add/Subtract
operation of the ∆-Phase ALU. When it is high the FM
data on the FMOD15-0 bus will be subtracted from the
carrier frequency, and when it is low the FM data will
be added to the carrier frequency. In this way the FM
data can be treated as a 17-bit signed-magnitude
number, where the FMSUB signal is the sign bit.
FRLD
The Frequency Load input is used to control the
transfer of the data from the ∆-Phase Buffer Registers
to the ∆-Phase ALU. The data at the output of the Mux
Block must be valid during the clock cycle following
the falling edge of FRLD. The data is then transferred
during the subsequent cycle. The frequency of the
NCO output will change 19 clock cycles after the FRLD
command due to pipelining delays.
FMADDR1 through FMADDR0
The two inputs FMADDR1-0 set the deviation of the
frequency modulation by controlling the significance
of the FM data in relation to the carrier frequency data.
The FM data word will be multiplied by 20, 24, 28, or 212
according to the state of FMADDR 1-0 , and the
consequent resolution and maximum values of the
deviation are shown in the table below. The deviations
and resolutions shown are for a clock frequency of 60
MHz.
PHSEL
The Phase Source Select input selects the sources of
data for the Phase ALUs. When it is high the sources
are the Sine and Cosine Phase Buffer Registers. They
are loaded from the DATA7-0 bus by setting address
line ADDR3 high, as shown in the tables. When
PHSEL is low, the sources for the phase modulation
data are the DATA7-0 and ADDR3-0 inputs, and the
data will be loaded independently of the states of
WRSTB and CSEL. The data on these 12 lines is
presented directly as a parallel 12-bit word to both
Phase ALUs, allowing high-speed phase modulation.
The 12-bit value is latched into the Phase ALUs by
means of the PHLD input. The data on the ADDR3-0
lines is mapped onto Phase Bits 3 to 0 and the data on
the DATA7-0 lines are mapped onto Phase Bits 11 to 4
in this case. When using the parallel phase load mode
CSEL and/or WRSTB should remain high to ensure
that the phase data is not written into the phase and
frequency buffer registers of the STEL-1377.
FMFM- Mult. factor Maximum
ADDR1 ADDR0 of FM data deviation
0
0
1
1
0
20
1
2
4
± 14.6 KHz 0.22 Hz
2
8
± 234 KHz
2
12
± 3.75 MHz 57 Hz
0
1
14 mHz
3.6 Hz
FMLD
The FM Load input controls the writing of the
frequency modulation data on the FMOD15-0 bus and
the FMSUB input into the device. When RATE1-0 = 00
the data at the output of the Frequency Modulation
Control Block must be valid during the clock cycle
following the falling edge of FMLD. The data is then
transferred during the subsequent cycle. When
RATE1-0 = 01, 10 or 11 are selected the FM data will be
loaded automatically without the use of the FMLD
input. Note that FMLD must be held low during
automatic operation, otherwise the loading will be
inhibited.
PHLD
The Phase Load input is used to control the latching of
the Phase Modulation data into the Phase ALUs. The
12-bit data at the output of the Phase Modulation
5
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± 915 Hz
Resolution
STEL-1377Q/S
SIMLD
The Simultaneous Load input allows the carrier
frequency data from the Mux Block and the FM data to
be updated simultaneously. When SIMLD is low,
only the FM data will be updated after a falling edge on
FMLD. When this input is high, both the FM data and
carrier frequency data will be updated
simultaneously. When SIMLD is low at least four
clock cycles are required between falling edges of
FMLD and FRLD to ensure glitch-free changes in the
outputs.
on the state of the RATE1-0 inputs. In the automatic
modulation modes (RATE1-0 ≠ 00) the data on the
FMOD15-0 bus will be written into the FM Buffer
Register on the rising edge of the clock following the
falling edge of FMSYNC. This signal can be used to
synchronize the updating of the FM data externally.
APPLICATIONS INFORMATION
Since the STEL-1377 combines high-speed digital and
analog circuits, care must be taken to minimize the
effects of noise from the digital circuit on the analog
output. The following precautions will help in this
area:
RATE1-0
The RATE1-0 signals control the rate at which the FM
data on the FMOD15-0 bus is added to or subtracted
from the carrier frequency, as shown in the table
below:
RATE1 RATE0
1.
Use ground and power planes on the printed
circuit board. Separate analog and digital ground
planes will also help.
2.
Decouple the DVEE (DAC) and AVEE (DAC) line
from the VEE supply with 0.3 to 1 µH inductors.
3.
Decouple all the power supply pins and the VREF
pin to the appropriate ground plane with 1000 pF
and 0.1 µF ceramic capacitors mounted as closely
as possible to the pins.
Modulation Update Rate
0
0
Manual, with FMLD signal
0
1
Every 4th clock cycle
1
0
Every 8th clock cycle
1
1
Every 16th clock cycle
CIN
The Carry Input is an arithmetic carry to the least
significant bit of the Accumulator. Normal operation
of the NCO requires that CIN be set at a logic 0. When
CIN is set at a logic 1 the effective value of the ∆-Phase
register is increased by one. This allows the resolution
of the accumulator to be expanded for higher
frequency resolution.
The clock input can be either a sine wave or a square
wave, the input buffer will square up a sinusoidal
input. The input is capacitively coupled internally. An
ECL level signal or a sine wave at about –5 to +5 dBm
(50 Ω) is recommended. The bias circuit shown can be
used to generate a stable VREF. If high stability, which
translates directly into output level stability, is not a
requirement a much simpler circuit can be realized by
replacing the 2.7KΩ and 2.2KΩ resistors and the
reference diode with a single 8.2KΩ resistor from
VREF to the analog ground. The output level can be
varied by adjusting the bias voltage with the 2KΩ pot
in either case.
OUTPUT SIGNALS
OUT (SIN) AND OUT (COS)
The signals appearing on the OUT pins are the analog
outputs of the DACs. They are stepped sinewaves,
where the number of steps in each cycle of the output
is equal to the ratio of the clock frequency to the output
frequency. When this number is not an integer the
steps will not repeat from one cycle to the next, but the
fundamental component of the output signal will
always be a sinewave at the desired frequency. There
will be a DC offset on the output signal. The outputs
can be capacitively coupled if operation down to very
low frequencies is not required, otherwise offset
compensation should be provided externally.
Ana. GND
59
2.7 K
2.2 K
V SS
+5 V
62
2.5 V
2K
FMSYNC
The FM Sync output indicates the instant in time when
the FM data on the FMOD bus is written into the
device. The FMSYNC output is normally high and
goes low for one clock cycle at a frequency depending
–5.2 V
(Ana.)
58
–5.2 V (Dig.)
2, 61, 57
VREF
V DD
52, 56
STEL-1377
V SS
AV EE
46, 54
Dig.
GND
V EE , DV EE
Recommended bias circuit for VREF
STEL-1377Q/S
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6
ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS
Warning: Stresses greater than those shown below may cause permanent damage to the
device. Exposure of the device to these conditions for extended periods may also affect device
reliability.
Symbol
Parameter
Range
Units
Tstg
Storage Temperature
–65 to +150
°C
Ta
Operating Temperature
–40 to +85
°C
VDDmax
Max. voltage between VCC and VSS
+7 to –0.7
volts
VEEmax
Max. voltage between VEE and VSS
–7 to +0.7
volts
VI/O(max)
Max. voltage on any input pin
VDD+0.7
volts
VI/O(min)
Min. voltage on any input pin
VSS–0.7
volts
RECOMMENDED OPERATING CONDITIONS (The VSS pins should be connected to ground)
Symbol
VDD
VEE
Ta
Parameter
Range
Units
+5 ± 10%
–5.2 ± 10%
0 to +70
Supply Voltage, +5 volts
Supply Voltage, –5.2 volts
Operating Temperature (Ambient)
volts
volts
°C
D.C. CHARACTERISTICS (Operating Conditions: VDD = 5.0 V ±5%, VEE = –5.2 V ±5%, Ta = 25°C)
Symbol
Parameter
Min. Typ. Max. Units
Conditions
IDD
Supply Current, +5 volts
700
mA
@ 60 MHz clock (/Q)
IEE
Supply Current, –5.2 volts
950
mA
@ 60 MHz clock (/Q)
VIH(min)
Min. High Level Input Voltage
volts
Guaranteed Logic '1'
VIL(max)
Max. Low Level Input Voltage
0.8
volts
Guaranteed Logic '0'
IIH(max)
Max. High Level Input Current
10
µA
VIN = +5.0 volts
IIL(max)
Max. Low Level Input Current
–10
µA
VIN = 0 volts
VCLK
Clock Input Voltage
volts
peak to peak
2.0
0.4
1.0
OUTPUT CHARACTERISTICS
Symbol
Parameter
Min. Typ. Max. Units
–5
Conditions
PO(max)
Max. Output Power
dBm
TCFS
Full-scale output Temp. coefficient
0.06
GE
Output glitch energy
15
Err(i)
Output integral linearity
VSPUR
Spurious signal level
–65
VSPUR
Spurious signal level
–62
dBc
.25 x fCLK < fOUT < .33 x fCLK
VSPUR
Spurious signal level
–60
dBc
.33 x fCLK < fOUT < .45 x fCLK
–0.1
%
50 Ω load
pV.sec.
+0.1
7
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0.12
%
of full-scale output
dBc fOUT < .25 x fCLK
STEL-1377Q/S
DDS FREQUENCY CHANGE SEQUENCE
CSEL
ADDR 3-0
DON'T CARE
DON'T CARE
tSU
WRSTB
t HD
tW
DATA 7-0
DON'T CARE
DON'T CARE
20 CLOCK
EDGES
CLOCK
tCH
1
t CL
2
3
19
20
t SU
FRLD
tW
FSYNC
OLD FREQUENCY
NEW FREQUENCY
OUT
A.C. CHARACTERISTICS (Operating Conditions: VDD=5.0 V ±5%, VEE=–5.2 V ±5%, Ta=25°C)
Symbol
Parameter
Min. Typ. Max. Units
tRS
Reset Pulse Width
20
nsec.
tSU
DATA, ADDR or CSEL
5
nsec.
5
nsec.
Conditions
to WRSTB or PHLD Setup
and FRLD, PHLD, FMLD
or FMOD to CLOCK Setup
tHD
DATA, ADDR or CSEL
to WRSTB or PHLD Setup
and FRLD, PHLD, FMLD
or FMOD to CLOCK Hold
tCH
CLOCK high
5
nsec.
fCLK= 60 MHz
tCL
CLOCK low
5
nsec.
fCLK= 60 MHz
tW
WRSTB, FRLD, PHLD
5
nsec.
or FMLD pulse width
STEL-1377Q/S
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8
DDS PHASE CHANGE SEQUENCE
1. PHSEL = 0.DIRECT LOADING
13 CLOCK
EDGES
CLOCK
tSU 1
DATA
7-0
ADDR
3-0
2
3
12 13
DON'T CARE
DON'T CARE
tSU tHD
PHLD
tW
OLD PHASE
NEW PHASE
OUT
2. PHSEL = 1.BUS LOADING
CSEL
ADDR 3-0
DON'T CARE
DON'T CARE
t HD
t SU
tW
WRSTB
DATA 7-0
DON'T CARE
DON'T CARE
13 CLOCK
EDGES
CLOCK
t SU 1
2
3
12 13
PHLD
tW
OLD PHASE
NEW PHASE
OUT
9
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STEL-1377Q/S
NCO FREQUENCY MODULATION SEQUENCE
1. RATE = 00.MANUAL LOADING
20 CLOCK EDGES
CLOCK
tHD
tSU
FMOD
DON'T CARE
15-0
VALID
DON'T CARE
tSU
FMLD
tW
FMSYNC
tCD
SYNC
OLD FREQUENCY
NEW FREQUENCY
OUT
2. RATE ≠ 00.AUTOMATIC LOADING
(RATE = 01 shown)
4 CLOCK CYCLES
CLOCK
FMOD 15-0
DON'T CARE
VALID
DON'T CARE
tHD
t SU
FMSYNC
SINE 11-0
COS 11-0
FMLD
STEL-1377Q/S
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10
VALID
DON'T CARE
11
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STEL-1377Q/S
SPECTRAL PURITY
A spectral plot of the NCO output after conversion
with a DAC (Sony CX20202A-1) is shown below. In
this case, the clock frequency is 60 MHz and the output
frequency is programmed to 6.789 MHz. The
maximum non-harmonic spur level observed over the
output frequency range shown in this case is –70 dBc.
The spur levels are limited by the dynamic linearity of
the DAC. It is important to remember that when the
output frequency exceeds 25% of the clock frequency,
the second harmonic frequency will be higher than the
Nyquist frequency, 50% of the clock frequency. When
this happens, the image of the harmonic at the
frequency fc– 2fo, which is not harmonically related to
the output signal, will become intrusive since its
frequency falls as the output frequency rises,
eventually crossing the fundamental output when its
frequency crosses through f c /3. The same
phenomenon occurs with the third harmonic when
the frequency crosses through fc/4.
When an NCO is used with a digital to analog
converter (DAC) to generate an analog waveform the
spectral purity of the synthesized waveform is a
function of many variables, including the phase and
amplitude quantization, the ratio of the clock
frequency to output frequency, and the dynamic
characteristics of the DAC. The sine signals generated
by the STEL-1177 have 12 bits of amplitude resolution
and 13 bits of phase resolution which results in
spurious levels which are theoretically at least 75 dB
down. The highest output frequency the NCO can
generate is half the clock frequency (fc/2), and the
spurious components at frequencies greater than fc/2
can be removed by filtering. As the output frequency
fo of the NCO approaches fc/2, the "image" spur at
f c – f o (created by the sampling process) also
approaches fc/2 from above. If the programmed
output frequency is very close to fc/2 it will be virtually
impossible to remove this image spur by filtering. For
this reason, the maximum practical output frequency
of the NCO should be limited to about 40% of the clock
frequency.
TYPICAL SPECTRUM
Center Frequency:
10.0 MHz
Frequency Span:
20.0 MHz
Reference Level:
–5 dBm
Resolution Bandwidth: 1 KHz
Scale:
Log, 10 dB/div
Output frequency:
6.789 MHz
Clock frequency:
60 MHz
STEL-1377Q/S
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12
Information in this document is provided in connection with
Intel® products. No license, express or implied, by estoppel
or otherwise, to any intellectual property rights is granted by
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