STEL-1173 Data Sheet STEL-1173 (50 MHz) 48-Bit Resolution CMOS Numerically Controlled Oscillator R Powered by ICminer.com Electronic-Library Service CopyRight 2003 FEATURES FUNCTIONAL DESCRIPTION ■ ■ ■ ■ The STEL-1173 Numerically Controlled Oscillator (NCO) uses digital techniques to provide a costeffective solution for low noise signal sources. The NCO device combines low power 1.5µ CMOS technology with a unique architectural design resulting in a power efficient, high-speed sinusoidal waveform generator able to achieve fine tuning resolution and exceptional spectral purity with clock frequencies up to 50 MHz. ■ ■ ■ ■ ■ 48-BIT FREQUENCY RESOLUTION 50 MHz CLOCK FREQUENCY (0 TO 70°C) SINE OR COSINE OUTPUT AVAILABLE 12-BIT AMPLITUDE RESOLUTION AND 13-BIT PHASE RESOLUTION GIVES HIGH SPECTRAL PURITY, ALL SPURS <–75 dBc (AT DIGITAL OUTPUT) MICROPROCESSOR BUS COMPATIBLE CONTROL INPUTS CASCADABLE ACCUMULATOR FOR HIGHER FREQUENCY RESOLUTION 2's COMPLEMENT OR OFFSET BINARY OUTPUT CODES LOW POWER CMOS MILITARY AND COMMERCIAL TEMPERATURE RANGES AVAILABLE The NCO generates digital sine or cosine functions of very precise frequency to be used directly in digital signal processing applications or, in conjunction with a D/A converter, in analog frequency generation applications. The NCO is designed to interface with and be controlled from an 8-bit microprocessor bus. The NCO maintains a record of phase which is accurate to 48 bits. At each clock cycle, the number stored in the 48 bit ∆-Phase register is added to the previous value of the phase accumulator. The number in the phase accumulator represents the current phase of the synthesized sine and cosine functions. The number in the ∆-Phase register represents the change of phase for each cycle of the clock. This number is directly related to the output frequency by the following: APPLICATIONS ■ ■ ■ ■ ■ FREQUENCY SYNTHESIZERS SINGLE SIDEBAND CONVERTERS BASEBAND RECEIVERS DIGITAL SIGNAL PROCESSORS HIGH SPEED HOPPED FREQUENCY SOURCES fo= fc x ∆-Phase 248 where: fo is the frequency of the output signal and: fc is the clock frequency. BLOCK DIAGRAM LDSTB 48 DATA 7-0 8 WRN ADDR. SELECT LOGIC –PHASE BUFFER REGISTERS 48 –PHASE REGISTER 3 CSN ADDR 6 2-0 RESET CLOCK STEL-1173 Powered by ICminer.com Electronic-Library Service CopyRight 2003 2 48 48–BIT PHASE ACCUMULATOR 13 SINE LOOKUP TABLE 12 OUT 11-0 PIN CONFIGURATION -- STEL-1173/CL VSS CARRY IN DATA 0 DATA 1 DATA 2 DATA 3 DATA 4 DATA 4 DATA 6 DATA 7 I.C. WRN I.C. I.C. I.C. SIN TWOSCOMP LDSTB CARRY OUT CSN N.C. I.C. RESET VDD VDD ADDR 2 ADDR 1 ADDR 0 CLOCK I.C. N.C. N.C. I.C. SYNC VSS OUT 11 OUT 10 OUT 9 OUT 8 OUT 7 OUT 6 OUT 5 OUT 4 OUT 3 OUT 2 OUT 1 OUT 0 N.C. 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Seating plane 0.15" typ. 0.2" max. 0.13" typ. 0.1" ± 0.01" Note: tolerance not cumulative 0.55" typ. 2.46 max. 0.6" (at seating plane) 48 pin plastic Package: 40 DIP or ceramic DIP Thermal coefficient, θjc = 15°/W Note: pin spacing for Ceramic DIP is the same PIN CONFIGURATION -- STEL-1173/CM Package: 44-pin PLCC Thermal coefficient, θja = 60° C/W 0.18" max. 4 4 4 4 4 6 5 4 3 2 1 4 3 2 1 0 7 8 9 10 11 12 13 14 15 16 17 39 38 37 36 35 0.690" 34 33 ± .005" 32 31 30 29 0.017" ± 0.004" (2) 0.05" nom. (1) 0.02" min. 1 1 2 2 2 2 2 2 2 2 2 8 9 0 1 2 3 4 5 6 7 8 0.653" ± 0.010" PIN CONNECTIONS 1 2 3 4 5 6 7 8 VSS CARRY IN DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 9 10 11 12 13 14 15 16 17 DATA6 DATA7 I.C. WRN I.C. I.C. I.C. SINE TWOSCOMP 18 19 20 21 22 23 24 25 26 LDSTB CARRY OUT CSN I.C. RESET VDD OUT0 (LSB) OUT1 OUT2 27 28 29 30 31 32 33 34 35 OUT3 OUT4 OUT5 OUT6 OUT7 OUT8 OUT9 OUT10 OUT11 (MSB) 36 VSS 37 SYNC 38 I.C. 39 I.C. 40 CLOCK 41 ADDR0 42 ADDR1 43 ADDR2 44 VDD Notes: 1. Tolerances on pin spacing are not cumulative. 2. I.C. denotes Internal Connection. These pins must be left unconnected. Do not use for vias. 3. N.C. denotes No Connection. These pins may be used for vias. 3 Powered by ICminer.com Electronic-Library Service CopyRight 2003 STEL-1173 CIRCUIT DESCRIPTION FUNCTION BLOCK DESCRIPTION The sine and cosine functions are generated from the 13 most significant bits of the phase accumulator. The frequency of the NCO is determined by the number stored in the ∆-Phase register which may be programmed by an eight-bit microprocessor. ADDRESS SELECT LOGIC BLOCK This block controls the writing of data into the device via the DATA7-0 inputs. The data is written into the device on the rising edge of the WRN input, and the register into which the data is written is selected by the ADDR2-0 inputs. The writing of data is also controlled with the CSN input; this input must be low to enable writing. The frequency programming capability of the NCO is analogous to sampling a sine wave where the sampling function is the clock. If the output frequency is very low with respect to the clock (< fc /8096), then the NCO output will sequence through each of the 8096 states of the sine function. As the output frequency is increased with respect to the clock the sine function will appear to be more discontinuous since there will be fewer samples in each cycle. At the Nyquist limit, when the output frequency is exactly half the clock, the output waveform reduces to a square wave. The practical upper limit of the NCO output frequency is about 40% of the clock frequency because spurious components created by sampling, which are at a frequency greater than half the clock frequency, become difficult to remove by filtering. BUFFER REGISTER BLOCK The Buffer Register is used to temporarily store the ∆Phase data written into the device. This allows the data to be written asynchronously as six bytes per 48-bit ∆-Phase word. The data is transferred from this register into the ∆-Phase Register after a falling edge on the LDSTB input. ∆-PHASE REGISTER BLOCK This block controls the updating of the ∆-Phase word used in the Accumulator. The frequency data from the Buffer Register Block is loaded into this block after a falling edge on the LDSTB input. The SYNC output, which indicates the instant of frequency change at the output at the end of the pipeline delay, is generated in this block. The phase noise of the NCO output signal may be determined by knowing the phase noise of the clock signal input, and the ratio of the output frequency to the clock frequency. This ratio squared times the phase noise power of the clock specified in a given bandwidth is the phase noise power that may be expected in that same bandwidth relative to the output frequency. PHASE ACCUMULATOR BLOCK This block forms the core of the NCO function. It is a high-speed, pipelined, 48-bit parallel accumulator, generating a new sum in every clock cycle. A carry input (CARRY IN) allows the resolution of the accumulator to be expanded by means of an auxiliary NCO or phase accumulator. The overflow signal is discarded (and is available at the CARRY OUT pin), since the required output is the modulo (248) sum only. This represents the modulo (2π) phase angle. The NCO achieves its high operating frequency by making extensive use of pipelining in its architecture. The pipeline delays within the NCO represent 20 clock cycles. This effectively limits the minimum possible frequency switching period of the NCO. After new frequency data is entered, the load command is given. After the 20 cycle pipeline delay, the output will instantaneously switch frequency while maintaining phase coherence. After this, the next new frequency may be entered. If a 50 MHz clock were utilized, the NCO could be continuously switched between programmed frequencies with a minimum practical average switching time of about 0.4 µsec. STEL-1173 Powered by ICminer.com Electronic-Library Service CopyRight 2003 SINE LOOKUP TABLE BLOCK This block is the sine memory. The 13 most significant bits from the Phase Accumulator are used to address this memory to generate the 12-bit OUT11-0 outputs. INPUT SIGNALS RESET The RESET input is asynchronous and active low. When RESET goes low, all registers including the 48bit input buffer are cleared within 30 nsecs. The data on the OUT11-0 bus will then be invalid for 6 clock cycles, and thereafter will remain at the value corresponding to zero phase, i.e., 2049 (801H), until a new frequency is loaded into the ∆-Phase register with a LDSTB command after the RESET returns to a logic one. 4 CLOCK All synchronous functions performed within the NCO are referenced to the rising edge of the CLOCK input. The CLOCK signal should be nominally a square wave at a maximum frequency of 50 MHz. A nonrepetitive CLOCK waveform is permissible as long as the minimum duration positive or negative pulse on the waveform is always greater than 8 nanoseconds. At each positive transition of the CLOCK signal, the number stored in the ∆-Phase register is added to the contents of the phase accumulator and the result is placed in the phase accumulator. CARRY IN Normal operation of the NCO requires that CARRY IN be set at a logic 0. When CARRY IN is a logic 1, the effective value of the ∆-Phase register is increased by one. Two NCOs can be cascaded together to obtain 96 bits of frequency resolution by using the CARRY OUT of the lower order NCO and the CARRY IN of the higher order NCO. TWOSCOMP When the TWOSCOMP input is set high, the data appearing on the OUT11-0 bus is presented in two's complement code, and when it is set low, the data is presented in offset binary code. The limits of the data values in both codes is shown below: WRN On the rising edge of the WRN input, the information on the 8-bit data bus is transferred to the buffer register selected by the ADDR2-0 bus. Code → SINE When the SINE input signal is set to a logic low level, the output signal appearing on the OUT11-0 bus is the cosine of the 48-bit accumulator’s 13 most significant bits (bits 47-35, with 47 being the MSB). Normally set high, this signal allows the NCO to generate either sine or cosine signals. By using two devices, one set in the sine mode and the other set in the cosine mode, quadrature outputs may be obtained. The quadrature phase relationship of the two outputs will be maintained at all times provided the two devices are reset simultaneously and operate from a common clock signal. ADDR2 ADDR1 ADDR0 ∆-Phase Register Field 0 1 0 1 0 1 – 2047 (801H) +2047 (7FFH) 0 (000H) Both number formats produce sine or cosine waves which are symmetrical about the phase quadrant axis and the mean-value magnitude axis. ADDR2 through ADDR0 The three address lines ADDR2-0 control the use of the DATA7-0 bus for writing frequency data to the ∆-Phase buffer registers as shown in the table below: 0 0 1 1 0 0 2's Complement Minimum value +1 (001H) Maximum value +4095 (FFFH) Mean value +2048 (800H) CSN The CSN (Chip Select) input is active low and can be used to control the writing of data into the chip. When this input is high all data writing via the DATA7-0 bus is inhibited. 0 0 0 0 1 1 Offset binary Bits0 (LSB) –7 Bits 8–15 Bits 16–23 Bits 24–31 Bits 32–39 Bits 40–47 (MSB) To write to all 48 bits of the phase write registers, the DATA7-0 bus must be used 6 times. Note that it is not necessary to reload unchanged bytes, and that the byte loading sequence may be random. A high level on the SINE input sets the output to be the sine of the 48-bit accumulator’s 13 most significant bits. The value of the output for a given phase value follows the relationship: DATA7 through DATA0 The eight bit DATA7-0 bus is used to program the 48bit ∆-Phase register. DATA0 is the least significant bit of the bus. 2’s comp = 2047 x sin (360 x phase) offset bin = 2047 x sin (360 x phase) +2048 The result is accurate to within 1 LSB. LDSTB On the rising edge of the clock following the falling edge of the LDSTB input, the information in the 48-bit buffer register is transferred to the ∆-Phase register. The frequency of the NCO output will change 20 clock cycles after the LDSTB command due to pipelining delays. When this input is set low the output will be the cosine of the 48-bit accumulator’s 13 most significant bits. The value of the output for a given phase value follows the relationship: 2’s comp = 2047 x cos (360 x phase) offset bin = 2047 x cos (360 x phase) +2048 again, accurate to within 1 LSB. 5 Powered by ICminer.com Electronic-Library Service CopyRight 2003 STEL-1173 OUTPUT SIGNALS OUT11-0 The signal appearing on the OUT11-0 bus is derived from the 13 most significant bits of the phase accumulator. The 12-bit sine or cosine function is presented in offset binary or two's complement format, depending on the status of the TWOSCOMP input. When the phase accumulator is zero, e.g., after a reset, the decimal value of the output is 2049 in offset binary and 1 in two's complement. The nominal phase (in degrees) of the sine wave output may be determined at any point by multiplying the decimal equivalent of the 13 most significant bits of the phase accumulator by (360/8192) and then adding (360/16384). OUT11 is the MSB, and OUT0 is the LSB. CARRY OUT Each time the contents of the phase accumulator exceeds the maximum value that can be represented by a 48 bit number the CARRY OUT signal goes high for one clock cycle. SYNC The normally high SYNC output goes low for one clock cycle, 20 clock cycles after a LDSTB command, to indicate the end of the pipeline delay and the start of the new steady state condition. ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS Warning: Stresses greater than those shown below may cause permanent damage to the device. Exposure of the device to these conditions for extended periods may also affect device reliability. All voltages are referenced to VSS. Symbol Parameter Range Units °C Tstg Storage Temperature –40 to +125 (Plastic package) VDDmax Supply voltage on VDD –0.3 to + 7 volts VI(max) Input voltage –0.3 to VDD + 0.3 volts Ii DC input current ± 10 mA RECOMMENDED OPERATING CONDITIONS Symbol VDD Ta Parameter Range Units Supply Voltage +5 ± 5% Volts (Commercial) Operating Temperature (Ambient) 0 to +70 °C (Commercial) STEL-1173 Powered by ICminer.com Electronic-Library Service CopyRight 2003 6 D.C. CHARACTERISTICS (Operating Conditions: VDD= 5.0 V ±5%, VSS = 0 V, Ta= 0° to 70° C, Commercial Symbol Parameter Min. Typ. Max. Units Conditions mA Static, no clock IDD(Q) Supply Current, Quiescent 1.0 IDD Supply Current, Operational 3.0 mA/MHz VIH(min) High Level Input Voltage Standard Operating Conditions 2.0 volts Logic '1' Extended Operating Conditions 2.25 volts Logic '1' 0.8 volts Logic '0' 110 µA CIN and CSEL, VIN = VDD VIL(max) Low Level Input Voltage IIH(min) High Level Input Current IIH(min) High Level Input Current 10 µA All other inputs, VIN = VDD IIL(max) Low Level Input Current –10 µA CIN and CSEL, VIN = VSS IIL(max) Low Level Input Current –15 –45 –130 µA All other inputs, VIN = VSS VOH(min) High Level Output Voltage 2.4 4.5 volts IO = –4.0 mA VOL(max) Low Level Output Voltage IOS Output Short Circuit Current CIN COUT 10 35 0.2 0.4 volts IO = +4.0 mA 20 65 130 mA VOUT = VDD, VDD = max –10 –45 –130 mA VOUT = VSS, VDD = max pF pF All inputs All outputs Input Capacitance Output Capacitance 2 4 A.C. CHARACTERISTICS (Operating Conditions: VDD= 5.0 V ±5%, VSS = 0 V, Ta= 0° to 70° C, Commercial STEL-1173 (Commercial) Symbol Parameter Min. Max Units tRS RESET pulse width 30 nsec. tSR RESET to CLOCK Setup 10 nsec. tSU DATA, ADDR or CSEL 18 nsec. 12 nsec. Conditions to WRN Setup, and LDSTB to CLOCK Setup tHD DATA, ADDR or CSEL to WRN Hold, and LDSTB to CLOCK Hold tCH CLOCK high 8 nsec. fCLK = max. tCL CLOCK low 8 nsec. fCLK = max. tW WRN or FRLD pulse width 20 nsec. tCD CLOCK to output delay 5 7 Powered by ICminer.com Electronic-Library Service CopyRight 2003 10 nsec. Load = 15 pF STEL-1173 NCO RESET SEQUENCE tRS RESET 5 CLOCK EDGES CLOCK 1 OUT 2 3 NOT VALID 11-0 4 5 801H NCO FREQUENCY CHANGE CSN ADDR 2-0 DON'T CARE DON'T CARE tSU WRN tHD DATA 7-0 tWR DON'T CARE DON'T CARE 20 CLOCK EDGES CLOCK tSU t CH t CL LDSTB t LS SYNC t CD OLD FREQUENCY OUT 11-0 STEL-1173 Powered by ICminer.com Electronic-Library Service CopyRight 2003 8 NEW FREQUENCY TYPICAL APPLICATION HIGH PURITY, HIGH RESOLUTION SYNTHESIZER DATA ADDR 0-2 8 3 WR STEL1173 NCO LDSTB RESET SINE D/A 12 CLK BPF 6-14 MHz ⊗ BPF 66-74 MHz 66-74 MHz CLK 60 MHz OSCILLATOR 50 MHz CLOCK If the STEL-1173 is combined with a suitable high-speed DAC, signals with spectral purity of better than –65 dBc can be generated up to 10 MHz. In this way a signal can be generated in the 70 MHz band for use in a baseband downconverter tracking oscillator. The very high frequency resolution of the STEL1173 allows the incoming signal to be tracked very closely and with minimal "hunting", resulting in low phase noise. The phase continuous frequency switching characteristics of the STEL-1173 also make it suitable for use in Frequency Hopping Spread Spectrum applications. SPECTRAL PURITY In many applications the NCO is used with a Digital to Analog converter (DAC) to generate an analog waveform which approximates an ideal sinewave. The spectral purity of this synthesized waveform is a function of many variables including the phase and amplitude quantization, the ratio of the clock frequency to output frequency, and the dynamic characteristics of the DAC. about –75 dBc. The highest output frequency the NCO can generate is half the clock frequency (fc /2), and the spurious components at frequencies greater than fc/2 can be removed by filtering. As the output frequency fo of the NCO approaches fc /2, the "image" spur at fc–fo (created by the sampling process) also approaches fc/2 from above. If the programmed output frequency is very close to fc/2 it will be virtually impossible to remove this image spur by filtering. For this reason, the maximum practical output frequency of the NCO should be limited to about 40% of the clock frequency. The signals generated by the STEL-1173 have 12 bits of amplitude resolution and 13 bits of phase resolution which results in spurious levels which are theoretically 9 Powered by ICminer.com Electronic-Library Service CopyRight 2003 STEL-1173 A spectral plot of the NCO output after conversion with a DAC (Sony CX20202A-1) is shown below. In this case, the clock frequency is 50 MHz and the output frequency is programmed to 6.789 MHz. This 10-bit DAC gives better performance than any of the currently available 12-bit DACs at clock frequencies higher than 10 or 20 MHz. The maximum nonharmonic spur level observed over the output frequency range shown in this case is –74 dBc. The spur levels are limited by the dynamic linearity of the DAC. It is important to remember that when the output frequency exceeds 25% of the clock frequency, the second harmonic frequency will be higher than the Nyquist frequency, 50% of the clock frequency. When this happens, the image of the harmonic at the frequency fc– 2fo, which is not harmonically related to the output signal, will become intrusive since its frequency falls as the output frequency rises, eventually crossing the fundamental output when its frequency crosses through fc/3. It would be necessary to select a DAC with better dynamic linearity to improve the harmonic spur levels. (The dynamic linearity of a DAC is a function of both its static linearity and its dynamic characteristics, such as settling time and slew rates.) At higher output frequencies the waveform produced by the DAC will have large output changes from sample to sample. For this reason, the settling time of the DAC should be short in comparison to the clock period. As a general rule, the DAC used should have the lowest possible glitch energy as well as the shortest possible settling time. TYPICAL SPECTRUM Center Frequency: 6.7 MHz Frequency Span: 10.0 MHz Reference Level: –5 dBm Resolution Bandwidth: 1 KHz Video Bandwidth: 3 kHz Scale: Log, 10 dB/div Output frequency: 6.789 MHz Clock frequency: 50 MHz STEL-1173 Powered by ICminer.com Electronic-Library Service CopyRight 2003 10 Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intels Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel® products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. For Further Information Call or Write INTEL CORPORATION Cable Network Operation 350 E. Plumeria Drive, San Jose, CA 95134 Customer Service Telephone: (408) 545-9700 Technical Support Telephone: (408) 545-9799 FAX: (408) 545-9888 Copyright © Intel Corporation, December 15, 1999. All rights reserved Powered by ICminer.com Electronic-Library Service CopyRight 2003