ETC STEL-1375A+80

STEL-1375A+80
Data Sheet
STEL-1375A+80
80 MHz, 32-Bit Resolution
Modulated Digital Direct
Frequency Synthesizer
R
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FEATURES
APPLICATIONS
■
HIGH MAXIMUM CLOCK FREQUENCY
■
FREQUENCY SYNTHESIZERS
– UP TO 80 MHz OVER FULL
COMMERCIAL TEMPERATURE RANGE
■
FSK AND PSK MODULATORS
■
DIGITAL SIGNAL PROCESSORS
HIGH OUTPUT BANDWIDTH
■
HOPPED FREQUENCY SOURCES
■
– UP TO 35 MHz OUTPUT FREQUENCY
■
HIGH FREQUENCY–RESOLUTION
– 32 BITS, 19 milliHz @ 80 MHz
■
HIGH SPEED FREQUENCY HOPPING
OR MODULATION
– MAXIMUM UPDATE RATE 20 MHz
■
PRECISION PHASE MODULATION
– 12 BITS, 0.09° RESOLUTION CAN BE
USED FOR LINEAR PM OR PULSESHAPED PSK AT UP TO 20 MHz
■
SINE OR COSINE OUTPUT
■
HIGH-SPEED, LOW GLITCH ECL DAC
■
HIGH SPECTRAL PURITY
–60 dBc SPURIOUS TYPICAL
■
MICROPROCESSOR COMPATIBLE
INPUTS
■
2.5" BY 1.3" BY 0.35"
BLOCK DIAGRAM
DATA 7-0
8
ADDR 3-0
4
WRSTB
FRLD
FRSEL
PHLD
PHSEL
STEL-1175
NCO
10
10-BIT
DAC
SIN/COS
RESET
50 Ω
CLOCK
CLOCK BUFFER
STEL-1375A+80
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OUT
2
The STEL-1375A+80 is a complete Digital Direct
Frequency Synthesizer in a single DIL package
measuring only 2.5 x 1.3". The STEL-1375A+80 makes
it possible to use DDS technology in places where
space constraints previously made this impossible.
The STEL-1375A+80 is a printed circuit unit using the
STEL-1175 Modulated Numerically Controlled
Oscillator (MNCO) chip driving a high-speed 10-bit
DAC (AD9721) to generate an analog output signal.
Surface mount technology (SMT) components are used
throughout. The device is guaranteed to operate at
clock frequencies up to 80 MHz over the temperature
range of 0-70°C, giving an output frequency range of 0
to over 35 MHz, with a frequency resolution of 19 milliHz (32 bits). In addition, the device features both
phase and frequency modulation capabilities at
extremely high modulation rates, up to 25% of the
clock frequency. The phase modulation capability
allows either digital (PSK) or linear PM with up to 12
bits of resolution to be implemented. Binary FSK can
be implemented very easily by loading the two
frequencies into the A and B frequency registers, and
any kind of frequency modulation can be performed
by modulating the frequency control word. For more
detailed information on the STEL-1175 MNCO please
refer to the STEL-1175 data sheet. For more information
on the DAC please refer to the AD9721 data sheet. The
output frequency is directly related to the clock
frequency by the following:
fo=
fc x ∆-Phase
232
where: fo is the frequency of the output signal
and:
fc is the clock frequency.
PIN CONFIGURATION
Package: 35-pin DIP
0.4" max.
0.45" ± .005"
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
0.2" max.
Pin diameter: 0.018" ± .002"
0.1" ± .005"
Component area, unencapsulated
2.5" ± .01"
1.2" ± .01"
0.35" ± .005"
1.3" ± .01"
PIN CONNECTIONS
10
1
VSS
11
2
CLOCK
12
3
N.C.
13
4
VSS
14
5
VDD
15
6
VEE**
7
ADDR3
16
17
8
ADDR2
18
9
ADDR1
19
20
21
22
23
24
25
26
27
ADDR0
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
FRSEL
SINE
VSS
FRLD
RESET
PHLD
WRSTB
PHSEL
VDD
28
29
30
31
32
33
34
35
CSEL
VSS
CIN
VDD
DVEE (DAC)
AVEE (DAC)
VSS
OUT
** Pin 6 is not used in the STEL-1375A+80. This pin may be connected to
VEE for pin compatibility with the STEL-1375A (60 MHz version).
3
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STEL-1375A+80
CIRCUIT DESCRIPTION
INPUT SIGNALS
The frequency of the NCO is determined by the number
stored in the ∆-Phase register which is programmed
from the interface bus. The number stored in the
∆-Phase register is added to the current contents of the
accumulator every clock cycle to generate a
monotonically increasing phase angle. The NCO
generates digitized sine and cosine functions by
addressing a sine/cosine lookup table with the phase
accumulator. Phase modulation data is added to the
accumulator output before the lookup table.
The NCO is controlled from a microprocessor based
interface. Bytes of data can be written into the frequency
and phase control registers from the data bus. For
high-speed phase modulation it is also possible to load
the phase modulation data as a parallel 12-bit word.
Please refer to the STEL-1175 data sheet for information
on programming the NCO.
The NCO output is loaded synchronously into a highspeed 10-bit DAC which incorporates CMOS-ECL level
translators and a fixed voltage reference circuit..
RESET
The RESET input is asynchronous and active low.
When RESET goes low, all registers are cleared within
30 nsecs. The signal on the OUT pin will then be
invalid for 7 clock cycles, and thereafter will remain at
the value corresponding to zero phase until a new
frequency or phase is loaded into the ∆-Phase Register
or Phase Register with a FRLD or PHLD command
after the RESET returns high.
CLOCK
All synchronous functions performed within the NCO
are referenced to the rising edge of the CLOCK input.
The CLOCK signal should be nominally a square
wave or sine wave at a maximum frequency of 80
MHz. A non-repetitive CLOCK waveform is
permissible as long as the minimum duration positive
or negative pulses on the waveform are always greater
than 5 nanoseconds.
CSEL
The CSEL (Chip Select) input is active low and can be
used to control the writing of data into the chip. When
this input is high all data writing via the DATA7-0 bus
is inhibited.
FUNCTION BLOCK
DESCRIPTION
DATA7 through DATA0
The eight bit DATA7-0 bus is used to program the 32 bit
∆-Phase registers and the 12-bit Phase register. DATA0
is the least significant bit of the bus.
NCO BLOCK
The NCO block is the core of the STEL-1375A+80 DDS.
It consists of a front-end which may be programmed
from the control inputs. The NCO is described fully in
the STEL-1175 data sheet. Please refer to this data sheet
for more detailed information.
ADDR3 through ADDR0
The four address lines ADDR3-0 control the use of the
DATA7-0 bus for writing frequency data to the ∆-Phase
Buffer Registers and phase data to the Phase
Modulation Registers, as shown in the tables:
CLOCK GENERATION BLOCK
The clock generation block generates the different
clocks required for the NCO and DAC blocks from the
incoming sinusoidal clock signal.
ADDR3 ADDR2
DAC BLOCK
The DAC block consists of the AD9721 digital to analog
converter and the necessary supporting circuitry. The
DAC incorporates CMOS to ECL translation circuits
and a reference generator. The reference level, which
determines the output signal level, is not adjustable.
0
0
1
Register Selected
0
1
X
∆-Phase Register 'A'
∆-Phase Register 'B'
Phase Modulation Register
ADDR3 ADDR1 ADDR0
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
Register Field
Bits 7–0 (LSB)
Bits 15–8
Bits 23–16
Bits 31–24
Bits 3–0(LSB)*
Bits 11-4*
* Notes: The Phase Modulation Register is a 12-bit
register. When the least significant byte of this register
STEL-1375A+80
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CIN
Normal operation of the NCO requires that Carry In be
set at a logic 0. When CIN is a logic 1, the effective
value of the ∆-Phase register is increased by one. Two
NCOs can be cascaded together to obtain 64 bits of
frequency resolution by using the COUT of the lower
order NCO and the CIN of the higher order NCO.
Only one DAC is used in this configuration, it is
connected to the higher significance NCO. If this
facility is used, the STEL-1375A+80 should be used for
the 32 MSBs of the 64-bit frequency control word, and
an STEL-1175 should be used for the 32 LSBs.
is selected (ADDR3-0 =1000), DATA7-4 is written into
Bits 3–0 of the register. In all cases, it is not necessary
to reload unchanged bytes, and the byte loading
sequence can be random.
WRSTB
On the rising edge of the WRSTB input, the information
on the 8-bit data bus is transferred to the buffer register
selected by the ADDR3-0 bus.
FRSEL
When the Frequency Register Select line is high
∆-Phase Register 'A' is selected as the source for the
Phase Accumulator, and the frequency corresponding
to the data stored in this register will be generated by
the NCO after the next FRLD command. When this
line is low, ∆-Phase Register 'B' is selected as the
source.
SINE
When the SINE input signal is set low the output
signal appearing on the OUT pin will be a cosine
function and when it is set high the DDS output will be
a sine function. After a reset the device will always
start at a phase angle of zero, irrespective of the status
of the SINE input. In this way, by using two devices,
one set in the sine mode and the other set in the cosine
mode, quadrature outputs may be obtained. The
quadrature phase relationship of the two outputs will
be maintained at all times provided the two devices are
operated from common RESET, FRLD and CLOCK
signals. The use of phase modulation will, of course,
modify this relationship, unless the devices are also
phase modulated together.
FRLD
On the rising edge of the clock following the falling
edge of the Frequency Load input, the information in
the 32-bit Buffer Register is transferred to the ∆-Phase
Register. The frequency of the DDS output will change
20 clock cycles after the FRLD command due to
pipelining delays.
PHSEL
When the Phase Source Select line is set high the
source for the phase modulation data is the phase
modulation register. It is loaded from the DATA7-0
bus by setting address line ADDR3 high, as shown in
the tables. When this line is set low, the sources for the
phase modulation data are the DATA7-0 bus and the
ADDR3-0 bus, and data will be loaded directly from
these inputs independently of the states of WRSTB
and CSEL. The data on these 12 inputs is presented
directly as a parallel 12-bit word to the phase modulator,
allowing high-speed phase modulation. The data on
the ADDR3-0 lines are mapped onto Phase Bits 3 to 0
and the data on the DATA7-0 lines are mapped onto
Phase Bits 11 to 4 in this case. When using the parallel
phase load mode CSEL and/or WRSTB should remain
high to ensure that the phase data is not written into the
phase and frequency buffer registers of the STEL1375A+80.
OUTPUT SIGNALS
OUT
The signal appearing on the OUT pin is the analog
output of the DAC. It is a stepped sinewave, where the
number of steps in each cycle of the output is equal to
the ratio of the clock frequency to the output frequency.
When this number is not an integer the steps will not
repeat from one cycle to the next, but the fundamental
component of the output signal will always be a
sinewave at the desired frequency. There will be a DC
offset on the output signal. The output can be
capacitively coupled if operation down to very low
frequencies is not required, otherwise offset
compensation should be provided externally.
POWER SUPPLY
CONNECTIONS
PHLD
The 12-bit data at the input of the phase modulator is
added to the output of the phase accumulator on the
rising edge of the clock following the falling edge of the
Phase Load input. The source of this data will be
determined by the state of the PHSEL line. The phase
of the DDS output will change 13 clock cycles after the
PHLD command, due to pipelining delays.
It is recommended that adequate decoupling of the +5
volt and –5.2 volt power supplies be provided. In
addition, it is recommended that decoupling inductors
be used on the DVEE (DAC) and AVEE (DAC) supplies
to minimize the noise on the power supplies to the
DAC. Suitable values for the inductors are 0.3 to 1 µH.
5
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STEL-1375A+80
ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS
Note: Stresses greater than those shown below may cause permanent damage to
the device. Exposure of the device to these conditions for extended periods may
also affect device reliability.
Symbol
Tstg
Ta
VDDmax
VEEmax
VI/O(max)
VI/O(min)
Parameter
Storage Temperature
Operating Temperature
Max. voltage between VDD and VSS
Max. voltage between VEE and VSS
Max. voltage on any input pin
Min. voltage on any input pin
Range
Units
–65 to +125
–40 to +85
+7 to –0.7
–7 to +0.7
VDD + 0.7
VSS – 0.7
°C
°C
volts
volts
volts
volts
RECOMMENDED OPERATING CONDITIONS (The VSS pins should be connected to ground)
Symbol
VDD
VEE
Ta
Parameter
Supply Voltage, +5 volts
Supply Voltage, –5.2 volts
Operating Temperature (Ambient)
STEL-1375A+80
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Range
Units
+5 ± 10%
–5.2 ± 10%
0 to +70
volts
volts
°C
6
D.C. CHARACTERISTICS (Operating Conditions: VDD = 5.0 V ±5%, VEE = -5.2 V ±5%, Ta = 25°C)
Symbol
Parameter
Min. Typ. Max. Units
Conditions
IDD
Supply Current, +5 volts
250
mA
@ 80 MHz clock
IEE
Supply Current, –5.2 volts
200
mA
@ 80 MHz clock
VIH(min)
Min. High Level Input Voltage
volts
Guaranteed Logic '1'
VIL(max)
Max. Low Level Input Voltage
0.8
volts
Guaranteed Logic '0'
IIH(max)
Max. High Level Input Current
10
35
110
µA
VIN = +5.0 volts
IIL(max)
Max. Low Level Input Current
–10
–45
–130
µA
VIN = 0 volts
VCLK
Clock Input
+10
dBm
into 50Ω
2.0
0
OUTPUT CHARACTERISTICS
Symbol
Parameter
PO(max)
Max. Output Power
Err(i)
Output integral linearity
VSPUR
Spurious signal level
VSPUR
Spurious signal level
Min. Typ. Max. Units
–5
–4
dBm
50Ω load, fOUT < .25 x fCLK
%
of full-scale output
–60
dBc
fOUT < .25 x fCLK
–55
dBc
fOUT > .25 x fCLK
–0.1
–2
Conditions
+0.1
A.C. CHARACTERISTICS (Operating Conditions: VDD = 5.0 V ±5%, VEE = -5.2 V ±5%, Ta = 25°C)
Symbol
Parameter
tRS
Reset
tSU
DATA, ADDR or CSEL
Min. Typ. Max. Units
30
nsec.
5
nsec.
2
nsec.
Conditions
to WRSTB or PHLD Setup
tHD
DATA, ADDR or CSEL
to WRSTB or PHLD Hold
tCH
Clock high
7
nsec.
fCLK= 80 MHz
tCL
Clock low
7
nsec.
fCLK= 80 MHz
tWR
WRSTB pulse width
7
nsec.
tLS
FRLD or PHLD pulse width
7
nsec.
7
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STEL-1375A+80
DDS FREQUENCY CHANGE SEQUENCE
CSEL
ADDR 3-0
DON'T CARE
DON'T CARE
tSU
WRSTB
t HD
tW
DATA 7-0
DON'T CARE
DON'T CARE
20 CLOCK
EDGES
CLOCK
tCH
1
t CL
2
3
19
20
t SU
FRLD
tW
FSYNC
OLD FREQUENCY
OUT
STEL-1375A+80
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8
NEW FREQUENCY
NCO PHASE CHANGE SEQUENCE
1. PHSEL = 1. BUS LOADING.
CSEL
ADDR
3-0
DON'T CARE
DON'T CARE
tHD
tW
tSU
WRSTB
DATA
7-0
DON'T CARE
DON'T CARE
13 CLOCK
EDGES
CLOCK
tSU 1
2
12 13
3
PHLD
tW
OLD PHASE
NEW PHASE
OUT
2. PHSEL = 0. DIRECT LOADING.
13 CLOCK
EDGES
CLOCK
tSU 1
DATA
7-0
ADDR
3-0
2
DON'T CARE
3
12 13
DON'T CARE
tSU tHD
PHLD
tW
OLD PHASE
NEW PHASE
OUT
9
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STEL-1375A+80
APPLICATIONS INFORMATION
Since the STEL-1375A+80 combines high-speed digital
and analog circuits, care must be taken to minimize the
effects of noise from the digital circuit on the analog
output. The following precautions will help in this
area:
1. Use ground and power planes on the printed
circuit board. Separate analog and digital ground
planes will also help.
2. Decouple the analog VEE line from the VEE supply
with a 1 µH inductor.
The clock input can be either a sine wave or a square
wave, the input buffer will square up a sinusoidal
input. The input is capacitively coupled internally. A
sine wave signal at about 0 to +10 dBm (50 Ω) is
recommended.
USING THE STEL-1375A+80
IN A HIGH-SPEED PHASE
MODULATOR
By routing the data and address lines
from the microcontroller via 2:1
multiplexers (e.g. 74HC157) the
MNCO can be set up from the
microcontroller and then phase
modulated at high-speed from an
external source. The PHSEL line
should be set to a logic 0 to enable this
mode of operation. The system shown
modulates all 12 bits. In a typical PSK
system only 1 to 4 bits of modulation
will be used, simplifying the system
considerably.
+5 V
34
Ana.
GND
33
–5.2 V (Dig.)
32
STEL-1375A+80
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VSS
AVEE
5, 27,
31
1, 4,
21, 29
Dig.
GND
DV EE
WRSTB
FRLD
4
4
4
PHASE0-11

FROM 
PHASE 
MOD. 
FREQ./PH SEL
PHASE LOAD
VDD
STEL-1375A+80
–5.2 V (Ana.)
WRITE

FROM FREQ. LOAD
µC DATA
 0-7
ADDR0-3
VSS
4
4
4
A
B
A/B
A
B
A/B
A
B
A/B
D0
.
.
D3
D4
.
. STEL-1375A
DDS
D7
A0
.
.
A3
PHLD
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SPECTRAL PURITY
A spectral plot of the NCO output after conversion
with a DAC (AD9721) is shown below. In this case, the
clock frequency is 80 MHz and the output frequency is
programmed to 12.3456789 MHz. The maximum nonharmonic spur level observed over the output
frequency range shown in this case is –62 dBc. The
spur levels are limited by the dynamic linearity of the
DAC. It is important to remember that when the
output frequency exceeds 25% of the clock frequency,
the second harmonic frequency will be higher than the
Nyquist frequency, 50% of the clock frequency. When
this happens, the image of the harmonic at the frequency
fc– 2fo, which is not harmonically related to the output
signal, will become intrusive since its frequency falls as
the output frequency rises, eventually crossing the
fundamental output when its frequency crosses
through fc/3. The same phenomenon occurs with the
third harmonic when the frequency crosses through
fc/4.
When an NCO is used with a digital to analog converter
(DAC) to generate an analog waveform the spectral
purity of the synthesized waveform is a function of
many variables, including the phase and amplitude
quantization, the ratio of the clock frequency to output
frequency, and the dynamic characteristics of the DAC.
The sine signals generated by the STEL-1175 have 12
bits of amplitude resolution and 13 bits of phase
resolution which results in spurious levels which are
theoretically at least 75 dB down. The highest output
frequency the NCO can generate is half the clock
frequency (fc/2), and the spurious components at
frequencies greater than fc/2 can be removed by
filtering. As the output frequency fo of the NCO
approaches fc/2, the "image" spur at fc– fo (created by
the sampling process) also approaches fc/2 from above.
If the programmed output frequency is very close to
fc/2 it will be virtually impossible to remove this image
spur by filtering. For this reason, the maximum practical
output frequency of the NCO should be limited to
about 40% of the clock frequency.
TYPICAL SPECTRUM
Frequency Span:
0 to 30 MHz
Reference Level:
–7 dBm
Resolution Bandwidth: 1 KHz
Scale:
Log, 10 dB/div
Output frequency:
12.3456789 MHz
Clock frequency:
80 MHz
STEL-1375A+80
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12
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Intel® products. No license, express or implied, by estoppel
or otherwise, to any intellectual property rights is granted by
this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability
whatsoever, and Intel disclaims any express or implied
warranty, relating to sale and/or use of Intel® products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent,
copyright or other intellectual property right. Intel products
are not intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
For Further Information Call or Write
INTEL CORPORATION
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