TI TPS70102PWP

TPS70145, TPS70148, TPS70151, TPS70158, TPS70102
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS
SLVS222A – DECEMBER 1999 – REVISED MARCH 2000
D
D
D
D
D
D
Dual Output Voltages for Split-Supply
Applications
Selectable Power Up Sequencing for DSP
Applications
Output Current Range of 500 mA on
Regulator 1 and 250 mA on Regulator 2
Fast Transient Response
Voltage Options are 3.3-V/2.5-V, 3.3-V/1.8-V,
3.3-V/1.5-V, 3.3-V/1.2-V, and Dual Adjustable
Outputs
Open Drain Power-On Reset With 120-ms
Delay
D
D
D
D
Open Drain Power Good for Regulator 1
Ultra Low 190 µA (typ) Quiescent Current
1 µA Input Current During Standby
Low Noise: 65 µVRMS Without Bypass
Capacitor
Quick Output Capacitor Discharge Feature
Two Manual Reset Inputs
2% Accuracy Over Load and Temperature
Undervoltage Lockout (UVLO) Feature
20-Pin PowerPAD TSSOP Package
Thermal Shutdown Protection
D
D
D
D
D
D
PWP PACKAGE
(TOP VIEW)
description
TPS701xx family devices are designed to provide
a complete power management solution for DSP,
processor power, ASIC, FPGA, and digital
applications where dual output voltage regulators
are required. Easy programmability of the
sequencing function makes this family ideal for
any DSP applications with power sequencing
requirement. Differentiated features, such as
accuracy, fast transient response, SVS supervisory circuit, manual reset inputs, and enable
function, provide a complete system solution.
NC
VIN1
VIN1
MR1
MR2
EN
SEQ
GND
VIN2
VIN2
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
TPS70151 PWP
5V
0.1 µF
250 kΩ
PG1
PG1
MR2
MR2
>2 V
<0.7 V
0.1 µF
>2 V
EN
250 kΩ
RESET
RESET
MR1
EN
I/O
10 µF
VSENSE1
VIN2
DSP
3.3 V
VOUT1
VIN1
NC
VOUT1
VOUT1
VSENSE1/FB1
PG1
RESET
VSENSE2/FB2
VOUT2
VOUT2
NC
MR1
>2 V
<0.7 V
<0.7 V
VSENSE2
SEQ
VOUT2
1.8 V
Core
10 µF
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments Incorporated.
Copyright  2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
TPS70145, TPS70148, TPS70151, TPS70158, TPS70102
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS
SLVS222A – DECEMBER 1999 – REVISED MARCH 2000
description (continued)
The TPS701xx family of voltage regulators offers very low dropout voltage and dual outputs with power up
sequence control, which is designed primarily for DSP applications. These devices have extremely low noise
output performance without using any added filter bypass capacitors and are designed to have a fast transient
response and be stable with 10 uF low ESR capacitors.
These devices have fixed 3.3-V/2.5-V, 3.3-V/1.8-V, 3.3-V/1.5-V, 3.3-V/1.2-V, and adjustable/adjustable voltage
options. The 3.3-V output regulator (regulator 1) can support up to 500 mA, and the other regulator (regulator
2) can support up to 250 mA. Separate voltage inputs allow the designer to configure the source power.
Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (typically 170 mV
on regulator 1) and is directly proportional to the output current. Additionally, since the PMOS pass element is
a voltage-driven device, the quiescent current is very low and independent of output loading (maximum of
225 µA over the full range of output current). This LDO family also features a sleep mode; applying a high signal
to EN (enable) shuts down both regulators, reducing the input current to 1 µA at TJ = 25°C.
The device is enabled when the EN pin is connected to a low-level input voltage. The output voltages of the two
regulators are sensed at the VSENSE1 and VSENSE2 pins respectively. The input signal at the SEQ pin controls
the power-up sequence of the two regulators. When the device is enabled and the SEQ terminal is pulled high
or left open, VOUT2 will turn on first and VOUT1 will remain off until VOUT2 reaches approximately 83% of it’s
regulated output voltage. At that time VOUT1 will be turned on. If VOUT2 is pulled below 83% (i.e. over load
condition) VOUT1 will be turned off. Pulling the SEQ terminal low, reverses the power-up order and VOUT1 will
be turned on first. The SEQ pin is connected to an internal pullup current source.
For each regulator, there is an internal discharge transistor to discharge the output capacitor when the regulator
is turned off(disabled).
The PG1 pin reports the voltage conditions at the VOUT1, which can be used to implement a SVS (power on
reset) for the circuitry supplied by regulator 1.
The TPS701xx features a RESET (SVS, POR, or Power On Reset). RESET output initiates a reset in DSP
systems in the event of an undervoltage condition. RESET indicates the status of the VOUT2 and both manual
reset pins (MR1 and MR2). When VOUT2 reaches 95% of it’s regulated voltage and MR1 and MR2 are in the
logic high state, RESET will go to a high impedance state after 120 ms delay. RESET will go to logic low state
when VOUT2 regulated output voltage is pulled below 95% (i.e. over load condition) of it’s regulated voltage. To
monitor VOUT1 , the PG1 output pin can be connected to MR1 or MR2.
The device has an undervoltage lockout UVLO circuit which prevents the internal regulators from turning on until
VIN1 reaches 2.5V.
AVAILABLE OPTIONS
TJ
– 40°C to 125°C
REGULATOR 1
VO (V)
REGULATOR 2
VO (V)
TSSOP
(PWP)
3.3 V
1.2 V
TPS70145PWP
3.3 V
1.5 V
TPS70148PWP
3.3 V
1.8 V
TPS70151PWP
3.3 V
2.5 V
TPS70158PWP
Adjustable
(1.22 V to 5.5 V)
Adjustable
(1.22 V to 5.5 V)
TPS70102PWP
NOTE: The TPS70102 is programmable using external resistor dividers (see
application information) The PWP package is available taped and reeled. Add
an R suffix to the device type (e.g., TPS70102PWPR).
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TPS70145, TPS70148, TPS70151, TPS70158, TPS70102
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS
SLVS222A – DECEMBER 1999 – REVISED MARCH 2000
detailed block diagram – fixed voltage version
VOUT1 (2 Pin)
VIN1 (2 Pins)
Shutdown
V_UVLO
10 kΩ
Current
Sense
UVLO
–
Reference
GND
+
VREF
Thermal
Shutdown
VSENSE1
(see Note A)
ENA_1
ENA_1
FB1
VREF
PG1
FB1
Rising Edge
Deglitch
0.95 × VREF
VCC
MR2
SHUTDOWN
FB2
UV Comp
FB2
Falling Edge
Deglitch
0.83 × VREF
FB1
Falling Edge
Deglitch
0.83 × VREF
PG1 Comp
0.95 × VREP
Power
Sequence
Logic
VIN1
ENA_!
ENA_2
VREF
UV Comp
EN
RESET
Falling Edge
Delay
Rising Edge
Deglitch
–
MR1
FB2
+
ENA_2
VCC
Current
Sense
SEQ
(see Note B)
VSENSE2
(see Note A)
ENA_2
10 kΩ
VOUT2(2 Pin)
VIN2 (2 Pins)
NOTES: A. For most applications, VSENSE1 and VSENSE2 should be externally connected to VOUT as close as possible to the device.
For other implementations, refer to SENSE terminal connection discussion in Application information section.
B. If the SEQ terminal is floating at the input, the VOUT2 will power-up first.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
TPS70145, TPS70148, TPS70151, TPS70158, TPS70102
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS
SLVS222A – DECEMBER 1999 – REVISED MARCH 2000
detailed block diagram – adjustable voltage version
VOUT1 (2 Pin)
VIN1 (2 Pins)
Current
Sense
UVLO
Shutdown
2.5 V
–
GND
Reference
Thermal
Shutdown
FB1
(see Note A)
ENA_1
+
ENA_1
VREF
VREF
PG1
FB1
Rising Edge
Deglitch
0.95 × VREF
VCC
MR2
SHUTDOWN
FB2
UV Comp
FB2
Falling Edge
Deglitch
0.83 × VREF
FB1
Falling Edge
Deglitch
0.83 × VREF
PG1 Comp
0.95 × VREP
Power
Sequence
Logic
RESET
Falling Edge
Delay
Rising Edge
Deglitch
VIN1
ENA_!
ENA_2
MR1
VREF
UV Comp
EN
–
VCC
+
Current
Sense
SEQ
(see Note B)
ENA_2
ENA_2
FB2
(see Note A)
VOUT2 (2 Pin)
VIN2 (2 Pins)
NOTES: A. For most applications, FB1 and FB2 should be externally connected to resistor dividers as close as possible to the device.
For other implementations, refer to FB terminals connection discussion in Application information section.
B. If the SEQ terminal is floating at the input, the VOUT2 will power-up first.
4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TPS70145, TPS70148, TPS70151, TPS70158, TPS70102
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS
SLVS222A – DECEMBER 1999 – REVISED MARCH 2000
RESET timing diagram
VIN1 and VIN2
Vres
(see Note A)
Vres
t
VOUT2
VIT +(see Note B)
VIT +(see Note B)
Threshold
Voltage
VIT –
(see Note B)
VIT –
(see Note B)
t
RESET
Output
Output
Undefined
Î
Î
Î
Î
Î
120 ms
Delay
Î
Î
Î
Î
Î
120 ms
Delay
Output
Undefined
t
NOTES: A. Vres is the minimum input voltage for a valid RESET. The symbol Vres is not currently listed within EIA or JEDEC standards
for semiconductor symbology.
B. VIT –Trip voltage is typically 5% lower than the output voltage (95%VO) VIT– to VIT+ is the hysteresis voltage.
PG timing diagram
VIN1 and VIN2
Vres
(see Note A)
Vres
t
VOUT2
VIT +(see Note B)
VIT+ (see Note B)
Threshold
Voltage
VIT –
(see Note B)
VIT –
(see Note B)
t
PG
Output
Output
Undefined
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
Output
Undefined
t
NOTES: A. Vres is the minimum input voltage for a valid PG. The symbol Vres is not currently listed within EIA or JEDEC
standards for semiconductor symbology.
B. VIT –Trip voltage is typically 5% lower than the output voltage (95%VO) VIT– to VIT+ is the hysteresis
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
TPS70145, TPS70148, TPS70151, TPS70158, TPS70102
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS
SLVS222A – DECEMBER 1999 – REVISED MARCH 2000
Terminal Functions
TERMINAL
NO.
NAME
I/O
I
DESCRIPTION
EN
6
GND
8
Active low enable
MR1
4
I
Manual reset input 1, active low, pulled up internally
MR2
5
I
Manual reset input 2, active low, pulled up internally
Ground
NC
1, 11, 20
PG1
16
O
Open drain output, low when VOUT1 voltage is less than 55 of the nominal regulated voltage
RESET
15
O
Open drain output, SVS (power on reset) signal, active low
SEQ
7
I
Power up sequence control: SEQ=High, VOUT2 powers up first; SEQ=Low, VOUT1 powers up first, SEQ
terminal pulled up internally.
VIN1
VIN2
2, 3
I
Input voltage of regulator 1
VOUT1
VOUT2
VSENSE2/FB2
VSENSE1/FB1
No connection
9, 10
I
Input voltage of regulator 2
18, 19
O
Output voltage of regulator 1
12, 13
O
Output voltage of regulator 2
14
I
Regulator 2 output voltage sense/ regulator 2 feedback for adjustable
17
I
Regulator 1 output voltage sense/ regulator 2 feedback for adjustable
absolute maximum ratings over operating junction temperature (unless otherwise noted)†
Input voltage range‡: VIN1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V
VIN2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V
Voltage range at EN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V
Output voltage range (VOUT1, VSENSE1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Output voltage range (VOUT2, VSENSE2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Maximum RESET, PG1 voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Maximum MR1, MR2, and SEQ voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VIN1
Peak output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internally limited
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Tables
Operating virtual junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 125°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
ESD rating, HBM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 kV
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
‡ All voltages are tied to network ground.
ÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁ
ÁÁÁÁÁÁ
DISSIPATION RATING TABLE
PACKAGE
PWP§
AIR FLOW
(CFM)
TA ≤ 25°C
DERATING FACTOR
TA = 70°C
TA = 85°C
0
3.067 W
30.67 mW/°C
1.687 W
1.227 W
250
4.115 W
41.15 mW/°C
2.265 W
1.646 W
§ This parameter is measured with the recommended copper heat sink pattern on a 4-layer PCB, 1 oz. copper on 4-in × 4-in
ground layer. For more information, refer to TI technical brief SLMA002.
6
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TPS70145, TPS70148, TPS70151, TPS70158, TPS70102
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS
SLVS222A – DECEMBER 1999 – REVISED MARCH 2000
recommended operating conditions
Input voltage, VI†
MIN
MAX
2.7
6
0
500
mA
0
250
mA
1.22
5.5
V
Output current, IO (regulator 1)
Output current, IO (regulator 2)
Output voltage range (for adjustable option)
UNIT
V
Operating virtual junction temperature, TJ
–40
125
°C
† To calculate the minimum input voltage for maximum output current, use the following equation: VI(min) = VO(max) + VDO(max load).
electrical characteristics over recommended operating junction temperature (TJ = –40°C to 125°C)
VI= VO(nom) + 1 V, IO = 1 mA, EN = 0, CO = 33 µF(unless otherwise noted)
PARAMETER
TEST CONDITIONS
Adjustable
j
voltage
1 2 V Output
1.2
VO
Out ut voltage
Output
((see Notes 1 and 3))
1 5 V Output
1.5
1 8 V Output
1.8
2
5 V Output
2.5
3 3 V Output
3.3
Regulator 2
Regulator 2
Thermal shutdown junction temperature
Regulator 1
II(standby)
I( t db )
Standby current
Regulator 2
PSRR
2.7 V < VIN < 6 V,
TJ = 25°C
0.98 VO
TJ = 25°C
1.02 VO
1.224
1.5
2.7 V < VIN < 6 V
1.47
2.8 V < VIN < 6 V,
TJ = 25°C
1.53
1.8
2.8 V < VIN < 6 V
1.764
3.5 V < VIN < 6 V,
TJ = 25°C
1.836
2.45
TJ = 25°C
2.55
3.3
4.3 V < VIN < 6 V
3.234
TJ = 25°C
3.366
190
230
TJ = 25°C, (see Note 1)
(see Note 1)
TJ = 25°C
VO = 0 VI
TJ = 25°C
EN = VI,
0.1%
1.6
1.9
0.750
1
1
3
TJ = 25°C
1
EN = VI
3
TJ = 25°C, (see Note 1)
60
V
A
°C
150
EN = VI,
µA
µVrms
65
EN = VI
V
mV
65
TJ = 25°C
f = 1 kHz, CO = 33 µF,
Power supply ripple rejection
0.01%
1
kHz CO = 33 µF
BW = 300 Hz to 50 kHz,
µF,
V
2.5
3.5 V < VIN < 6 V
4.3 V < VIN < 6 V,
UNIT
VO
1.176
2.7 V < VIN < 6 V,
MAX
1.2
2.7 V < VIN < 6 V
TJ = 25°C
Regulator 1
Regulator 1
Output current limit
2.7 V < VIN < 6 V,
VO + 1 V < VI ≤ 6 V,
VO + 1 V < VI ≤ 6 V,
Load regulation for VOUT1 and VOUT2
Output noise voltage
1.22 V ≤ VO ≤ 5.5 V,
FB connected to VO
TYP
See Note 3
Output voltage
g line regulation
g
(∆V
( O/VO) for
regulator 1 and regulator 2 (see Note 2)
Vn
2.7 V < VIN < 6 V,
See Note 3,
Quiescent current (GND
(
current)) for regulator
g
1 and
regulator 2, EN = 0 V, (see Note 1)
MIN
1.22 V ≤ VO ≤ 5.5 V,
FB connected to VO
µA
µA
dB
NOTES: 1. Minimum input operating voltage is 2.7 V or VO(typ) + 1 V, whichever is greater. Maximum input voltage = 6 V, minimum output current
1 mA.
2. If VO < 1.8 V then Vimax = 6 V, Vimin = 2.7 V:
Line Regulation (mV)
+ ǒ%ńVǓ
V
O
ǒ
V
ǒ
If VO > 2.5 V then Vimax = 6 V, Vimin = Vo + 1 V:
+ ǒ%ńVǓ
Ǔ
* 2.7 V
imax
100
*
ǒ
)
ǓǓ
V
1
imax
O
1000
100
3. IO = 1 mA to 500 mA for Regulator 1 and 1 mA to 250 mA for Regulator 2.
Line Regulation (mV)
V
O
V
1000
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
7
TPS70145, TPS70148, TPS70151, TPS70158, TPS70102
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS
SLVS222A – DECEMBER 1999 – REVISED MARCH 2000
electrical characteristics over recommended operating junction temperature (TJ = –40°C to 125°C)
VI = VO(nom) + 1 V, IO = 1 mA, EN = 0, CO = 33 µF(unless otherwise noted) (continued)
PARAMETER
RESET
PG
TEST CONDITIONS
Minimum input voltage for valid RESET
I(RESET) = 300 µA,
Trip threshold voltage
VO decreasing
Hysteresis voltage
Measured at VO
t(RESET)
RESET pulse duration
tr(RESET)
Rising edge deglitch
Output low voltage
VI = 3.5 V,
Leakage current
V(RESET) = 6 V
Minimum input voltage for valid PG
IO(PG) = 300 µA,
Trip threshold voltage
VO decreasing
Hysteresis voltage
Measured at VO
tr(PG1)
Rising edge deglitch
Output low voltage
VI = 2.7 V,
Leakage current
V(PG1) = 6 V
80
120
0.15
V(PG1) ≤ 0.8 V
1.0
92%
–1
Measured at VO
V
1
µA
1.3
µs
0.4
V
1
µA
0.7
V
1
µA
µs
140
V
Low level SEQ input voltage
0.7
Measured at VO
µs
6
µA
V
Low level input voltage
0.7
Measured at VO
Pull up current source
VOUT2 UV comparator – positive-going input
threshold voltage of VOUT1 UV comparator
80% VO
VOUT2 UV comparator – hysteresis
V
140
2
Falling edge deglitch
V
VO
VO
2
Falling edge deglitch
ms
V
Low level EN input voltage
Input current (EN)
VO
µs
98%
0.15
V
0.4
30
IO(PG) = 1 mA
UNIT
VO
160
0.5%
High level input voltage
V
140
µs
6
µA
83% VO
86% VO
V
0.5% VO
mV
VOUT2 UV comparator – falling edge deglitch
VSENSE_2 decreasing below threshold
140
µs
Peak output current
2 ms pulse width
375
mA
Discharge transistor current
VOUT2 = 1.5 V
7.5
mA
VOUT1 UV comparator – positive-going input
threshold voltage of VOUT1 UV comparator
80% VO
VOUT1 UV comparator – hysteresis
VOUT1
98%
30
IO(RESET) = 1 mA
SEQ pull up current source
VOUT2
1.3
0.5%
High level SEQ input voltage
MR1 / MR2
MAX
1.0
2
Falling Edge deglitch
SEQ
TYP
92%
High level EN input voltage
EN
MIN
V(RESET) ≤ 0.8 V
VOUT1 UV comparator – falling edge deglitch
Dropout voltage (see Note 4)
83% VO
0.5% VO
mV
140
µs
IO = 500 mA, VIN1 = 3.2 V
170
IO = 500 mA,
VIN1 = 3.2 V
275
2 ms pulse width
750
Discharge transistor current
VOUT1 = 1.5 V
7.5
UVLO threshold
FB
Input current – TPS70102
V
VSENSE_1 decreasing below threshold
Peak output current
VOUT1 UVLO
86% VO
2.4
FB = 1.8 V
mA
mA
2.65
2
mV
V
nA
NOTE 4: Input voltage(VIN1 or VIN2) = VO(Typ) – 100 mV. 1.5 V, 1.8 V and 2.5 V regulators, the dropout voltage is limited by input voltage range.
The 3.3 V regulator input voltage is to 3.2 V to perform this test.
8
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TPS70145, TPS70148, TPS70151, TPS70158, TPS70102
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS
SLVS222A – DECEMBER 1999 – REVISED MARCH 2000
Table of Graphs
FIGURE
VO
vs Output current
1–3
vs Temperature
4–7
Ground current
vs Temperature
8, 9
Power supply rejection ratio
vs Frequency
10 – 13
Output spectral noise density
vs Frequency
14 – 17
Output impedance
vs Frequency
18 – 21
vs Temperature
22, 23
vs Input voltage
24, 25
Output voltage
PSRR
Zo
Dropout voltage
Load transient response
26, 27
Line transient response
Stability
28, 29
Output voltage
vs. Time (start-up)
30, 31
Equivalent series resistance (ESR)
vs Output current
33 – 36
TYPICAL CHARACTERISTICS
TPS70151
TPS70151
OUTPUT VOLTAGE
vs
OUTPUT CURRENT
OUTPUT VOLTAGE
vs
OUTPUT CURRENT
1.802
3.300
VIN1 = 4.3 V
TA = 25°C
VOUT1
3.298
VO – Output Voltage – V
VO – Output Voltage – V
3.299
VIN2 = 2.8V
TA = 25°C
VOUT2
1.801
3.297
3.296
3.295
1.800
1.799
1.798
1.797
3.294
1.796
3.293
1.795
3.292
0
0.1
0.4
0.2
0.3
IO – Output Current – A
0.5
0.6
0
0.05
0.1
0.15
0.2
0.25
0.3
IO – Output Current – A
Figure 1
Figure 2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
9
TPS70145, TPS70148, TPS70151, TPS70158, TPS70102
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS
SLVS222A – DECEMBER 1999 – REVISED MARCH 2000
TYPICAL CHARACTERISTICS
TPS70145
OUTPUT VOLTAGE
vs
OUTPUT CURRENT
1.201
VIN2 = 2.7 V
TA = 25°C
VOUT2
VO – Output Voltage – V
1.200
1.199
1.198
1.197
1.196
1.195
0
0.05
0.1
0.15
0.2
0.25
0.3
IO – Output Current – A
Figure 3
TPS70151
OUTPUT VOLTAGE
vs
TEMPERATURE
TPS70151
OUTPUT VOLTAGE
vs
TEMPERATURE
3.288
3.286
3.284
VIN1 = 4.3 V
IO = 1 mA
VOUT1
3.284
VO – Output Voltage – V
VO – Output Voltage – V
3.282
3.280
3.278
3.276
3.274
3.282
3.280
3.278
3.276
3.272
3.274
3.270
3.272
3.268
–40 –25 –10
5
20 35 50 65 80
T – Temperature – °C
95 110 125
3.270
–40 –25 –10
5 20 35 50 65 80
T – Temperature – °C
Figure 5
Figure 4
10
VIN1 = 4.3 V
IO = 500 mA
VOUT1
3.286
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
95 110 125
TPS70145, TPS70148, TPS70151, TPS70158, TPS70102
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS
SLVS222A – DECEMBER 1999 – REVISED MARCH 2000
TYPICAL CHARACTERISTICS
TPS70151
OUTPUT VOLTAGE
vs
TEMPERATURE
TPS70151
OUTPUT VOLTAGE
vs
TEMPERATURE
1.800
1.798
1.799
VIN2 = 2.8 V
IO = 1 mA
VOUT2
1.798
VIN2 = 2.8 V
IO = 250 mA
VOUT2
VO – Output Voltage – V
VO – Output Voltage – V
1.797
1.796
1.794
1.792
1.790
1.796
1.795
1.794
1.793
1.792
1.788
1.791
1.786
–40 –25 –10
5 20 35 50 65 80
T – Temperature – °C
1.790
–40 –25 –10
95 110 125
5
Figure 6
20 35 50 65 80
T – Temperature – °C
95 110 125
Figure 7
GROUND CURRENT
vs
TEMPERATURE
GROUND CURRENT
vs
TEMPERATURE
135
70
VOUT1
68
130
IO = 1 mA
66
Ground Current – µ A
Ground Current – µ A
125
IO = 1 mA
120
115
IO = 500 mA
110
64
62
60
58
IO = 250 mA
56
105
54
100
95
–40 –25 –10
52
5
20
35 50 65
80
95 110 125
VOUT2
50
–40 –25 –10
T – Temperature – °C
5
20
35 50 65
80
95 110 125
T – Temperature – °C
Figure 8
Figure 9
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
11
TPS70145, TPS70148, TPS70151, TPS70158, TPS70102
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS
SLVS222A – DECEMBER 1999 – REVISED MARCH 2000
TYPICAL CHARACTERISTICS
TPS70151
TPS70151
POWER SUPPLY REJECTION RATIO
vs
FREQUENCY
POWER SUPPLY REJECTION RATIO
vs
FREQUENCY
10
PSRR – Power Supply Rejection Ratio – dB
PSRR – Power Supply Rejection Ratio – dB
–10
IO = 10 mA
CO = 22 µF
VOUT1
–20
–30
–40
–50
–60
–70
–80
–90
IO = 500 mA
CO = 22 µF
VOUT1
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
10
100
1k
100 k
10 k
10
1M
100
f – Frequency – Hz
Figure 10
TPS70151
TPS70151
POWER SUPPLY REJECTION RATIO
vs
FREQUENCY
POWER SUPPLY REJECTION RATIO
vs
FREQUENCY
1M
10
IO = 10 mA
CO = 22 µF
VOUT2
–20
PSRR – Power Supply Rejection Ratio – dB
PSRR – Power Supply Rejection Ratio – dB
100 k
Figure 11
–10
–30
–40
–50
–60
–70
–80
–90
10
100
1k
10 k
f – Frequency – Hz
100 k
1M
IO = 250 mA
CO = 22 µF
VOUT2
0
–10
–20
–30
–40
–50
–60
–70
10
Figure 12
12
1k
10 k
f – Frequency – Hz
100
1k
10 k
f – Frequency – Hz
Figure 13
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
100 k
1M
TPS70145, TPS70148, TPS70151, TPS70158, TPS70102
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS
SLVS222A – DECEMBER 1999 – REVISED MARCH 2000
TYPICAL CHARACTERISTICS
OUTPUT SPECTRAL NOISE DENSITY
vs
FREQUENCY
OUTPUT SPECTRAL NOISE DENSITY
vs
FREQUENCY
10
VIN1 = 4.3 V
VOUT1 = 3.3 V
IO = 10 mA
Output Spectral Noise Density – µV Hz
Output Spectral Noise Density – µV Hz
10
1
0.1
0.01
100
1k
10 k
f – Frequency – Hz
VIN1 = 4.3 V
VOUT1 = 3.3 V
IO = 500 mA
1
0.1
0.01
100
100 k
1k
10 k
f – Frequency – Hz
Figure 14
Figure 15
OUTPUT SPECTRAL NOISE DENSITY
vs
FREQUENCY
OUTPUT SPECTRAL NOISE DENSITY
vs
FREQUENCY
10
VIN2 = 2.8 V
VOUT2 = 1.8 V
IO = 10 mA
Output Spectral Noise Density – µV Hz
Output Spectral Noise Density – µV Hz
10
1
0.1
0.01
100
100 k
1k
10 k
f – Frequency – Hz
100 k
VIN2 = 2.8 V
VOUT2 = 1.8 V
IO = 250 mA
1
0.1
0.01
100
Figure 16
1k
10 k
f – Frequency – Hz
100 k
Figure 17
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
13
TPS70145, TPS70148, TPS70151, TPS70158, TPS70102
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS
SLVS222A – DECEMBER 1999 – REVISED MARCH 2000
TYPICAL CHARACTERISTICS
OUTPUT IMPEDANCE
vs
FREQUENCY
OUTPUT IMPEDANCE
vs
FREQUENCY
100
CO = 33 µF
IO = 500 mA
VOUT1 = 3.3 V
TA = 25 C
10
Z O – Output Impedance – Ω
Z O – Output Impedance – Ω
100
1
0.1
0.01
10
100
1k
10 k
100 k
1M
10
1
0.1
0.01
10 M
CO = 33 µF
IO = 10 mA
VOUT1 = 3.3 V
TA = 25 C
10
100
Figure 19
1M
10 M
1M
10 M
OUTPUT IMPEDANCE
vs
FREQUENCY
100
CO = 33 µF
IO = 250 mA
VOUT2 = 1.8 V
TA = 25 C
10
Z O – Output Impedance – Ω
Z O – Output Impedance – Ω
100 k
Figure 18
100
14
10 k
f – Frequency – Hz
OUTPUT IMPEDANCE
vs
FREQUENCY
1
0.1
0.01
1k
f – Frequency – Hz
10
100
1k
10 k
100 k
1M
10 M
CO = 33 µF
IO = 10 mA
VOUT2 = 1.8 V
TA = 25 C
10
1
0.1
0.01
10
100
1k
10 k
100 k
f – Frequency – Hz
f – Frequency – Hz
Figure 20
Figure 21
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TPS70145, TPS70148, TPS70151, TPS70158, TPS70102
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS
SLVS222A – DECEMBER 1999 – REVISED MARCH 2000
TYPICAL CHARACTERISTICS
DROPOUT VOLTAGE
vs
TEMPERATURE
DROPOUT VOLTAGE
vs
TEMPERATURE
6
250
CO = 33 µF
VIN1 = 3.2 V
CO = 33 µF
VIN1 = 3.2 V
5
200
IO = 10 mA
Dropout Voltage – mV
Dropout Voltage – mV
IO = 500 mA
150
100
50
4
3
2
1
IO = 0 mA
0
–40 –25 –10
5
20 35 50 65 80
T – Temperature – °C
0
–40 –25 –10
95 110 125
Figure 22
TPS70102
TPS70102
DROPOUT VOLTAGE
vs
INPUT VOLTAGE
DROPOUT VOLTAGE
vs
INPUT VOLTAGE
500
IO = 500 mA
VIN1
IO = 250 mA
VIN2
250
400
TJ = 125°C
Dropout Voltage – mV
Dropout Voltage – mV
95 110 125
Figure 23
300
200
TJ = 25°C
150
100
TJ= – 40°C
TJ = 125°C
300
TJ = 25°C
200
TJ = – 40°C
100
50
0
2.5
5 20 35 50 65 80
T – Temperature – °C
3
3.5
4
4.5
5
5.5
0
2.5
3
VI – Input Voltage – V
3.5
4
4.5
5
5.5
VI – Input Voltage – V
Figure 24
Figure 25
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
15
TPS70145, TPS70148, TPS70151, TPS70158, TPS70102
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS
SLVS222A – DECEMBER 1999 – REVISED MARCH 2000
TYPICAL CHARACTERISTICS
IO – Output Current – mA
LOAD TRANSIENT RESPONSE
CO = 33 µF
TA = 25°C
VOUT1 = 3.3 V
500
250
0
∆ VO – Change in
Output Voltage – mV
∆ VO – Change in
Output Voltage – mV
IO – Output Current – mA
LOAD TRANSIENT RESPONSE
20
0
–20
0
0.2
0.4 0.6 0.8
1
1.2
1.4 1.6
1.8
CO = 33 µF
TA = 25°C
VOUT2 = 1.8 V
250
0
20
0
–20
2
0
0.2
0.4 0.6 0.8
t – Time – ms
Figure 26
VI – Input Voltage – V
4.3
50
0
IO = 500 mA
CO = 33 µF
VOUT1
20
40
60
1.8
2
80 100 120 140 160 180 200
t – Time – µs
3.8
2.8
10
0
IO = 250 mA
CO = 33 µF
VOUT2
–10
0
20
Figure 28
16
1.4 1.6
LINE TRANSIENT RESPONSE (VOUT2 )
∆ VO – Change in
Output Voltage – mV
VI – Input Voltage – V
∆ VO – Change in
Output Voltage – mV
5.3
0
1.2
Figure 27
LINE TRANSIENT RESPONSE (VOUT1)
–50
1
t – Time – ms
40
60
80 100 120 140 160 180 200
t – Time – µs
Figure 29
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TPS70145, TPS70148, TPS70151, TPS70158, TPS70102
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS
SLVS222A – DECEMBER 1999 – REVISED MARCH 2000
TYPICAL CHARACTERISTICS
VO – Output Voltage
(VOUT2 ) – V
OUTPUT VOLTAGE
vs
TIME (START-UP)
VO = 3.3 V
CO = 33 µF
IO = 500 mA
VOUT1
SEQ = Low
3
2
1
0
VO = 1.8 V
CO = 33 µF
IO = 250 mA
VOUT2
SEQ = High
2
1
0
–1
Enable Voltage – V
Enable Voltage – V
VO – Output Voltage
(VOUT1 ) – V
OUTPUT VOLTAGE
vs
TIME (START-UP)
5
0
–5
0
0.2 0.4
0.6
0.8 10 12
t – Time – ms
14
16
18
20
5
0
–5
0
0.2 0.4
Figure 30
VI
0.6
0.8 10 12
t – Time – ms
14
16
18
20
Figure 31
To Load
IN
OUT
+
EN
CO
GND
RL
ESR
Figure 32. Test Circuit for Typical Regions of Stability
† Equivalent series resistance (ESR) refers to the total series resistance, including the ESR of the capacitor, any series resistance added
externally, and PWB trace resistance to CO.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
17
TPS70145, TPS70148, TPS70151, TPS70158, TPS70102
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS
SLVS222A – DECEMBER 1999 – REVISED MARCH 2000
TYPICAL CHARACTERISTICS
TYPICAL REGION OF STABILITY
TYPICAL REGION OF STABILITY
EQUIVALENT SERIES RESISTANCE†
vs
OUTPUT CURRENT
EQUIVALENT SERIES RESISTANCE†
vs
OUTPUT CURRENT
10
VO = 3.3 V
CO = 10 µF
TA = 25°C
9
8
ESR – Equivalent Series Resistance – Ω
ESR – Equivalent Series Resistance – Ω
10
REGION OF INSTABILITY
7
6
5
4
3
2
1
0
VO = 3.3 V
CO = 6.8 µF
TA = 25°C
9
8
7
6
5
4
3
2
1
250 mΩ
0
0
100
200
300
400
500
0
100
IO – Output Current – mA
200
300
400
500
IO – Output Current – mA
Figure 33
Figure 34
TYPICAL REGION OF STABILITY
TYPICAL REGION OF STABILITY
EQUIVALENT SERIES RESISTANCE†
vs
OUTPUT CURRENT
EQUIVALENT SERIES RESISTANCE†
vs
OUTPUT CURRENT
10
10
VO = 1.8 V
CO = 10 µF
TA = 25°C
9
8
ESR – Equivalent Series Resistance – Ω
ESR – Equivalent Series Resistance – Ω
REGION OF INSTABILITY
REGION OF INSTABILITY
7
6
5
4
3
2
1
0
VO = 1.8 V
CO = 6.8 µF
TA = 25°C
9
8
REGION OF INSTABILITY
7
6
5
4
3
2
1
250 mΩ
0
0
50
100
150
200
250
0
IO – Output Current – mA
50
100
150
200
250
IO – Output Current – mA
Figure 35
Figure 36
† Equivalent series resistance (ESR) refers to the total series resistance, including the ESR of the capacitor, any series resistance added
externally, and PWB trace resistance to CO.
18
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TPS70145, TPS70148, TPS70151, TPS70158, TPS70102
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS
SLVS222A – DECEMBER 1999 – REVISED MARCH 2000
APPLICATION INFORMATION
pin functions
enable
The EN terminal is an input which enables or shuts down the device. If EN is at a voltage high signal the device
will be in shutdown mode. When the EN goes to voltage low, then the device will be enabled.
sequence
The SEQ terminal is an input that programs which output voltage (VOUT1 or VOUT2) will be turned on first. When
the device is enabled and the SEQ terminal is pulled high or left open, VOUT2 will turn on first and VOUT1 will
remain off until VOUT2 reaches approximately 83% of its regulated output voltage. At that time the VOUT1 will
be turned on. If VOUT2 is pulled below 83% (i.e., over load condition) VOUT1 will be turned off. For a detailed
timing diagram, refer to Figures 37 – 43. These terminals have a 6-µA pullup current to VIN1.
Pulling the SEQ terminal low reverses the power-up order and VOUT1 will be turned on first. For detail timing
diagram refer to Figures 37 and 42.
power–good
The PG1 is an open drain, active high output terminal which indicates the status of the VOUT1 regulator. When
the VOUT1 reaches 95% of its regulated voltage, PG1 will go to a high impedance state. It will go to a low
impedance state when it is pulled below 95% (i.e. over load condition) of its regulated voltage. The open drain
output of the PG1 terminal requires a pullup resistor.
manual reset pins (MR1 and MR2)
MR1 and MR2 are active low input terminals used to trigger a reset condition. When either MR1 or MR2 is pulled
to logic low, a POR (RESET) will occur. These terminals have a 6-µA pullup current to VIN1.
sense (VSENSE1, VSENSE2)
The sense terminals of fixed-output options must be connected to the regulator output, and the connection
should be as short as possible. Internally, sense connects to high-impedance wide-bandwidth amplifiers
through a resistor-divider network and noise pickup feeds through to the regulator output. It is essential to route
the sense connection in such a way to minimize/avoid noise pickup. Adding RC networks between the VSENSE
terminals and VOUT terminals to filter noise is not recommended because it can cause the regulators to oscillate.
FB1 and FB2
FB1 and FB2 are input terminals used for adjustable-output devices and must be connected to the external
feedback resistor divider. FB1 and FB2 connections should be as short as possible. it is essential to route them
in such a way as to minimize/avoid noise pickup. Adding RC networks between the FB terminals and VOUT
terminals to filter noise is not recommended because it can cause the regulators to oscillate.
RESET indicator
The TPS701xx features a RESET (SVS, POR, or Power On Reset). RESET can be used to drive power-on reset
circuitry or a low-battery indicator. RESET is an active low, open drain output which indicates the status of the
VOUT2 regulator and both manual reset pins (MR1 and MR2). When VOUT2 exceeds to 95% of it’s regulated
voltage, and MR1 and MR2 are in the high impedance state, RESET will go to a high-impedance state after
120-ms delay. RESET will go to a low impedance state when VOUT2 is pulled below 95% (i.e. over load condition)
of it’s regulated voltage. To monitor VOUT1 , PG1 output pin can be connected to MR1 or MR2. The open drain
output of the RESET terminal requires a pullup resistor. If RESET is not used, it can be left floating.
VIN1 and VIN2
VIN1 and VIN2 are input to the regulators. Internal bias voltages are powered by VIN1.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
19
TPS70145, TPS70148, TPS70151, TPS70158, TPS70102
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS
SLVS222A – DECEMBER 1999 – REVISED MARCH 2000
APPLICATION INFORMATION
VOUT1 and VOUT2
VOUT1 and VOUT2 are output terminals of the LDO.
The TPS701xx low dropout regulator family provides dual regulated output voltages for DSP applications, which
require high performance power management solution. These devices provide fast transient response and high
accuracy with small output capacitors, while drawing low quiescent current. Programmable sequencing
provides a power solution for DSPs without any external component requirements. This reduces the component
cost and board space while increasing total system reliability. TPS701xx family has an enable feature which puts
the device in sleep mode reducing the input currents to less than 3 µA. Other features are integrated SVS (Power
On Reset, RESET) and Power Good (PG1) that monitor output voltages and provide logic output to the system.
These differentiated features provide a complete DSP power solution.
The TPS701xx, unlike many other LDOs, feature very low quiescent current which remains virtually constant
even with varying loads. Conventional LDO regulators use a pnp pass element, the base current of which is
directly proportional to the load current through the regulator (IB = IC/β). The TPS701xx uses a PMOS transistor
to pass current; because the gate of the PMOS is voltage driven, operating current is low and stable over the
full load range.
20
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TPS70145, TPS70148, TPS70151, TPS70158, TPS70102
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS
SLVS222A – DECEMBER 1999 – REVISED MARCH 2000
APPLICATION INFORMATION
sequencing timing diagram
The following figures provide a timing diagram of how this device functions in different configurations.
Application condition; MR2 is tied to PG1, VIN1
and VIN2 are tied to same input voltage, the SEQ
pin is tied to logic low and the device is toggled
with enable (EN) function.
When the device is enabled (EN is pulled low)
VOUT1 will turn on first and VOUT2 will remain off
until VOUT1 reaches to approximately 83% of its
regulated output voltage. At that time VOUT2 will
be turned on. When VOUT1 reaches to 95% of its
regulated output the PG1 will turn on (active high).
Since MR2 is connected to PG1 for this
application, it will follow the logic of PG1. When
VOUT2 reaches to 95% of its regulated voltage,
RESET will switch to high voltage level after
120 ms delay (see Figure 37).
TPS701xxPWP
(Fixed Output Option)
VIN
VIN1
0.1 µF
VOUT1
VOUT1
10 µF
VSENSE1
PG1
VIN2
0.1 µF
>2 V
EN
EN
<0.7 V
MR2
MR2
RESET
RESET
MR1
MR1
VSENSE2
SEQ
VOUT2
VOUT2
10 µF
EN
SEQ
VOUT2
95%
83%
VOUT1
95%
83%
PG1
MR1
MR2
(MR2 tied to PG1)
RESET
t1
120ms
Figure 37. Timing When SEQ = Low
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
21
TPS70145, TPS70148, TPS70151, TPS70158, TPS70102
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS
SLVS222A – DECEMBER 1999 – REVISED MARCH 2000
APPLICATION INFORMATION
Application condition; MR2 is tied to PG1, VIN1
and VIN2 are tied to same input voltage, the SEQ
pin is tied to logic high and the device is toggled
with enable (EN) function.
TPS701xxPWP
(Fixed Output Option)
VIN
VIN1
0.1 µF
When the device is enabled (EN is pulled low),
VOUT2 will begin to power up and when it reaches
to 83% of its regulated voltage, VOUT1 will begin
to power up. PG1 will turn on when VOUT1 reaches
95% of its regulated voltage, and since MR2 and
PG1 is tied together, MR2 will follow the logic of
the PG1 output. When VOUT1 reaches 95% of its
regulated voltage, RESET will switch to high
voltage level after 120 ms delay (see Figure 38).
VOUT1
VOUT1
10 µF
VSENSE1
PG1
VIN2
0.1 µF
EN
EN
MR2
MR2
RESET
RESET
MR1
MR1
>2 V
VSENSE2
<0.7 V
SEQ
VOUT2
VOUT2
10 µF
EN
SEQ
VOUT2
95%
83%
VOUT1
95%
83%
PG1
MR1
MR2
(MR2 tied to PG1)
RESET
t1
120ms
Figure 38. Timing When SEQ = High
22
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TPS70145, TPS70148, TPS70151, TPS70158, TPS70102
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS
SLVS222A – DECEMBER 1999 – REVISED MARCH 2000
APPLICATION INFORMATION
Application condition; MR2 is tied to PG1, VIN1
and VIN2 are tied to same input voltage, the SEQ
pin is tied to logic high and MR1 is toggled.
TPS701xxPWP
(Fixed Output Option)
VIN
VIN1
When the device is enabled (EN is pulled low),
VOUT2 will begin to power up and when it reaches
to 83% of its regulated voltage, VOUT1 will begin
to power up. PG1 will turn on when VOUT1 reaches
to 95% of its regulated voltage, and since the MR2
and PG1 is tied together, MR2 will follow the logic
of the PG1 output. When VOUT1 reaches to 95%
of its regulated voltage, the RESET will switch to
high voltage level after 120 ms delay. When MR1
is toggled, it causes RESET to occur but the
regulators will remain in regulation. (see
Figure 39)
0.1 µF
VOUT1
VOUT1
10 µF
VSENSE1
PG1
VIN2
0.1 µF
EN
EN
MR2
MR2
RESET
RESET
MR1
>2 V
MR1
2V
0.7 V
VSENSE2
<0.7 V
SEQ
VOUT2
VOUT2
10 µF
EN
SEQ
VOUT2
95%
83%
VOUT1
95%
83%
PG1
MR1
MR2
(MR2 tied to PG1)
RESET
120ms
t1
120ms
Figure 39. Timing When MR1 is Toggled
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
23
TPS70145, TPS70148, TPS70151, TPS70158, TPS70102
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS
SLVS222A – DECEMBER 1999 – REVISED MARCH 2000
APPLICATION INFORMATION
Application condition; MR2 is tied to PG1, VIN1
and VIN2 are tied to same input voltage, the SEQ
pin is tied to logic high and VOUT1 faults out.
TPS701xxPWP
(Fixed Output Option)
VIN
VIN1
VOUT2 will begin to power up when device is
enabled (EN is pulled low). When VOUT2 reaches
83% of its regulated voltage, then VOUT1 will begin
to power up.
0.1 µF
VOUT1
VSENSE1
VOUT1
10 µF
PG1
When VOUT1 reaches 95% of its regulated
voltage, the PG1 will turn on and RESET will
switch to high voltage level after 120 ms delay.
When VOUT1 faults out, VOUT2 remains powered
on. PG1 is tied to MR2 and they change state to
logic low. RESET will be driven by VOUT1. (see
Figure 40).
VIN2
0.1 µF
EN
EN
MR2
MR2
RESET
RESET
MR1
MR1
>2 V
VSENSE2
<0.7 V
SEQ
VOUT2
VOUT2
10 µF
EN
SEQUENCE
VOUT2
95%
83%
VOUT1
95%
83%
Vout1 faults out
PG1
MR1
MR2
(MR2 tied to PG1)
RESET
120ms
t1
t1 – Vout1 and Vout2 are greater than the PG thresholds and MR1 is logic high.
Figure 40. Timing When VOUT1 Faults Out
24
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TPS70145, TPS70148, TPS70151, TPS70158, TPS70102
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS
SLVS222A – DECEMBER 1999 – REVISED MARCH 2000
APPLICATION INFORMATION
Application condition; MR2 is tied to PG1, VIN1
and VIN2 are tied to same input voltage, the SEQ
is tied to logic high, device is enabled, and VOUT2
faults out.
TPS701xxPWP
(Fixed Output Option)
VIN
VIN1
0.1 µF
When VOUT2 faults out. VOUT2 will begin to power
up when device is enabled (EN is pulled low).
When VOUT2 reaches 95% of its regulated
voltage, then VOUT1 will begin to power up. When
VOUT1 reaches 95% of its regulated voltage, PG1
will turn on and RESET will switch to high voltage
level after 120 ms delay. When VOUT2 faults out,
VOUT1 will be powered down. PG1 is tied to MR2
and they change state to logic low. RESET will be
driven by VOUT2.(see Figure 41).
VOUT1
VSENSE1
VOUT1
10 µF
PG1
VIN2
0.1 µF
EN
EN
MR2
MR2
RESET
RESET
MR1
MR1
>2 V
VSENSE2
<0.7 V
SEQ
VOUT2
VOUT2
10 µF
ENABLE
SEQUENCE
VOUT2
95%
83%
VOUT1
Vout2 faults out
95%
83%
PG1
MR1
MR2
(MR2 tied to PG1)
RESET
120ms
t1
t1 – Vout1 and Vout2 are greater than the PG thresholds and MR1 is logic high.
Figure 41. Timing When VOUT2 Faults Out
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
25
TPS70145, TPS70148, TPS70151, TPS70158, TPS70102
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS
SLVS222A – DECEMBER 1999 – REVISED MARCH 2000
APPLICATION INFORMATION
split voltage DSP application
Figure 42 shows a typical application where the TPS70151 is powering up a DSP. In this application by grounding
the SEQ pin, VOUT1(I/O) will be powered up first, and then VOUT2(core).
TPS70151 PWP
5V
3.3 V
VOUT1
VIN1
0.1 µF
10 µF
VSENSE1
250 kΩ
PG1
PG1
MR2
VIN2
MR2
>2 V
<0.7 V
0.1 µF
>2 V
EN
250 kΩ
RESET
RESET
MR1
EN
DSP
MR1
>2 V
<0.7 V
<0.7 V
VSENSE2
SEQ
1.8 V
VOUT2
10 µF
EN
SEQ
VOUT2
(Core)
95%
83%
VOUT1
(I/O)
95%
83%
PG1
RESET
t1
120ms
Figure 42. Application Timing Diagram (SEQ = Low)
26
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
Core
I/O
TPS70145, TPS70148, TPS70151, TPS70158, TPS70102
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS
SLVS222A – DECEMBER 1999 – REVISED MARCH 2000
APPLICATION INFORMATION
split voltage DSP application
Figure 43 shows a typical application where the TPS70151 is powering up a DSP. In this application by pulling
up the SEQ pin, VOUT2(Core) will be powered up first, and then VOUT1(I/O).
TPS70151 PWP
5V
0.1 µF
3.3 V
VOUT1
VIN1
10 µF
VSENSE1
MR2
MR2
RESET
RESET
MR1
EN
EN
250 kΩ
250 kΩ
0.1 µF
>2 V
<0.7 V
I/O
PG1
PG1
VIN2
DSP
MR1
VSENSE2
SEQ
1.8 V
VOUT2
Core
10 µF
EN
SEQ
VOUT2
(Core)
95%
83%
VOUT1
(I/O)
95%
83%
PG1
RESET
120ms
t1
Figure 43. Application Timing Diagram (SEQ = High)
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
27
TPS70145, TPS70148, TPS70151, TPS70158, TPS70102
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS
SLVS222A – DECEMBER 1999 – REVISED MARCH 2000
APPLICATION INFORMATION
input capacitor
For a typical application, an input bypass capacitor (0.1 µF – 1 µF) is recommended. This capacitor will filter
any high frequency noise generated in the line. For fast transient condition where droop at the input of the LDO
may occur due to high inrush current, it is recommended to place a larger capacitor at the input as well. The
size of this capacitor is dependant on the output current and response time of the main power supply, as well
as the distance to the load (LDO).
output capacitor
As with most LDO regulators, the TPS701xx requires an output capacitor connected between OUT and GND
to stabilize the internal control loop. The minimum recommended capacitance value is 10 µF and the ESR
(equivalent series resistance) must be between 50 mΩ and 2.5 Ω. Capacitor values 10 µF or larger are
acceptable, provided the ESR is less than 2.5 Ω. Solid tantalum electrolytic, aluminum electrolytic, and
multilayer ceramic capacitors are all suitable, provided they meet the requirements described above. Larger
capacitors provide a wider range of stability and better load transient response. Below is a partial listing of
surface-mount capacitors usable with the TPS701xx. for fast transient response application.
This information, along with the ESR graphs, is included to assist in selection of suitable capacitance for the
user’s application. When necessary to achieve low height requirements along with high output current and/or
high load capacitance, several higher ESR capacitors can be used in parallel to meet the guidelines above.
VALUE
MFR.
MAX ESR†
22 µF
Kemet
345 mΩ
7495C226K0010AS
33 µF
Sanyo
100 mΩ
10TPA33M
47 µF
Sanyo
100 mΩ
6TPA47M
68 µF
Sanyo
45 mΩ
10TPC68M
PART NO.
ESR and transient response
LDOs typically require an external output capacitor for stability. In fast transient response applications,
capacitors are used to support the load current while LDO amplifier is responding. In most applications, one
capacitor is used to support both functions.
Besides its capacitance, every capacitor also contains parasitic impedances. These parasitic impedances are
resistive as well as inductive. The resistive impedance is called equivalent series resistance (ESR), and the
inductive impedance is called equivalent series inductance (ESL). The equivalent schematic diagram of any
capacitor can therefore be drawn as shown in Figure 44.
RESR
LESL
C
Figure 44. – ESR and ESL
In most cases one can neglect the effect of inductive impedance ESL. Therefore, the following application
focuses mainly on the parasitic resistance ESR.
28
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TPS70145, TPS70148, TPS70151, TPS70158, TPS70102
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS
SLVS222A – DECEMBER 1999 – REVISED MARCH 2000
APPLICATION INFORMATION
Figure 45 shows the output capacitor and its parasitic impedances in a typical LDO output stage.
IO
LDO
+
VESR
RESR
–
VI
RLOAD
VO
CO
Figure 45. – LDO Output Stage With Parasitic Resistances ESR and ESL
In steady state (dc state condition), the load current is supplied by the LDO (solid arrow) and the voltage across
the capacitor is the same as the output voltage (V(CO) = VO). This means no current is flowing into the CO
branch. If IO suddenly increases (transient condition), the following occurs;
The LDO is not able to supply the sudden current need due to its response time (t1 in Figure 46). Therefore,
capacitor CO provides the current for the new load condition (dashed arrow). CO now acts like a battery with
an internal resistance, ESR. Depending on the current demand at the output, a voltage drop will occur at RESR.
This voltage is shown as VESR in Figure 45.
When CO is conducting current to the load, initial voltage at the load will be VO = V(CO) – VESR. Due to the
discharge of CO, the output voltage VO will drop continuously until the response time t1 of the LDO is reached
and the LDO will resume supplying the load. From this point, the output voltage starts rising again until it reaches
the regulated voltage. This period is shown as t2 in Figure 46.
The figure also shows the impact of different ESRs on the output voltage. The left brackets show different levels
of ESRs where number 1 displays the lowest and number 3 displays the highest ESR.
From above, the following conclusions can be drawn:
D
D
The higher the ESR, the larger the droop at the beginning of load transient.
The smaller the output capacitor, the faster the discharge time and the bigger the voltage droop during the
LDO response period.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
29
TPS70145, TPS70148, TPS70151, TPS70158, TPS70102
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS
SLVS222A – DECEMBER 1999 – REVISED MARCH 2000
APPLICATION INFORMATION
conclusion
To minimize the transient output droop, capacitors must have a low ESR and be large enough to support the
minimum output voltage requirement.
IO
VO
1
2
ESR 1
3
ESR 2
ESR 3
t1
t2
Figure 46. – Correlation of Different ESRs and Their Influence to the Regulation of VO at a
Load Step From Low-to-High Output Current
30
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TPS70145, TPS70148, TPS70151, TPS70158, TPS70102
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS
SLVS222A – DECEMBER 1999 – REVISED MARCH 2000
APPLICATION INFORMATION
programming the TPS70102 adjustable LDO regulator
The output voltage of the TPS70102 adjustable regulators are programmed using external resistor dividers as
shown in Figure 47.
Resistors R1 and R2 should be chosen for approximately 50 µA divider current. Lower value resistors can be
used, but offer no inherent advantage and waste more power. Higher values should be avoided as leakage
currents at the sense terminal increase the output voltage error. The recommended design procedure is to
choose R2 = 30.1 kΩ to set the divider current at approximately 50 µA and then calculate R1 using:
R1
+
ǒ Ǔ
V
V
O
ref
*1
R2
Where:
Vref = 1.224 V typ (the internal reference voltage)
OUTPUT VOLTAGE
PROGRAMMING GUIDE
TPS70102
VI
OUTPUT
VOLTAGE
IN
0.1 µF
>2.0 V
OUT
EN
VO
<0.7V
R1
+
R1
R2
UNIT
2.5 V
33.5
30.1
kΩ
3.3 V
53.6
30.1
kΩ
3.6 V
61.9
30.1
kΩ
FB
GND
R2
Figure 47. TPS70102 Adjustable LDO Regulator Programming
regulator protection
Both TPS701xx PMOS-pass transistors have built-in back diodes that conduct reverse currents when the input
voltage drops below the output voltage (e.g., during power down). Current is conducted from the output to the
input and is not internally limited. When extended reverse voltage is anticipated, external limiting may be
appropriate.
The TPS701xx also features internal current limiting and thermal protection. During normal operation, the
TPS701xx regulator 1 limits output current to approximately 1.6 A (typ) and regulator 2 limits output current to
approximately 750 mA (typ). When current limiting engages, the output voltage scales back linearly until the
overcurrent condition ends. While current limiting is designed to prevent gross device failure, care should be
taken not to exceed the power dissipation ratings of the package. If the temperature of the device exceeds
150°C(typ), thermal-protection circuitry shuts it down. Once the device has cooled below 130°C(typ), regulator
operation resumes.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
31
TPS70145, TPS70148, TPS70151, TPS70158, TPS70102
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS
SLVS222A – DECEMBER 1999 – REVISED MARCH 2000
power dissipation and junction temperature
Specified regulator operation is assured to a junction temperature of 125°C; the maximum junction temperature
should be restricted to 125°C under normal operating conditions. This restriction limits the power dissipation
the regulator can handle in any given application. To ensure the junction temperature is within acceptable limits,
calculate the maximum allowable dissipation, PD(max), and the actual dissipation, PD, which must be less than
or equal to PD(max).
The maximum-power-dissipation limit is determined using the following equation:
P
T max * T
J
A
+
D(max)
R
qJA
Where:
TJmax is the maximum allowable junction temperature.
RθJA is the thermal resistance junction-to-ambient for the package, i.e., 32.6°C/W for the 20-terminal
PWP with no airflow.
TA is the ambient temperature.
ǒ
Ǔ
The regulator dissipation is calculated using:
P
D
+ VI * VO
I
O
Power dissipation resulting from quiescent current is negligible. Excessive power dissipation will trigger the
thermal protection circuit.
32
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TPS70145, TPS70148, TPS70151, TPS70158, TPS70102
DUAL-OUTPUT LOW-DROPOUT VOLTAGE REGULATORS
WITH POWER UP SEQUENCING FOR SPLIT VOLTAGE DSP SYSTEMS
SLVS222A – DECEMBER 1999 – REVISED MARCH 2000
MECHANICAL DATA
PWP (R-PDSO-G**)
PowerPAD PLASTIC SMALL-OUTLINE PACKAGE
20-PIN SHOWN
0,30
0,19
0,65
20
0,10 M
11
Thermal Pad
(See Note D)
4,50
4,30
0,15 NOM
6,60
6,20
Gage Plane
1
10
0,25
A
0°– 8°
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
14
16
20
24
28
A MAX
5,10
5,10
6,60
7,90
9,80
A MIN
4,90
4,90
6,40
7,70
9,60
DIM
4073225/E 03/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusions.
The package thermal performance may be enhanced by bonding the thermal pad to an external thermal plane. This pad is electrically
and thermally connected to the backside of the die and possibly selected leads.
E. Falls within JEDEC MO-153
PowerPAD is a trademark of Texas Instruments Incorporated.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
33
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