2.5 V to 5.5 V, 500 A, 2-Wire Interface Quad Voltage Output, 8-/10-/12-Bit DACs AD5305/AD5315/AD5325* FEATURES AD5305: 4 Buffered 8-Bit DACs in 10-Lead MSOP A Version: ⴞ1 LSB INL, B Version: ⴞ0.625 LSB INL AD5315: 4 Buffered 10-Bit DACs in 10-Lead MSOP A Version: ⴞ4 LSB INL, B Version: ⴞ2.5 LSB INL AD5325: 4 Buffered 12-Bit DACs in 10-Lead MSOP A Version: ⴞ16 LSB INL, B Version: ⴞ10 LSB INL Low Power Operation: 500 A @ 3 V, 600 A @ 5 V 2-Wire (I 2C® Compatible) Serial Interface 2.5 V to 5.5 V Power Supply Guaranteed Monotonic by Design over All Codes Power-Down to 80 nA @ 3 V, 200 nA @ 5 V Three Power-Down Modes Double-Buffered Input Logic Output Range: 0 V to V REF Power-On Reset to 0 V Simultaneous Update of Outputs (LDAC Function) Software Clear Facility Data Readback Facility On-Chip Rail-to-Rail Output Buffer Amplifiers Temperature Range –40ⴗC to +105ⴗC GENERAL DESCRIPTION The AD5305/AD5315/AD5325 are quad 8-, 10-, and 12-bit buffered voltage output DACs in a 10-lead MSOP that operate from a single 2.5 V to 5.5 V supply, consuming 500 µA at 3 V. Their on-chip output amplifiers allow rail-to-rail output swing with a slew rate of 0.7 V/µs. A 2-wire serial interface, which operates at clock rates up to 400 kHz, is used. This interface is SMBus compatible at VDD < 3.6 V. Multiple devices can be placed on the same bus. The references for the four DACs are derived from one reference pin. The outputs of all DACs may be updated simultaneously using the software LDAC function. The parts incorporate a power-on reset circuit, which ensures that the DAC outputs power up to 0 V and remain there until a valid write takes place to the device. There is also a software clear function that resets all input and DAC registers to 0 V. The parts contain a power-down feature that reduces the current consumption of the devices to 200 nA @ 5 V (80 nA @ 3 V). The low power consumption of these parts in normal operation makes them ideally suited to portable battery-operated equipment. The power consumption is 3 mW at 5 V, 1.5 mW at 3 V, reducing to 1 µW in power-down mode. APPLICATIONS Portable Battery-Powered Instruments Digital Gain and Offset Adjustment Programmable Voltage and Current Sources Programmable Attenuators Industrial Process Control FUNCTIONAL BLOCK DIAGRAM VDD REF IN LDAC SCL SDA INPUT REGISTER DAC REGISTER STRING DAC A BUFFER VOUTA INPUT REGISTER DAC REGISTER STRING DAC B BUFFER VOUTB INPUT REGISTER DAC REGISTER STRING DAC C BUFFER VOUTC INPUT REGISTER DAC REGISTER STRING DAC D BUFFER VOUTD INTERFACE LOGIC A0 POWER-ON RESET AD5305/AD5315/AD5325 POWER-DOWN LOGIC GND *Protected by U.S.Patent No. 5,969,657and 5,684,481. REV. F Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © 2004 Analog Devices, Inc. All rights reserved. AD5305/AD5315/AD5325–SPECIFICATIONS (VDD = 2.5 V to 5.5 V; VREF = 2 V; RL = 2 k⍀ to GND; CL = 200 pF to GND; all specifications TMIN to TMAX, unless otherwise noted.) Parameter1 Min A Version2 Typ Max Min B Version2 Typ Max Unit Conditions/Comments 3, 4 DC PERFORMANCE AD5305 Resolution Relative Accuracy Differential Nonlinearity 8 ± 0.15 ± 0.02 ±1 ± 0.25 8 ± 0.15 ± 0.02 ± 0.625 ± 0.25 Bits LSB LSB AD5315 Resolution Relative Accuracy Differential Nonlinearity 10 ± 0.5 ± 0.05 ±4 ± 0.5 10 ± 0.5 ± 0.05 ± 2.5 ± 0.5 Bits LSB LSB AD5325 Resolution Relative Accuracy Differential Nonlinearity 12 ±2 ± 0.2 ± 16 ±1 12 ±2 ± 0.2 ± 10 ±1 Bits LSB LSB Offset Error Gain Error Lower Deadband ± 0.4 ± 0.15 20 ±3 ±1 60 ± 0.4 ± 0.15 20 ±3 ±1 60 % of FSR % of FSR mV Offset Error Drift 5 Gain Error Drift 5 Power Supply Rejection Ratio 5 DC Crosstalk5 –12 –5 –60 200 DAC REFERENCE INPUTS 5 VREF Input Range VREF Input Impedance 0.25 37 Reference Feedthrough OUTPUT CHARACTERISTICS 5 Minimum Output Voltage 6 Maximum Output Voltage 6 DC Output Impedance Short Circuit Current Power-Up Time VDD 0.25 37 VDD V kΩ MΩ dB 0.001 0.001 V VDD – 0.001 0.5 25 16 2.5 VDD – 0.001 0.5 25 16 2.5 V Ω mA mA µs 5 5 µs ±1 0.8 0.6 0.5 VIH, Input High Voltage 2.4 2.1 2.0 Pin Capacitance ±1 0.8 0.6 0.5 2.4 2.1 2.0 3 Guaranteed Monotonic by Design over All Codes Guaranteed Monotonic by Design over All Codes Lower deadband exists only if offset error is negative. ppm of FSR/°C ppm of FSR/°C dB ⌬VDD = ± 10% µV RL = 2 kΩ to GND or VDD 45 >10 –90 45 >10 –90 LOGIC INPUTS (A0) 5 Input Current VIL, Input Low Voltage LOGIC INPUTS (SCL, SDA) VIH, Input High Voltage VIL, Input Low Voltage IIN, Input Leakage Current VHYST, Input Hysteresis CIN, Input Capacitance Glitch Rejection –12 –5 –60 200 Guaranteed Monotonic by Design over All Codes 3 µA V V V V V V pF Normal Operation Power-Down Mode Frequency = 10 kHz This is a measure of the minimum and maximum drive capability of the output amplifier. VDD = 5 V VDD = 3 V Coming out of Power-Down Mode. VDD = 5 V Coming out of Power-Down Mode. VDD = 3 V VDD = 5 V ± VDD = 3 V ± VDD = 2.5 V VDD = 5 V ± VDD = 3 V ± VDD = 2.5 V 10% 10% 10% 10% 5 0.7 VDD –0.3 VDD + 0.3 0.7 VDD 0.3 VDD –0.3 ±1 0.05 VDD 0.05 VDD 0.4 0.6 ±1 0.4 0.6 ±1 8 LOGIC OUTPUT (SDA) 5 VOL, Output Low Voltage Three-State Leakage Current Three-State Output Capacitance 50 VDD + 0.3 V 0.3 VDD V ±1 µA V pF 50 ns 8 8 8 –2– V V µA pF SMBus Compatible at VDD < 3.6 V SMBus Compatible at VDD < 3.6 V Input filtering suppresses noise spikes of less than 50 ns. ISINK = 3 mA ISINK = 6 mA REV. F AD5305/AD5315/AD5325 Parameter 1 Min POWER REQUIREMENTS VDD IDD (Normal Mode) 7 VDD = 4.5 V to 5.5 V VDD = 2.5 V to 3.6 V IDD (Power-Down Mode) VDD = 4.5 V to 5.5 V A Version2 Typ 2.5 VDD = 2.5 V to 3.6 V Max Min 5.5 2.5 B Version2 Typ Max Unit 5.5 V 600 500 900 700 600 500 900 700 µA µA 0.2 1 0.2 1 µA 0.08 1 0.08 1 µA Conditions/Comments VIH = VDD and VIL = GND VIH = VDD and VIL = GND IDD = 4 µA (Max) During 0 Readback on SDA IDD = 1.5 µA (Max) During 0 Readback on SDA NOTES 1 See the Terminology section. 2 Temperature range (A, B Version): –40°C to +105°C; typical at +25°C. 3 DC specifications tested with the outputs unloaded. 4 Linearity is tested using a reduced code range: AD5305 (Code 8 to 248); AD5315 (Code 28 to 995); AD5325 (Code 115 to 3981). 5 Guaranteed by design and characterization, not production tested. 6 For the amplifier output to reach its minimum voltage, offset error must be negative; to reach its maximum voltage, V REF = VDD and offset plus gain error must be positive. 7 IDD specification is valid for all DAC codes. Interface inactive. All DACs active and excluding load currents. Specifications subject to change without notice. (VDD = 2.5 V to 5.5 V; RL = 2 k⍀ to GND; CL = 200 pF to GND; all specifications TMIN to TMAX, unless AC CHARACTERISTICS1 otherwise noted.) Parameter 2 Output Voltage Settling Time AD5305 AD5315 AD5325 Slew Rate Major-Code Transition Glitch Energy Digital Feedthrough Digital Crosstalk DAC-to-DAC Crosstalk Multiplying Bandwidth Total Harmonic Distortion A, B Version3 Min Typ Max Unit 6 7 8 0.7 12 1 1 3 200 –70 µs µs µs V/µs nV-s nV-s nV-s nV-s kHz dB 8 9 10 NOTES 1 Guaranteed by design and characterization, not production tested. 2 See the Terminology section. 3 Temperature range (A, B Version): –40°C to +105°C; typical at +25°C. Specifications subject to change without notice. REV. F –3– Conditions/Comments VREF = VDD = 5 V 1/4 Scale to 3/4 Scale Change (0x40 to 0xC0) 1/4 Scale to 3/4 Scale Change (0x100 to 0x300) 1/4 Scale to 3/4 Scale Change (0x400 to 0xC00) 1 LSB Change around Major Carry VREF = 2 V ± 0.1 V p-p VREF = 2.5 V ± 0.1 V p-p, Frequency = 10 kHz AD5305/AD5315/AD5325 TIMING CHARACTERISTICS1, 2 Parameter fSCL t1 t2 t3 t4 t5 t6 3 t7 t8 t9 t10 t11 CB (VDD = 2.5 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted.) Limit at TMIN, TMAX (A, B Version) Unit Conditions/Comments 400 2.5 0.6 1.3 0.6 100 0.9 0 0.6 0.6 1.3 300 0 250 0 300 20 + 0.1CB4 400 kHz max µs min µs min µs min µs min ns min µs max µs min µs min µs min µs min ns max ns min ns max ns min ns max ns min pF max SCL Clock Frequency SCL Cycle Time tHIGH, SCL High Time tLOW, SCL Low Time tHD,STA, Start/Repeated Start Condition Hold Time tSU,DAT, Data Setup Time tHD,DAT, Data Hold Time tHD,DAT, Data Hold Time tSU,STA, Setup Time for Repeated Start tSU,STO, Stop Condition Setup Time tBUF, Bus Free Time between a STOP and a START Condition tR, Rise Time of SCL and SDA when Receiving tR, Rise Time of SCL and SDA when Receiving (CMOS Compatible) tF, Fall Time of SDA when Transmitting tF, Fall Time of SDA when Receiving (CMOS Compatible) tF, Fall Time of SCL and SDA when Receiving tF, Fall Time of SCL and SDA when Transmitting Capacitive Load for Each Bus Line NOTES 1 See Figure 1. 2 Guaranteed by design and characterization; not production tested. 3 A master device must provide a hold time of at least 300 ns for the SDA signal (referred to V IH min of the SCL signal) in order to bridge the undefined region of SCL’s falling edge. 4 CB is the total capacitance of one bus line in pF. t R and tF measured between 0.3 V DD and 0.7 VDD. Specifications subject to change without notice. SDA t9 t3 t 10 t 11 t4 SCL t4 START CONDITION t6 t2 t1 t5 t8 t7 REPEATED START CONDITION STOP CONDITION Figure 1. 2-Wire Serial Interface Timing Diagram –4– REV. F AD5305/AD5315/AD5325 ABSOLUTE MAXIMUM RATINGS 1, 2 MSOP Power Dissipation . . . . . . . . . . . . . . . . . . . (TJ max – TA)/JA JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 206°C/W JC Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 44°C/W Reflow Soldering Peak Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C Time at Peak Temperature . . . . . . . . . . . . . 10 sec to 40 sec (TA = 25°C, unless otherwise noted.) VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V SCL, SDA to GND . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V A0 to GND . . . . . . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V Reference Input Voltage to GND . . . . . –0.3 V to VDD + 0.3 V VOUT A–D to GND . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V Operating Temperature Range Industrial (A, B Version) . . . . . . . . . . . . . . –40°C to +105°C Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C Junction Temperature (TJ max) . . . . . . . . . . . . . . . . . . . 150°C NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Transient currents of up to 100 mA will not cause SCR latch-up. ORDERING GUIDE Model AD5305ARM AD5305ARM-REEL7 AD5315ARM AD5315ARM-REEL7 AD5325ARM AD5325ARM-REEL7 AD5305BRM AD5305BRM-REEL AD5305BRM-REEL7 AD5315BRM AD5315BRM-REEL AD5315BRM-REEL7 AD5325BRM AD5325BRM-REEL AD5325BRM-REEL7 Temperature Range Package Description Package Option Branding –40°C to +105°C –40°C to +105°C –40°C to +105°C –40°C to +105°C –40°C to +105°C –40°C to +105°C –40°C to +105°C –40°C to +105°C –40°C to +105°C –40°C to +105°C –40°C to +105°C –40°C to +105°C –40°C to +105°C –40°C to +105°C –40°C to +105°C 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP 10-Lead MSOP RM-10 RM-10 RM-10 RM-10 RM-10 RM-10 RM-10 RM-10 RM-10 RM-10 RM-10 RM-10 RM-10 RM-10 RM-10 DEA DEA DFA DFA DGA DGA DEB DEB DEB DFB DFB DFB DGB DGB DGB CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD5305/AD5315/AD5325 feature proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV. F –5– AD5305/AD5315/AD5325 PIN CONFIGURATION VDD 1 VOUTA 2 VOUTB 3 VOUTC 4 REFIN 5 10 A0 AD5305/ AD5315/ AD5325 TOP VIEW (Not to Scale) 9 SCL 8 SDA 7 GND 6 VOUTD PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Function 1 VDD Power Supply Input. These parts can be operated from 2.5 V to 5.5 V and the supply should be decoupled to GND. 2 VOUTA Buffered Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation. 3 VOUTB Buffered Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation. 4 VOUTC Buffered Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation. 5 REFIN Reference Input Pin for All Four DACs. It has an input range from 0.25 V to VDD. 6 VOUTD Buffered Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation. 7 GND Ground Reference Point for All Circuitry on the Part. 8 SDA Serial Data Line. This is used in conjunction with the SCL line to clock data into or out of the 16-bit input shift register. It is a bidirectional open-drain data line that should be pulled to the supply with an external pull-up resistor. 9 SCL Serial Clock Line. This is used in conjunction with the SDA line to clock data into or out of the 16-bit input shift register. Clock rates of up to 400 kbit/s can be accommodated in the 2-wire interface. 10 A0 Address Input. Sets the least significant bit of the 7-bit slave address. TERMINOLOGY Relative Accuracy Offset Error Drift This is a measure of the change in offset error with changes in temperature. It is expressed in (ppm of full-scale range)/°C. For the DAC, relative accuracy or integral nonlinearity (INL) is a measure of the maximum deviation, in LSB, from a straight line passing through the endpoints of the DAC transfer function. Typical INL versus code plots can be seen in TPCs 1, 2, and 3. Gain Error Drift This is a measure of the change in gain error with changes in temperature. It is expressed in (ppm of full-scale range)/°C. Differential Nonlinearity Power Supply Rejection Ratio (PSRR) Differential nonlinearity (DNL) is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of ± 1 LSB maximum ensures monotonicity. This DAC is guaranteed monotonic by design. Typical DNL versus code plots can be seen in TPCs 4, 5, and 6. This indicates how the output of the DAC is affected by changes in the supply voltage. PSRR is the ratio of the change in VOUT to a change in VDD for full-scale output of the DAC. It is measured in dB. VREF is held at 2 V and VDD is varied ± 10%. DC Crosstalk This is the dc change in the output level of one DAC at midscale in response to a full-scale code change (all 0s to all 1s and vice versa) and output change of another DAC. It is expressed in µV. Offset Error This is a measure of the offset error of the DAC and the output amplifier. It is expressed as a percentage of the full-scale range. Reference Feedthrough Gain Error This is the ratio of the amplitude of the signal at the DAC output to the reference input when the DAC output is not being updated. It is expressed in dB. This is a measure of the span error of the DAC. It is the deviation in slope of the actual DAC transfer characteristic from the ideal expressed as a percentage of the full-scale range. –6– REV. F AD5305/AD5315/AD5325 Major-Code Transition Glitch Energy Major-code transition glitch energy is the energy of the impulse injected into the analog output when the code in the DAC register changes state. It is normally specified as the area of the glitch in nV-s and is measured when the digital code is changed by 1 LSB at the major carry transition (011 . . . 11 to 100 . . . 00, or 100 . . . 00 to 011 . . . 11). GAIN ERROR PLUS OFFSET ERROR OUTPUT VOLTAGE IDEAL ACTUAL Digital Feedthrough Digital feedthrough is a measure of the impulse injected into the analog output of the DAC from the digital input pins of the device when the DAC output is not being updated. It is specified in nV-s and is measured with a worst-case change on the digital input pins, e.g., from all 0s to all 1s or vice versa. NEGATIVE OFFSET ERROR DAC CODE Digital Crosstalk This is the glitch impulse transferred to the output of one DAC at midscale in response to a full-scale code change (all 0s to all 1s and vice versa) in the input register of another DAC. It is expressed in nV-s. DEAD BAND CODES DAC-to-DAC Crosstalk AMPLIFIER FOOTROOM (1mV) This is the glitch impulse transferred to the output of one DAC due to a digital code change and subsequent output change of another DAC. This includes both digital and analog crosstalk. It is measured by loading one of the DACs with a full-scale code change (all 0s to all 1s and vice versa) with the LDAC bit set low and monitoring the output of another DAC. The energy of the glitch is expressed in nV-s. NEGATIVE OFFSET ERROR Figure 2. Transfer Function with Negative Offset Multiplying Bandwidth The amplifiers within the DAC have a finite bandwidth. The multiplying bandwidth is a measure of this. A sine wave on the reference (with full-scale code loaded to the DAC) appears on the output. The multiplying bandwidth is the frequency at which the output amplitude falls to 3 dB below the input. ACTUAL GAIN ERROR PLUS OFFSET ERROR OUTPUT VOLTAGE Total Harmonic Distortion This is the difference between an ideal sine wave and its attenuated version using the DAC. The sine wave is used as the reference for the DAC and the THD is a measure of the harmonics present on the DAC output. It is measured in dB. IDEAL POSITIVE OFFSET DAC CODE Figure 3. Transfer Function with Positive Offset REV. F –7– AD5305/AD5315/AD5325–Typical Performance Characteristics 12 3 1.0 TA = 25ⴗC VDD = 5V TA = 25ⴗC VDD = 5V TA = 25ⴗC VDD = 5V 8 2 0 INL ERROR (LSB) INL ERROR (LSB) INL ERROR (LSB) 0.5 1 0 –1 4 0 –4 –0.5 –8 –2 –1.0 0 50 100 150 CODE 200 –3 250 TPC 1. AD5305 Typical INL Plot 0.3 TA = 25ⴗC VDD = 5V 0.2 –12 0 200 400 600 CODE 800 1000 0 1000 2000 CODE 3000 4000 TPC 2. AD5315 Typical INL Plot TPC 3. AD5325 Typical INL Plot 0.6 1.0 TA = 25ⴗC VDD = 5V TA = 25ⴗC VDD = 5V 0.4 0 –0.1 DNL ERROR (LSB) DNL ERROR (LSB) DNL ERROR (LSB) 0.5 0.1 0.2 0 –0.2 0 –0.5 –0.2 –0.3 –0.4 0 50 100 150 CODE 200 –0.6 250 TPC 4. AD5305 Typical DNL Plot –1.0 0 400 200 600 CODE 800 0 1000 0.5 VDD = 5V TA = 25ⴗC 0.4 0.3 2000 CODE 3000 4000 TPC 6. AD5325 Typical DNL Plot TPC 5. AD5315 Typical DNL Plot 0.50 1000 1.0 VDD = 5V VREF = 3V VDD = 5V VREF = 2V MAX INL OFFSET ERROR 0.5 0.25 0 MIN DNL MAX DNL 0.1 ERROR (%) MAX DNL ERROR (LSB) ERROR (LSB) 0.2 MAX INL 0 –0.1 0 MIN DNL GAIN ERROR –0.2 –0.5 –0.25 –0.3 MIN INL MIN INL –0.50 0 1 2 3 VREF (V) –0.4 4 TPC 7. AD5305 INL and DNL Error vs. VREF 5 –0.5 ⴚ40 0 40 80 TEMPERATURE (ⴰC) TPC 8. AD5305 INL and DNL Error vs. Temperature –8– 120 –1.0 ⴚ40 0 40 80 120 TEMPERATURE (ⴰC) TPC 9. AD5305 Offset Error and Gain Error vs. Temperature REV. F AD5305/AD5315/AD5325 0.2 5 TA = 25ⴰC VREF = 2V 0.1 5V SOURCE 500 3V SOURCE 400 4 0 –0.1 3 IDD (A) –0.2 2 –0.3 300 200 –0.4 OFFSET ERROR 1 3V SINK 100 5V SINK –0.5 –0.6 TA = 25ⴰC VDD = 5V VREF =2V GAIN ERROR VOUT (V) ERROR (%) 600 0 1 2 3 VDD (V) 4 5 0 6 TPC 10. Offset Error and Gain Error vs. VDD 0 2 5 1 3 4 SINK/SOURCE CURRENT (mA) 0 6 ZERO SCALE TPC 11. VOUT Source and Sink Current Capability 600 TPC 12. Supply Current vs. DAC Code 0.5 750 ⴚ40ⴰC TA = 25ⴗC 500 0.4 +25ⴰC 650 300 0.3 ⴚ40ⴰC 0.2 ⴙ25ⴰC 200 INCREASING 550 VDD = 3V 0.1 100 ⴙ105ⴰC 0 2.5 3.0 3.5 4.0 VDD (V) 4.5 5.0 0 2.5 5.5 TPC 13. Supply Current vs. Supply Voltage CH1 DECREASING IDD (A) IDD (A) IDD (A) VDD = 5V +105ⴰC 400 FULL SCALE CODE TA = 25ⴗC 5µs VDD = 5V VREF = 5V SCL CH1 1V, CH2 5V, TIME BASE = 1s/DIV TPC 16. Half-Scale Settling (1/4 to 3/4 Scale Code Change) REV. F 3.5 4.0 VDD (V) 4.5 5.0 5.5 TPC 14. Power-Down Current vs. Supply Voltage CH1 VOUTA CH2 450 3.0 TA = 25ⴗC 5µs VDD = 5V VREF = 2V 0 1.0 2.0 3.0 VLOGIC (V) 4.0 TPC 15. Supply Current vs. Logic Input Voltage for SDA and SCL Voltage Increasing and Decreasing CH1 TA = 25ⴗC VDD = 5V VREF = 2V VOUTA VDD VOUTA SCL CH2 CH2 CH1 2V, CH2 200mV, TIME BASE = 200s/DIV TPC 17. Power-On Reset to 0 V –9– 5.0 CH1 500mV, CH2 5V, TIME BASE = 1s/DIV TPC 18. Exiting Power-Down to Midscale AD5305/AD5315/AD5325 2.50 10 0 VDD = 5V –10 2.49 –20 dB FREQUENCY VOUT (V) VDD = 3V –30 2.48 –40 –50 2.47 300 350 400 450 500 IDD (A) 550 600 –60 10 1s/DIV TPC 19. IDD Histogram with VDD = 3 V and VDD = 5 V TPC 20. AD5325 Major-Code Transition Glitch Energy 100 1k 10k 100k FREQUENCY (Hz) 1M 10M TPC 21. Multiplying Bandwidth (Small-Signal Frequency Response) 0.02 VDD = 5V 0.01 1mV/DIV FULL-SCALE ERROR (V) TA = 25ⴗC 0 –0.01 –0.02 0 1 2 3 VREF (V) 4 5 6 50ns/DIV TPC 22. Full-Scale Error vs. VREF TPC 23. DAC-to-DAC Crosstalk FUNCTIONAL DESCRIPTION where The AD5305/AD5315/AD5325 are quad resistor-string DACs fabricated on a CMOS process with resolutions of 8, 10, and 12 bits, respectively. Each contains four output buffer amplifiers and is written to via a 2-wire serial interface. They operate from single supplies of 2.5 V to 5.5 V, and the output buffer amplifiers provide rail-to-rail output swing with a slew rate of 0.7 V/µs. The four DACs share a single reference input pin. The devices have three programmable power-down modes, in which all DACs may be turned off completely with a high impedance output, or the outputs may be pulled low by on-chip resistors. D = decimal equivalent of the binary code, which is loaded to the DAC register: 0–255 for AD5305 (8 bits) 0–1023 for AD5315 (10 bits) 0–4095 for AD5325 (12 bits) N = DAC resolution REFIN Digital-to-Analog Section The architecture of one DAC channel consists of a resistor-string DAC followed by an output buffer amplifier. The voltage at the REFIN pin provides the reference voltage for the DAC. Figure 4 shows a block diagram of the DAC architecture. Since the input coding to the DAC is straight binary, the ideal output voltage is given by VOUT = INPUT REGISTER DAC REGISTER RESISTOR STRING VOUTA OUTPUT BUFFER AMPLIFIER Figure 4. DAC Channel Architecture VREF × D 2N –10– REV. F AD5305/AD5315/AD5325 Resistor String SERIAL INTERFACE The resistor string section is shown in Figure 5. It is simply a string of resistors, each of value R. The digital code loaded to the DAC register determines at what node on the string the voltage is tapped off to be fed into the output amplifier. The voltage is tapped off by closing one of the switches connecting the string to the amplifier. Because it is a string of resistors, it is guaranteed monotonic. The AD5305/AD5315/AD5325 are controlled via an I2C compatible serial bus. The DACs are connected to this bus as slave devices (i.e., no clock is generated by the AD5305/AD5315/ AD5325 DACs). This interface is SMBus compatible at VDD < 3.6 V. The AD5305/AD5315/AD5325 have a 7-bit slave address. The 6 MSB are 000110 and the LSB is determined by the state of the A0 pin. The facility to make hardwired changes to A0 allows the user to use up to two of these devices on one bus. R The 2-wire serial bus protocol operates as follows: R R 1. The master initiates data transfer by establishing a START condition, which is when a high-to-low transition on the SDA line occurs while SCL is high. The following byte is the address byte, which consists of the 7-bit slave address followed by an R/W bit (this bit determines whether data will be read from or written to the slave device). TO OUTPUT AMPLIFIER R The slave whose address corresponds to the transmitted address responds by pulling SDA low during the ninth clock pulse (this is termed the acknowledge bit). At this stage, all other devices on the bus remain idle while the selected device waits for data to be written to or read from its shift register. R Figure 5. Resistor String 2. Data is transmitted over the serial bus in sequences of nine clock pulses (eight data bits followed by an acknowledge bit). The transitions on the SDA line must occur during the low period of SCL and remain stable during the high period of SCL. DAC Reference Inputs There is a single reference input pin for the four DACs. The reference input is unbuffered. The user can have a reference voltage as low as 0.25 V and as high as VDD since there is no restriction due to headroom and footroom of any reference amplifier. 3. When all data bits have been read or written, a STOP condition is established. In write mode, the master will pull the SDA line high during the 10th clock pulse to establish a STOP condition. In read mode, the master will issue a No Acknowledge for the ninth clock pulse (i.e., the SDA line remains high). The master will then bring the SDA line low before the 10th clock pulse and then high during the 10th clock pulse to establish a STOP condition. It is recommended to use a buffered reference in the external circuit (e.g., REF192). The input impedance is typically 45 kΩ. Output Amplifier The output buffer amplifier is capable of generating rail-to-rail voltages on its output, which gives an output range of 0 V to VDD when the reference is VDD. It is capable of driving a load of 2 kΩ to GND or VDD, in parallel with 500 pF to GND or VDD. The source and sink capabilities of the output amplifier can be seen in the plot in TPC 11. Read/Write Sequence The slew rate is 0.7 V/µs with a half-scale settling time to ±0.5 LSB (at eight bits) of 6 µs. POWER-ON RESET The AD5305/AD5315/AD5325 are provided with a power-on reset function, so that they power up in a defined state. The power-on state is • Normal operation • Output voltage set to 0 V In the case of the AD5305/AD5315/AD5325, all write access sequences and most read sequences begin with the device address (with R/W = 0) followed by the pointer byte. This pointer byte specifies the data format and determines which DAC is being accessed in the subsequent read/write operation. (See Figure 6.) In a write operation, the data follows immediately. In a read operation, the address is resent with R/W = 1 and then the data is read back. However, it is also possible to perform a read operation by sending only the address with R/W = 1. The previously loaded pointer settings are then used for the readback operation. See Figure 7 for a graphical explanation of the interface. Both input and DAC registers are filled with zeros and remain so until a valid write sequence is made to the device. This is particularly useful in applications where it is important to know the state of the DAC outputs while the device is powering up. REV. F MSB X LSB X 0 0 DACD DACC DACB DACA Figure 6. Pointer Byte –11– AD5305/AD5315/AD5325 CLR Pointer Byte Bits The following is an explanation of the individual bits that make up the pointer byte. X Don’t care bits. 0 DACD DACC DACB DACA Reserved bits, must be set to 0. 1: The following data bytes are for DAC D. 1: The following data bytes are for DAC C. 1: The following data bytes are for DAC B. 1: The following data bytes are for DAC A. 0: All DAC registers and input registers are filled with zeros on completion of the write sequence. 1: Normal operation. LDAC 0: All four DAC registers and, therefore, all DAC outputs simultaneously updated on completion of the write sequence. 1: Only addressed input register is updated. There is no change in the contents of the DAC registers. Default Readback Condition Input Shift Register The input shift register is 16 bits wide. Data is loaded into the device as two data bytes on the serial data line, SDA, under the control of the serial clock input, SCL. The timing diagram for this operation is shown in Figure 1. The two data bytes consist of four control bits followed by 8, 10, or 12 bits of DAC data, depending on the device type. The first two bits loaded are PD1 and PD0 bits that control the mode of operation of the device. See the Power-Down Modes section for a complete description. Bit 13 is CLR, Bit 12 is LDAC, and the remaining bits are leftjustified DAC data bits, starting with the MSB. See Figure 7. All pointer byte bits power up to 0. Therefore, if the user initiates a readback without writing to the pointer byte first, no single DAC channel has been specified. In this case, the default readback bits are all 0, except for the CLR bit, which is a 1. Multiple-DAC Write Sequence Because there are individual bits in the pointer byte for each DAC, it is possible to write the same data and control bits to 2, 3, or 4 DACs simultaneously by setting the relevant bits to 1. Multiple-DAC Readback Sequence If the user attempts to read back data from more than one DAC at a time, the part will read back the default, power-on reset conditions, i.e., all 0s except for CLR, which is 1. DATA BYTES (WRITE AND READBACK) MOST SIGNIFICANT DATA BYTE 8-BIT AD5305 MSB PD1 PD0 CLR PD0 CLR MSB PD1 D6 D5 D8 D7 10-BIT AD5315 MSB PD1 LDAC D7 LDAC D9 12-BIT AD5325 PD0 CLR LDAC D11 D10 D9 LSB MSB D4 D3 LSB MSB D6 D5 LSB MSB D8 D7 LEAST SIGNIFICANT DATA BYTE 8-BIT AD5305 D2 D1 D4 D3 D0 0 LSB 0 0 D0 0 10-BIT AD5315 D2 D1 LSB D5 D4 D3 0 LSB 12-BIT AD5325 D6 0 D2 D1 D0 Figure 7. Data Formats for Write and Readback –12– REV. F AD5305/AD5315/AD5325 WRITE OPERATION When writing to the AD5305/AD5315/AD5325 DACs, the user must begin with an address byte (R/W = 0), after which the DAC will acknowledge that it is prepared to receive data by pulling SDA low. This address byte is followed by the pointer byte, which is also acknowledged by the DAC. Two bytes of data are then written to the DAC, as shown in Figure 8. A STOP condition follows. SCL SDA 0 0 START COND BY MASTER 0 1 1 ADDRESS BYTE 0 A0 X R/W X ACK MSB BY AD53x5 LSB POINTER BYTE ACK BY AD53x5 SCL SDA MSB MOST SIGNIFICANT DATA BYTE LSB MSB ACK BY AD53x5 LEAST SIGNIFICANT DATA BYTE Figure 8. Write Sequence REV. F –13– LSB ACK BY AD53x5 STOP COND BY MASTER AD5305/AD5315/AD5325 However, if the master sends an ACK and continues clocking SCL (no STOP is sent), the DAC will retransmit the same two bytes of data on SDA. This allows continuous readback of data from the selected DAC register. READ OPERATION When reading data back from the AD5305/AD5315/AD5325 DACs, the user begins with an address byte (R/W = 0), after which the DAC will acknowledge that it is prepared to receive data by pulling SDA low. This address byte is usually followed by the pointer byte, which is also acknowledged by the DAC. Following this, there is a repeated start condition by the master and the address is resent with R/W = 1. This is acknowledged by the DAC indicating that it is prepared to transmit data. Two bytes of data are then read from the DAC, as shown in Figure 9. A STOP condition follows. Alternatively, the user may send a START followed by the address with R/W = 1. In this case, the previously loaded pointer settings are used and readback of data can commence immediately. SCL 0 SDA 0 0 1 START COND BY MASTER 1 0 A0 X R/W X ACK MSB BY AD53x5 ADDRESS BYTE LSB POINTER BYTE ACK BY AD53x5 SCL SDA 0 REPEATED START COND BY MASTER 0 0 1 1 0 A0 MSB R/W ACK BY AD53x5 ADDRESS BYTE LSB DATA BYTE ACK BY MASTER SCL SDA LSB MSB LEAST SIGNIFICANT DATA BYTE NO ACK BY MASTER STOP COND BY MASTER NOTE: DATA BYTES ARE THE SAME AS THOSE IN THE WRITE SEQUENCE EXCEPT THAT DON’T CARES ARE READ BACK AS 0s. Figure 9. Readback Sequence –14– REV. F AD5305/AD5315/AD5325 DOUBLE-BUFFERED INTERFACE The AD5305/AD5315/AD5325 DACs have double-buffered interfaces consisting of two banks of registers—input registers and DAC registers. The input register is directly connected to the input shift register and the digital code is transferred to the relevant input register on completion of a valid write sequence. The DAC register contains the digital code used by the resistor string. input condition for whatever is connected to the output of the DAC amplifier. There are three different options. The output is connected internally to GND through either a 1 kΩ resistor or a 100 kΩ resistor, or it is left open-circuited (three-state). Resistor tolerance = ± 20%. The output stage is illustrated in Figure 10. Access to the DAC register is controlled by the LDAC bit. When the LDAC bit is set high, the DAC register is latched and, therefore, the input register may change state without affecting the contents of the DAC register. However, when the LDAC bit is set low, the DAC register becomes transparent and the contents of the input register are transferred to it. This is useful if the user requires simultaneous updating of all DAC outputs. The user may write to three of the input registers individually and then, by setting the LDAC bit low when writing to the remaining DAC input register, all outputs will update simultaneously. These parts contain an extra feature whereby the DAC register is not updated unless its input register has been updated since the last time that LDAC was brought low. Normally, when LDAC is brought low, the DAC registers are filled with the contents of the input registers. In the case of the AD5305/AD5315/AD5325, the part will update the DAC register only if the input register has been changed since the last time the DAC register was updated, thereby removing unnecessary digital crosstalk. RESISTOR STRING DAC AMPLIFIER POWER-DOWN CIRCUITRY The AD5305/AD5315/AD5325 have very low power consumption, dissipating typically 1.5 mW with a 3 V supply and 3 mW with a 5 V supply. Power consumption can be further reduced when the DACs are not in use by putting them into one of three power-down modes, which are selected by Bits 15 and 14 (PD1 and PD0) of the data byte. Table I shows how the state of the bits corresponds to the mode of operation of the DAC. Figure 10. Output Stage during Power-Down The bias generator, the output amplifiers, the resistor string, and all other associated linear circuitry are shut down when the power-down mode is activated. However, the contents of the DAC registers are unchanged when in power-down. The time to exit power-down is typically 2.5 µs for VDD = 5 V and 5 µs when VDD = 3 V. This is the time from the rising edge of the eighth SCL pulse to when the output voltage deviates from its power-down voltage. See TPC 18 for a plot. The AD5305/AD5315/AD5325 can be used with a wide range of reference voltages where the devices offer full, one-quadrant multiplying capability over a reference range of 0 V to VDD. More typically, these devices are used with a fixed, precision reference voltage. Suitable references for 5 V operation are the AD780 and REF192 (2.5 V references). For 2.5 V operation, a suitable external reference would be the AD589, a 1.23 V band gap reference. Figure 11 shows a typical setup for the AD5305/AD5315/AD5325 when using an external reference. Note that A0 can be high or low. Table I. PD1/PD0 Operating Modes PD0 Operating Mode 0 0 1 1 0 1 0 1 Normal Operation Power-Down (1 kΩ Load to GND) Power-Down (100 kΩ Load to GND) Power-Down (Three-State Output) VDD = 2.5V TO 5.5V 0.1F 10F AD5305/ AD5315/ AD5325 VIN EXT REF When both bits are set to 0, the DAC works normally with its normal power consumption of 600 µA at 5 V. However, for the three power-down modes, the supply current falls to 200 nA at 5 V (80 nA at 3 V). Not only does the supply current drop, but the output stage is also internally switched from the output of the amplifier to a resistor network of known values. This has an advantage in that the output impedance of the part is known while the part is in power-down mode and provides a defined REV. F RESISTOR NETWORK APPLICATIONS Typical Application Circuit POWER-DOWN MODES PD1 VOUT VOUTA VOUT REFIN VOUTB 1F VOUTC AD780/REF192 WITH VDD = 5V OR AD589 WITH VDD = 2.5V SCL SDA A0 VOUTD GND SERIAL INTERFACE Figure 11. AD5305/AD5315/AD5325 Using External Reference –15– AD5305/AD5315/AD5325 If an output range of 0 V to VDD is required, the simplest solution is to connect the reference input to VDD. As this supply may not be very accurate and may be noisy, the AD5305/AD5315/AD5325 may be powered from the reference voltage; for example, using a 5 V reference such as the REF195. The REF195 will output a steady supply voltage for the AD5305/AD5315/AD5325. The typical current required from the REF195 is 600 µA supply current and approximately 112 µA into the reference input. This is with no load on the DAC outputs. When the DAC outputs are loaded, the REF195 also needs to supply the current to the loads. The total current required (with a 10 kΩ load on each output) is Multiple Devices on One Bus Figure 13 shows two AD5305 devices on the same serial bus. Each has a different slave address since the state of the A0 pin is different. This allows each of eight DACs to be written to or read from independently. VDD PULL-UP RESISTORS A0 The AD5305/AD5315/AD5325 have been designed for singlesupply operation, but a bipolar output range is also possible using the circuit in Figure 12. This circuit will give an output voltage range of ± 5 V. Rail-to-rail operation at the amplifier output is achievable using an AD820 or an OP295 as the output amplifier. R1 = 10k⍀ 10F AD820/ OP295 0.1F +5V AD5305 AD1585 VIN VOUT GND 1F 5V 0.1F 10F VIN –5V VREF 1/2 AD5305/ AD5315/ AD5325* VOUTD GND SCL SDA DIN SDA SCL SCL 1k⍀ 1k⍀ FAIL PASS VDD REFIN VOUTC A0 AD5305 A digitally programmable upper/lower limit detector using two of the DACs in the AD5305/AD5315/AD5325 is shown in Figure 14. The upper and lower limits for the test are loaded to DACs A and B, which, in turn, set the limits on the CMP04. If the signal at the VIN input is not within the programmed window, an LED will indicate the fail condition. Similarly, DACs C and D can be used for window detection on a second VIN signal. ⴞ5V VOUTB REFIN SCL AD5305/AD5315/AD5325 as a Digitally Programmable Window Detector VOUTA VDD SCL Figure 13. Multiple AD5305 Devices on One Bus Bipolar Operation Using the AD5305/AD5315/AD5325 6V TO 12V SDA SDA The load regulation of the REF195 is typically 2 ppm/mA, which results in an error of 5.4 ppm (27 µV) for the 2.7 mA current drawn from it. This corresponds to a 0.0014 LSB error at eight bits and 0.022 LSB error at 12 bits. R2 = 10k⍀ AD5305 MICROCONTROLLER 712 µA + 4(5V / 10 kΩ) = 2.70 mA +5V A0 VOUTA 1/2 CMP04 VOUTB PASS/FAIL 1/6 74HC05 GND 2-WIRE SERIAL INTERFACE *ADDITIONAL PINS OMITTED FOR CLARITY Figure 12. Bipolar Operation with the AD5305 The output voltage for any input code can be calculated as follows: ( ) REFIN × D / 2 N × VOUT = – REFIN × ( R2 / R1) ( R1 + R2 ) / R1 where D is the decimal equivalent of the code loaded to the DAC. N is the DAC resolution. REFIN is the reference voltage input. with REFIN= 5 V, R1 = R2 = 10 kΩ: ( ) VOUT = 10 × D / 2 N – 5 V Figure 14. Window Detection Coarse and Fine Adjustment Using the AD5305/AD5315/ AD5325 Two of the DACs in the AD5305/AD5315/AD5325 can be paired together to form a coarse and fine adjustment function, as shown in Figure 15. DAC A is used to provide the coarse adjustment while DAC B provides the fine adjustment. Varying the ratio of R1 and R2 will change the relative effect of the coarse and fine adjustments. With the resistor values and external reference shown, the output amplifier has unity gain for the DAC A output, so the output range is 0 V to 2.5 V – 1 LSB. For DAC B, the amplifier has a gain of 7.6 × 10–3, giving DAC B a range equal to 19 mV. Similarly, DACs C and D can be paired together for coarse and fine adjustment. The circuit is shown with a 2.5 V reference, but reference voltages up to VDD may be used. The op amps indicated will allow a rail-to-rail output swing. –16– REV. F AD5305/AD5315/AD5325 VDD = 5V 0.1F R3 51.2k⍀ to the device. The AD5305/AD5315/AD5325 should have ample supply bypassing of 10 µF in parallel with 0.1 µF on the supply located as close to the package as possible, ideally right up against the device. The 10 µF capacitors are the tantalum bead type. The 0.1 µF capacitor should have low effective series resistance (ESR) and effective series inductance (ESI), like the common ceramic types that provide a low impedance path to ground at high frequencies, to handle transient currents due to internal logic switching. R4 390⍀ 10F 5V VIN EXT V OUT REF GND AD780/REF192 WITH VDD = 5V VOUT VDD REFIN 1F VOUTA 1/2 AD5305/ AD5315/ AD5325* VOUTB GND R1 390⍀ AD820/ OP295 R2 51.2k⍀ *ADDITIONAL PINS OMITTED FOR CLARITY Figure 15. Coarse/Fine Adjustment POWER SUPPLY DECOUPLING In any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. The printed circuit board on which the AD5305/AD5315/AD5325 is mounted should be designed so that the analog and digital sections are separated and confined to certain areas of the board. If the AD5305/AD5315/AD5325 is in a system where multiple devices require an AGND-to-DGND connection, the connection should be made at one point only. The star ground point should be established as close as possible REV. F The power supply lines of the AD5305/AD5315/AD5325 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. Fast switching signals such as clocks should be shielded with digital ground to avoid radiating noise to other parts of the board, and should never be run near the reference inputs. A ground line routed between the SDA and SCL lines will help reduce crosstalk between them (not required on a multilayer board as there will be a separate ground plane, but separating the lines will help). Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each other. This reduces the effects of feedthrough through the board. A microstrip technique is by far the best, but is not always possible with a double-sided board. In this technique, the component side of the board is dedicated to ground plane while signal traces are placed on the solder side. –17– AD5305/AD5315/AD5325 Table II. Overview of All AD53xx Serial Devices Resolution No. of DACs DNL Interface Settling Time (s) Package Pins AD5300 AD5310 AD5320 8 10 12 1 1 1 ± 0.25 ± 0.5 ± 1.0 SPI® SPI SPI 4 6 8 SOT-23, MSOP SOT-23, MSOP SOT-23, MSOP 6, 8 6, 8 6, 8 AD5301 AD5311 AD5321 8 10 12 1 1 1 ± 0.25 ± 0.5 ± 1.0 2-Wire 2-Wire 2-Wire 6 7 8 SOT-23, MSOP SOT-23, MSOP SOT-23, MSOP 6, 8 6, 8 6, 8 AD5302 AD5312 AD5322 8 10 12 2 2 2 ± 0.25 ± 0.5 ± 1.0 SPI SPI SPI 6 7 8 MSOP MSOP MSOP 8 8 8 AD5303 AD5313 AD5323 8 10 12 2 2 2 ± 0.25 ± 0.5 ± 1.0 SPI SPI SPI 6 7 8 TSSOP TSSOP TSSOP 16 16 16 AD5304 AD5314 AD5324 8 10 12 4 4 4 ± 0.25 ± 0.5 ± 1.0 SPI SPI SPI 6 7 8 MSOP MSOP MSOP 10 10 10 AD5305 AD5315 AD5325 8 10 12 4 4 4 ± 0.25 ± 0.5 ± 1.0 2-Wire 2-Wire 2-Wire 6 7 8 MSOP MSOP MSOP 10 10 10 AD5306 AD5316 AD5326 8 10 12 4 4 4 ± 0.25 ± 0.5 ± 1.0 2-Wire 2-Wire 2-Wire 6 7 8 TSSOP TSSOP TSSOP 16 16 16 AD5307 AD5317 AD5327 8 10 12 4 4 4 ± 0.25 ± 0.5 ± 1.0 SPI SPI SPI 6 7 8 TSSOP TSSOP TSSOP 16 16 16 8 10 12 8 8 8 ± 0.25 ± 0.5 ± 1.0 SPI SPI SPI 6 7 8 TSSOP TSSOP TSSOP 16 16 16 Part No. SINGLES DUALS QUADS OCTALS AD5308 AD5318 AD5328 Visit www.analog.com/support/standard_linear/selection_guides/AD53xx.html for more information. Table III. Overview of AD53xx Parallel Devices Part No. Resolution DNL VREF Pins Settling Time (s) SINGLES AD5330 AD5331 AD5340 AD5341 8 10 12 12 ± 0.25 ± 0.5 ± 1.0 ± 1.0 1 1 1 1 6 7 8 8 DUALS AD5332 AD5333 AD5342 AD5343 8 10 12 12 ± 0.25 ± 0.5 ± 1.0 ± 1.0 2 2 2 1 6 7 8 8 QUADS AD5334 AD5335 AD5336 AD5344 8 10 10 12 ± 0.25 ± 0.5 ± 0.5 ± 1.0 2 2 4 4 6 7 7 8 Additional Pin Functions BUF ✓ ✓ ✓ GAIN ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ ✓ –18– Package Pins ✓ CLR ✓ ✓ ✓ ✓ TSSOP TSSOP TSSOP TSSOP 20 20 24 20 ✓ ✓ ✓ ✓ ✓ TSSOP TSSOP TSSOP TSSOP 20 24 28 20 ✓ ✓ ✓ TSSOP TSSOP TSSOP TSSOP 24 24 28 28 HBEN ✓ REV. F AD5305/AD5315/AD5325 OUTLINE DIMENSIONS 10-Lead Mini Small Outline Package [MSOP] (RM-10) Dimensions shown in millimeters 3.00 BSC 10 6 4.90 BSC 3.00 BSC 1 5 PIN 1 0.50 BSC 0.95 0.85 0.75 1.10 MAX 0.15 0.00 0.27 0.17 SEATING PLANE 0.23 0.08 8ⴗ 0ⴗ COPLANARITY 0.10 COMPLIANT TO JEDEC STANDARDS MO-187BA REV. F –19– 0.80 0.60 0.40 AD5305/AD5315/AD5325 Revision History Location Page 10/04—Data Sheet changed from REV. E to REV. F. Changes to Pointer Byte Bits section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Changes to Figure 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 8/03—Data Sheet changed from REV. D to REV. E. Added A Version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Universal Changes to FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Changes to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Changes to TPC 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Added OCTALS SECTION to Table II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4/01—Data Sheet changed from REV. C to REV. D. Edit to Features section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Edit to Figure 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Edits to RIGHT/LEFT and DOUBLE sections of Pointer Byte Bits section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Edit to Input Shift Register section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Edit to Multiple-DAC Readback Sequence section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Edits to Figure 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Edits to WRITE OPERATION section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Edits to Figure 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Edits to READ OPERATION section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Edits to Figure 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Edits to POWER-DOWN MODES section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Edits to Figure 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Purchase of licensed I 2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I 2C Patent Rights to use these components in an I 2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. –20– REV. F C00930–0–10/04(F) Changes to Figure 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11