10BIT 165MSPS DAC
DAC1268X
GENERAL DESCRIPTION
FEATURES
This is CMOS 10-bit D/A Converter
for general applications. Its typical conversion rate
is 165MHz and Supply voltage is 3.3V
•
•
•
•
•
TYPICAL APPLICATIONS
165MHz Operation
+3.3V power supply
BGR (Internal / External)
10bit Voltage parallel Input
Power Down mode(High active)
• Graphic display
• General purpose high-speed
• Digital Camera
FUNCTIONAL BLOCK DIAGRAM
AVDD33A
AVSS33A AVDD33D AVSS33D AVBB33A AVBB33D
IO1
Decoder
D[9:0]
1st
Latch
2nd
Latch
Buffer
CK1
CLK
Clock
Generator
CK2
Current
Cell
Array
CCOMP
CK1
+
CK2
Amp
_
CM
Block
SIN
CCOMP
VREFOUT IRSET SLEEPCCOMP
Ver 1.8 (Apr. 2002)
No responsibility is assumed by SEC for its use nor for any
infringements of patents or other rights of third parties that may
result from its use. The content of this datasheet is subject to
change without any notice.
SAMSUNG ELECTRONICS Co. LTD
IO1B
DAC1268X
10BIT 165MSPS DAC
CORE PIN DESCRIPTION
NAME
I/O
TYPE
I/O PAD
PIN DESCRIPTION
IO1,IO1B
D[9:0]
CLK
SLEEP
AO
DI
DI
DI
phoa_abb
phicc_abb
phicc_abb
phicc_abb
VREFOUT
AB
phoa_abb
CCOMP
SIN
IRSET
AVDD33D
AVSS33D
AVDD33A
AVSS33A
AVBB33A
AVBB33D
AB
AB
AB
DP
DG
AP
AG
AG
AG
phoa_abb
phoa_abb
phoa_abb
vdd3t_abb
vss3t_abb
vdd3t_abb
vss3t_abb
vbb3t_abb
vbb3_abb
Analog DAC output
Digital input
Clock
Power down mode (hign active)
Reference voltage input &
monitoring
External capacitance connection
External capacitance connection
external resistor connection
Digital Power
Digital Ground
Analog Power
Analog Ground
Analog Bulk
Digital Bulk
I/O TYPE ABBR.
•
•
•
•
AI : Analog Input
DI : Digital Input
AO : Analog Output
DO : Digital Output
•
•
•
•
•
•
AP :
DP :
AG :
DG :
AB :
DB :
Analog Power
Digital Power
Analog Ground
Digital Ground
Analog Bidirection
Analog Bidirection
CORE CONFIGURATION
AVDD33A AVSS33A AVDD33D AVSS33D AVBB33A
IO
D[9:0]
dac1268x
CLK
SLEEP
IOB
VREFOUT
SEC ASIC
IRSET CCOMP
2 / 12
SIN
ANALOG
DAC1268X
10BIT 165MSPS DAC
FUNCTIONAL DESCRIPTION
This is 10bit 165MSPS digital to analog data
converter and uses segment architecture for 5bits of
MSB sides , binary-weighted architecture for 5bits of
LSB side and master slave architecture for 2bit of
LSB. it contains of First latch block, decoder block
Second latch block, AMP block ,BGR block, switch
buffer block, SLEEP block for power down,
CM(current mirror)block and analog switch block. This
core uses reference current to decide the 1LSB current
size by dividing the reference current by 32times. So
the reference current must be constant and the
switch's physical real size can be constant by using
OPA block with high DC gain. The most significant
block of this core is analog switch block and it must
maintain the uniformity at each switch, so layout
designer must care of the matching characteristics on
analog switch and CM block. And more than 80%
of supply current is dissipated at analog switch block
and AMP block. And it uses samsung(SEC) standard
cell as all digital cell of latch ,decoder and buffer.
And to adjust full current output, you must decide the
"Rset" resistor value(connected to IREF pin) and
"Vbias" voltage value(connected to VREFOUT pin).
Its voltage output can be obtained by connecting
RL1(connected to IO1,IO1B pin) .
SEC ASIC
Linearity Error : Linearity error is defined as the
maximum deviation of the actual analog output from
the ideal output, determined by a straight line drawn
from zero to full scale.
Monotonicity : A D/A converter is monotonic if
the output either increases or remains constants as
the digital input increases.
Offset Error : The deviation of the output current
from the ideal of zero is called offset error. For IO ,
0mV output expected when the inputs are all 0s.
Gain Errors : The difference between the actual
andideal output span. The actual span is determined
by the output when all inputs are set to 1s minus the
output when all inputs are set to 0s.
Output Compliance Range : The range of allowable
voltage at the output of a current-output DAC.
Operation beyond the maximum compliance limits may
cause either output stage saturation or breakdown
resulting in nonlinear performance.
Settling Time : The time required for the output to
reach and remain within a specified error band about
its final value, measured from the start of the output
transition
Glitch Impulse : Asymmetrical switching times in a
DAC give rise to undesired output transients that are
quantified by a glitch impulse. It is specified as the
net area of the glitch in pV-s
3 / 12
ANALOG
DAC1268X
10BIT 165MSPS DAC
ABSOLUTE MAXIMUM RATINGS
CHARACTERISTICS
SYMBOL
VALUES
UNIT
Supply Voltage
AVDD33A
AVDD33D
-0.5 TO 3.3
V
Voltage on any Digital Voltage
Vin
AVSS33A-0.3 to AVDD33A+0.3
V
Storage Temperature Range
Tstg
-45 to 150
ºC
NOTES
1. It is strongly recommended that to avoid power latch-up all the supply
Pins(AVDD33A,AVSS33A) be driven from the same source.
2. Absolute Maximum Rating values applied individually while all other
parameters are within specified operating conditions. Function operation
under any of these conditions is not implied.
3. Applied voltage must be current limited to specified range.
4. Absolute Maximum Ratings are value beyond which the device may be
damaged permanently. Normal operation is not guaranteed.
RECOMMENDED OPERATING CONDITIONS
CHARACTERISTICS
SYMBOL
MIN
TYP
MAX
UNIT
Operating Supply Voltage
AVDD33A
3.0
3.3
3.6
V
Digital input Voltage HIGH
LOW
Vih
Vil
0.7*AVDD33A
-
-
0.3*AVDD33A
V
Operating Temperature Range
Topr
-40
33
85
ºC
SEC ASIC
4 / 12
ANALOG
DAC1268X
10BIT 165MSPS DAC
DC ELECTRICAL CHARACTERISTICS
CHARACTERISTICS
SYMBOL
MIN
TYP
MAX
UNIT
Resolution
10
-
-
-
Bits
Differential Linearity Error
DLE
-
-
±1
LSB
Integral Linearity Error
ILE
-
-
±2
LSB
Monotonicity
Guaranteed
Maximum Output Compliance
Voc
0
-
+1.2
V
Internal BGR Reference Voltage
-
0.63
0.7
0.77
V
Full Scale Output Current
Ifs
15.87
16.7
17.54
mA
Power Supply Current
Is
17
18.35
23
mA
NOTES
1. White to Black Pedestal Voltage can be changed by using external RSET resistor
2. Converter Specifications (unless otherwise specified)
AVDD33A=3.3V AVDD33D=3.3V AVSS33A=GND AVSS33D=GND
Ta=33ºC C(load)=10pF VREFOUT=0.7V
AC ELECTRICAL CHARACTERISTICS
CHARACTERISTICS
SYMBOL
MIN
TYP
MAX
UNIT
Conversion Speed
Fop
165
-
-
MHz
Analog Output Delay
Td
-
0.5
2
ns
Analog Output Rise Time
Tr
-
0.24
2
ns
Analog Output Fall Time
Tf
-
0.98
2
ns
Analog Output Settling Time
Ts
-
114.5
200
ns
Glitch Impulse
GI
-100
31.7
100
pVsec
Setup Time
Ts
-
-
0.5
nsec
Hold Time
Th
-
-
0.5
nsec
THD(Total Harmonic Distortion)
THD
-55
-65
-
dB
SNDR( Fin=5MHz , Fck=160MHz)
SNDR
-48
-56
-
dB
NOTES
1. The above parameters are guaranteed over the full temperature range.
2. Clock and data feed through is a function of the amount of overshoot and undershoot on the
digital inputs .Settling time does not include clock and data feed through . Glitch impulse include
clock and data feed through.
3. Setup and Hold Time are simulation values, not a test result
SEC ASIC
5 / 12
ANALOG
DAC1268X
10BIT 165MSPS DAC
TIMING DIAGRAM ( FOR ONE CHANNEL )
Digital
Input
DI (1)
DI (2)
DI (3)
DI (4)
DI (5)
1/2 CLK PIPELINE DELAY
CLK
td
AO(1)
Analog
Output
AO(2)
AO (1)
AO(3)
AO (2)
AO(4)
AO (3)
AO (4)
D[9:0]
Ts
Th
CLK
Td
Tset
0.1%
50%
IO
Half clock pipeline delay
NOTES
1. Output delay measured from the 50% point of the rising edge of CLK to the full scale
transition
2. Settling time measured from the 50% point of full scale transition to the output remaining
within ±1,2LSB.
3. Output rise/fall time measured between the 10% and 90% points of full scale transition.
SEC ASIC
6 / 12
ANALOG
DAC1268X
10BIT 165MSPS DAC
CORE EVALUATION GUIDE
Analog Analog
Power Ground
Digital Digital
Power Ground
3.3V GND
3.3V GND
Cc
Cc
Ct
Ct
AVDD33A AVSS33A AVBB33A AVDD33D AVSS33D AVBB33D
VO1
IO
10
HOST
DSP
CORE
10
D[9:0]
MUX
CLK
RO1
dac1268x
Analog
Ground
GND
SLEEP
VO2
IOB
IRSET
VREFOUT CCOMP
SIN
RO2
Analog
Ground
TEST PATH
GND
Ct
10
RSET
(=1.27kΩ)
GND
Cc
0.7V
Cc
3.3V
Analog
Ground
Analog
Power
3.3V
Analog
Power
SEC ASIC
LOCATION
DESCRIPTION
Cc
0.1uF
RSET
1.27k Ohm
RO1,RO2
37.5 Ohm
Ct
10uF
Cc
0.1uF
7 / 12
ANALOG
DAC1268X
10BIT 165MSPS DAC
TEST CHIP EVALUATION GUIDE
Cc
Ct
+
L2
AVBB33D
NC
48
2
AVSS33D
NC
47
3
AVDD33D
NC
46
4
NC
NC
45
5
NC
NC
44
D[9]
6
D[9]
AVBB33A 43
D[8]
7
D[8]
AVSS33A 42
D[7]
8
D[7]
NC
41
D[6]
9
D[6]
NC
40
D[5]
10
D[5]
D[4]
11
D[4]
D[3]
12
D[3]
D[2]
13
D[2]
D[1]
14
D[1]
D[0]
15
D[0]
16
NC(1/2LSB)
DAC1268X
1
(VSS)
0.0V
c
Cc
Ct
+
c
AVDD33A 39
NC
38
NC
37
NC
36
IRSET
35
0.7V
VREFOUT 34
100[ohm]
NC
SIN
32
CCOMP
31
NC
30
SLEEP
NC
29
NC
IO1
28
NC(1/4LSB)
18
NC
19
CLK
20
21
RSET
33
Cc
17
3.3V
(VDD)
Analog
Ground
Cc
GND
VO1
VO2
22
NC
IO1B
27
23
NC
NC
26
RO1
RO2
24
NC
NC
25
Analog
Ground
GND
LOCATION
DESCRIPTION
Analog
Ground
GND
Note
caution(1) :
C1
10uF
CAPACITOR
C2
0.1uF CERAMIC
CAPACITOR
Ro1,Ro2
37.5 ohm RESISTOR
RSET
1270ohm 1% METAL FILM RESISTOR
* This chip was originally made with the target of 12 bit resolution.
* You should test this sample chip only as a single output that is probing
only between ground and IO1 neglecting IO1B with applying GND to
NC PIN(#16,#17).
* If you want to test it as differential output you should apply as follows.
1. apply GND to NC(#16)
2. apply VDD to NC(#17)
3. then probe the output between IO1 and IO1B.
* If you want single output (IO1), connect NC(#16,17) pin to
caution(2)
VSS .
:
* Probe Pin #34,#35 , you will see 0.7V in these nodes.
Caution(4) : Pin #20(SLEEP)
* In case of operating this chip properly, you have to put GND to this pin.
If you want to check power down mode, apply VDD to this pin.
SEC ASIC
8 / 12
ANALOG
DAC1268X
10BIT 165MSPS DAC
The voltage is scaled factor of 1/32 for VIDEO. The full scale current is given as the decimal value equivalent to
the digital code.
1. Resolution
If you want to change the resolution, use as many appear bits as you want and connect the rest
lower bits to the ground as above diagram which is 10bit application.
2. Output Range Alteration
In order to change the output swing, use following equation.
Vout = { V(IRSET)/(RSET*32)}*(DAC_CODE)*Rio
Output swing level is a function of V(IRSET), RSET, and Rio, The maximum output swing level is 0.66V
SEC ASIC
9 / 12
ANALOG
DAC1268X
10BIT 165MSPS DAC
PHANTOM CELL INFORMATION
- Pins of the core can be assigned externally (Package pins) or internally (internal ports) depending
on design methods.
The term "External" implies that the pins should be assigned externally like power pins.
The term "External/internal" implies that the applications of these pins depend on the user.
AVDD33A
AVSS33A
AVBB33A
AVDD33D
AVSS33D
AVBB33D
Pin Name
Pin Usage
VDDA
External
VSSA
External
VBB
External
VDDD
External
Pin Layout Guide
- Maintain the large width of lines as
far as the pads.
- place the port positions to minimize
the length of power lines.
- Do not merge the analog powers with
another power from other blocks.
VSSD
External
dac1268x
- Use good power and ground source
on board.
10bit 165MSPS DAC
IRSET
VREFOUT
CCOMP
External
IRSET
External
SIN
External
IO1B
External
- Do not overlap with digtal lines.
- Maintain the shortest path to pads.
- Separate from all other analog signals
- Maintain the larger width and the
D[9]
D[8]
CCOMP
D[7]
SIN
shorter length as far as the pads.
IO1
External
D[5]
CLK
External/Internal
D[4]
SLEEP
External/Internal
D[3]
D[9]
External/Internal
D[8]
External/Internal
D[7]
External/Internal
D[6]
External/Internal
D[5]
External/Internal
D[4]
External/Internal
D[3]
External/Internal
D[2]
External/Internal
D[1]
External/Internal
D[0]
External/Internal
- Separate from all other digital lines.
D[6]
D[2]
D[1]
D[0]
CLK
SLEEP
AVDD33A
AVSS33A
AVBB33A
IO1
IO1B
AVDD33D
AVSS33D
AVBB33D
SEC ASIC
10 / 12
- Separated from the analog clean
signals if possible.
- Do not exceed the length by
1,000um.
- In Phantom cell in case of many
ports of one power name , you must
drag the
ports individually to PAD in parallel.
- Customer must use two PAD's
individually for analog power ports
because of PAD's current limitation.
ANALOG
DAC1268X
10BIT 165MSPS DAC
FEEDBACK REQUEST
We appreciate your interest in out products. If you have further questions, please specify in
the attached form.
Thank you very much.
DC / AC ELECTRICAL CHARACTERISTIC
Characteristics
Min
Typ
Max
Unit
Supply Voltage
V
Power dissipation
mW
Resolution
Bits
Analog Output Voltage
V
Operating Temperature
ºC
Output Load Capacitor
pF
Output Load Resistor
Ohm
Integral Non-Linearity Error
LSB
Differential Non-Linearity Error
LSB
Maximum Conversion Rate
MHz
Remarks
VOLTAGE OUTPUT DAC
Reference Voltage TOP
BOTTOM
V
Analog Output Voltage Range
Digital Input Format
V
Binary Code or 2's Complement Code
CURRENT OUTPUT DAC
Analog Output Maximum Current
mA
Analog Output Maximum Signal
Frequency
MHz
Reference Voltage
V
External Resistor for Current
Setting(RSET)
Ohm
Pipeline Delay
sec
- Do you want to Power down mode?
- Do you want to Internal Reference Voltage(BGR)?
- Which do you want to Serial Input TYPE or parallel Input TYPE?
SEC ASIC
11 / 12
ANALOG
DAC1268X
10BIT 165MSPS DAC
VERSION LIST
Version
Date
Modified Items
Ver 1..0
00.05.20
Original version published
Ver 1..1
00.07.20
DC spec TBD(to be determine) adding
Scaling factor M=8 --> M=128 modify
Output voltage level Vmax=1V --> Vmax=0.66 modify
Ver 1.2
00.10.28
I/O pad vss3t_abb --> vbb3t_abb
Ver 1.3
00.11.20
Ver 1.4
01.06.27
Core specification completion
12bit 300Mhz --> 10bit 165MHz changing
Ver.1.5
01.07.02
Typo correction (There are no spec modification)
Ver 1.6
01.07.06
Test chip evaluation guide addition
Ver 1.7
02.02.27
Internal BGR Reference Voltage range modified
Ver 1.8
02.04.20
SEC ASIC
Comments
Add phantom cell guide
ANALOG