10BIT 30MSPS ADC ADC1298X GENERAL DESCRIPTION FEATURES The ADC1298X is a CMOS 10-bit low-voltage and high-speed A/D converter (ADC) for video and other applications. It has a four-step pipelined architecture, which consists of sample & hold amplifier, multiplying D/A converters (DACs), and subranging flash ADCs. The maximum conversion rate of ADC1298X is 30MSPS and supply voltage is 3.3V single. TYPICAL APPLICATIONS • • • • • • • • • Process : CMOS Resolution : 10Bit Maximum Conversion Rate : 30MSPS Power Supply : 3.3V Single Power Consumption : 60mW Differential Linearity Error : ±1.0 LSB (Typ) Integral Linearity Error : ±2.0 LSB (Typ) Internal Sample-and-Hold Operational Temperature Range : 0 ~ 70 ºC • CCD imaging processors Camcorders, scanners, and security cameras. • Read channel LSI HDD, DVD, and CD-ROM drives • IF and baseband signal digitizers • Portable equipments for low-power applications FUNCTIONAL BLOCK DIAGRAM AVDD33A AVSS33A AVBB33A AVDD33D AVSS33D AVBB33D DO[0] (LSB) AIP 3 BIT MDAC 3 BIT MDAC SAH AIN 3 BIT MDAC DO[1] DO[2] DO[3] 4 BIT FLASH 3 BIT FLASH DO[4] 3 BIT FLASH 3 BIT FLASH DO[5] DO[6] 4 BITS 3 BITS 3 BITS 3BITS CLK DO[7] DO[8] DIGITAL CORECTION LOGIC DO[9] (MSB) EOC STBY SU IT BIAS CURRENT GENERATOR RT RB CLOCK GENERATOR CML GENERATOR CK CML Ver 1.1 (April. 2002) This datasheet is a preliminary version. No responsibility is assumed by SEC for its use nor for any infringements of patents or other rights of third parties that may result from its use. The content of this datasheet is subject to change without any notice. SAMSUNG ELECTRONICS Co. LTD ADC1298X 10BIT 30MSPS ADC CORE PIN DESCRIPTION NAME I/O TYPE I/O PAD PIN DESCRIPTION AIP AI phiar50_abb Analog Input (RB ~ RT) AIN AI phiar50_abb Analog Input (RT ~ RB) STBY DI phicc_abb STandBy (Active High) SU DI phicc_abb SpeedUp (Active High) STC DI phicc_abb STart of Conversion (Active High) CK DI phicc_abb Input Clock (30MHz) DO[9:0] DO phob8_abb Digital Output EOC DO phob8_abb End-Of-Conversion RT AB phoa_abb Reference Top Bias (+2.15V) RB AB phoa_abb Reference Bottom Bias (+1.15V) CML AB phoa_abb Common-Mode Level (+1.65V) IT AB phiar50_abb AVDD33A AP vdd3t_abb Analog Power AVSS33A AG vss3t_abb Analog Ground AVBB33A AG vbb3_abb Analog Substrate Bias AVDD33D DP vdd3t_abb Digital Power AVSS33D DG vss3t_abb Digital Ground AVBB33D DG vbb3_abb Digital Substrate Bias I/O TYPE ABBR. • • • • • • AI : Analog Input DI : Digital Input AO : Analog Output DO : Digital Output AB : Analog Bidirectional DB : Digital Bidirectional • • • • AP DP AG DG : : : : Analog Power Digital Power Analog Ground Digital Ground Bias Current Generator Test 100uA in Normal, 10uA in STBY mode CORE CONFIGURATION AVDD33A AVSS33A AVBB33A RT DO[0] (LSB) RB DO[1] CML DO[2] IT DO[3] AIP adc1298x AIN CK DO[4] DO[5] DO[6] DO[7] STBY DO[8] SU DO[9] (MSB) STC EOC AVDD33D AVSS33D AVBB33D SEC ASIC 2 / 14 MIXED ADC1298X 10BIT 30MSPS ADC ABSOLUTE MAXIMUM RATINGS Characteristics Symbol Value Unit Supply Voltage AVDD33A AVDD33D -0.3 to 4.5 V Analog Input Voltage AIP / AIN -0.3 to AVDD33A+0.3 V Digital Input Voltage CK -0.3 to AVDD33D+0.3 V VOH, VOL -0.3 to AVDD33D+0.3 V Tstg -45 to 125 °C Digital Output Voltage Storage Temperature Range NOTES 1. ABSOLUTE MAXIMUM RATING specifies the values beyond which the device may be damaged permanently. Exposure to ABSOLUTE MAXIMUM RATING conditions for extended periods may affect reliability. Each condition value is applied with the other values kept within the following operating conditions and function operation under any of these conditions is not implied. 2. All voltages are measured with respect to AVSS33A/AVSS33D unless otherwise specified. 3. 100pF capacitor is discharged through a 1.5kΩ resistor (Human body model) RECOMMENDED OPERATING CONDITIONS Symbol Min Typ Max Unit Supply Voltage AVDD33A - AVSS33A AVDD33D - AVSS33D 3.15 3.3 3.45 V Supply Voltage Difference AVDD33A - AVDD33D -0.1 0.0 0.1 V RT RB AVSS33A 2.15 1.15 AVDD33A - V AIP / AIN RB - RT V Clock High Time Clock Low Time Tpwh Tpwl - 16.6 16.6 - ns Digital Input 'L' Voltage Digital Input 'H' Voltage VIL VIH 3.0 - 0.3 - V Operating Temperature Topr 0 - 70 °C Characteristics Reference Input Voltage Analog Input Voltage NOTES 1. It is strongly recommended that all the supply pins (AVDD33A, AVDD33D) be powered from the same source to avoid power latch-up. SEC ASIC 3 / 14 MIXED ADC1298X 10BIT 30MSPS ADC DC ELECTRICAL CHARACTERISTICS Characteristics Symbol Min Typ Max Unit - - 10 - Bits - Differential Linearity Error DLE - - ±1.0 LSB AIP/AIN : RB ~ RT (Ramp Input) Integral Linearity Error ILE - - ±2.0 LSB Fs : 1MHz 20MHz Reference Current IREF - 1.25 2 mA 1.0V/800Ω = 1.25mA Bottom Offset Voltage Error EOB - - ±10 LSB EOB = AI(0, 1) - 0 Top Offset Voltage Error EOT - - ±10 LSB EOT = RT - AI(1022, 1023) Resolution Conditions NOTES 1. Converter Specifications (unless otherwise specified) AVDD33A=3.3V AVDD33D=3.3V AVSS33A=GND AVSS33D=GND RT=2.15V RB=1.15V STBY=LOW STC=HIGH SU=LOW Ta=25°C 2. AI(D1, D2) denotes the net voltage difference between AIP and AIN at the instant when of which the counterpart Digital Output code transits from D1 to D2. AC ELECTRICAL CHARACTERISTICS Symbol Min Typ Max Unit Clock High Time Tpwh - 16.6 - ns Clock Low Time Tpwl - 16.6 - ns Conversion Rate Fs 30 - - MSPS Dynamic Supply Current Is - 18 25 mA Is = I(REF) + I(AVDD33A) + I(AVDD33D) Fs : 30MHz Analog Input Range Vin AVSS 2.0 AVDD Vpp SNDR varies according to Vin Analog Input Capacitance Cin - 10 - pF - Analog Input Bandwidth Fin - 1 6 MHz - Digital Output Data Delay td - 10 - ns See "DELAY TIMING DIAGRAM" SNDR1 SNDR2 SNDR3 - 48 - dB AIN : 1, 2, 4MHz respectively (Sine Input) Fs : 30MHz Characteristics Signal to Noise Distortion Ratio (SNDR) SEC ASIC 4 / 14 Conditions - MIXED ADC1298X 10BIT 30MSPS ADC INPUT-OUTPUT MAPPING TABLE Index AIP (V) AIN (V) Digital Output 0 1.15 ~ 1.15+1×LSBD 2.15-1×LSBD ~ 2.15 0000000000 1 1.15+1×LSBD ~1.15+2×LSBD 2.15-2×LSBD ~ 2.15-1×LSBD 0000000001 2 1.15+2×LSBD ~1.15+3×LSBD 2.15-3×LSBD ~ 2.15-2×LSBD 0000000010 ••• ••• ••• ••• 511 1.15+511×LSBD ~1.15+512×LSBD 2.15-512×LSBD ~ 2.15-511×LSBD 0111111111 512 1.15+512×LSBD ~1.15+513×LSBD 2.15-513×LSBD ~ 2.15-512×LSBD 1000000000 513 1.15+513×LSBD ~1.15+514×LSBD 2.15-514×LSBD ~ 2.15-513×LSBD 1000000001 ••• ••• ••• ••• 1021 1.15+1021×LSBD ~1.15+1022×LSBD 2.15-1022×LSBD ~2.15-1021×LSBD 1111111101 1022 1.15+1022×LSBD ~1.15+1023×LSBD 2.15-1023×LSBD ~2.15-1022×LSBD 1111111110 1023 1.15+1023×LSBD ~ 2.15 1.25 ~ 2.15-1023×LSBD 1111111111 NOTES 1. For Differential Input .AIP = RB ~ RT .AIN = RT ~ RB .1×LSBD = (RT - RB)/1024 = 0.9765mV and for Single Input .AIP = (RT + RB)/2 - (RT - RB) ~ (RT + RB)/2 + (RT - RB) .AIN = (RT + RB)/2 .1×LSBS = 2×(RT - RB)/1024 = 1.9530mV SEC ASIC 5 / 14 MIXED ADC1298X 10BIT 30MSPS ADC DELAY TIMING DIAGRAM AI(3) AI(4) AI(5) AI(6) AI(7) AI(8) AI STC CK td DO DO (0) DO (1) DO (2) DO (3) DO (4) 3 CLOCK PIPELINE DELAY 4ns 8ns 4ns 8ns CK STC Tsafe Tsafe Notes 1. Digital Output Code, DO[9:0], is renewed only when STC (STart-Of-Conversion) is 'HIGH' and the last code during the STC is 'HIGH' will be kept otherwise. 2. During STC is 'HIGH', ADC1298X generates EOC (End-Of-Conversion) and DO[9:0] with the pipeline delay of 3 clock periods from the instant that the counterpart analog input was sampled. 3. The state transition of STC to 'LOW' will be immediately reflected to DO[9:0] and EOC, while the transition to 'HIGH' requires the same delay as the pipeline delay to ensure the validity of DO[9:0] and EOC. 4. The signal transition of STC is valid only in the Tsafe region, so the setup-hold timing constraints must be carefully taken into consideration on STC generation. 5. Because EOC is generated by STC regardless of the state of STBY, EOC will be toggled normally in spite of STBY 'HIGH' if only STC is 'HIGH'. Do not refer to the EOC while STBY is 'HIGH', because it is invalid in actual although it is toggled normaly with STC 'HIGH'. SEC ASIC 6 / 14 MIXED ADC1298X 10BIT 30MSPS ADC DELAY TIMING DIAGRAM AI(3) AI(a) AI(b) AI(c) AI(d) AI STC CK Td DO DO (0) DO(0) INVALID INVALID INVALID DO (a) 3 CLOCK PIPELINE DELAY STBY CK Td DO DO (0) DO(0) INVALID INVALID DO (a) 1us Stabilization Delay Notes 1. When STBY goes 'HIGH', the internal circuitry remains active but not operates properly because the current supplied to each internal block is reduced. So although the digital output DO[9:0] seems to be generated normally, it is totally invalid while STBY remains 'HIGH' 2. When STBY returns to 'LOW', it takes about 1us stabilization time for internal circuitry to stabilize itself and begin to generate vaild outputs. If the current were forced to be zero with STBY 'HIGH', it would take quite longer time than the case we had it small but not zero. That is why we leave some amount of current in low-current mode rather than cutting the current off, and why we call this control signal as 'STBY (STand-BY)' rather than 'PD (Power-Down)'. SEC ASIC 7 / 14 MIXED ADC1298X 10BIT 30MSPS ADC FUNCTIONAL 1. DESCRIPTION ADC1298X is a four-stage pipelined A/D Converter comprising a sample-and-hold, two multiflying DAC (MDAC) and four flash ADC each of which yields 4, 3, 3 and 3 bits. The N-bit flash ADC is composed of 2n latching comparators, and multiplying DAC is composed of N+2 capacitors and a fully-differential amplifier. 2. ADC1298X operates as follows. During the first "Low" cycle of the external clock the analog input data is tracked by the sample-and-holder and sampled at the rising edge of the clock to be converted. The sampled data is fed to the first MDAC and first 4-bit flash ADC which produce 4-bit digital output code corresponding to the sampled analog data. The first MDAC reconstructs the analog voltage corresponding to the first 4-bit flash ADC's digital output, and amplifies, by the gain of 23, the residue voltage which is the voltage difference between the recunstructed voltage and the input voltage of the first MDAC. The 3-bit flash ADC, and MDAC of second to fourth stage operate as the same manner with the first stage but that finally these blocks produce 3-bit digital output codes and amplify a residue voltage by a gain of 22. The respective digital output codes from each of the flash ADCs are fed to the Digital Correction Logic (DCL) to correct the inter-stage conversion error. guarantee fidelity of the following 10-bit data conversion process. This SAH consists of fully differential op-amp, switching transistors, and sampling capacitors. The sampling clocks are non-overlapping (Q1, Q2) and sampling capacitance is 1.0pF. SAH uses its own bias circuit to avoid interference from any other blocks and SAH amp is designed to have open-loop dc gain higher than 80dB and phase margin higher than 60 degree. Its input block is designed to be the rail-to-rail architecture using complementary differential pair. 2. FLASH The flash converter compares analog input signal with reference voltages, and the result are transferred to MDAC and digital correction logic block. The comparators inside have a fully differential structure. 3. MDAC MDAC is the most important block next to SAH and it governs the overall performances of ADC as SAH does. MDAC consists of amp, selection logic and capacitor array. Capacitor array is made up of the sampling capacitors and switches to implement D/A conversion process and predefined gain. 3. ADC1298X has the error correction scheme, which handles the offset error which stems from the mismatch between the first, second, third and fourth flash ADC's comparator. MAIN BLOCK DESCRIPTION 1. SAH SAH (sample-and-hold) is the circuit which samples the analog input signal and holds the sampled value until the next sampling instant. It is required that the difference between the real analog input signal and the sampled output signal of SAH be as small as it can be to SEC ASIC 8 / 14 MIXED ADC1298X 10BIT 30MSPS ADC TIMING DIAGRAM A6 A5 A4 A7 A8 AI CK track sample track sample REF sample Amplify Preset Latch Track Latch Encode MDAC1 AI sample Residue amplify FLASH2 REF sample Amplify Preset Latch Track MDAC2 AI sample Residue amplify FLASH3 REF sample Amplify Preset Latch Track MDAC3 AI sample Residue amplify FLASH4 REF sample Amplify Preset SAH FLASH1 track sample track Latch Encode Latch Track Latch Encode Track A1 track Latch Encode Digital Correction DO sample A2 A3 Latch A4 3 CLOCK PIPELINE DELEY SEC ASIC 9 / 14 MIXED GND +3.3V Analog Power GND RT AVDD33A AVSS33A AVBB33A RB +2.15V +1.15V CML IT AIP adc1298x (+1.65V) (100uA) Input Span +1.15 ~ +2.15V AIN CK STBY 30MHz GND STC GND NOTES SU AVDD33D AVSS33D AVBB33D +3.3V GND +3.3V Digital Power DO[0] (LSB) DO[1] DO[2] DO[3] DO[4] DO[5] DO[6] DO[7] DO[8] DO[9] (MSB) EOC : EXTERNAL PINS : INTERNAL PINS NOTES CORE DSP HOST : 10uF ELECTROLYTIC CAPACITOR UNLESS OTHERWISE SPECIFIED : 0.1uF CERAMIC CAPACITOR UNLESS OTHERWISE SPECIFIED MUX BIDIRECTIONAL PAD ADC Function Measuring & Digital Input Forcing MIXED 10 / 14 SEC ASIC GUIDE CORE EVALUATION ADC1298X 10BIT 30MSPS ADC 1. ADC function is evaluated by external check on the bidirectional pads connected to input nodes of HOST DSP back-end circuit. ADC1298X 10BIT 30MSPS ADC USER GUIDE 1. Input Signal Range following Signal Mode The differential mode input signal is recommend to allow wider dynamic input range and to enhance noise immunity of internal sample-and-holder, although ADC1298X is designed to be able to adopt both the single and the differential mode input. < Differential Mode Input Range > Pin Input range Conditions AIP RB ~ RT - AIN RT ~ RB 180º phase shifted with respect to AIP < Single Mode Input Range > Pin Input range Conditions AIP (RT+RB)/2-(RT-RB) ~ (RT+RB)/2-(RT-RB) - AIN (RT + RB)/2 Tied to Clean DC Source (Recommended) Or Internal CML can be used by connecting AIN to CML 2. Input Signal Speed Normal Input Bandwidth of ADC1298X is in range of 1 ~ 6MHz, which is targeted to the frequency content of the signals in normal video systems. If it is necessary to have the bandwidth of the input signal to ADC1298X near or over nyquist frequency (15MHz, half the clock frequency) to use ADC1298X for the application signals of which to feed to ADC1298X can have signal frequencies higher than 6MHz, contact SEC for the guide on additional performance issues. SEC ASIC 11 / 14 MIXED ADC1298X 10BIT 30MSPS ADC AVBB33A AVDD33A AVBB33A AVSS33A AVSS33A LAYOUT GUIDE AVDD33A AVBB33A PHANTOM AVBB33A AVBB33A SUB/Guard Ring AVDD33A Power/Guard Ring AVSS33A GND Ring AVDD33A AVDD33A AVSS33A AVSS33A AIN AIP RB CML adc1298x 10Bit 30MHz ADC RT SU IT STBY AVSS33D AVSS33D AVSS33D GND Ring AVDD33D Power/Guard Ring AVSS33D SUB/Guard Ring AVDD33D AVBB33D AVBB33D AVBB33D AVDD33D AVSS33D CK 12 / 14 STC EOC DO[9] DO[8] DO[7] DO[6] DO[5] DO[4] DO[3] DO[2] DO[1] DO[0] AVSS33D AVDD33D AVBB33D SEC ASIC AVDD33D MIXED ADC1298X 10BIT 30MSPS ADC GENERAL LAYOUT GUIDE PORT NAME I/O TYPE I/O PAD AIP AI AIN AI STBY DI phicc_abb . Keep it from Crossing Analog Signal Line, if possible. [5] SU DI phicc_abb . Keep it from Crossing Analog Signal Line, if possible. [X] STC DI phicc_abb . Keep it from Crossing Analog Signal Line, if possible. [X] CK DI phicc_abb . Keep it from Crossing any Analog Signal Line. (strong requirement) [2] DO[9:0] DO phob8_abb . Keep it from Crossing Analog Signal Lines, if possible. [4] . Make it not to Run over 1,000um. [6] EOC DO phob8_abb . Keep it from Crossing any Analog Signal Line. (strong requirement) [2] . Make it not to Run over 1,000um. [6] RT AB phoa_abb Layout Guide [Priority] . Keep the Paths to PADs as Short as Possible. [1] phiar50_abb . Overlaps by other Signal Lines, especially by Digital Signal Lines, are not allowed (strong requirement). [1] . Put as many Contacts/Vias as Possible on Contact Area, if Metal Layers are Switched. [-] phiar50_abb . Shield, if Possible. [7] . Keep the Paths to PADs as Short as Possible. [1] . Overlaps by other Signal Lines, especially by Digital Signal Lines, are not RB AB phoa_abb CML AB phoa_abb IT AB AVDD33A AP vdd3t_abb AVSS33A AG vss3t_abb AG vbb3_abb AVDD33D DP vdd3t_abb AVSS33D DG vss3t_abb DG . Put as many Contacts/Vias as Possible on Contact Area, if Metal Layers are Switched. [-] . Shield, if Possible. [7] phiar50_abb . Leave it Float. AVBB33A AVBB33D allowed. (strong requirement) [1] vbb3_abb . Overlaps by Digital Signal Lines are not allowed. (strong requirement) [4] . Keep the Paths to PADs as Short as Possible. [3] . Put as many Contacts/Vias as Possible on Contact Area, if Metal Layers are Switched. [-] .Ports exist on 3 sides of Core and internally connected to each other by the power ring. Connect PAD to the Port which is most convenient to Route interconnecting Line. [-] . Overlaps by Analog Signal Lines are not allowed. (strong requirement) [2] . Keep the Paths to PADs as Short as Possible. [4] . Put as many Contacts/Vias as Possible on Contact Area, if Metal Layers are Switched. [-] .Ports exist on 3 sides of Core and internally connected to each other by the power ring. Connect PAD to the Port which is most convenient to Route interconnecting Line. [-] . Keep the Phantom Port Width to PAD or Other Core. SEC ASIC 13 / 14 MIXED ADC1298X 10BIT 30MSPS ADC PACKAGE CONFIGURATION 2.15V 3.3V 1.15V 1 2 (1.65V) 3 4 3.3V 0.0V 12 13 14 3.3V 0.0V 30MHz 15 16 17 18 19 20 21 22 23 24 CML AVDD33A AVDD33A AVBB33A AVSS33A AVSS33A AIP NC AIN NC SU IT STBY AVDD33R AVSS33R CK NC NC NC NC adc1298x 5 6 7 8 9 10 11 RT RT RB RB AVDD33D AVDD33D AVBB33D AVSS33D AVSS33D STC EOC NC NC NC NC NC DO[9] DO[8] 48 47 DO[7] DO[6] DO[5] DO[4] DO[3] DO[2] DO[1] DO[0] NC NC 34 33 32 31 30 29 46 45 0.0V 44 43 42 41 40 39 38 37 36 35 28 27 26 25 : Actual Input/Output Pin : Control Input Pin : Eliminable Input/Output Pin : Default Setting for Control Input Pin SEC ASIC 14/ 14 MIXED ADC1298X 10BIT 30MSPS ADC FEEDBACK REQUEST It should be quite helpful to our ADC core development if you specify your system requirements on ADC in the following characteristic checking table and fill out the additional questions. We appreciate your interest in our products. Thank you very much. Characteristics Min Typ Max Unit Analog Power Supply Voltage V Digital Power Supply Voltage V Bit Resolution Bit Reference Input Voltage V Analog Input Voltage Vpp Operating Temperature °C Integral Non-linearity Error LSB Differential Non-linearity Error LSB Bottom Offset Voltage Error LSB Top Offset Voltage Error LSB Maximum Conversion Rate MSPS Dynamic Supply Current mA Power Dissipation mW Signal-to-noise+distortion Ratio dB Pipeline Delay Remarks CLK Digital Output Format (Provide detailed description & timing diagram) 1. Between single input-output and differential input-output configurations, which one is suitable for your system and why? 2. Please comment on the internal/external pin configurations you want our ADC to have, if you have any reason to prefer some type of configuration. 3. Freely list those functions you want to be implemented in our ADC, if you have any. SEC ASIC MIXED ADC1298X 10BIT 30MSPS ADC HISTORY CARD Version Date Modified Items ver 1.0 00.9.21 Initial Release (preliminary version) ver 1.1 02.04.23 .Phantom Layout Guide Attached .General Layout Guide Attached .Package Configuration Attached SEC ASIC Comments MIXED