NTHS5443T1 Power MOSFET P-Channel ChipFET 3.6 Amps, 20 Volts Features • Low RDS(on) for Higher Efficiency • Logic Level Gate Drive • Miniature ChipFET Surface Mount Package Saves Board Space http://onsemi.com 3.6 AMPS 20 VOLTS RDS(on) = 65 m Applications • Power Management in Portable and Battery–Powered Products; i.e., Cellular and Cordless Telephones and PCMCIA Cards S MAXIMUM RATINGS (TA = 25°C unless otherwise noted) Rating Symbol 5 secs G Steady State Unit Drain–Source Voltage VDS –20 V Gate–Source Voltage VGS 12 V Continuous Drain Current (TJ = 150°C) (Note 1.) TA = 25°C TA = 85°C ID IDM Continuous Source Current (Note 1.) IAS Maximum Power Dissipation (Note 1.) TA = 25°C TA = 85°C PD Operating Junction and Storage Temperature Range P–Channel MOSFET 4.9 3.5 Pulsed Drain Current 3.6 2.6 15 –2.1 A –1.1 A W 2.5 1.3 TJ, Tstg D A ChipFET CASE 1206A STYLE 1 1.3 0.7 °C –55 to +150 1. Surface Mounted on 1″ x 1″ FR4 Board. MARKING DIAGRAM PIN CONNECTIONS 8 1 D 1 8 D 7 2 D 2 7 D 6 3 D 3 6 S 5 4 G 4 5 A4 D A4 = Specific Device Code ORDERING INFORMATION Semiconductor Components Industries, LLC, 2001 May, 2001 – Rev. 2 1 Device Package Shipping NTHS5443T1 ChipFET 3000/Tape & Reel Publication Order Number: NTHS5443T1/D NTHS5443T1 THERMAL CHARACTERISTICS Characteristic Symbol Maximum Junction–to–Ambient (Note 2.) t 5 sec Steady State RthJA Maximum Junction–to–Foot (Drain) Steady State RthJF Typ Max 40 80 50 95 15 20 Unit °C/W °C/W ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Characteristic Symbol Test Condition Min Typ Max Unit VGS(th) VDS = VGS, ID = –250 µA –0.6 – – V Gate–Body Leakage IGSS VDS = 0 V, VGS = 12 V – – 100 nA Zero Gate Voltage Drain Current IDSS VDS = –16 V, VGS = 0 V – – –1.0 µA VDS = –16 V, VGS = 0 V, TJ = 85°C – – –5.0 ID(on) VDS –5.0 V, VGS = –4.5 V –15 – – A rDS(on) VGS = –4.5 V, ID = –3.6 A VGS = –3.6 V, ID = –3.3 A – – 0.056 0.065 0.065 0.074 Ω Static Gate Threshold Voltage On–State Drain Current (Note 3.) Drain–Source On–State Resistance (Note 3.) Forward Transconductance (Note 3.) Diode Forward Voltage (Note 3.) VGS = –2.5 V, ID = –2.7 A – 0.095 0.110 gfs VDS = –10 V, ID = –3.6 A – 10 – S VSD IS = –1.1 A, VGS = 0 V – –0.8 –1.2 V – 9.0 14 nC – 2.2 – – 2.2 – – 15 25 – 30 45 – 50 75 – 35 50 – 30 60 Dynamic (Note 4.) Total Gate Charge Qg Gate–Source Charge Qgs Gate–Drain Charge Qgd Turn–On Delay Time td(on) Rise Time Turn–Off Delay Time VDS = –10 10 V V, VGS = –4.5 45V V, ID = –3.6 A tr td(off) Fall Time tf Source–Drain Reverse Recovery Time trr VDD = –10 V, RL = 10 Ω ID –1.0 –1 0 A, A VGEN = –4 –4.5 5V V, RG = 6 Ω IF = –1.1 A, di/dt = 100 A/µs 2. Surface Mounted on 1″ x 1″ FR4 Board. 3. Pulse Test: Pulse Width 300 µs, Duty Cycle 2%. 4. Guaranteed by design, not subject to production testing. http://onsemi.com 2 s ns NTHS5443T1 TYPICAL ELECTRICAL CHARACTERISTICS –6 V 10 –2.4 V –2.2 V –3.4 V –2.8 V –2.6 V TJ = 25°C –5 V 8 –4 V 6 –ID, DRAIN CURRENT (AMPS) –ID, DRAIN CURRENT (AMPS) 10 –2 V –1.8 V 4 –1.6 V 2 VGS = –1.4 V 0 6 4 125°C 2 25°C TJ = –55°C 0.5 1 1.5 2 2.5 3 0.5 2.5 3 Figure 1. On–Region Characteristics Figure 2. Transfer Characteristics ID = –3.6 A TJ = 25°C 0.15 0.1 0.05 0 2 1 4 3 6 5 0.08 TJ = 25°C 0.06 VGS = –4.5 V VGS = –6 V 0.04 0.02 1 2 3 4 5 6 7 8 9 –VGS, GATE–TO–SOURCE VOLTAGE (VOLTS) –ID, DRAIN CURRENT (AMPS) Figure 3. On–Resistance versus Gate–to–Source Voltage Figure 4. On–Resistance versus Drain Current and Gate Voltage 1.6 10 10,000 ID = –3.6 A VGS = –4.5 V VGS = 0 V –IDSS , LEAKAGE (nA) 1.4 1.2 1 0.8 0.6 –50 2 –VGS, GATE–TO–SOURCE VOLTAGE (VOLTS) 0.2 0 1.5 1 –VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS) RDS(on), DRAIN–TO–SOURCE RESISTANCE (Ω) RDS(on), DRAIN–TO–SOURCE RESISTANCE (Ω) 8 0 0 RDS(on), DRAIN–TO–SOURCE RESISTANCE (NORMALIZED) VDS ≥ –10 V TJ = 150°C 1000 100 TJ = 100°C 10 –25 0 25 50 75 100 125 150 0 4 8 12 16 TJ, JUNCTION TEMPERATURE (°C) –VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS) Figure 5. On–Resistance Variation with Temperature Figure 6. Drain–to–Source Leakage Current versus Voltage http://onsemi.com 3 20 NTHS5443T1 VDS = 0 V TJ = 25°C Ciss 1500 C, CAPACITANCE (pF) VGS = 0 V 1200 Crss 900 600 Coss 300 0 10 5 5 0 –VGS –VDS 10 15 20 6 24 QT 20 5 VDS VGS 4 16 3 12 Q1 2 Q2 8 ID = –3.6 A TJ = 25°C 1 4 0 0 0 2 4 6 8 10 Qg, TOTAL GATE CHARGE (nC) GATE–TO–SOURCE OR DRAIN–TO–SOURCE VOLTAGE (VOLTS) –VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS) 1800 –VGS, GATE–TO–SOURCE VOLTAGE (VOLTS) TYPICAL ELECTRICAL CHARACTERISTICS Figure 8. Gate–to–Source and Drain–to–Source Voltage versus Total Charge Figure 7. Capacitance Variation 1000 VDD = –10 V ID = –1.0 V VGS = –4.5 V 100 t, TIME (ns) td(off) tf tr 10 td(on) 1 1 10 100 RG, GATE RESISTANCE (OHMS) NORMALIZED EFFECTIVE TRANSIENT THERMAL IMPEDANCE Figure 9. Resistive Switching Time Variation versus Gate Resistance 1 Duty Cycle = 0.5 0.2 0.1 0.1 PDM 0.05 t1 0.02 t2 DUTY CYCLE, D = t1/t2 PER UNIT BASE = RθJA = 80°C/W TJM - TA = PDMZθJA(t) SURFACE MOUNTED Single Pulse 0.01 0.0001 0.001 0.01 0.1 1 10 100 SQUARE WAVE PULSE DURATION (sec) Figure 10. Normalized Thermal Transient Impedance, Junction–to–Ambient http://onsemi.com 4 1000 NTHS5443T1 –IS, SOURCE CURRENT (AMPS) 20 VGS = 0 V TJ = 25°C 15 10 5 0 0.4 0.5 0.6 0.7 0.8 0.9 –VSD, SOURCE–TO–DRAIN VOLTAGE (VOLTS) Figure 11. Diode Forward Voltage versus Current 80 mm 80 mm 18 mm 25 mm 68 mm 28 mm 28 mm 26 mm 26 mm Figure 12. Figure 13. BASIC PAD PATTERNS confines of the basic footprint. The drain copper area is 0.0054 sq. in. (or 3.51 sq. mm). This will assist the power dissipation path away from the device (through the copper leadframe) and into the board and exterior chassis (if applicable) for the single device. The addition of a further copper area and/or the addition of vias to other board layers will enhance the performance still further. The basic pad layout with dimensions is shown in Figure 12. This is sufficient for low power dissipation MOSFET applications, but power semiconductor performance requires a greater copper pad area, particularly for the drain leads. The minimum recommended pad pattern shown in Figure 13 improves the thermal area of the drain connections (pins 1, 2, 3, 6, 7, 8) while remaining within the http://onsemi.com 5 NTHS5443T1 PACKAGE DIMENSIONS ChipFET CASE 1206A–03 ISSUE C A 8 7 M 6 K 5 S 5 6 7 8 4 3 2 1 B 1 2 3 L 4 D NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. MOLD GATE BURRS SHALL NOT EXCEED 0.13 MM PER SIDE. 4. LEADFRAME TO MOLDED BODY OFFSET IN HORIZONTAL AND VERTICAL SHALL NOT EXCEED 0.08 MM. 5. DIMENSIONS A AND B EXCLUSIVE OF MOLD GATE BURRS. 6. NO MOLD FLASH ALLOWED ON THE TOP AND BOTTOM LEAD SURFACE. 7. 1206A-01 AND 1206A-02 OBSOLETE. NEW STANDARD IS 1206A-03. J G DIM A B C D G J K L M S C 0.05 (0.002) MILLIMETERS MIN MAX 2.95 3.10 1.55 1.70 1.00 1.10 0.25 0.35 0.65 BSC 0.10 0.20 0.28 0.42 0.55 BSC 5 ° NOM 1.80 2.00 STYLE 1: PIN 1. 2. 3. 4. 5. 6. 7. 8. http://onsemi.com 6 DRAIN DRAIN DRAIN GATE SOURCE DRAIN DRAIN DRAIN INCHES MIN MAX 0.116 0.122 0.061 0.067 0.039 0.043 0.010 0.014 0.025 BSC 0.004 0.008 0.011 0.017 0.022 BSC 5 ° NOM 0.072 0.080 NTHS5443T1 Notes http://onsemi.com 7 NTHS5443T1 ChipFET is a trademark of Vishay Siliconix ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. 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