32 Mbit Concurrent SuperFlash + 2 / 4 Mbit SRAM ComboMemory SST34HF3223B / SST34HF3243B SST34HF3223B / SST24HF3243B32 Mbit Concurrent SuperFlash + 2/4 Mbit SRAM ComboMemories Preliminary Information FEATURES: • Flash Organization: Two 1M x16 • Quad-Bank Architecture for Concurrent Read-While-Write Operation – 12 Mbit + 4 Mbit + 12 Mbit + 4 Mbit • SRAM Organization: – 2 Mbit: 256K x8 or 128K x16 – 4 Mbit: 512K x8 or 256K x16 • Single 2.7-3.3V Read-While-Write Operations • Superior Reliability – Endurance: 100,000 Cycles (typical) – Greater than 100 years Data Retention • Low Power Consumption: – Active Current: 35 mA (typical) – Standby Current: 25 µA (typical) • Sector-Erase Capability – Uniform 1 KWord sectors • Block-Erase Capability – Uniform 32 KWord blocks • Read Access Time – Flash: 70 and 90 ns – SRAM: 70 and 90 ns • Latched Address and Data • Fast Erase and Word-Program: – Sector-Erase Time: 18 ms (typical) – Block-Erase Time: 18 ms (typical) – Chip-Erase Time: 70 ms (typical) – Word-Program Time: 14 µs (typical) – Chip Rewrite Time: 30 seconds (typical) • Automatic Write Timing – Internal VPP Generation • End-of-Write Detection – Toggle Bit – Data# Polling • CMOS I/O Compatibility • JEDEC Standard Command Set • Packages Available – 56-ball LFBGA (10mm x 12mm x 1.4mm) PRODUCT DESCRIPTION The SST34HF3223B/3243B ComboMemory devices integrate four CMOS flash memory banks with a 256K x8 / 128K x16 or 512K x8 / 256K x16 CMOS SRAM memory bank in a Multi-Chip Package (MCP). These devices are fabricated using SST’s proprietary, high-performance CMOS SuperFlash technology incorporating the split-gate cell design and thick oxide tunneling injector to attain better reliability and manufacturability compared with alternate approaches. The SST34HF3223B/3243B devices are ideal for applications such as cellular phones, PDAs and other portable electronic devices in a low power and small form factor system. The SST34HF3223B/3243B features multiple flash memory bank architecture allowing for concurrent operations between the four flash memory banks and the SRAM. The devices can read data from either bank while an Erase or Program operation is in progress in the opposite bank. The four flash memory banks are partitioned as two 12 Mbit and two 4 Mbit for storing boot code, program code, configuration/parameter data and user data. The SuperFlash technology provides fixed Erase and Program times, independent of the number of Erase/Program cycles that have occurred. Therefore, the system software or hardware does not have to be modified or de-rated as is necessary with alternative flash technologies, whose Erase ©2002 Silicon Storage Technology, Inc. S71197-00-000 1/02 543 1 and Program times increase with accumulated Erase/Program cycles. The SST34HF3223B/3243B devices offer a typical endurance of 100,000 cycles. Data retention is rated at greater than 100 years. With high performance WordProgram, the flash memory banks provide a typical WordProgram time of 14 µsec. The entire flash memory bank can be erased and programmed word-by-word in typically 30 seconds for the SST34HF3223B/3243B, when using interface features such as Toggle Bit or Data# Polling to indicate the completion of Program operation. To protect against inadvertent flash write, the SST34HF3223B/3243B devices contain on-chip hardware and software data protection schemes. The flash and SRAM operate as two independent memory banks with respective bank enable signals. The memory bank selection is done by two bank enable signals. The SRAM bank enable signal, BES1# and BES2, selects the SRAM bank. The flash memory bank enable signal, BEF# (BEF1# or BEF2#), has to be used with Software Data Protection (SDP) command sequence when controlling the Erase and Program operations in the flash memory bank. The memory banks are superimposed in the same memory address space where they share common address lines, data lines, WE# and OE# which minimize power consumption and area. The SST logo and SuperFlash are Trademarks registered by Silicon Storage Technology, Inc. in the U.S. Patent and Trademark Office. Concurrent SuperFlash, CSF, and ComboMemory are trademarks of Silicon Storage Technology, Inc. These specifications are subject to change without notice. 32 Mbit Concurrent SuperFlash + 2 / 4 Mbit SRAM ComboMemory SST34HF3223B / SST34HF3243B Preliminary Information Designed, manufactured, and tested for applications requiring low power and small form factor, the SST34HF3223B/ 3243B are offered in both commercial and extended temperatures and a small footprint package to meet board space constraint requirements. word address and word data. During the Word-Program operation, the addresses are latched on the falling edge of either BEF# (BEF1# or BEF2#) or WE#, whichever occurs last. The data is latched on the rising edge of either BEF# (BEF1# or BEF2#) or WE#, whichever occurs first. The third step is the internal Program operation which is initiated after the rising edge of the fourth WE# or BEF# (BEF1# or BEF2#), whichever occurs first. The Program operation, once initiated, will be completed (typically) within 10 µs. See Figures 8 and 9 for WE# and BEF# (BEF1# or BEF2#) controlled Program operation timing diagrams and Figure 22 for flowcharts. During the Program operation, the only valid reads are Data# Polling and Toggle Bit. During the internal Program operation, the host is free to perform additional tasks. Any commands issued during the internal Program operation are ignored. Device Operation The SST34HF3223B/3243B uses BES1#, BES2 and BEF# (BEF1# or BEF2#) to control operation of either the flash or the SRAM memory bank. When BEF# (BEF1# or BEF2#) is low, the flash bank is activated for Read, Program or Erase operation. When BES1# is low, and BES2 is high the SRAM is activated for Read and Write operation. BEF# (BEF1# or BEF2#) and BES1# cannot be at low level, and BES2 cannot be at high level at the same time. If all bank enable signals are asserted, bus contention will result and the device may suffer permanent damage. All address, data, and control lines are shared by flash and SRAM memory banks which minimizes power consumption and loading. The device goes into standby when BEF# (BEF1# and BEF2#) and BES1# bank enables are raised to VIHC (Logic High) or when BEF# (BEF1# and BEF2#) are high and BES2 is low. Flash Sector/Block-Erase Operation The Sector/Block-Erase operation allows the system to erase the device on a sector-by-sector or block-by-block basis. The SST34HF3223B/3243B offer both Sector-Erase and Block-Erase mode. The sector architecture is based on uniform sector size of 1 KWord. The Block-Erase mode is based on uniform block size of 32 KWord. The SectorErase operation is initiated by executing a six-byte command sequence with Sector-Erase command (30H) and sector address (SA) in the last bus cycle. The Block-Erase operation is initiated by executing a six-byte command sequence with Block-Erase command (50H) and block address (BA) in the last bus cycle. The sector or block address is latched on the falling edge of the sixth WE# pulse, while the command (30H or 50H) is latched on the rising edge of the sixth WE# pulse. The internal Erase operation begins after the sixth WE# pulse. See Figures 13 and 14 for timing waveforms. Any commands issued during the Sector- or Block-Erase operation are ignored. Concurrent Read/Write Operation Quadruple bank architecture of SST34HF3223B/3243B devices allows the Concurrent Read/Write operation whereby the user can read from one bank while Program or Erase in the other bank. This operation can be used when the user needs to read system code in one bank while updating data in the other bank. See Figure 1 for Quad-Bank Memory Organization. Flash Read Operation The Read operation of the SST34HF3223B/3243B is controlled by BEF# (BEF1# or BEF2#) and OE#, both have to be low for the system to obtain data from the outputs. BEF# (BEF1# or BEF2#) is used for device selection. When BEF# (BEF1# or BEF2#) is high, the chip is deselected and only standby power is consumed. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either BEF# (BEF1# or BEF2#) or OE# is high. Refer to the Read cycle timing diagram for further details (Figure 7). Flash Chip-Erase Operation The SST34HF3223B/3243B provide a Chip-Erase operation, which allows the user to erase all unprotected sectors/ blocks to the “1” state. This is useful when the device must be quickly erased. The Chip-Erase operation is initiated by executing a sixbyte command sequence with Chip-Erase command (10H) at address 5555H in the last byte sequence. The Erase operation begins with the rising edge of the sixth WE# or BEF# (BEF1# or BEF2#), whichever occurs first. The selected flash bank, either BEF1# or BEF2# will complete the Chip-Erase operation. During the Erase operation, the only valid Read is Toggle Bit or Data# Polling. See Table 4 Flash Word-Program Operation The SST34HF3223B/3243B are programmed on a wordby-word basis. Before the Program operation, the memory must be erased first. The Program operation consists of three steps. The first step is the three-byte load sequence for Software Data Protection. The second step is to load ©2002 Silicon Storage Technology, Inc. S71197-00-000 1/02 2 543 32 Mbit Concurrent SuperFlash + 2 / 4 Mbit SRAM ComboMemory SST34HF3223B / SST34HF3243B Preliminary Information for the command sequence, Figure 12 for timing diagram, and Figure 25 for the flowchart. Any commands issued during the Chip-Erase operation are ignored. tion is completed, DQ7 will produce a ‘1’. The Data# Polling (DQ7) is valid after the rising edge of fourth WE# or (BEF1# or BEF2#) pulse for Program operation. For Sector-, Block-, or Chip-Erase, the Data# Polling (DQ7) is valid after the rising edge of sixth WE# or (BEF1# or BEF2#) pulse. See Figure 10 for Data# Polling (DQ7) timing diagram and Figure 23 for a flowchart. There is a 1 µs bus recovery time (TBR) required before valid data can be read on the data bus. New commands can be entered immediately after DQ7 becomes true data. Flash Write Operation Status Detection The SST34HF3223B/3243B provide one hardware and two software means to detect the completion of a Write (Program or Erase) cycle, in order to optimize the system Write cycle time. The hardware detection uses the Ready/Busy# (RY/BY#) pin. The software detection includes two status bits: Data# Polling (DQ7) and Toggle Bit (DQ6). The End-of-Write detection mode is enabled after the rising edge of WE#, which initiates the internal Program or Erase operation. Flash Toggle Bit (DQ6) During the internal Program or Erase operation, any consecutive attempts to read DQ6 will produce alternating 1s and 0s, i.e., toggling between 1 and 0. When the internal Program or Erase operation is completed, the DQ6 bit will stop toggling. The device is then ready for the next operation. The Toggle Bit (DQ6) is valid after the rising edge of fourth WE# or (BEF1# or BEF2#) pulse for Program operation. For Sector-, Block- or Chip-Erase, the Toggle Bit (DQ6) is valid after the rising edge of sixth WE# or (BEF1# or BEF2#) pulse. See Figure 11 for Toggle Bit timing diagram and Figure 23 for a flowchart. There is a 1 µs bus recovery time (TBR) required before valid data can be read on the data bus. New commands can be entered immediately after DQ6 no longer toggles. The actual completion of the nonvolatile Write is asynchronous with the system; therefore, either a Ready/Busy# (RY/ BY#), Data# Polling (DQ7), or Toggle Bit (DQ6) Read may be simultaneous with the completion of the Write cycle. If this occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with either DQ7 or DQ6. In order to prevent spurious rejection, if an erroneous result occurs, the software routine should include a loop to read the accessed location an additional two (2) times. If both reads are valid, then the device has completed the Write cycle, otherwise the rejection is valid. Ready/Busy# (RY/BY#) Data Protection The SST34HF3223B/3243B includes a Ready/Busy# (RY/BY#) output signal that applies to flash Bank 2 only. During any SDP initiated operation, e.g., Erase, Program, CFI or ID Read operation, RY/BY# is actively pulled low, indicating a SDP controlled operation is in progress. The status of RY/BY# is valid after the rising edge of fourth WE# (or CE#) pulse for Program operation. For Sector-, Block-, or Bank-Erase, the RY/BY# is valid after the rising edge of sixth WE# or (CE#) pulse. RY/BY# is an open drain output that allows several devices to be tied in parallel to VDD via an external pull-up resistor. Ready/Busy# is in high impedance whenever OE# or CE# is high or RST# is low. The SST34HF3223B/3243B provide both hardware and software features to protect nonvolatile data from inadvertent writes. Hardware Data Protection Noise/Glitch Protection: A WE# or BEF# (BEF1# or BEF2#) pulse of less than 5 ns will not initiate a Write cycle. Write Inhibit Mode: Forcing OE# low, BEF# (BEF1# or BEF2#) high, or WE# high will inhibit the Write operation. This prevents inadvertent writes during power-up or power-down. Flash Data# Polling (DQ7) Hardware Block Protection When the SST34HF3223B/3243B are in the internal Program operation, any attempt to read DQ7 will produce the complement of the true data. Once the Program operation is completed, DQ7 will produce true data. Note that even though DQ7 may have valid data immediately following the completion of an internal Write operation, the remaining data outputs may still be invalid: valid data on the entire data bus will appear in subsequent successive Read cycles. During internal Erase operation, any attempt to read DQ7 will produce a ‘0’. Once the internal Erase opera- The SST34HF3223B/3243B provide a hardware block protection which protects the outermost 4 KWord in Bank 1A. The block is protected when WP# is held low. See Figure 1 for Block-Protection location. A user can disable block protection by driving WP# high thus allowing erase or program of data into the protected sectors. WP# must be held high prior to issuing the write command and remain stable until after the entire Write operation has completed. ©2002 Silicon Storage Technology, Inc. S71197-00-000 1/02 3 543 32 Mbit Concurrent SuperFlash + 2 / 4 Mbit SRAM ComboMemory SST34HF3223B / SST34HF3243B Preliminary Information Hardware Reset (RST#) TABLE 1: PRODUCT IDENTIFICATION The RST# pin provides a hardware method of resetting the device to read array data. When the RST# pin is held low for at least TRP, any in-progress operation will terminate and return to Read mode (see Figure 19). When no internal Program/Erase operation is in progress, a minimum period of TRHR is required after RST# is driven high before a valid Read can take place (see Figure 18). Address Data 0000H 00BFH SST34HF3223B 0001H 2761M SST34HF3243B 0001H 2761M Manufacturer’s ID Device ID T1.1 543 Product Identification Mode Exit The Erase operation that has been interrupted needs to be reinitiated after the device resumes normal operation mode to ensure data integrity. In order to return to the standard Read mode, the Software Product Identification mode must be exited. Exit is accomplished by issuing the Software ID Exit command sequence, which returns the device to the Read mode. This command may also be used to reset the device to the Read mode after any inadvertent transient condition that apparently causes the device to behave abnormally, e.g., not read correctly. Please note that the Software ID Exit command is ignored during an internal Program or Erase operation. See Table 4 for software command codes, Figure 17 for timing waveform and Figure 24 for a flowchart. Software Data Protection (SDP) The SST34HF3223B/3243B provide the JEDEC standard Software Data Protection scheme for all data alteration operations, i.e., Program and Erase. Any Program operation requires the inclusion of the three-byte sequence. The three-byte load sequence is used to initiate the Program operation, providing optimal protection from inadvertent Write operations, e.g., during the system power-up or power-down. Any Erase operation requires the inclusion of six-byte sequence. The SST34HF3223B/3243B are shipped with the Software Data Protection permanently enabled. See Table 4 for the specific software command codes. During SDP command sequence, invalid commands will abort the device to Read mode within TRC. The contents of DQ15-DQ8 can be VIL or VIH, but no other value, during any SDP command sequence. SRAM Operation With BES1# low, BES2 and BEF# (BEF1# and BEF2#) high, the SST34HF3223B operates as 256K x8 or 128K x16 CMOS SRAM, and the SST34HF3243B operates as 512K x8 or 256K x16 CMOS SRAM, with fully static operation requiring no external clocks or timing strobes. The CIOs pin configures the SRAM for x8 or x16 SRAM operation modes. The SST34HF3223B SRAM is mapped into the first 128 KWord address space of the device, and the SST34HF3243B SRAM is mapped into the first 256 KWord address space. When BES1#, BEF# (BEF1# and BEF2#) are high and BES2 is low, all memory banks are deselected and the device enters standby. Read and Write cycle times are equal. The control signals UBS# and LBS# provide access to the upper data byte and lower data byte. See Table 3 for SRAM Read and Write data byte control modes of operation. Product Identification The Product Identification mode identifies the devices as the SST34HF3223B and SST34HF3243B and manufacturer as SST. This mode may be accessed by software operations only. The hardware device ID Read operation, which is typically used by programmers cannot be used on this device because of the shared lines between flash and SRAM in the multi-chip package. Therefore, application of high voltage to pin A9 may damage this device. Users may use the software Product Identification operation to identify the part (i.e., using the device code) when using multiple manufacturers in the same socket. For details, see Tables 3 and 4 for software operation, Figure 15 for the software ID entry and Read timing diagram and Figure 24 for the ID entry command sequence flowchart. SRAM Read The SRAM Read operation of the SST34HF3223B/3243B is controlled by OE# and BES1#, both have to be low with WE# and BES2 high for the system to obtain data from the outputs. BES1# and BES2 are used for SRAM bank selection. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when OE# is high. Refer to the Read cycle timing diagram, Figure 4, for further details. ©2002 Silicon Storage Technology, Inc. S71197-00-000 1/02 4 543 32 Mbit Concurrent SuperFlash + 2 / 4 Mbit SRAM ComboMemory SST34HF3223B / SST34HF3243B Preliminary Information SRAM Write The SRAM Write operation of the SST34HF3223B/3243B is controlled by WE# and BES1#, both have to be low, BES2 has to be high for the system to write to the SRAM. During the Word-Write operation, the addresses and data are referenced to the rising edge of BES1# or WE# the fall- ing edge of BES2 whichever occur first. The write time is measured from the last falling edge of BES1# or WE# or the rising edge of BES2 to the first rising edge of BES1# or WE# or the falling edge of BES2. Refer to the Write cycle timing diagram, Figures 5 and 6, for further details. FUNCTIONAL BLOCK DIAGRAM Address Buffers AMS - A0 BEF1# BEF2# SA LBS# UBS# WE# OE# BES1# BES2 CIOs WP# RST# RY/BY# SuperFlash Memory (Bank 1) SuperFlash Memory (Bank 2) Control Logic DQ15 - DQ8 I/O Buffers DQ7 - DQ0 2 Mbit or 4 Mbit SRAM Address Buffers 543 ILL B1.0 AMS = Most significant address ©2002 Silicon Storage Technology, Inc. S71197-00-000 1/02 5 543 32 Mbit Concurrent SuperFlash + 2 / 4 Mbit SRAM ComboMemory SST34HF3223B / SST34HF3243B Preliminary Information 001000H 000000H Block 60 Block 59 Block 58 Block 57 Block 56 Bank 2 Block 55 Block 54 Block 35 Block 34 Block 33 Block 32 Block 31 Block 30 Block 29 Block 28 Block 27 Block 26 Block 25 Block 24 Block 23 Bank 1 Block 22 Block 21 Bank 1A 4 KWord Sector Protection (Four 1 KWord Sectors) Block 61 Bank 1B 1FFFFH 18000H 17FFFH 10000H 00FFFFH 008000H 007FFFH Block 62 Bank 2A 11FFFFH 118000H 117FFFH 110000H 10FFFFH 108000H 107FFFH 100000H FFFFFH F8000H F7FFFH F0000H EFFFFH E8000H E7FFFH E0000H DFFFFH D8000H D7FFFH D0000H CFFFFH C8000H C7FFFH C0000H BFFFFH B8000H B7FFFH B0000H AFFFFH A8000H Block 63 Bank 2B 1FFFFFH 1F8000H 1F7FFFH 1F0000H 1EFFFFH 1E8000H 1E7FFFH 1E0000H 1DFFFFH 1D8000H 1D7FFFH 1D0000H 1CFFFFH 1C8000H 1C7FFFH 1C0000H 1BFFFFH 1B8000H 1B7FFFH 1B0000H Block 3 Block 2 Block 1 Block 0 543 ILL F01.1 FIGURE 1: 2 MEGABIT X 16 CONCURRENT SUPERFLASH QUAD-BANK MEMORY ORGANIZATION ©2002 Silicon Storage Technology, Inc. S71197-00-000 1/02 6 543 32 Mbit Concurrent SuperFlash + 2 / 4 Mbit SRAM ComboMemory SST34HF3223B / SST34HF3243B Preliminary Information TOP VIEW (balls facing down) 8 7 6 5 4 A15 BEF1# BEF2# A16 A11 A12 A13 A14 A8 A19 A9 A10 WE# BES2 NC SA NC VSS DQ15 DQ7 DQ14 DQ6 DQ13 DQ12 DQ5 DQ4 VDDS CIOs WP# RST# RY/BY# DQ3 VDDF DQ11 3 LBS# UBS# A18 A17 DQ1 DQ9 DQ10 DQ2 VSS OE# 2 A7 A6 A5 A4 A3 A2 A1 DQ0 DQ8 1 NC A0 BES1# A B C D E F G H SST34HF3223B/3243B FIGURE 2: PIN ASSIGNMENTS FOR 56-BALL LFBGA (10MM X 543 ILL F02.2 12MM) TOP VIEW (balls facing down) 8 7 6 5 4 A15 NC NC A16 A11 A12 A13 A14 SA A8 A19 A9 A10 NC VSS DQ15 DQ7 DQ14 DQ6 DQ13 DQ12 DQ5 WE# BES2 A20 DQ4 VDDS CIOs WP# RST# RY/BY# DQ3 VDDF DQ11 3 LBS# UBS# A18 A17 DQ1 DQ9 DQ10 DQ2 VSS OE# 2 A7 A6 A5 A4 A3 A2 A1 DQ0 DQ8 1 A0 BEF# BES1# A B C D E F G H SST34HF322x/324x FIGURE 3: PIN ASSIGNMENTS FOR 56-BALL LFBGA (10MM X 543 ILL F03.0 12MM) APPLY TO FUTURE SST34HF322X/324X Note: Please refer to application note, Design-In SST34HF3223A/3243A/3223B/3243B Devices, to achieve dropin replacement when SST34HF322x/324x/328x becomes available. ©2002 Silicon Storage Technology, Inc. S71197-00-000 1/02 7 543 32 Mbit Concurrent SuperFlash + 2 / 4 Mbit SRAM ComboMemory SST34HF3223B / SST34HF3243B Preliminary Information TABLE 2: PIN DESCRIPTION Symbol Pin Name Functions AMS1 to A0 Address Inputs To provide flash address, A19-A0. To provide SRAM address, A16-A0 for 2M and A17-A0 for 4M SA Address Input (SRAM) To provide SRAM address input in byte mode (x8). When CIOs is VIL, the SRAM is in byte mode and SA provides the most significant address input. When CIOs is VIH, the SRAM is in Word mode and SA becomes a “Don’t Care” pin. DQ15DQ0 Data Inputs/Outputs To output data during Read cycles and receive input data during Write cycles. Data is internally latched during a flash Erase/Program cycle. The outputs are in tri-state when OE# is high or BES1# is high/BES2 is low, and BEF# (BEF1# and BEF2#) is high. BEF1# Flash Memory Bank 1 Enable To activate the flash memory bank 1 when BEF1# is low BEF2# Flash Memory Bank 2 Enable To activate the flash memory bank 2 when BEF2# is low BES1# SRAM Memory Bank Enable To activate the SRAM memory bank when BES1# is low BES2 SRAM Memory Bank Enable To activate the SRAM memory bank when BES2 is high OE# Output Enable To gate the data output buffers WE# Write Enable To control the Write operations UBS# Upper Byte Control (SRAM) To enable DQ15-DQ8 LBS# Lower Byte Control (SRAM) To enable DQ7-DQ0 CIOs I/O Configuration (SRAM) CIOs = VIH is Word mode (x16), CIOs = VIL is Byte mode (x8) WP# Write Protect To protect and unprotect sectors from Erase or Program operation (for Bank 1 only) RST# Reset To Reset and return the device to Read mode RY/BY# Ready/Busy# To output the status of the Program or Erase operation (for Bank 2 only). RY/BY# is an open drain output, so a 10KΩ-100KΩ pull-up resistor is required to allow RY/BY# to transition high indicating the device is ready to read. VSS Ground VDDF VDDS Power Supply (flash) Power Supply to flash only (2.7-3.3V) Power Supply (SRAM) Power Supply to SRAM only (2.7-3.3V) NC No Connection Unconnected pins T2.3 543 1. AMS = Most Significant Address ©2002 Silicon Storage Technology, Inc. S71197-00-000 1/02 8 543 32 Mbit Concurrent SuperFlash + 2 / 4 Mbit SRAM ComboMemory SST34HF3223B / SST34HF3243B Preliminary Information TABLE 3: OPERATIONAL MODES SELECTION BEF#1 BES1# BES22 CIOs3 OE# WE# SA LBS# UBS# DQ7-0 DQ15-8 Flash Read VIL VIH X4 X VIL VIH X X X DOUT DOUT X VIL Flash Write VIL VIH X X VIH VIL X X X DIN DIN X VIL Flash Erase VIL VIH X X VIH VIL X X X X X X VIL SRAM Read VIH VIL VIH VIH VIL VIH X VIL VIL DOUT DOUT X VIH VIL HIGH-Z DOUT X VIL VIH DOUT HIGH-Z Mode SRAM Write VIH VIL VIH VIL VIL VIH SA X X DOUT HIGH-Z VIH VIL VIH VIH X VIL X VIL VIL DIN DIN X VIH VIL HIGH-Z DIN X VIL VIH DIN HIGH-Z VIH VIL VIH VIL X VIL SA X X DIN HIGH-Z Full Standby VIH VIH X X X X X X X HIGH-Z HIGH-Z X VIL X X X X X X Output Disable VIH VIL VIH X VIH VIH X X X HIGH-Z HIGH-Z VIL VIH VIH VIL VIH X VIH VIH VIL VIH X X VIH VIH X X X HIGH-Z HIGH-Z X VIL VIL VIH X X VIL VIH X X X Manufacturer’s ID5 X VIL Product Identification Software Mode Device ID5 T3.0 543 1. BEF# = BEF1# for operations that apply to flash Bank 1. BEF# = BEF2# for operations that apply to flash Bank 2. 2. Do not apply BEF# = VIL, BES1# = VIL and BES2 = VIH at the same time 3. SRAM I/O configuration input CIOs; VIH = x16 (Word mode), VIL = x8 (Byte mode) 4. X can be VIL or VIH, but no other value. 5. With A19-A1 =0; SST Manufacturer’s ID = 00BFH, is read with A0 = 0, SST34HF3223B Device ID = 2761H, is read with A0 = 1. SST34HF3243B Device ID = 2761H, is read with A0 = 1. . ©2002 Silicon Storage Technology, Inc. S71197-00-000 1/02 9 543 32 Mbit Concurrent SuperFlash + 2 / 4 Mbit SRAM ComboMemory SST34HF3223B / SST34HF3243B Preliminary Information TABLE 4: SOFTWARE COMMAND SEQUENCE Command Sequence 1st Bus Write Cycle Addr1 Data2 2nd Bus Write Cycle Addr1 Data2 3rd Bus Write Cycle Addr1 4th Bus Write Cycle Data2 Addr1 Data2 Data AAH Word-Program 5555H AAH 2AAAH 55H 5555H A0H WA3 Sector-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H 5th Bus Write Cycle 6th Bus Write Cycle Addr1 Data2 Addr1 Data2 2AAAH 55H SAX4 30H 50H 10H Block-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H BAX4 Chip-Erase 5555H AAH 2AAAH 55H 5555H 80H 5555H AAH 2AAAH 55H 5555H Entry5 5555H AAH 2AAAH 55H 5555H 90H Software ID Exit5,6 5555H AAH 2AAAH 55H 5555H F0H Software ID T4.2 543 1. 2. 3. 4. Address format A14-A0 (Hex), Address A19-A15 can be VIL or VIH, but no other value, for Command sequence. DQ15-DQ8 can be VIL or VIH, but no other value, for Command sequence. WA = Program Word address. SAX for Sector-Erase; uses A19-A11 address lines. BAX for Block-Erase; uses A19-A15 address lines. 5. The device does not remain in Software Product Identification Mode if powered down. SST Manufacturer’s ID = 00BFH, is read with A0 = 0 6. With A20-A1 = 0; SST34HF3223B/3243B Device ID = 2761H, is read with A0 = 1. Absolute Maximum Stress Ratings (Applied conditions greater than those listed under “Absolute Maximum Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -20°C to +85°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +125°C D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD + 0.3V Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0V to VDD + 1.0V Package Power Dissipation Capability (Ta = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W Output Short Circuit Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA OPERATING RANGE Range Commercial Extended AC CONDITIONS OF TEST Input Rise/Fall Time . . . . . . . . . . . . . . . 5 ns Ambient Temp VDD 0°C to +70°C 2.7-3.3V Output Load . . . . . . . . . . . . . . . . . . . . . CL = 30 pF -20°C to +85°C 2.7-3.3V See Figures 20 and 21 ©2002 Silicon Storage Technology, Inc. S71197-00-000 1/02 10 543 32 Mbit Concurrent SuperFlash + 2 / 4 Mbit SRAM ComboMemory SST34HF3223B / SST34HF3243B Preliminary Information TABLE 5: DC OPERATING CHARACTERISTICS (VDD1 = 2.7-3.3V) Limits Symbol Parameter IDD Active VDD Current Min Max Units Test Conditions Address input = VIL/VIH, at f=1/TRC Min, VDD=VDD Max, all DQs open 35 mA OE#=VIL, WE#=VIH BEF#=VIL, BES1#=VIH or BES2 = VIL 20 mA BEF#=VIH, BES1#=VIL, BES2 = VIH Concurrent Operation 60 mA BEF#=VIH, BES#=VIL Write2 Flash 40 mA WE#=VIL BEF#=VIL, BES1#=VIH or BES2 = VIL, OE#=VIH Read Flash SRAM SRAM 20 mA BEF#=VIH, BES1#=VIL, BES2 = VIH 40 75 µA µA VDD = VDD Max, BEF#=BES1#=VIHC BES2 = VILC Input Leakage Current 1 µA VIN=GND to VDD, VDD=VDD Max Output Leakage Current 1 µA VOUT=GND to VDD, VDD=VDD Max 0.8 V VDD=VDD Min 0.3 V ISB Standby VDD Current 3.0V 3.3V ILI ILO VIL Input Low Voltage VILC Input Low Voltage (CMOS) VIH Input High Voltage VIHC Input High Voltage (CMOS) VOLF Flash Output Low Voltage VOHF Flash Output High Voltage VOLS SRAM Output Low Voltage VOHS SRAM Output High Voltage 0.7 VDD VDD-0.3 V VDD=VDD Max V 0.2 VDD-0.2 V IOL=100 µA, VDD=VDD Min V IOH=-100 µA, VDD=VDD Min 0.4 2.2 IOL=1 mA, VDD=VDD Min V IOH=-500 µA, VDD=VDD Min T5.4 543 1. VDD = VDDF and VDDS 2. IDD active while Erase or Program is in progress. Note: BEF# = BEF1# for operations that apply to flash Bank 1. BEF2# for operations that apply to flash Bank 2. ©2002 Silicon Storage Technology, Inc. S71197-00-000 1/02 11 543 32 Mbit Concurrent SuperFlash + 2 / 4 Mbit SRAM ComboMemory SST34HF3223B / SST34HF3243B Preliminary Information TABLE 6: RECOMMENDED SYSTEM POWER-UP TIMINGS Symbol Parameter Minimum Units TPU-READ Power-up to Read Operation 100 µs TPU-WRITE Power-up to Write Operation 100 µs T6.0 543 TABLE 7: CAPACITANCE (Ta = 25°C, f=1 Mhz, other pins open) Parameter Description Test Condition Maximum CI/O1 I/O Pin Capacitance VI/O = 0V 24 pF Input Capacitance VIN = 0V 12 pF CIN 1 T7.0 543 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE 8: FLASH RELIABILITY CHARACTERISTICS Symbol Parameter Minimum Specification Units Test Method NEND1 Endurance 10,000 Cycles JEDEC Standard A117 TDR1 Data Retention 100 Years JEDEC Standard A103 ILTH1 Latch Up 100 + IDD mA JEDEC Standard 78 T8.0 543 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. ©2002 Silicon Storage Technology, Inc. S71197-00-000 1/02 12 543 32 Mbit Concurrent SuperFlash + 2 / 4 Mbit SRAM ComboMemory SST34HF3223B / SST34HF3243B Preliminary Information AC CHARACTERISTICS TABLE 9: SRAM READ CYCLE TIMING PARAMETERS SST34HF3223B/3243B-70 Symbol Parameter Min 70 Max SST34HF3223B/3243B-90 Min Max Units 90 ns TRCS Read Cycle Time TAAS Address Access Time TBES Bank Enable Access Time 70 90 ns TOES Output Enable Access Time 35 45 ns TBYES UBS#, LBS# Access Time TBLZS1 Bank Enable to Active Output 0 0 ns TOLZS1 Output Enable to Active Output 0 0 ns TBYLZS1 UBS#, LBS# to Active Output 0 0 ns TBHZS 1 90 70 70 ns 90 ns Bank Enable to High-Z Output 25 35 ns TOHZS1 Output Disable to High-Z Output 25 35 ns TBYHZS1 UBS#, LBS# to High-Z Output 45 ns TOHS Output Hold from Address Change 35 10 10 ns T9.0 543 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. TABLE 10: SRAM WRITE CYCLE TIMING PARAMETERS SST34HF3223B/3243B-70 Symbol Parameter Min Max SST34HF3223B/3243B-90 Min Max Units TWCS Write Cycle Time 70 90 ns TBWS Bank Enable to End-of-Write 60 80 ns TAWS Address Valid to End-of-Write 60 80 ns TASTS Address Set-up Time 0 0 ns TWPS Write Pulse Width 60 80 ns TWRS Write Recovery Time 0 0 ns TBYWS UBS#, LBS# to End-of-Write 60 TODWS Output Disable from WE# Low TOEWS Output Enable from WE# High 0 0 ns TDSS Data Set-up Time 30 40 ns TDHS Data Hold from Write Time 0 0 80 30 ns 40 ns ns T10.0 543 ©2002 Silicon Storage Technology, Inc. S71197-00-000 1/02 13 543 32 Mbit Concurrent SuperFlash + 2 / 4 Mbit SRAM ComboMemory SST34HF3223B / SST34HF3243B Preliminary Information TABLE 11: FLASH READ CYCLE TIMING PARAMETERS VDD = 2.7-3.3V SST34HF3223B/3243B-70 Max SST34HF3223B/3243B-90 Symbol Parameter Min TRC Read Cycle Time 70 TCE Chip Enable Access Time 70 90 ns TAA Address Access Time 70 90 ns TOE Output Enable Access Time 45 ns TCLZ1 CE# Low to Active Output 0 TOLZ1 TCHZ1 TOHZ1 TOH1 TRP1 TRHR1 TRY1,2 OE# Low to Active Output Max 0 90 0 ns 0 ns 20 OE# High to High-Z Output Units ns 35 CE# High to High-Z Output Output Hold from Address Change Min 30 20 30 ns ns 0 0 ns RST# Pulse Width 500 500 ns RST# High before Read 50 50 ns RST# Pin Low to Read Mode 150 150 µs T11.6 543 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. 2. This parameter applies to Sector-Erase, Block-Erase, and Program operations. This parameter does not apply to Chip-Erase. TABLE 12: FLASH PROGRAM/ERASE CYCLE TIMING PARAMETERS Symbol Parameter TBP Word-Program Time TAS Address Setup Time 0 ns TAH Address Hold Time 40 ns TCS WE# and CE# Setup Time 0 ns TCH WE# and CE# Hold Time 0 ns TOES OE# High Setup Time 0 ns TOEH OE# High Hold Time 10 ns TCP CE# Pulse Width 40 ns TWP WE# Pulse Width 40 ns TWPH1 WE# Pulse Width High 30 ns TCPH1 CE# Pulse Width High 30 ns TDS Data Setup Time 30 ns TDH1 Data Hold Time 0 ns TIDA1 Software ID Access and Exit Time 150 ns TSE Sector-Erase 25 ms TBE Block-Erase 25 ms TSCE Chip-Erase2 100 ms TBY1,3 RY/BY# Delay Time TBR 1 Min Max Units 20 µs 90 Bus Recovery Time ns 1 µs T12.6 543 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. 2. Chip-Erase operation needs to be done to each individual bank (BEF1# and BEF2#). 3. This parameter applies to Sector-Erase, Block-Erase, and Program operations. This parameter does not apply to Chip-Erase. ©2002 Silicon Storage Technology, Inc. S71197-00-000 1/02 14 543 32 Mbit Concurrent SuperFlash + 2 / 4 Mbit SRAM ComboMemory SST34HF3223B / SST34HF3243B Preliminary Information TRCS ADDRESSES AMSS-0 TOHS TAAS BES1# TBES BES2 TBES TBLZS TBHZS TOES OE# TOHZS TOLZS TBYES UBS#, LBS# TBYLZS TBYHZS DQ15-0 DATA VALID 543 ILL F04.0 AMSS = Most Significant SRAM Address FIGURE 4: SRAM READ CYCLE TIMING DIAGRAM ©2002 Silicon Storage Technology, Inc. S71197-00-000 1/02 15 543 32 Mbit Concurrent SuperFlash + 2 / 4 Mbit SRAM ComboMemory SST34HF3223B / SST34HF3243B Preliminary Information TWCS ADDRESSES AMSS-0 TASTS TWPS TWRS WE# TAWS TBWS BES1# BES2 TBWS TBYWS UBS#, LBS# TOEWS TODWS TDSS VALID DATA IN NOTE 2 DQ15-8, DQ7-0 TDHS NOTE 2 543 ILL F05.0 Notes: 1. If OE# is High during the Write cycle, the outputs will remain at high impedance. 2. If BES1# goes Low or BES2 goes High coincident with or after WE# goes Low, the output will remain at high impedance. If BES1# goes High or BES2 goes Low coincident with or before WE# goes High, the output will remain at high impedance. Because DIN signals may be in the output state at this time, input signals of reverse polarity must not be applied. FIGURE 5: SRAM WRITE CYCLE TIMING DIAGRAM (WE# CONTROLLED)1 ©2002 Silicon Storage Technology, Inc. S71197-00-000 1/02 16 543 32 Mbit Concurrent SuperFlash + 2 / 4 Mbit SRAM ComboMemory SST34HF3223B / SST34HF3243B Preliminary Information TWCS ADDRESSES AMSS-0 TWPS TWRS WE# TBWS BES1# TBWS BES2 TAWS TASTS TBYWS UBS#, LBS# TDSS DQ15-8, DQ7-0 NOTE 2 TDHS VALID DATA IN NOTE 2 543 ILL F06.0 Notes: 1. If OE# is High during the Write cycle, the outputs will remain at high impedance. 2. Because DIN signals may be in the output state at this time, input signals of reverse polarity must not be applied. FIGURE 6: SRAM WRITE CYCLE TIMING DIAGRAM (UBS#, LBS# CONTROLLED)1 ©2002 Silicon Storage Technology, Inc. S71197-00-000 1/02 17 543 32 Mbit Concurrent SuperFlash + 2 / 4 Mbit SRAM ComboMemory SST34HF3223B / SST34HF3243B Preliminary Information TRC TAA ADDRESS A19-0 TCE BEF# TOE OE# TOHZ TOLZ VIH WE# TCHZ TOH TCLZ HIGH-Z HIGH-Z DQ15-0 DATA VALID DATA VALID 543 ILL F07.0 FIGURE 7: FLASH READ CYCLE TIMING DIAGRAM TBP 5555 TAH ADDRESS A19-0 2AAA 5555 ADDR TWP WE# TAS TWPH OE# TCH BEF# TCS TBY TBR RY/BY# TDS TDH DQ15-0 XXAA XX55 XXA0 DATA WORD (ADDR/DATA) VALID 543 ILL F32.1 Note: X can be VIL or VIH, but no other value. FIGURE 8: FLASH WE# CONTROLLED WORD-PROGRAM CYCLE TIMING DIAGRAM ©2002 Silicon Storage Technology, Inc. S71197-00-000 1/02 18 543 32 Mbit Concurrent SuperFlash + 2 / 4 Mbit SRAM ComboMemory SST34HF3223B / SST34HF3243B Preliminary Information TBP 5555 TAH ADDRESS A19-0 2AAA 5555 ADDR TCP BEF# TAS TCPH OE# TCH WE# TCS TBY RY/BY# TBR TDS TDH DQ15-0 XXAA XX55 XXA0 VALID DATA WORD (ADDR/DATA) 543 ILL F33.1 Note: X can be VIL or VIH, but no other value. FIGURE 9: FLASH BEF# CONTROLLED WORD-PROGRAM CYCLE TIMING DIAGRAM ADDRESS A19-0 TCE BEF# TOES TOEH OE# TOE WE# TBR DQ7 DATA# DATA# VALID DATA 543 ILL F34.0 FIGURE 10: FLASH DATA# POLLING TIMING DIAGRAM ©2002 Silicon Storage Technology, Inc. S71197-00-000 1/02 19 543 32 Mbit Concurrent SuperFlash + 2 / 4 Mbit SRAM ComboMemory SST34HF3223B / SST34HF3243B Preliminary Information ADDRESS A19-0 TCE BEF# TOEH TOE OE# WE# TBR DQ6 VALID DATA TWO READ CYCLES WITH SAME OUTPUTS 543 ILL F35.1 FIGURE 11: FLASH TOGGLE BIT TIMING DIAGRAM TSCE SIX-BYTE CODE FOR CHIP-ERASE ADDRESS A19-0 5555 2AAA 5555 5555 2AAA 5555 BEF# OE# TWP WE# TBY TBR RY/BY# DQ15-0 XXAA XX55 XX80 XXAA XX55 XX10 VALID 543 ILL F36.2 Note: This device also supports BEF# controlled Chip-Erase operation. The WE# and BEF# signals are interchageable as long as minimum timings are met. (See Table 12) X can be VIL or VIH, but no other value. FIGURE 12: FLASH WE# CONTROLLED CHIP-ERASE TIMING DIAGRAM ©2002 Silicon Storage Technology, Inc. S71197-00-000 1/02 20 543 32 Mbit Concurrent SuperFlash + 2 / 4 Mbit SRAM ComboMemory SST34HF3223B / SST34HF3243B Preliminary Information TBE SIX-BYTE CODE FOR BLOCK-ERASE ADDRESS A19-0 5555 2AAA 5555 5555 2AAA BAX BEF# OE# TWP WE# TBR TBY RY/BY# DQ15-0 XXAA XX55 XX80 XXAA XX55 XX50 VALID 543 ILL F37.2 Note: This device also supports BEF# controlled Block-Erase operation. The WE# and BEF# signals are interchageable as long as minimum timings are met. (See Table 12) BAX = Block Address X can be VIL or VIH, but no other value. FIGURE 13: FLASH WE# CONTROLLED BLOCK-ERASE TIMING DIAGRAM SIX-BYTE CODE FOR SECTOR-ERASE 5555 ADDRESS A19-0 2AAA 5555 5555 2AAA TSE SAX BEF# OE# TWP WE# TBY TBR RY/BY# DQ15-0 XXAA XX55 XX80 XXAA XX55 XX30 VALID 543 ILL F38.2 Note: This device also supports BEF# controlled Sector-Erase operation. The WE# and BEF# signals are interchageable as long as minimum timings are met. (See Table 12) SAX = Sector Address X can be VIL or VIH, but no other value. FIGURE 14: FLASH WE# CONTROLLED SECTOR-ERASE TIMING DIAGRAM ©2002 Silicon Storage Technology, Inc. S71197-00-000 1/02 21 543 32 Mbit Concurrent SuperFlash + 2 / 4 Mbit SRAM ComboMemory SST34HF3223B / SST34HF3243B Preliminary Information THREE-BYTE SEQUENCE FOR SOFTWARE ID ENTRY ADDRESS A14-0 5555 2AAA 5555 0000 0001 BEF# OE# TIDA TWP WE# TWPH DQ15-0 XXAA XX55 TAA XX90 00BF Device ID 543 ILL F39.1 Device ID = 2761H for SST34HF3223B and 2761H for SST34HF3243B Note: X can be VIL or VIH, but no other value. FIGURE 15: FLASH SOFTWARE ID ENTRY AND READ THREE-BYTE SEQUENCE FOR CFI QUERY ENTRY 5555 ADDRESS A14-0 2AAA 5555 BEF# OE# TIDA TWP WE# TWPH DQ15-0 XXAA XX55 TAA XX98 543 ILL F30.1 Note: X can be VIL or VIH, but no other value. FIGURE 16: CFI ENTRY AND READ ©2002 Silicon Storage Technology, Inc. S71197-00-000 1/02 22 543 32 Mbit Concurrent SuperFlash + 2 / 4 Mbit SRAM ComboMemory SST34HF3223B / SST34HF3243B Preliminary Information THREE-BYTE SEQUENCE FOR SOFTWARE ID EXIT AND RESET 5555 ADDRESS A14-0 DQ15-0 2AAA XXAA 5555 XX55 XXF0 TIDA BEF# OE# TWP WE# TWHP 543 ILL F15.2 Note: X can be VIL or VIH, but no other value. FIGURE 17: FLASH SOFTWARE ID EXIT/CFI EXIT RY/BY# 0V TRP RST# BEF#/OE# 543 ILL F40.1 TRHR FIGURE 18: RST# TIMING DIAGRAM (WHEN NO INTERNAL OPERATION IS IN PROGRESS) ©2002 Silicon Storage Technology, Inc. S71197-00-000 1/02 23 543 32 Mbit Concurrent SuperFlash + 2 / 4 Mbit SRAM ComboMemory SST34HF3223B / SST34HF3243B Preliminary Information TRY RY/BY# RST# TRP BEF# TBR OE# 543 ILL F41.1 FIGURE 19: RST# TIMING DIAGRAM (DURING SECTOR- OR BLOCK-ERASE OPERATION) VIHT INPUT VIT REFERENCE POINTS VOT OUTPUT VILT 543 ILL F19.0 AC test inputs are driven at VIHT (0.9 VDD) for a logic “1” and VILT (0.1 VDD) for a logic “0”. Measurement reference points for inputs and outputs are VIT (0.5 VDD) and VOT (0.5 VDD). Input rise and fall times (10% ↔ 90%) are <5 ns. Note: VIT - VINPUT Test VOT - VOUTPUT Test VIHT - VINPUT HIGH Test VILT - VINPUT LOW Test FIGURE 20: AC INPUT/OUTPUT REFERENCE WAVEFORMS TO TESTER TO DUT CL 543 ILL F20.0 FIGURE 21: A TEST LOAD EXAMPLE ©2002 Silicon Storage Technology, Inc. S71197-00-000 1/02 24 543 32 Mbit Concurrent SuperFlash + 2 / 4 Mbit SRAM ComboMemory SST34HF3223B / SST34HF3243B Preliminary Information Start Load data: XXAAH Address: 5555H Load data: XX55H Address: 2AAAH Load data: XXA0H Address: 5555H Load Word Address/Word Data Wait for end of Program (TBP, Data# Polling bit, or Toggle bit operation) Program Completed 543 ILL F21.0 Note: X can be VIL or VIH, but no other value. FIGURE 22: WORD-PROGRAM ALGORITHM ©2002 Silicon Storage Technology, Inc. S71197-00-000 1/02 25 543 32 Mbit Concurrent SuperFlash + 2 / 4 Mbit SRAM ComboMemory SST34HF3223B / SST34HF3243B Preliminary Information Internal Timer Toggle Bit Data# Polling Program/Erase Initiated Program/Erase Initiated Program/Erase Initiated Wait TBP, TSCE, TSE or TBE Read word Read DQ7 Read same word Program/Erase Completed No Is DQ7 = true data? Yes No Does DQ6 match? Program/Erase Completed Yes Program/Erase Completed 543 ILL F22.0 FIGURE 23: WAIT OPTIONS ©2002 Silicon Storage Technology, Inc. S71197-00-000 1/02 26 543 32 Mbit Concurrent SuperFlash + 2 / 4 Mbit SRAM ComboMemory SST34HF3223B / SST34HF3243B Preliminary Information CFI Query Entry Command Sequence Software Product ID Entry Command Sequence Software ID Exit/CFI Exit Command Sequence Load data: XXAAH Address: 5555H Load data: XXAAH Address: 5555H Load data: XXAAH Address: 5555H Load data: XX55H Address: 2AAAH Load data: XX55H Address: 2AAAH Load data: XX55H Address: 2AAAH Load data: XX98H Address: 5555H Load data: XX90H Address: 5555H Load data: XXF0H Address: 5555H Wait TIDA Wait TIDA Wait TIDA Read CFI data Read Software ID Return to normal operation 543 ILL F23.1 Note: X can be VIL or VIH, but no other value. FIGURE 24: SOFTWARE PRODUCT ID/CFI COMMAND FLOWCHARTS ©2002 Silicon Storage Technology, Inc. S71197-00-000 1/02 27 543 32 Mbit Concurrent SuperFlash + 2 / 4 Mbit SRAM ComboMemory SST34HF3223B / SST34HF3243B Preliminary Information Chip-Erase Command Sequence Sector-Erase Command Sequence Block-Erase Command Sequence Load data: XXAAH Address: 5555H Load data: XXAAH Address: 5555H Load data: XXAAH Address: 5555H Load data: XX55H Address: 2AAAH Load data: XX55H Address: 2AAAH Load data: XX55H Address: 2AAAH Load data: XX80H Address: 5555H Load data: XX80H Address: 5555H Load data: XX80H Address: 5555H Load data: XXAAH Address: 5555H Load data: XXAAH Address: 5555H Load data: XXAAH Address: 5555H Load data: XX55H Address: 2AAAH Load data: XX55H Address: 2AAAH Load data: XX55H Address: 2AAAH Load data: XX10H Address: 5555H Load data: XX30H Address: SAX Load data: XX50H Address: BAX Wait Options1 Wait Options1 Wait Options1 Chip erased to FFFFH Sector erased to FFFFH Block erased to FFFFH 543 ILL F24.0 Note: X can be VIL or VIH, but no other value. Refer to Figure 23 FIGURE 25: ERASE COMMAND SEQUENCE ©2002 Silicon Storage Technology, Inc. S71197-00-000 1/02 28 543 32 Mbit Concurrent SuperFlash + 2 / 4 Mbit SRAM ComboMemory SST34HF3223B / SST34HF3243B Preliminary Information PRODUCT ORDERING INFORMATION Device Speed SST34HF32x3B - XXX Suffix1 - XX Suffix2 - XX Package Modifier P = 56 pins Package Type L = LFBGA (10mm x 12mm x 1.4mm) Temperature Range C = Commercial = 0°C to +70°C E = Extended = -20°C to +85°C Minimum Endurance 4 =10,000 cycles Read Access Speed 70 = 70 ns 90 = 90 ns Version Bank Split 3 = 16 Mbit (12+4) + 16 Mbit (12+4). Total 4 banks. SRAM Density 0 = no SRAM 2 = 2 Mbit 4 = 4 Mbit Flash Density 32 = 32 Mbit Voltage H = 2.7-3.3V Device Family 34 = CSF + SRAM ComboMemory Valid combinations for SST34HF3223B SST34HF3223B-70-4C-LP SST34HF3223B-90-4C-LP SST34HF3223B-70-4E-LP SST34HF3223B-90-4E-LP Valid combinations for SST34HF3243B SST34HF3243B-70-4C-LP SST34HF3243B-90-4C-LP SST34HF3243B-70-4E-LP SST34HF3243B-90-4E-LP Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations. ©2002 Silicon Storage Technology, Inc. S71197-00-000 1/02 29 543 32 Mbit Concurrent SuperFlash + 2 / 4 Mbit SRAM ComboMemory SST34HF3223B / SST34HF3243B Preliminary Information PACKAGING DIAGRAMS BOTTOM VIEW 12.00 ± 0.20 5.60 TOP VIEW 0.80 8 8 7 7 10.00 ± 0.20 6 6 5.60 5 5 4 4 3 3 2 2 1 1 0.80 0.45 ± 0.05 (56X) A1 CORNER H G F E D C B A A B C D E F G H A1 CORNER 1.30 ± 0.10 SIDE VIEW 56ba-LFBGA-LP-10x12-450mic-ILL.2 0.15 SEATING PLANE 1mm 0.35 ± 0.05 Note: 1. Although many dimensions are similar to those of JEDEC Publication 95, MO-210, this specific package is not registered. 2. All linear dimensions are in millimeters (min/max). 3. Coplanarity: 0.1 (±.05) mm. 4. The actual shape of the corners may be slightly different than as portrayed in the drawing. 56-BALL LOW-PROFILE, FINE-PITCH BALL GRID ARRAY (LFBGA) 10MM SST PACKAGE CODE: LP X 12MM (64 POSSIBLE BALL POSITIONS) Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036 www.SuperFlash.com or www.sst.com ©2002 Silicon Storage Technology, Inc. S71197-00-000 1/02 30 543