STK20C04 STK20C04 CMOS nvSRAM High Performance 512 x 8 Nonvolatile Static RAM FEATURES DESCRIPTION • • • • • • • • • • • • • The Simtek STK20C04 is a fast static RAM (30, 35, 45ns), with a nonvolatile electrically-erasable PROM (EEPROM) element incorporated in each static memory cell. The SRAM can be read and written an unlimited number of times, while independent nonvolatile data resides in EEPROM. Data may easily be transferred from the SRAM to the EEPROM (STORE), or from the EEPROM to the SRAM (RECALL) using the NE pin. It combines the high performance and ease of use of a fast SRAM with nonvolatile data integrity. 30, 35 and 45ns Access Times 15, 20 and 25ns Output Enable Access Unlimited Read and Write to SRAM Hardware STORE Initiation Automatic STORE Timing 105 STORE cycles to EEPROM 10 year data retention in EEPROM Automatic RECALL on Power Up Hardware RECALL Initiation Unlimited RECALL cycles from EEPROM Single 5V±10% Operation Commercial and Industrial Temperatures Available in 600 mil PDIP package The STK20C04 features the industry standard pinout for nonvolatile RAMs in a 28-pin 600 mil plastic DIP. LOGIC BLOCK DIAGRAM PIN CONFIGURATIONS NE NC A7 EEPROM ARRAY 64 X 64 STORE A4 A5 A6 A7 ROW DECODER A3 RECALL STATIC RAM A 6 A A A 5 A ARRAY A A 64 X 64 DQ DQ DO A8 4 3 2 1 0 0 1 1 28 2 27 3 26 V CC W NC 4 25 A 5 24 6 23 7 22 NC NC G 8 21 9 20 10 19 NC E DQ 7 11 18 DQ 6 12 17 13 16 DQ 5 DQ 4 14 15 DQ 3 2 VSS 8 28 - 600 PDIP DQ 0 COLUMN I/O DQ 2 DQ 3 DQ 4 DQ 5 INPUT BUFFERS DQ 1 STORE/ RECALL CONTROL PIN NAMES COLUMN DECODER A0 A1 A2 G NE DQ 6 Address Inputs W Write Enable DQ0 - DQ7 Data In/Out E Chip Enable G Output Enable NE Nonvolatile Enable E VCC Power (+5V) W VSS Ground DQ 7 2-39 A0 - A8 STK20C04 ABSOLUTE MAXIMUM RATINGS a Voltage on typical input relative to VSS. . . . . . . . . . . . . –0.6V to 7.0V Voltage on DQ0-7 and G. . . . . . . . . . . . . . . . . . .–0.5V to (VCC+0.5V) Temperature under bias . . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C Storage temperature. . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C Power dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1W DC output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15mA Note a: Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. (One output at a time, one second duration) (VCC = 5.0V ± 10%) DC CHARACTERISTICS SYMBOL ICC b 1 ICC d 2 COMMERCIAL INDUSTRIAL MIN MIN PARAMETER Average VCC Current Average VCC Current MAX MAX UNITS 80 85 mA tAVAV = 30ns 75 80 mA tAVAV = 35ns 65 75 mA tAVAV = 45ns 50 50 mA 1 All inputs at VIN ≤ 0.2V or ≥ (VCC – 0.2V) during STORE cycle ISB c NOTES Average VCC Current 27 30 mA tAVAV = 30ns (Standby, Cycling TTL Input Levels) 23 27 mA tAVAV = 35ns 20 23 mA tAVAV = 45ns 1 1 mA E ≥ (VCC – 0.2V) VCC = max E ≥ VIH; all others cycling ISB c 2 Average VCC Current all others VIN ≤ 0.2V or ≥ (VCC – 0.2V) (Standby, Stable CMOS Input Levels) IILK Input Leakage Current (Any Input) ±1 ±1 µA IOLK Off State Output Leakage Current ±5 ±5 µA VIN = VSS to VCC VCC = max VIN = VSS to VCC VIH Input Logic "1" Voltage 2.2 VCC+.5 2.2 VCC+.5 V All Inputs VIL Input Logic "0" Voltage VSS–.5 0.8 VSS–.5 0.8 V All Inputs VOH Output Logic "1" Voltage VOL Output Logic "0" Voltage TA Operating Temperature 2.4 2.4 0.4 0 70 –40 V IOUT = –4mA 0.4 V IOUT = 8mA 85 °C Note b: ICC1 is dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded. Note c: Bringing E ≥ VIH will not produce standby current levels until any nonvolatile cycle in progress has timed out. See MODE SELECTION table. Note d: ICC 2 is the average current required for the duration of the store cycle (t STORE) after the sequence (tWC) that initiates the cycle. AC TEST CONDITIONS Input Pulse Levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . V SS to 3V Input Rise and Fall Times. . . . . . . . . . . . . . . . . . . . . . . . . . ≤ 5ns Input and Output Timing Reference Levels. . . . . . . . . . . . . . 1.5V Output Load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1 5.0V 480 Ohms Output CAPACITANCE (TA=25°C, f=1.0MHz)e 255 Ohms SYMBOL PARAMETER MAX UNITS CONDITIONS CIN Input Capacitance 7 pF ∆V = 0 to 3V COUT Output Capacitance & W 7 pF ∆V = 0 to 3V 30pF INCLUDING SCOPE AND FIXTURE Figure 1: AC Output Loading Note e: These parameters are guaranteed but not tested. 2-40 STK20C04 (VCC = 5.0V ± 10%) READ CYCLES #1 & #2 SYMBOLS NO. 1 #1, #2 tELQV g STK20C04-30 STK20C04-35 STK20C04-45 MIN MIN MIN PARAMETER Alt. tACS Chip Enable Access Time tRC Read Cycle Time tAA Address Access Time MAX 30 MAX 35 45 3 tAVQV h 4 tGLQV tOE Output Enable to Data Valid 5 tAXQX tOH Output Hold After Address Change 5 5 5 ns 6 tELQX tLZ Chip Enable to Output Active 5 5 5 ns 7 tEHQZi tHZ Chip Disable to Output Inactive 8 tGLQX tOLZ Output Enable to Output Active tGHQZ 30 ns 35 15 20 18 0 45 ns tAVAVR 9 35 UNITS 2 i 30 MAX 20 ns 25 ns 25 0 0 ns ns tOHZ Output Disable to Output Inactive tELICCH e tPA Chip Enable to Power Active 11 tEHICCL c,e tPS Chip Disable to Power Standby 25 25 25 ns 11A tWHQV tWR Write Recovery Time 35 45 55 ns 10 Note c: Note e: Note f: Note g: Note h: 18 45 0 20 25 0 0 ns Bringing E high will not produce standby currents until any nonvolatile cycle in progress has timed out. See MODE SELECTION table. Parameter guaranteed but not tested. NE must be high during entire cycle. For READ CYCLE #1 and #2, W and NE must be high for entire cycle. Device is continuously selected with E low and G low. Note i: Measured ± 200mV from steady state output voltage. READ CYCLE #1 f,g,h 2 tAVAVR ADDRESS 3 tAVQV 5 tAXQX DQ (Data Out) DATA VALID W 11A tWHQV READ CYCLE #2 f,g 2 tAVAVR ADDRESS 1 tELQV 6 E 9 tGHQZ 8 tGLQX DQ (Data Out) DATA VALID 10 tELICCH W 7 tEHQZ 4 tGLQV G ICC 11 tEHICCL tELQX ACTIVE STANDBY 11A tWHQV 2-41 ns STK20C04 (VCC = 5.0V ± 10%) WRITE CYCLES #1 & #2 SYMBOLS NO. #1 #2 #3 PARAMETER STK20C04-30 STK20C04-35 STK20C04-45 MIN MIN MIN MAX MAX MAX UNITS 12 tAVAVW tAVAVW tWC Write Cycle Time 45 45 45 ns 13 tWLWH tWLEH tWP Write Pulse Width 35 35 35 ns 14 tELWH tELEH tCW Chip Enable to End of Write 35 35 35 ns 15 tDVWH tDVEH tDW Data Set-up to End of Write 30 30 30 ns 16 tWHDX tEHDX tDH Data Hold After End of Write 0 0 0 ns 17 tAVWH tAVEH tAW Address Set-up to End of Write 35 35 35 ns 18 tAVWL tAVEL tAS Address Set-up to Start of Write 0 0 0 ns 19 tWHAX tEHAX tWR Address Hold After End of Write 0 0 0 ns tWZ Write Enable to Output Disable tOW Output Active After End of Write i,m 20 tWLQZ 21 tWHQX Note f: 35 35 5 35 5 5 NE must be high during entire cycle. Note i: Measured ± 200mV from steady state output voltage. Note k: E or W must be high during address transitions. Note m: If W is low when E goes low, the outputs remain in the high impedance state. WRITE CYCLE #1: W CONTROLLED f,k 12 tAVAVW ADDRESS 14 tELWH 19 tWHAX E 17 tAVWH 18 13 tWLWH tAVWL W 15 tDVWH DATA IN 16 tWHDX DATA VALID 20 tWLQZ DATA OUT 21 tWHQX HIGH IMPEDANCE PREVIOUS DATA WRITE CYCLE #2: E CONTROLLED f,k 12 tAVAVW ADDRESS 18 tAVEL 14 tELEH 19 tEHAX E 17 tAVEH W 13 tWLEH 15 tDVEH DATA IN DATA OUT 16 tEHDX DATA VALID HIGH IMPEDANCE 2-42 ns ns STK20C04 NONVOLATILE MEMORY OPERATION MODE SELECTION E W G NE MODE POWER H X L H X X Not Selected Standby L H Read RAM L Active L X H Write RAM Active L H L L Nonvolatile RECALLn Active L L H L Nonvolatile STORE ICC L L L L No operation Active L H H X 2 (VCC = 5.0V ± 10%) STORE CYCLES #1 & #2 SYMBOLS NO. #1 #2 Alt. 22 tWLQXp tELQXS tSTORE 23 tWLNH q tELNHS tWC 24 tGHNL 25 26 tNLWL 27 tELWL 28 PARAMETER MIN STORE Cycle Time STORE Initiation Cycle Time MAX UNITS 10 ms 45 ns Output Disable Set-up to NE Fall 0 ns tGHEL Output Disable Set-up to E Fall 0 ns tNLEL NE Set-up 0 ns Chip Enable Set-up 0 ns Write Enable Set-up 0 ns tWLEL Note: n: An automatic RECALL also takes place at power up, starting when VCC exceeds 3.8V, and taking tRECALL from the time at which VCC exceeds 4.5V. VCC must not drop below 3.8V once it has exceeded it for the RECALL to function properly. Note o: If E is low for any period of time in which W is high while G and NE are low, then a RECALL cycle may be initiated. Note p: Measured with W and NE both returned high, and G returned low. Note that STORE cycles are inhibited/aborted by VCC < 3.8V (STORE inhibit). Note q: Once tWC has been satisfied by NE, G, W and E, the STORE cycle is completed automatically. Any of NE, G, W or E may be used to terminate the STORE initiation cycle. STORE CYCLE #1: W CONTROLLEDo NE G 24 tGHNL 26 tNLWL 23 tWLNH W E DQ (Data Out) 27 tELWL 22 tWLQX HIGH IMPEDANCE STORE CYCLE #2: E CONTROLLEDo 26 tNLEL NE 25 tGHEL G W 28 tWLEL 23 tELNHS E DQ (Data Out) 22 tELQXS HIGH IMPEDANCE 2-43 STK20C04 (VCC = 5.0V ± 10%) RECALL CYCLES #1, #2 & #3 SYMBOLS NO. #1 #2 Alt. PARAMETER MIN MAX UNITS 20 µs 29 tNLQXr tELQXR tGLQXR 30 s tELNHR tGLNH RECALL Initiation Cycle Time 25 ns tNLEL tNLGL NE Set-up 0 ns Output Enable Set-up 0 ns Write Enable Set-up 0 ns Chip Enable Set-up 0 tNLNH 31 32 33 tGLNL tWHNL 34 tELNL 35 tNLQZ tGLEL tWHEL tWHGL tELGL t RECALL Cycle Time NE Fall to Outputs Inactive ns 25 ns Note r: Measured with W and NE both high, and G and E low. Note s: Once tNLNH has been satisfied by NE, G, W and E, the RECALL cycle is completed automatically. Any of NE, G or E may be used to terminate the RECALL initiation cycle. Note t: If W is low at any point in which both E and NE are low and G is high, then a STORE cycle will be initiated instead of a RECALL. RECALL CYCLE #1: NE CONTROLLED o 30 tNLNH NE 32 tGLNL G W 33 tWHNL E 34 tELNL 29 tNLQX 35 tNLQZ HIGH IMPEDANCE DQ (Data Out) RECALL CYCLE #2: E CONTROLLEDo 31 tNLEL NE G 32 tGLEL 33 tWHEL W 30 tELNHR E DQ (Data Out) 29 tELQXR HIGH IMPEDANCE RECALL CYCLE #3: G CONTROLLEDo,t 31 tNLGL NE 30 tGLNH G 33 tWHGL W E DQ (Data Out) 34 tELGL 29 tGLQXR HIGH IMPEDANCE 2-44 STK20C04 DEVICE OPERATION The STK20C04 has two modes of operation: SRAM mode and nonvolatile mode, determined by the state of the NE pin. When in SRAM mode, the memory operates as an ordinary static RAM. While in nonvolatile mode, data is transferred in parallel from SRAM to EEPROM or from EEPROM to SRAM. If E and G are LOW and W and NE are HIGH at the end of the cycle, a READ will be performed and the outputs will go active, signaling the end of the STORE. SRAM READ HARDWARE PROTECT The STK20C04 performs a READ cycle whenever E and G are LOW and NE and W are HIGH. The address specified on pins A0-8 determines which of the 512 data bytes will be accessed. When the READ is initiated by an address transition, the outputs will be valid after a delay of tAVQV (READ CYCLE #1). If the READ is initiated by E or G, the outputs will be valid at t ELQV or at tGLQV whichever is later ( READ CYCLE #2). The data outputs will repeatedly respond to address changes within the tAVQV access time without the need for transitions on any control input pins, and will remain valid until another address change or until E or G is brought HIGH or W or NE is brought LOW. The STK20C04 offers two levels of protection to suppress inadvertent STORE cycles. If the control signals (E, G, W, and NE) remain in the STORE condition at the end of a STORE cycle, a second STORE cycle will not be started. The STORE (or RECALL) will be initiated only after a transition on any one of these signals to the required state. In addition to multi-trigger protection, the STK20C04 offers hardware protection through V CC Sense. A STORE cycle will not be initiated, and one in progress will discontinue if V CC goes below 3.8V. 3.8V is a typical, characterized value. SRAM WRITE A write cycle is performed whenever E and W are LOW and NE is HIGH. The address inputs must be stable prior to entering the WRITE cycle and must remain stable until either E or W go HIGH at the end of the cycle. The data on pins DQ0-7 will be written into the memory if it is valid tDVWH before the end of a W controlled WRITE or tDVEH before the end of an E controlled WRITE. It is recommended that G be kept HIGH during the entire WRITE cycle to avoid data bus contention on common I/O lines. If G is left LOW, internal circuitry will turn off the output buffers tWLQZ after W goes LOW. NONVOLATILE STORE A STORE cycle is performed when NE, E and W are LOW and G is HIGH. While any sequence to achieve this state will initiate a STORE, only W initiation (STORE CYCLE #1) and E initiation (STORE CYCLE #2) are practical without risking an unintentional SRAM WRITE that would disturb SRAM data. During a STORE cycle, previous nonvolatile data is erased and the SRAM contents are then programmed into nonvolatile elements. Once a STORE cycle is initiated, further input and output is disabled and the DQ0-7 pins are tri-stated until the cycle is completed. NONVOLATILE RECALL A RECALL cycle is performed when E, G, and NE are LOW and W is HIGH. Like the STORE cycle, RECALL is initiated when the last of the four clock signals goes to the RECALL state. Once initiated, the RECALL cycle will take tNLQX to complete, during which all inputs are ignored. When the RECALL completes, any READ or WRITE state on the input pins will take effect. Internally, RECALL is a two step procedure. First, the SRAM data is cleared and second, the nonvolatile information is transferred into the SRAM cells. The RECALL operation in no way alters the data in the nonvolatile cells. The nonvolatile data can be recalled an unlimited number of times. Like the STORE cycle, a transition must occur on any control pin to cause a recall, preventing inadvertent multi-triggering. On power-up, once V CC exceeds the VCC sense voltage of 3.8V, a RECALL cycle is automatically initiated. The voltage on the V CC pin must not drop below 3.8V once it has risen above it in order for the RECALL to operate properly. Due to this automatic RECALL, SRAM operation cannot commence until t NLQX after VCC exceeds 3.8V. 3.8V is a typical, characterized value. 2-45 STK20C04 ORDERING INFORMATION STK20C04 - W 30 I Temperature Range blank = Commercial (0 to 70 degrees C) I = Industrial (–40 to 85 degrees C) Access Time 30 = 30ns 35 = 35ns 45 = 45ns Package W = Plastic 28 pin 600 mil DIP 2-46