ETC HB52R1289E2-A6A

HB52R1289E2-A6A/B6A
1 GB Registered SDRAM DIMM
128-Mword × 72-bit, 100 MHz Memory Bus, 2-Bank Module
(36 pcs of 64 M × 4 Components)
PC/100 SDRAM
ADE-203-949 (Z)
Preliminary, Rev. 0.0
Sept. 22, 1998
Description
The HB52R1289E2 belongs to 8-byte DIMM (Dual In-line Memory Module) family, and has been
developed as an optimized main memory solution for 8-byte processor applications. The HB52R1289E2 is
a 64M × 72 × 2-bank Synchronous Dynamic RAM Module, mounted 36 pieces of 256-Mbit SDRAM
(HM5225405A-A6/B6) sealed in TCP package, 1 piece of PLL clock driver, 3 pieces register driver and 1
piece of serial EEPROM (2-kbit EEPROM) for Presence Detect (PD). An outline of the HB52R1289E2 is
168-pin socket type package (dual lead out ). Therefore, the HB52R1289E2 makes high density mounting
possible without surface mount technology. The HB52R1289E2 provides common data inputs and outputs.
Decoupling capacitors are mounted beside TCP on the module board.
Note: Do not push the cover or drop the modules in order to protect from mechanical defects, which
would be electrical defects.
Features
• Fully compatible with : JEDEC standard outline unbuffered 8-byte DIMM
: Intel PCB Reference design (Rev. 1.0)
• 168-pin socket type package (dual lead out)
 Outline: 133.37 mm (length) × 38.10 mm (Height) × 4.80 mm (Thickness)
 Lead pitch: 1.27 mm
• 3.3 V power supply
• Clock frequency: 100 MHz (max)
• LVTTL interface
• Data bus width: × 72ECC
• Single pulsed RAS
• 4 Banks can operates simultaneously and independently
• Burst read/write operation and burst read/single write operation capability
• Programmable burst length: 1/2/4/8/full page
• 2 variations of burst sequence
This Material Copyrighted by Its Respective Manufacturer
HB52R1289E2-A6A/B6A
•
•
•
•
•
 Sequential
 Interleave
Programmable CE latency : 3/4 (HB52R1289E2-A6A)
: 4 (HB52R1289E2-B6A)
Byte control by DQMB
Refresh cycles: 8192 refresh cycles/64 ms
2 variations of refresh
 Auto refresh
 Self refresh
Full page burst length capability
 Sequential burst
 Burst stop capability
Ordering Information
Type No.
Frequency
CE latency
Package
HB52R1289E2-A6A
100 MHz
3/4
168-pin dual lead out socket type Gold
HB52R1289E2-B6A
100 MHz
4
Contact pad
Pin Arrangement
1 pin 10 pin 11 pin
40 pin 41 pin
85 pin 94 pin 95 pin 124 pin 125 pin
2
This Material Copyrighted by Its Respective Manufacturer
84 pin
168 pin
HB52R1289E2-A6A/B6A
Pin No.
Pin name
Pin No.
Pin name
Pin No.
Pin name
Pin No.
Pin name
1
VSS
43
VSS
85
VSS
127
VSS
2
DQ0
44
NC
86
DQ32
128
CKE0
3
DQ1
45
S2
87
DQ33
129
S3
4
DQ2
46
DQMB2
88
DQ34
130
DQMB6
5
DQ3
47
DQMB3
89
DQ35
131
DQMB7
6
VCC
48
NC
90
VCC
132
NC
7
DQ4
49
VCC
91
DQ36
133
VCC
8
DQ5
50
NC
92
DQ37
134
NC
9
DQ6
51
NC
93
DQ38
135
NC
10
DQ7
52
CB2
94
DQ39
136
CB6
11
DQ8
53
CB3
95
DQ40
137
CB7
12
VSS
54
VSS
96
VSS
138
VSS
13
DQ9
55
DQ16
97
DQ41
139
DQ48
14
DQ10
56
DQ17
98
DQ42
140
DQ49
15
DQ11
57
DQ18
99
DQ43
141
DQ50
16
DQ12
58
DQ19
100
DQ44
142
DQ51
17
DQ13
59
VCC
101
DQ45
143
VCC
18
VCC
60
DQ20
102
VCC
144
DQ52
19
DQ14
61
NC
103
DQ46
145
NC
20
DQ15
62
NC
104
DQ47
146
NC
21
CB0
63
NC
105
CB4
147
REGE
22
CB1
64
VSS
106
CB5
148
VSS
23
VSS
65
DQ21
107
VSS
149
DQ53
24
NC
66
DQ22
108
NC
150
DQ54
25
NC
67
DQ23
109
NC
151
DQ55
26
VCC
68
VSS
110
VCC
152
VSS
27
W
69
DQ24
111
CE
153
DQ56
28
DQMB0
70
DQ25
112
DQMB4
154
DQ57
29
DQMB1
71
DQ26
113
DQMB5
155
DQ58
30
S0
72
DQ27
114
S1
156
DQ59
31
NC
73
VCC
115
RE
157
VCC
32
VSS
74
DQ28
116
VSS
158
DQ60
33
A0
75
DQ29
117
A1
159
DQ61
34
A2
76
DQ30
118
A3
160
DQ62
35
A4
77
DQ31
119
A5
161
DQ63
3
This Material Copyrighted by Its Respective Manufacturer
HB52R1289E2-A6A/B6A
Pin No.
Pin name
Pin No.
Pin name
Pin No.
Pin name
Pin No.
Pin name
36
A6
78
VSS
120
A7
162
VSS
37
A8
79
CK2
121
A9
163
CK3
38
A10 (AP)
80
NC
122
BA0
164
NC
39
BA1
81
WP
123
A11
165
SA0
40
VCC
82
SDA
124
VCC
166
SA1
41
VCC
83
SCL
125
CK1
167
SA2
42
CK0
84
VCC
126
A12
168
VCC
Pin Description
Pin name
Function
A0 to\~A12
Address input
Row address
A0 to A12
Column address
A0 to A9, A11
BA0/BA1
Bank select address
DQ0 to DQ63
Data input/output
CB0 to CB7
Check bit (Data input/output)
S0 to S3
Chip select input
RE
Row enable (RAS) input
CE
Column enable (CAS) input
W
Write enable input
DQMB0 to DQMB7
Byte data mask
CK0 to CK3
Clock input
CKE0
Clock enable input
WP
BA0/BA1
Write protect for serial PD
1
REGE*
Register enable
SDA
Data input/output for serial PD
SCL
Clock input for serial PD
SA0 to SA2
Serial address input
VCC
Primary positive power supply
VSS
Ground
NC
No connection
Note:
1. REGE is the Register Enable pin which permits the DIMM to operate in “buffered” mode and
“registered” mode. To conform to this specification, mother boards must pull this pin to high
state (“registered” mode).
4
This Material Copyrighted by Its Respective Manufacturer
HB52R1289E2-A6A/B6A
Serial PD Matrix*1
Byte No. Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments
0
Number of bytes used by
module manufacturer
1
0
0
0
0
0
0
0
80
128
1
Total SPD memory size
0
0
0
0
1
0
0
0
08
256 byte
2
Memory type
0
0
0
0
0
1
0
0
04
SDRAM
3
Number of row addresses bits
0
0
0
0
1
1
0
1
0D
13
4
Number of column addresses
bits
0
0
0
0
1
0
1
1
0B
11
5
Number of banks
0
0
0
0
0
0
1
0
02
2
6
Module data width
0
1
0
0
1
0
0
0
48
72 bit
7
Module data width (continued)
0
0
0
0
0
0
0
0
00
0 (+)
8
Module interface signal levels
0
0
0
0
0
0
0
1
01
LVTTL
9
SDRAM cycle time
(highest CE latency)
10 ns
1
0
1
0
0
0
0
0
A0
CL = 3
10
SDRAM access from Clock
(highest CE latency)
6 ns
0
1
1
0
0
0
0
0
60
*3
11
Module configuration type
0
0
0
0
0
0
1
0
02
ECC
12
Refresh rate/type
1
0
0
0
0
0
1
0
82
Normal
(7.8125 µs)
Self refresh
13
SDRAM width
0
0
0
0
0
1
0
0
04
64M × 4
14
Error checking SDRAM width
0
0
0
0
0
1
0
0
04
×4
15
SDRAM device attributes:
0
minimum clock delay for back-toback random column addresses
0
0
0
0
0
0
1
01
1 CLK
16
SDRAM device attributes:
Burst lengths supported
1
0
0
0
1
1
1
1
8F
1, 2, 4, 8,
full page
17
SDRAM device attributes:
number of banks on SDRAM
device
0
0
0
0
0
1
0
0
04
4
18
SDRAM device attributes:
CE latency
(-A6A)
0
0
0
0
0
1
1
0
06
2/3
(-B6A)
0
0
0
0
0
1
0
0
04
3
SDRAM device attributes:
CS latency
0
0
0
0
0
0
0
1
01
0
19
5
This Material Copyrighted by Its Respective Manufacturer
HB52R1289E2-A6A/B6A
Byte No. Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments
20
SDRAM device attributes:
W latency
0
0
0
0
0
0
0
1
01
0
21
SDRAM device attributes
0
0
0
1
0
1
1
0
16
Registered
22
SDRAM device attributes:
General
0
0
0
0
1
1
1
0
0E
VCC ± 10%
23
SDRAM cycle time
(2nd highest CE latency)
(-A6A) 10 ns
1
0
1
0
0
0
0
0
A0
CL = 2
0
0
0
0
0
0
0
0
00
SDRAM access from Clock (2nd 0
highest CE latency)
(-A6A) 6 ns
1
1
0
0
0
0
0
60
0
0
0
0
0
0
0
0
00
(-B6A) Undefined
24
(-B6A) Undefined
25
SDRAM cycle time
(3rd highest CE latency)
Undefined
0
0
0
0
0
0
0
0
00
26
SDRAM access from Clock (3rd 0
highest CE latency)
Undefined
0
0
0
0
0
0
0
00
27
Minimum row precharge time
0
0
0
1
0
1
0
0
14
20 ns
28
Row active to row active min
0
0
0
1
0
1
0
0
14
20 ns
29
RE to CE delay min
0
0
0
1
0
1
0
0
14
20 ns
30
Minimum RE pulse width
0
0
1
1
0
0
1
0
32
50 ns
31
Density of each bank on module 1
0
0
0
0
0
0
0
80
2 bank
512M byte
32
Address and command signal
input setup time
0
0
1
0
0
0
0
0
20
2 ns* 3
33
Address and command signal
input hold time
0
0
0
1
0
0
0
0
10
1 ns* 3
34
Data signal input setup time
0
0
1
0
0
0
0
0
20
2 ns* 3
35
Data signal input hold time
0
0
0
1
0
0
0
0
10
1 ns* 3
36 to 61 Superset information
0
0
0
0
0
0
0
0
00
Future use
62
SPD data revision code
0
0
0
1
0
0
1
0
12
Rev. 1.2A
63
Checksum for bytes 0 to 62
(-A6A)
1
0
0
1
1
0
1
1
9B
155
1
0
0
1
1
0
0
1
99
153
Manufacturer’s JEDEC ID code
0
0
0
0
0
1
1
1
07
HITACHI
65 to 71 Manufacturer’s JEDEC ID code
0
0
0
0
0
0
0
0
00
72
×
×
×
×
×
×
×
×
××
(-B6A)
64
Manufacturing location
6
This Material Copyrighted by Its Respective Manufacturer
* 4 (ASCII8bit code)
HB52R1289E2-A6A/B6A
Byte No. Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments
73
Manufacturer’s part number
0
1
0
0
1
0
0
0
48
H
74
Manufacturer’s part number
0
1
0
0
0
0
1
0
42
B
75
Manufacturer’s part number
0
0
1
1
0
1
0
1
35
5
76
Manufacturer’s part number
0
0
1
1
0
0
1
0
32
2
77
Manufacturer’s part number
0
1
0
1
0
0
1
0
52
R
78
Manufacturer’s part number
0
0
1
1
0
0
0
1
31
1
79
Manufacturer’s part
0
0
1
1
0
0
1
0
32
2
80
Manufacturer’s part number
0
0
1
1
1
0
0
0
38
8
81
Manufacturer’s part number
0
0
1
1
1
0
0
1
39
9
82
Manufacturer’s part number
0
1
0
0
0
1
0
1
45
E
83
Manufacturer’s part number
0
0
1
1
0
0
1
0
32
2
84
Manufacturer’s part number
0
0
1
0
1
1
0
1
2D
—
85
Manufacturer’s part number
(-A6A)
0
1
0
0
0
0
0
1
41
A
0
1
0
0
0
0
1
0
42
B
(-B6A)
86
Manufacturer’s part number
0
0
1
1
0
1
1
0
36
6
87
Manufacturer’s part number
0
1
0
0
0
0
0
1
41
A
88
Manufacturer’s part number
0
0
1
0
0
0
0
0
20
(Space)
89
Manufacturer’s part number
0
0
1
0
0
0
0
0
20
(Space)
90
Manufacturer’s part number
0
0
1
0
0
0
0
0
20
(Space)
91
Revision code
0
0
1
1
0
0
0
0
30
Initial
92
Revision code
0
0
1
0
0
0
0
0
20
(Space)
93
Manufacturing date
×
×
×
×
×
×
×
×
××
Year code
(BCD)*5
94
Manufacturing date
×
×
×
×
×
×
×
×
××
Week code
(BCD) *5
95 to 98 Assembly serial number
*7
99 to 125 Manufacturer specific data
—
—
—
—
—
—
—
—
—
*6
126
Intel specification frequency
0
1
1
0
0
1
0
0
64
100 MHz
127
Intel specification CE#
latency support
(-A6)
1
0
0
0
0
1
1
1
87
CL = 2/3
1
0
0
0
0
1
0
1
85
CL = 3
(-B6)
7
This Material Copyrighted by Its Respective Manufacturer
HB52R1289E2-A6A/B6A
Notes: 1. All serial PD data are not protected. 0: Serial data, “driven Low”, 1: Serial data, “driven High”
These SPD are based on Intel specification (Rev.1.2A).
2. Regarding byte32 to 35, based on JEDEC Committee Ballot JC42.5-97-119.
3. Byte10, 23, 24, 32 through 35 are component spec.
4. Byte72 is manufacturing location code. (ex: In case of Japan, byte72 is 4AH. 4AH shows “J” on
ASCII code.)
5. Regarding byte93 and 94, based on JEDEC Committee Ballot JC42.5-97-135. BCD is “Binary
Coded Decimal”.
6. All bits of 99 through 125 are not defined (“1” or “0”).
7. Bytes 95 through 98 are assembly serial number.
8
This Material Copyrighted by Its Respective Manufacturer
HB52R1289E2-A6A/B6A
Block Diagram
RS0
RS1
RDQMB0
RDQMB4
DQMB CS
4
N0
DQ0 to DQ3
I/O0
to I/O3
D0
DQMB CS
4
N1
DQ4 to DQ7
I/O0
to I/O3
D1
DQMB CS
DQMB CS
D18
I/O0
to I/O3
4
N10
4
N11
4
N12
4
N13
4
N14
DQMB CS
DQMB CS
D19
I/O0
to I/O3
I/O0
to I/O3
D9
DQ36 to DQ39
I/O0
to I/O3
D10
4
N2
DQ8 to DQ11
I/O0
to I/O3
D2
DQMB CS
4
N3
DQ12 to DQ15
I/O0
to I/O3
D3
DQMB CS
4
N4
I/O0
to I/O3
D4
DQMB CS
DQMB CS
D20
I/O0
to I/O3
DQ40 to DQ43
D21
I/O0
to I/O3
DQ44 to DQ47
DQMB CS
I/O0
to I/O3
D12
DQMB CS
D22
I/O0
to I/O3
I/O0
to I/O3
D11
DQMB CS
DQMB CS
CB4 to CB7
RS2
RS3
RDQMB2
I/O0
to I/O3
D27
DQMB CS
I/O0
to I/O3
D28
I/O0
to I/O3
D13
DQMB CS
I/O0
to I/O3
D29
DQMB CS
I/O0
to I/O3
D30
DQMB CS
I/O0
to I/O3
D31
RDQMB6
DQMB CS
4
N5
DQ16 to DQ19
I/O0
to I/O3
D5
DQMB CS
4
N6
I/O0
to I/O3
D6
DQMB CS
DQMB CS
I/O0
to I/O3
D23
DQ48 to DQ51
DQMB CS
I/O0
to I/O3
I/O0
to I/O3
D14
DQMB CS
D24
DQ52 to DQ55
RDQMB3
4
N15
I/O0
to I/O3
D15
DQMB CS
I/O0
to I/O3
D32
DQMB CS
I/O0
to I/O3
D33
RDQMB7
DQMB CS
4
N7
DQ24 to DQ27
I/O0
to I/O3
D7
DQMB CS
4
N8
DQ28 to DQ31
I/O0
to I/O3
D8
DQMB CS
DQMB CS
I/O0
to I/O3
D25
4
N16
4
N17
DQ56 to DQ59
DQMB CS
DQMB CS
I/O0
to I/O3
I/O0
to I/O3
D16
D26
DQ60 to DQ63
D17
I/O0
to I/O3
R1
CK0
S0, S1, S2, S3
DQMB0 to DQMB7
BA0 to BA1
A0 to A12
RE
CE
CKE0
W
VCC
REGE
PLL CK
DQMB CS
RDQMB5
DQMB CS
DQ20 to DQ23
N9
DQ32 to DQ35
RDQMB1
CB0 to CB3
4
R
E
G
I
S
T
E
R
10k
RS0, RS1, RS2, RS3
RDQMB0 to RDQMB7
RBA0 to RBA1 -> BA0 to BA1: SDRAMs D0 to D35 CK1
RA0 to RA12 -> A0 to A12: SDRAMs D0 to D35
to CK3
RRAS -> RAS: SDRAMs D0 to D35
RCAS -> CAS: SDRAMs D0 to D35
VCC
RCKE0 -> CKE: SDRAMs D0 to D35
C0 to C24
RW -> WE: SDRAMs D0 to D35
VSS
Serial PD
SCL
SCL
SDA
SDA
U0
A0
A1
WP
A2
R0
SA0 SA1 SA2 VSS
Notes:
1. The SDA pull-up resistor is required due to the open-drain/open-collector output.
2. The SCL pull-up resistor is recommended because of the normal SCL line inacitve "high" state.
DQMB CS
I/O0
to I/O3
D34
DQMB CS
I/O0
to I/O3
PLL
C200
D35
CK : SDRAMs
(D0 to D35)
Register
R2 to R4
VSS
C100 to C102
VCC (D0 to D35, U0)
C25 to C43
VSS (D0 to D35, U0)
* D0 to D35: HM5225405
PLL: CDC2510A
Register: ALVC162835
U0: 2k bit EEPROM
C0 to C24: 2200 pF
C25 to C43: 0.22 µF
C100 to C102 = 30 pF
C200 = 27 pF
R0: 47 kΩ
R1 to R4: 10 Ω
N0 to N17: Network registor 10 Ω
9
This Material Copyrighted by Its Respective Manufacturer
HB52R1289E2-A6A/B6A
Absolute Maximum Ratings
Parameter
Symbol
Value
Unit
Note
Voltage on any pin relative to V SS
VT
–0.5 to VCC + 0.5
(≤ 4.6 (max))
V
1
Supply voltage relative to VSS
VCC
–0.5 to +4.6
V
1
Short circuit output current
Iout
50
mA
Power dissipation
PT
18.0
W
Operating temperature
Topr
0 to +55
°C
Storage temperature
Tstg
–50 to +100
°C
Note:
1. Respect to V SS
DC Operating Conditions (Ta = 0 to +55°C)
Parameter
Symbol
Min
Max
Unit
Notes
Supply voltage
VCC
3.0
3.6
V
1
VSS
0
0
V
3
Input high voltage
VIH
2.0
VCC
V
1, 4, 5
Input low voltage
VIL
0
0.8
V
1, 6
Ambient illuminance
—
—
100
lx
Notes: 1.
2.
3.
4.
5.
6.
All voltage referred to VSS
The supply voltage with all VCC and V CCQ pins must be on the same level.
The supply voltage with all VSS and VSS Q pins must be on the same level.
CK, CKE, S, DQMB, DQ pins: VIH (max) = VCC + 0.5 V for pulse width ≤ 5 ns at VCC.
Others: V IH (max) = 4.6 V for pulse width ≤ 5 ns at VCC.
VIL (min) = –1.0 V for pulse width ≤ 5 ns at VSS.
10
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HB52R1289E2-A6A/B6A
VIL/VIH Clamp (Component characteristics)
This SDRAM component has VIL and V IH clamp for CK, CKE, S, DQMB and I/O pins.
Minimum VIL Clamp Current
VIL (V)
I (mA)
–2
–32
–1.8
–25
–1.6
–19
–1.4
–13
–1.2
–8
–1
–4
–0.9
–2
–0.8
–0.6
–0.6
0
–0.4
0
–0.2
0
0
0
0
–5
–2
–1.5
–1
–0.5
0
I (mA)
–10
–15
–20
–25
–30
–35
VIL (V)
11
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HB52R1289E2-A6A/B6A
Minimum VIH Clamp Current (referred to VIH)
VIH (V)
I (mA)
VCC + 2
10
VCC + 1.8
8
VCC + 1.6
5.5
VCC + 1.4
3.5
VCC + 1.2
1.5
VCC + 1
0.3
VCC + 0.8
0
VCC + 0.6
0
VCC + 0.4
0
VCC + 0.2
0
VCC + 0
0
10
I (mA)
8
6
4
2
0
VCC + 0
VCC + 0.5
VCC + 1
VIH (V)
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VCC + 1.5
VCC + 2
HB52R1289E2-A6A/B6A
IOL/IOH Characteristics (Component characteristics)
Output Low Current (IOL)
I OL
I OL
Vout (V)
Min (mA)
Max (mA)
0
0
0
0.4
27
71
0.65
41
108
0.85
51
134
1
58
151
1.4
70
188
1.5
72
194
1.65
75
203
1.8
77
209
1.95
77
212
3
80
220
3.45
81
223
250
IOL (mA)
200
150
min
max
100
50
0
0
0.5
1
1.5
2
2.5
3
3.5
Vout (V)
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HB52R1289E2-A6A/B6A
Output High Current (I OH ) (Ta = 0 to 55˚C, V CC = 3.0 V to 3.45 V, VSS = 0 V)
I OH
I OH
Vout (V)
Min (mA)
Max (mA)
3.45
—
–3
3.3
—
–28
3
0
–75
2.6
–21
–130
2.4
–34
–154
2
–59
–197
1.8
–67
–227
1.65
–73
–248
1.5
–78
–270
1.4
–81
–285
1
–89
–345
0
–93
–503
0
0
0.5
1
1.5
2
2.5
3
3.5
IOH (mA)
–100
–200
min
max
–300
–400
–500
–600
Vout (V)
14
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HB52R1289E2-A6A/B6A
DC Characteristics (Ta = 0 to 55°C, VCC = 3.3 V ± 0.3 V, VSS = 0 V)
HB52R1289E2
A6A
-B6A
Parameter
Symbol
Min
Max
Min
Max
Unit
Test conditions
Notes
Operating current
(CE latency = 3)
—
2945
—
—
mA
Burst length = 1
t RC = min
1, 2, 3
I CC1
(CE latency = 4)
I CC1
—
2945
—
2945
mA
Standby current in power I CC2P
down
—
803
—
803
mA
CKE = VIL, t CK = 12
ns
6
Standby current in power I CC2PS
down (input signal stable)
—
767
—
767
mA
CKE = VIL, t CK = ∞
7
Standby current in non
power down
I CC2N
—
1415
—
1415
mA
CKE, S = VIH,
t CK = 12 ns
4
Active standby current in
power down
I CC3P
—
911
—
911
mA
CKE = VIL, t CK = 12
ns
1, 2, 6
Active standby current in
non power down
I CC3N
—
1775
—
1775
mA
CKE, S = VIH,
t CK = 12 ns
1, 2, 4
t CK = min, BL = 4
1, 2, 5
I CC4
—
2945
—
—
mA
(CE latency = 4)
I CC4
—
2945
—
2945
mA
Refresh current
(CE latency = 3)
t RC = min
3
I CC5
—
5195
—
—
mA
(CE latency = 4)
I CC5
—
5195
—
5195
mA
Self refresh current
I CC6
—
TBD
—
TBD
mA
VIH ≥ VCC – 0.2 V
VIL ≤ 0.2 V
8
Input leakage current
I LI
–10
10
–10
10
µA
0 ≤ Vin ≤ VCC
Output leakage current
I LO
–10
10
–10
10
µA
0 ≤ Vout ≤ VCC
DQ = disable
Output high voltage
VOH
2.4
—
2.4
—
V
I OH = –4 mA
Output low voltage
VOL
—
0.4
—
0.4
V
I OL = 4 mA
Burst operating current
(CE latency = 3)
Notes: 1. I CC depends on output load condition when the device is selected. ICC (max) is specified at the
output open condition.
2. One bank operation.
3. Input signals are changed once per one clock.
4. Input signals are changed once per two clocks.
5. Input signals are changed once per four clocks.
6. After power down mode, CK operating current.
7. After power down mode, no CK operating current.
8. After self refresh mode set, self refresh current.
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This Material Copyrighted by Its Respective Manufacturer
HB52R1289E2-A6A/B6A
Capacitance (Ta = 25°C, VCC = 3.3 V ± 0.3 V)
Parameter
Symbol
Max
Unit
Notes
Input capacitance (Address)
CI1
25
pF
1, 2, 4
Input capacitance (RE, CE, W)
CI2
25
pF
1, 2, 4
Input capacitance (CKE)
CI3
45
pF
1, 2, 4
Input capacitance (S)
CI4
20
pF
1, 2, 4
Input capacitance (CK)
CI5
45
pF
1, 2, 4
Input capacitance (DQMB)
CI6
20
pF
1, 2, 4
Input/Output capacitance (DQ)
CI/O1
25
pF
1, 2, 3, 4
Notes: 1.
2.
3.
4.
Capacitance measured with Boonton Meter or effective capacitance measuring method.
Measurement condition: f = 1 MHz, 1.4 V bias, 200 mV swing.
DQMB = VIH to disable Data-out.
This parameter is sampled and not 100% tested.
AC Characteristics (Ta = 0 to 55°C, VCC = 3.3 V ± 0.3 V, VSS = 0 V)
HB52R1289E2
-A6A/B6A
HITACHI PC100
Symbol Symbol
Min
Max
Unit
Notes
t CK
Tclk
10
—
ns
1
(CE latency = 4)
t CK
Tclk
10
—
ns
CK high pulse width
t CKH
Tch
4
—
ns
1
CK low pulse width
t CKL
Tcl
4
—
ns
1
Access time from CK
(CE latency = 3)
t AC
Tac
—
6.9
ns
1, 2
(CE latency = 4)
t AC
Tac
—
6.9
ns
Data-out hold time
t OH
Toh
2.1
—
ns
1, 2
CK to Data-out low impedance
t LZ
1.1
—
ns
1, 2, 3
CK to Data-out high impedance
t HZ
—
6.9
ns
1, 4
Data-in setup time
t DS
Tsi
2.9
—
ns
1
Data in hold time
t DH
Thi
1.9
—
ns
1
Address setup time
t AS
Tsi
2.6
—
ns
1
Address hold time
t AH
Thi
1.6
—
ns
1, 5
CKE setup time
t CES
Tsi
2.6
—
ns
1, 5
CKE setup time for power down exit
t CESP
Tpde
2.6
—
ns
1
Parameter
System clock cycle time
(CE latency = 3)
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HB52R1289E2-A6A/B6A
AC Characteristics (Ta = 0 to 55°C, VCC = 3.3 V ± 0.3 V, VSS = 0 V) (cont)
HB52R1289E2- A6A/B6A
Parameter
HITACHI PC100
Symbol Symbol
Min
Max
Unit
Notes
CKE hold time
t CEH
Thi
1.6
—
ns
1
Command setup time
t CS
Tsi
2.6
—
ns
1
Command hold time
t CH
Thi
1.6
—
ns
1
Ref/Active to Ref/Active command period t RC
Trc
70
—
ns
1
Active to precharge command period
t RAS
Tras
50
120000
ns
1
Active command to column command
(same bank)
t RCD
Trcd
20
—
ns
1
Precharge to active command period
t RP
Trp
20
—
ns
1
Write recovery or data-in to precharge
lead time
t DPL
Tdpl
10
—
ns
1
Active (a) to Active (b) command period
t RRD
Trrd
20
—
ns
1
Transition time (rise to fall)
tT
1
5
ns
Refresh period
t REF
—
64
ms
Notes: 1.
2.
3.
4.
5.
AC measurement assumes t T = 1 ns. Reference level for timing of input signals is 1.5 V.
Access time is measured at 1.5 V. Load condition is C L = 50 pF.
t LZ (max) defines the time at which the outputs achieves the low impedance state.
t HZ (max) defines the time at which the outputs achieves the high impedance state.
t CES defines CKE setup time to CK rising edge except power down exit command.
Test Conditions
• Input and output timing reference levels: 1.5 V
• Input waveform and output load: See following figures
• Ambient illuminance: Under 100 lx
2.4 V
input
0.4 V
DQ
2.0 V
0.8 V
CL
t
T
tT
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HB52R1289E2-A6A/B6A
Relationship Between Frequency and Minimum Latency
Parameter
HB52R1289E2
Frequency (MHz)
-A6A/B6A
tCK (ns)
HITACHI PC/100
Symbol Symbol 10
Notes
Active command to column command (same bank)
I RCD
2
1
Active command to active command (same bank)
I RC
7
= [IRAS + IRP]
1
Active command to precharge command (same bank)
I RAS
5
1
Precharge command to active command (same bank)
I RP
2
1
Write recovery or data-in to precharge command
(same bank)
I DPL
1
1
Active command to active command (different bank)
I RRD
2
1
Self refresh exit time
I SREX
Tsrx
2
2
Last data in to active command
(Auto precharge, same bank)
I APW
Tdal
3
= [IDPL + IRP]
Self refresh exit to command input
I SEC
7
= [IRC]
3
Precharge command to high impedance
(CE latency = 3)
I HZP
Troh
3
I HZP
Troh
4
(CE latency = 4)
Tdpl
Last data out to active command (auto precharge)
(same bank)
I APR
0
Last data out to precharge (early precharge)
(CE latency = 3)
I EP
–2
I EP
–3
(CE latency = 4)
Column command to column command
I CCD
Tccd
1
Write command to data in latency
I WCD
Tdwd
1
DQMB to data in
I DID
Tdqm
1
DQMB to data out
I DOD
Tdqz
3
CKE to CK disable
I CLE
Tcke
2
Register set to active command
I RSA
Tmrd
1
S to command disable
I CDD
0
Power down exit to command input
I PEC
1
Burst stop to output valid data hold
(CE latency = 3)
I BSR
2
I BSR
3
(CE latency = 4)
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HB52R1289E2-A6A/B6A
Parameter
HB52R1289E2
Frequency (MHz)
-A6A/B6A
tCK (ns)
Burst stop to output high impedance
(CE latency = 3)
(CE latency = 4)
Burst stop to write data ignore
HITACHI PC100
Symbol Symbol 10
I BSH
3
I BSH
4
I BSW
1
Notes
Notes: 1. I RCD to IRRD are recommended value.
2. Be valid [DSEL] or [NOP] at next command of self refresh exit.
3. Except [DSEL] and [NOP]
Pin Functions
CK0 to CK3 (input pin): CK is the master clock input to this pin. The other input signals are referred at
CK rising edge.
S0 to S3 (input pin): When S is Low, the command input cycle becomes valid. When S is High, all inputs
are ignored. However, internal operations (bank active, burst operations, etc.) are held.
RE, CE and W (input pins): Although these pin names are the same as those of conventional DRAMs,
they function in a different way. These pins define operation commands (read, write, etc.) depending on
the combination of their voltage levels. For details, refer to the command operation section.
A0 to A12 (input pins): Row address (AX0 to AX12) is determined by A0 to A12 level at the bank active
command cycle CK rising edge. Column address (AY0 to AY9, AY11) is determined by A0 to A9, A11
level at the read or write command cycle CK rising edge. And this column address becomes burst access
start address. A10 defines the precharge mode. When A10 = High at the precharge command cycle, all
banks are precharged. But when A10 = Low at the precharge command cycle, only the bank that is
selected by BA0/BA1 (BA) is precharged.
BA0/BA1 (input pin): BA0/BA1 are bank select signal (BA). The memory array is divided into bank 0,
bank 1, bank 2 and bank 3. If BA0 is Low and BA1 is Low, bank 0 is selected. If BA0 is High and BA1 is
Low, bank 1 is selected. If BA0 is Low and BA1 is High, bank 2 is selected. If BA0 is High and BA1 is
High, bank 3 is selected.
CKE0 (input pin): This pin determines whether or not the next CK is valid. If CKE is High, the next CK
rising edge is valid. If CKE is Low, the next CK rising edge is invalid. This pin is used for power-down
and clock suspend modes.
DQMB0 to DQMB7 (input pins): Read operation: If DQMB is High, the output buffer becomes High-Z.
If the DQMB is Low, the output buffer becomes Low-Z.
Write operation: If DQMB is High, the previous data is held (the new data is not written). If DQMB is
Low, the data is written.
DQ0 to DQ63, CB0 to CB7 (input/output pins): Data is input to and output from these pins.
19
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VCC (power supply pins): 3.3 V is applied.
VSS (power supply pins): Ground is connected.
REGE (input pins): If REGE is High, the register is ″registered″ mode. If REGE is Low, the register is
″buffered″ mode.
20
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HB52R1289E2-A6A/B6A
Command Operation
Command Truth Table
The SDRAM module recognizes the following commands specified by the S, RE, CE, W and address pins.
CKE
Command
Symbol
n-1 n
S
RE
CE
W
A0
BA0/BA1 A10 to A12
Ignore command
DESL
H
×
H
×
×
×
×
×
×
No operation
NOP
H
×
L
H
H
H
×
×
×
Burst stop in full page
BST
H
×
L
H
H
L
×
×
×
Column address and read command
READ
H
×
L
H
L
H
V
L
V
Read with auto-precharge
READ A
H
×
L
H
L
H
V
H
V
Column address and write command
WRIT
H
×
L
H
L
L
V
L
V
Write with auto-precharge
WRIT A
H
×
L
H
L
L
V
H
V
Row address strobe and bank active
ACTV
H
×
L
L
H
H
V
V
V
Precharge select bank
PRE
H
×
L
L
H
L
V
L
×
Precharge all bank
PALL
H
×
L
L
H
L
×
H
×
Refresh
REF/SELF H
V
L
L
L
H
×
×
×
Mode register set
MRS
×
L
L
L
L
V
V
V
H
Note: H: VIH. L: V IL. ×: VIH or VIL. V: Valid address input
Ignore command [DESL]: When this command is set (S is High), the SDRAM module ignore command
input at the clock. However, the internal status is held.
No operation [NOP]: This command is not an execution command. However, the internal operations
continue.
Burst stop in full-page [BST]: This command stops a full-page burst operation (burst length = full-page)
and is illegal otherwise. When data input/output is completed for a full page of data, it automatically
returns to the start address, and input/output is performed repeatedly.
Column address strobe and read command [READ]: This command starts a read operation. In
addition, the start address of burst read is determined by the column address and the bank select address
(BA). After the read operation, the output buffer becomes High-Z.
Read with auto-precharge [READ A]: This command automatically performs a precharge operation
after a burst read with a burst length of 1, 2, 4 or 8. When the burst length is full-page, this command is
illegal.
21
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Column address strobe and write command [WRIT]: This command starts a write operation. When the
burst write mode is selected, the column address and the bank select address (BA) become the burst write
start address. When the single write mode is selected, data is only written to the location specified by the
column address and the bank select address (BA).
Write with auto-precharge [WRIT A]: This command automatically performs a precharge operation
after a burst write with a length of 1, 2, 4 or 8, or after a single write operation. When the burst length is
full-page, this command is illegal.
Row address strobe and bank activate [ACTV]: This command activates the bank that is selected by
Bank select address (BA) and determines the row address (AX0 to AX12). When BA0 and BA1 are Low,
bank 0 is activated. When BA0 is High and BA1 is Low, bank 1 is activated. When BA0 is Low and BA1
is High, bank 2 is activated. When BA0 and BA1 are High, bank 3 is activated.
Precharge selected bank [PRE]: This command starts precharge operation for the bank selected by Bank
select address (BA). If BA0 and BA1 are Low, bank 0 is selected. If BA0 is High and BA1 is Low, bank 1
is selected. If BA0 is Low and BA1 is High, bank 2 is selected. If BA0 and BA1 are High, bank 3 is
selected.
Precharge all banks [PALL]: This command starts a precharge operation for all banks.
Refresh [REF/SELF]: This command starts the refresh operation. There are two types of refresh
operation, the one is auto-refresh, and the other is self-refresh. For details, refer to the CKE truth table
section.
Mode register set [MRS]: The SDRAM module has a mode register that defines how it operates. The
mode register is specified by the address pins (A0 to BA0 and BA1) at the mode register set cycle. For
details, refer to the mode register configuration. After power on, the contents of the mode register are
undefined, execute the mode register set command to set up the mode register.
DQMB Truth Table
CKE
Command
Symbol
n-1
n
DQMB
Write enable/output enable
ENB
H
×
L
Write inhibit/output disable
MASK
H
×
H
Note: H: VIH. L: V IL. ×: VIH or VIL.
Write: IDID is needed.
Read: I DOD is needed.
The SDRAM module can mask input/output data by means of DQMB.
During reading, the output buffer is set to Low-Z by setting DQMB to Low, enabling data output. On the
other hand, when DQMB is set to High, the output buffer becomes High-Z, disabling data output.
22
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During writing, data is written by setting DQMB to Low. When DQMB is set to High, the previous data is
held (the new data is not written). Desired data can be masked during burst read or burst write by setting
DQMB. For details, refer to the DQMB control section of the SDRAM module operating instructions.
CKE Truth Table
CKE
Current state
Command
n-1
n
S
RE
CE
W
Address
Active
Clock suspend mode entry
H
L
H
×
×
×
×
Any
Clock suspend
L
L
×
×
×
×
×
Clock suspend
Clock suspend mode exit
L
H
×
×
×
×
×
Idle
Auto-refresh command (REF)
H
H
L
L
L
H
×
Idle
Self-refresh entry (SELF)
H
L
L
L
L
H
×
Idle
Power down entry
H
L
L
H
H
H
×
H
L
H
×
×
×
×
L
H
L
H
H
H
×
L
H
H
×
×
×
×
L
H
L
H
H
H
×
L
H
H
×
×
×
×
Self refresh
Power down
Self refresh exit (SELFX)
Power down exit
Note: H: VIH. L: V IL. ×: VIH or VIL.
Clock suspend mode entry: The SDRAM module enters clock suspend mode from active mode by
setting CKE to Low. The clock suspend mode changes depending on the current status (1 clock before) as
shown below.
ACTIVE clock suspend: This suspend mode ignores inputs after the next clock by internally maintaining
the bank active status.
READ suspend and READ with Auto-precharge suspend: The data being output is held (and continues
to be output).
WRITE suspend and WRIT with Auto-precharge suspend: In this mode, external signals are not
accepted. However, the internal state is held.
Clock suspend: During clock suspend mode, keep the CKE to Low.
Clock suspend mode exit: The SDRAM module exits from clock suspend mode by setting CKE to High
during the clock suspend state.
IDLE: In this state, all banks are not selected, and completed precharge operation.
Auto-refresh command [REF]: When this command is input from the IDLE state, the SDRAM module
starts auto-refresh operation. (The auto-refresh is the same as the CBR refresh of conventional DRAMs.)
During the auto-refresh operation, refresh address and bank select address are generated inside the SDRAM
module. For every auto-refresh cycle, the internal address counter is updated. Accordingly, 8192 times are
23
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HB52R1289E2-A6A/B6A
required to refresh the entire memory. Before executing the auto-refresh command, all the banks must be
in the IDLE state. In addition, since the precharge for all banks is automatically performed after autorefresh, no precharge command is required after auto-refresh.
Self-refresh entry [SELF]: When this command is input during the IDLE state, the SDRAM module
starts self-refresh operation. After the execution of this command, self-refresh continues while CKE is
Low. Since self-refresh is performed internally and automatically, external refresh operations are
unnecessary.
Power down mode entry: When this command is executed during the IDLE state, the SDRAM module
enters power down mode. In power down mode, power consumption is suppressed by cutting off the initial
input circuit.
Self-refresh exit: When this command is executed during self-refresh mode, the SDRAM module can exit
from self-refresh mode. After exiting from self-refresh mode, the SDRAM module enters the IDLE state.
Power down exit: When this command is executed at the power down mode, the SDRAM module can
exit from power down mode. After exiting from power down mode, the SDRAM module enters the IDLE
state.
Function Truth Table
The following table shows the operations that are performed when each command is issued in each mode of
the SDRAM module. The following table assumes that CKE is high.
24
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HB52R1289E2-A6A/B6A
Current state
S
RE
CE
W
Address
Command
Operation
Precharge
H
×
×
×
×
DESL
Enter IDLE after t RP
L
H
H
H
×
NOP
Enter IDLE after t RP
L
H
H
L
×
BST
NOP
L
H
L
H
BA, CA, A10 READ/READ A
ILLEGAL*4
L
H
L
L
BA, CA, A10 WRIT/WRIT A
ILLEGAL*4
L
L
H
H
BA, RA
ACTV
ILLEGAL*4
L
L
H
L
BA, A10
PRE, PALL
NOP*6
L
L
L
H
×
REF, SELF
ILLEGAL
L
L
L
L
MODE
MRS
ILLEGAL
H
×
×
×
×
DESL
NOP
L
H
H
H
×
NOP
NOP
L
H
H
L
×
BST
NOP
L
H
L
H
BA, CA, A10 READ/READ A
ILLEGAL*5
L
H
L
L
BA, CA, A10 WRIT/WRIT A
ILLEGAL*5
L
L
H
H
BA, RA
ACTV
Bank and row active
L
L
H
L
BA, A10
PRE, PALL
NOP
L
L
L
H
×
REF, SELF
Refresh
L
L
L
L
MODE
MRS
Mode register set
Idle
25
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Current state
S
RE
CE
W
Address
Command
Operation
Row active
H
×
×
×
×
DESL
NOP
L
H
H
H
×
NOP
NOP
L
H
H
L
×
BST
NOP
L
H
L
H
BA, CA, A10 READ/READ A
Begin read
L
H
L
L
BA, CA, A10 WRIT/WRIT A
Begin write
L
L
H
H
BA, RA
ACTV
Other bank active
ILLEGAL on same bank*3
L
L
H
L
BA, A10
PRE, PALL
Precharge
L
L
L
H
×
REF, SELF
ILLEGAL
L
L
L
L
MODE
MRS
ILLEGAL
H
×
×
×
×
DESL
Continue burst to end
L
H
H
H
×
NOP
Continue burst to end
L
H
H
L
×
BST
Burst stop to full page
L
H
L
H
BA, CA, A10 READ/READ A
Continue burst read to CE
latency and New read
L
H
L
L
BA, CA, A10 WRIT/WRIT A
Term burst read/start write
L
L
H
H
BA, RA
ACTV
Other bank active
ILLEGAL on same bank*3
L
L
H
L
BA, A10
PRE, PALL
Term burst read and
Precharge
L
L
L
H
×
REF, SELF
ILLEGAL
L
L
L
L
MODE
MRS
ILLEGAL
H
×
×
×
×
DESL
Continue burst to end and
precharge
L
H
H
H
×
NOP
Continue burst to end and
precharge
L
H
H
L
×
BST
ILLEGAL
L
H
L
H
BA, CA, A10 READ/READ A
ILLEGAL*4
L
H
L
L
BA, CA, A10 WRIT/WRIT A
ILLEGAL*4
L
L
H
H
BA, RA
ACTV
Other bank active
ILLEGAL on same bank*3
L
L
H
L
BA, A10
PRE, PALL
ILLEGAL*4
L
L
L
H
×
REF, SELF
ILLEGAL
L
L
L
L
MODE
MRS
ILLEGAL
Read
Read with autoprecharge
26
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Current state
S
RE
CE
W
Address
Command
Operation
Write
H
×
×
×
×
DESL
Continue burst to end
L
H
H
H
×
NOP
Continue burst to end
L
H
H
L
×
BST
Burst stop on full page
L
H
L
H
BA, CA, A10 READ/READ A
Term burst and New read
L
H
L
L
BA, CA, A10 WRIT/WRIT A
Term burst and New write
L
L
H
H
BA, RA
ACTV
Other bank active
ILLEGAL on same bank*3
L
L
H
L
BA, A10
PRE, PALL
Term burst write and
Precharge*2
L
L
L
H
×
REF, SELF
ILLEGAL
L
L
L
L
MODE
MRS
ILLEGAL
H
×
×
×
×
DESL
Continue burst to end and
precharge
L
H
H
H
×
NOP
Continue burst to end and
precharge
L
H
H
L
×
BST
ILLEGAL
L
H
L
H
BA, CA, A10 READ/READ A
ILLEGAL*4
L
H
L
L
BA, CA, A10 WRIT/WRIT A
ILLEGAL*4
L
L
H
H
BA, RA
ACTV
Other bank active
ILLEGAL on same bank*3
L
L
H
L
BA, A10
PRE, PALL
ILLEGAL*4
L
L
L
H
×
REF, SELF
ILLEGAL
L
L
L
L
MODE
MRS
ILLEGAL
H
×
×
×
×
DESL
Enter IDLE after t RC
L
H
H
H
×
NOP
Enter IDLE after t RC
L
H
H
L
×
BST
Enter IDLE after t RC
L
H
L
H
BA, CA, A10 READ/READ A
ILLEGAL*5
L
H
L
L
BA, CA, A10 WRIT/WRIT A
ILLEGAL*5
L
L
H
H
BA, RA
ACTV
ILLEGAL*5
L
L
H
L
BA, A10
PRE, PALL
ILLEGAL*5
L
L
L
H
×
REF, SELF
ILLEGAL
L
L
L
L
MODE
MRS
ILLEGAL
Write with autoprecharge
Refresh
(auto-refresh)
Notes: 1. H: VIH. L: V IL. ×: VIH or VIL.
The other combinations are inhibit.
2. An interval of t DPL is required between the final valid data input and the precharge command.
3. If tRRD is not satisfied, this operation is illegal.
4. Illegal for same bank, except for another bank.
5. Illegal for all banks.
6. NOP for same bank, except for another bank.
27
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From PRECHARGE state, command operation
To [DESL], [NOP] or [BST]: When these commands are executed, the SDRAM module enters the IDLE
state after tRP has elapsed from the completion of precharge.
From IDLE state, command operation
To [DESL], [NOP], [BST], [PRE] or [PALL]: These commands result in no operation.
To [ACTV]: The bank specified by the address pins and the ROW address is activated.
To [REF], [SELF]: The SDRAM module enters refresh mode (auto-refresh or self-refresh).
To [MRS]: The SDRAM module enters the mode register set cycle.
From ROW ACTIVE state, command operation
To [DESL], [NOP] or [BST]: These commands result in no operation.
To [READ], [READ A]: A read operation starts. (However, an interval of tRCD is required.)
To [WRIT], [WRIT A]: A write operation starts. (However, an interval of tRCD is required.)
To [ACTV]: This command makes the other bank active. (However, an interval of tRRD is required.)
Attempting to make the currently active bank active results in an illegal command.
To [PRE], [PALL]: These commands set the SDRAM module to precharge mode. (However, an interval
of t RAS is required.)
From READ state, command operation
To [DESL], [NOP]: These commands continue read operations until the burst operation is completed.
To [BST]: This command stops a full-page burst.
To [READ], [READ A]: Data output by the previous read command continues to be output. After CE
latency, the data output resulting from the next command will start.
To [WRIT], [WRIT A]: These commands stop a burst read, and start a write cycle.
To [ACTV]: This command makes other banks bank active. (However, an interval of tRRD is required.)
Attempting to make the currently active bank active results in an illegal command.
To [PRE], [PALL]: These commands stop a burst read, and the SDRAM module enters precharge mode.
28
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From READ with AUTO-PRECHARGE state, command operation
To [DESL], [NOP]: These commands continue read operations until the burst operation is completed, and
the SDRAM module then enters precharge mode.
To [ACTV]: This command makes other banks bank active. (However, an interval of tRRD is required.)
Attempting to make the currently active bank active results in an illegal command.
From WRITE state, command operation
To [DESL], [NOP]: These commands continue write operations until the burst operation is completed.
To [BST]: This command stops a full-page burst.
To [READ], [READ A]: These commands stop a burst and start a read cycle.
To [WRIT], [WRIT A]: These commands stop a burst and start the next write cycle.
To [ACTV]: This command makes the other bank active. (However, an interval of tRRD is required.)
Attempting to make the currently active bank active results in an illegal command.
To [PRE], [PALL]: These commands stop burst write and the SDRAM module then enters precharge
mode.
From WRITE with AUTO-PRECHARGE state, command operation
To [DESL], [NOP]: These commands continue write operations until the burst is completed, and the
SDRAM module enters precharge mode.
To [ACTV]: This command makes the other bank active. (However, an interval of t RRD is required.)
Attempting to make the currently active bank active results in an illegal command.
From REFRESH state, command operation
To [DESL], [NOP], [BST]: After an auto-refresh cycle (after tRC), the SDRAM module automatically
enters the IDLE state.
29
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Simplified State Diagram
SELF
REFRESH
SR ENTRY
SR EXIT
MRS
MODE
REGISTER
SET
REFRESH
IDLE
*1
AUTO
REFRESH
CKE
CKE_
IDLE
POWER
DOWN
ACTIVE
ACTIVE
CLOCK
SUSPEND
CKE_
CKE
ROW
ACTIVE
BST
(on full page)
BST
(on full page)
WRITE
Write
WRITE
SUSPEND
CKE_
WRITE
READ
WRITE
WITH
AP
READ
WRITE
CKE
READ
WITH AP
WRITE
WITH AP
WRITEA
CKE_
READ
CKE
CKE
POWER
ON
READ
SUSPEND
READ
WITH AP
CKE_
READA
CKE
PRECHARGE
POWER
APPLIED
WRITE
WITH AP
Read
PRECHARGE
CKE_
WRITEA
SUSPEND
READ
WITH
AP
READA
SUSPEND
PRECHARGE
PRECHARGE
PRECHARGE
Automatic transition after completion of command.
Transition resulting from command input.
Note: 1. After the auto-refresh operation, precharge operation is performed automatically and
enter the IDLE state.
30
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Mode Register Configuration
The mode register is set by the input to the address pins (A0 to A12, BA0 and BA1) during mode register
set cycles. The mode register consists of five sections, each of which is assigned to address pins.
BA1, BA0, A11, A10, A12, A9 A8: (OPCODE): The SDRAM module has two types of write modes.
One is the burst write mode, and the other is the single write mode. These bits specify write mode.
Burst read and burst write: Burst write is performed for the specified burst length starting from the
column address specified in the write cycle.
Burst read and single write: Data is only written to the column address specified during the write cycle,
regardless of the burst length.
A7: Keep this bit Low at the mode register set cycle. If this pin is high, the vender test mode is set.
A6, A5, A4: (LMODE): These pins specify the CE latency.
A3: (BT): A burst type is specified. When full-page burst is performed, only "sequential" can be selected.
A2, A1, A0: (BL): These pins specify the burst length.
BA1 BA0 A12
A11
A10
A9
A8
OPCODE
A7
A6
0
0
A3
A2
BT
A1
A0
BL
A3 Burst type
0
R
0 Sequential
1
A2 A1 A0
Burst length
BT=0
BT=1
0
0
1
R
0
0
0
1
1
0
1
0
3*
0
0
1
2
2
0
1
1
4
0
1
0
4
4
1
X
X
R
0
1
1
8
8
1
0
0
R
R
1
0
1
R
R
1
1
0
R
R
1
1
1
F.P.
R
A9
A8
0
0
0
0
0
0
0
X
X
X
X
X
0
1
X
X
X
X
X
1
0
X
X
X
X
X
1
1
BA1 BA0 A12 A11 A10
A4
LMODE
A6 A5 A4 CAS latency
0
A5
Write mode
Burst read and burst write
R
Burst read and single write
R
Interleave
F.P. = Full Page
R is Reserved (inhibit)
X: 0 or 1
Note: Only -A6.
31
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Burst Sequence
Burst length = 2
Burst length = 4
Starting Ad. Addressing(decimal)
A0
Sequential Interleave
Starting Ad. Addressing(decimal)
A1
A0
Sequential
Interleave
0
0, 1,
0, 1,
0
0
0, 1, 2, 3,
0, 1, 2, 3,
1
1, 0,
1, 0,
0
1
1, 2, 3, 0,
1, 0, 3, 2,
1
0
2, 3, 0, 1,
2, 3, 0, 1,
1
1
3, 0, 1, 2,
3, 2, 1, 0,
Burst length = 8
Addressing(decimal)
Starting Ad.
A2
A1
A0 Sequential
Interleave
0
0
0
0, 1, 2, 3, 4, 5, 6, 7,
0, 1, 2, 3, 4, 5, 6, 7,
0
0
1
1, 2, 3, 4, 5, 6, 7, 0,
1, 0, 3, 2, 5, 4, 7, 6,
0
1
0
2, 3, 4, 5, 6, 7, 0, 1,
2, 3, 0, 1, 6, 7, 4, 5,
0
1
1
3, 4, 5, 6, 7, 0, 1, 2,
3, 2, 1, 0, 7, 6, 5, 4,
1
0
0
4, 5, 6, 7, 0, 1, 2, 3,
4, 5, 6, 7, 0, 1, 2, 3,
1
0
1
5, 6, 7, 0, 1, 2, 3, 4,
5, 4, 7, 6, 1, 0, 3, 2,
1
1
0
6, 7, 0, 1, 2, 3, 4, 5,
6, 7, 4, 5, 2, 3, 0, 1,
1
1
1
7, 0, 1, 2, 3, 4, 5, 6,
7, 6, 5, 4, 3, 2, 1, 0,
32
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Operation of the Registered SDRAM module
Read/Write Operations
Bank active: Before executing a read or write operation, the corresponding bank and the row address must
be activated by the bank active (ACTV) command. Bank 0, bank 1, bank 2 or bank 3 is activated according
to the status of the Bank select address (BA) pin, and the row address (AX0 to AX12) is activated by the
A0 to A12 pins at the bank active command cycle. An interval of t RCD is required between the bank active
command input and the following read/write command input.
Read operation: A read operation starts when a read command is input. Output buffer becomes Low-Z in
the (CE Latency - 1) cycle after read command set. The SDRAM module can perform a burst read
operation.
The burst length can be set to 1, 2, 4, 8 or full-page. The start address for a burst read is specified by the
column address and the bank select address (BA) at the read command set cycle. In a read operation, data
output starts after the number of clocks specified by the CE Latency. The CE Latency can be set to 3 or 4.
When the burst length is 1, 2, 4 or 8, the Dout buffer automatically becomes High-Z at the next clock after
the successive burst-length data has been output.
The CE latency and burst length must be specified at the mode register.
CE Latency
CK
t RCD
Command
Address
Dout
ACTV
Row
CL = 3
CL = 4
READ
Column
out 0
out 1
out 2
out 3
out 0
out 1
out 2
out 3
CL = CE latency
Burst Length = 4
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Burst Length
CK
t RCD
Command
ACTV
READ
Address
Row
Column
out 0
BL = 1
out 0 out 1
BL = 2
out 0 out 1 out 2 out 3
Dout
BL = 4
out 0 out 1 out 2 out 3 out 4 out 5 out 6 out 7
BL = 8
out 0 out 1 out 2 out 3 out 4 out 5 out 6 out 7 out 8
out 0-1
BL = full page
out 0
out 1
BL : Burst Length
CE Latency = 3
Write operation: Burst write or single write mode is selected by the OPCODE (BA1, BA0, A12, A11,
A10, A9, A8) of the mode register.
1. Burst write: A burst write operation is enabled by setting OPCODE (A9, A8) to (0, 0). A burst write
starts in the next clock as a write command set. (The latency of data input is 1 clock.) The burst length can
be set to 1, 2, 4, 8, and full-page, like burst read operations. The write start address is specified by the
column address (and the bank select address (BA) at the write command set cycle.
CK
t RCD
Command
ACTV
WRIT
Address
Row
Column
BL = 1
in 0
in 0
in 1
in 0
in 1
in 2
in 3
in 0
in 1
in 2
in 3
in 4
in 5
in 6
in 7
in 0
in 1
in 2
in 3
in 4
in 5
in 6
in 7
BL = 2
Din
BL = 4
BL = 8
BL = full page
in 8
in 0-1
in 0
in 1
CE Latency = 3, 4
2. Single write: A single write operation is enabled by setting OPCODE (A9, A8) to (1, 0). In a single
write operation, data is only written to the column address and the bank select address (BA) specified by
the write command set cycle without regard to the burst length setting. (The latency of data input is 1
clock).
34
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CK
t RCD
Command
Address
WRIT
ACTV
Row
Column
Din
in 0
Auto Precharge
Read with auto-precharge: In this operation, since precharge is automatically performed after completing
a read operation, a precharge command need not be executed after each read operation. The command
executed for the same bank after the execution of this command must be the bank active (ACTV)
command. In addition, an interval defined by lAPR is required before execution of the next command.
CE latency
Precharge start cycle
4
2 cycle before the final data is output
3
1 cycle before the final data is output
Burst Read (Burst Length = 4)
CK
CL=3 Command
ACTV
READ A
ACTV
lRAS
Dout
out0
out1
out2
out3
lAPR = 0
CL=4 Command
ACTV
READ A
ACTV
lRAS
Dout
out0
out1
out2
out3
lAPR = 0
Note: Internal auto-precharge starts at the timing indicated by " ".
And an interval of tRAS (lRAS) is required between previous active (ACTV) command and internal precharge "
".
35
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Write with auto-precharge: In this operation, since precharge is automatically performed after
completing a burst write or single write operation, a precharge command need not be executed after each
write operation. The command executed for the same bank after the execution of this command must be the
bank active (ACTV) command. In addition, an interval of lAPW is required between the final valid data
input and input of next command.
Burst Write (Burst Length = 4)
CK
Command
ACTV
ACTV
WRIT A
IRAS
Din
in0
in1
in2
in3
lAPW
Note: Internal auto-precharge starts at the timing indicated by " ".
and an interval of tRAS (lRAS) is required between previous active (ACTV) command
and internal precharge " ".
Single Write
CK
Command
ACTV
ACTV
WRIT A
IRAS
Din
in
lAPW
Note: Internal auto-precharge starts at the timing indicated by " ".
and an interval of tRAS (lRAS) is required between previous active (ACTV) command
and internal precharge " ".
36
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Full-page Burst Stop
Burst stop command during burst read: The burst stop (BST) command is used to stop data output
during a full-page burst. The BST command sets the output buffer to High-Z and stops the full-page burst
read. The timing from command input to the last data changes depending on the CE latency setting. In
addition, the BST command is valid only during full-page burst mode, and is illegal with burst lengths 1, 2,
4 and 8.
CE latency
BST to valid data
BST to high impedance
3
2
3
4
3
4
CE Latency = 3, Burst Length = full page
CK
BST
Command
Dout
out
out
out
out
out
out
out
l BSH = 3 clocks
l BSR = 2 clock
CE Latency = 4, Burst Length = full page
CK
BST
Command
Dout
out
out
out
out
out
out
l BSR = 3 clocks
out
out
l BSH = 4 clocks
37
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Burst stop command at burst write: The burst stop command (BST command) is used to stop data input
during a full-page burst write. No data is written in the same clock as the BST command, and in
subsequent clocks. In addition, the BST command is only valid during full-page burst mode, and is illegal
with burst lengths of 1, 2, 4 and 8. And an interval of tDPL is required between last data-in and the next
precharge command.
Burst Length = full page
CK
BST
Command
Din
in
in
in
I BSW = 1 clock
t DPL
38
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PRE/PALL
HB52R1289E2-A6A/B6A
Command Intervals
Read command to Read command interval:
1. Same bank, same ROW address: When another read command is executed at the same ROW address
of the same bank as the preceding read command execution, the second read can be performed after an
interval of no less than 1 clock. Even when the first command is a burst read that is not yet finished, the
data read by the second command will be valid.
READ to READ Command Interval (same ROW address in same bank)
CK
Command
Address
ACTV
Row
READ
READ
Column A Column B
BA
Dout
out A0 out B0 out B1 out B2 out B3
Bank0
Active
Column =A Column =B
Read
Read
Column =A Column =B
Dout
Dout
CE Latency = 4
Burst Length = 4
Bank 0
2. Same bank, different ROW address: When the ROW address changes on same bank, consecutive
read commands cannot be executed; it is necessary to separate the two read commands with a precharge
command and a bank-active command.
3. Different bank: When the bank changes, the second read can be performed after an interval of no less
than 1 clock, provided that the other bank is in the bank-active state. Even when the first command is a
burst read that is not yet finished, the data read by the second command will be valid.
READ to READ Command Interval (different bank)
CK
Command
ACTV
ACTV
READ READ
Address
Row 0
Row 1
Column A Column B
BA
Dout
out A0 out B0 out B1 out B2 out B3
Bank0
Active
Bank3 Bank0 Bank3
Active Read Read
Bank0 Bank3
Dout
Dout
CE Latency = 4
Burst Length = 4
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Write command to Write command interval:
1. Same bank, same ROW address: When another write command is executed at the same ROW
address of the same bank as the preceding write command, the second write can be performed after an
interval of no less than 1 clock. In the case of burst writes, the second write command has priority.
WRITE to WRITE Command Interval (same ROW address in same bank)
CK
Command
Address
ACTV
Row
WRIT
WRIT
Column A Column B
BA
Din
in A0
Bank0
Active
in B0
in B1
in B2
in B3
Burst Write Mode
Burst Length = 4
Bank 0
Column =A Column =B
Write
Write
2. Same bank, different ROW address: When the ROW address changes, consecutive write commands
cannot be executed; it is necessary to separate the two write commands with a precharge command and a
bank-active command.
3. Different bank: When the bank changes, the second write can be performed after an interval of no less
than 1 clock, provided that the other bank is in the bank-active state. In the case of burst write, the second
write command has priority.
WRITE to WRITE Command Interval (different bank)
CK
Command
ACTV
Address
Row 0
ACTV WRIT
Row 1
WRIT
Column A Column B
BA
Din
in A0
Bank0
Active
Bank3 Bank0 Bank3
Active Write Write
40
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in B0
in B1
in B2
in B3
Burst Write Mode
Burst Length = 4
HB52R1289E2-A6A/B6A
Read command to Write command interval:
1. Same bank, same ROW address: When the write command is executed at the same ROW address of
the same bank as the preceding read command, the write command can be performed after an interval of no
less than 1 clock. However, DQMB must be set High so that the output buffer becomes High-Z before data
input.
READ to WRITE Command Interval (1)
CK
Command
READ WRIT
CL=3
DQMB
CL=4
in B0
Din
in B1
in B2
in B3
Burst Length = 4
Burst write
High-Z
Dout
READ to WRITE Command Interval (2)
CK
Command
READ
WRIT
DQMB
2 clock
CL=3
Dout
CL=4
High-Z
High-Z
Din
2. Same bank, different ROW address: When the ROW address changes, consecutive write commands
cannot be executed; it is necessary to separate the two commands with a precharge command and a bankactive command.
3. Different bank: When the bank changes, the write command can be performed after an interval of no
less than 1 clock, provided that the other bank is in the bank-active state. However, DQMB must be set
High so that the output buffer becomes High-Z before data input.
41
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HB52R1289E2-A6A/B6A
Write command to Read command interval:
1. Same bank, same ROW address: When the read command is executed at the same ROW address of
the same bank as the preceding write command, the read command can be performed after an interval of no
less than 1 clock. However, in the case of a burst write, data will continue to be written until one cycle
before the read command is executed.
WRITE to READ Command Interval (1)
CK
Command
WRIT
READ
DQMB
Din
in A0
Dout
out B0
Column = A
Write
Column = B
Read
out B1
out B2
out B3
Burst Write Mode
CE Latency = 3
Burst Length = 4
Bank 0
CE Latency
Column = B
Dout
WRITE to READ Command Interval (2)
CK
Command
WRIT
READ
DQMB
Din
in A0
in A1
Dout
out B0
Column = A
Write
out B1
CE Latency
Column = B
Read
Column = B
Dout
out B2
out B3
Burst Write Mode
CE Latency = 3
Burst Length = 4
Bank 0
2. Same bank, different ROW address: When the ROW address changes, consecutive read commands
cannot be executed; it is necessary to separate the two commands with a precharge command and a bankactive command.
3. Different bank: When the bank changes, the read command can be performed after an interval of no
less than 1 clock, provided that the other bank is in the bank-active state. However, in the case of a burst
write, data will continue to be written until one clock before the read command is executed (as in the case
of the same bank and the same address).
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HB52R1289E2-A6A/B6A
Read with auto precharge to Read command interval
1. Different bank: When some banks are in the active state, the second read command (another bank) is
executed. Even when the first read with auto-precharge is a burst read that is not yet finished, the data read
by the second command is valid. The internal auto-precharge of one bank starts at the next clock of the
second command.
Read with Auto Precharge to Read Command Interval (Different bank)
CK
Command
READ A
READ
bank0
Read A
bank3
Read
BA
Dout
out A0
out A1
out B0
out B1
CE Latency = 4
Burst Length = 4
Note: Internal auto-precharge starts at the timing indicated by "
".
2. Same bank: The consecutive read command (the same bank) is illegal.
Write with auto precharge to Write command interval
1. Different bank: When some banks are in the active state, the second write command (another bank) is
executed. In the case of burst writes, the second write command has priority. The internal auto-precharge
of one bank starts at the next clock of the second command .
Write with Auto Precharge to Write Command Interval (Different bank)
CK
Command
WRIT A
WRIT
BA
Din
in A0
bank0
Write A
in A1
in B0
in B1
bank3
Write
Note: Internal auto-precharge starts at the timing indicated by "
in B2
in B3
Burst Length = 4
".
2. Same bank: The consecutive write command (the same bank) is illegal.
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HB52R1289E2-A6A/B6A
Read with auto precharge to Write command interval
1. Different bank: When some banks are in the active state, the second write command (another bank) is
executed. However, DQMB must be set High so that the output buffer becomes High-Z before data input.
The internal auto-precharge of one bank starts at the next clock of the second command.
Read with Auto Precharge to Write Command Interval (Different bank)
CK
Command
READ A
WRIT
BA
DQMB
CL = 3
CL = 4
Din
in B0
Dout
in B1
in B2
in B3
High-Z
bank0
Read A
Burst Length = 4
bank3
Write
Note: Internal auto-precharge starts at the timing indicated by "
".
2. Same bank: The consecutive write command from read with auto precharge (the same bank) is illegal.
It is necessary to separate the two commands with a bank active command.
44
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HB52R1289E2-A6A/B6A
Write with auto precharge to Read command interval
1. Different bank: When some banks are in the active state, the second read command (another bank) is
executed. However, in case of a burst write, data will continue to be written until one clock before the read
command is executed. The internal auto-precharge of one bank starts at the next clock of the second
command.
Write with Auto Precharge to Read Command Interval (Different bank)
CK
Command
WRIT A
READ
BA
DQMB
Din
in A0
Dout
out B0
bank0
Write A
out B2
out B3
CE Latency = 4
Burst Length = 4
bank3
Read
Note: Internal auto-precharge starts at the timing indicated by "
out B1
".
2. Same bank: The consecutive read command from write with auto precharge (the same bank) is illegal.
It is necessary to separate the two commands with a bank active command.
45
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HB52R1289E2-A6A/B6A
Read command to Precharge command interval (same bank):
When the precharge command is executed for the same bank as the read command that preceded it, the
minimum interval between the two commands is one clock. However, since the output buffer then
becomes High-Z after the clocks defined by l HZP, there is a case of interruption to burst read data output will
be interrupted, if the precharge command is input during burst read. To read all data by burst read, the
clocks defined by lEP must be assured as an interval from the final data output to precharge command
execution.
READ to PRECHARGE Command Interval (same bank): To output all data
CE Latency = 3, Burst Length = 4
CK
Command
READ
PRE/PALL
Dout
out A0
out A1
CL=3
out A2
out A3
l EP = -2 cycle
CE Latency = 4, Burst Length = 4
CK
Command
READ
PRE/PALL
Dout
out A0
CL=4
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out A1
out A2
l EP = -3 cycle
out A3
HB52R1289E2-A6A/B6A
READ to PRECHARGE Command Interval (same bank): To stop output data
CE Latency =3, Burst Length = 1, 2, 4, 8, full page burst
CK
Command
READ
PRE/PALL
Dout
out A0
High-Z
lHZP = 3
CE Latency = 4, Burst Length = 1, 2, 4, 8, full page burst
CK
Command
READ
PRE/PALL
Dout
out A0
High-Z
lHZP = 4
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HB52R1289E2-A6A/B6A
Write command to Precharge command interval (same bank): When the precharge command is
executed for the same bank as the write command that preceded it, the minimum interval between the two
commands is 1 clock. However, if the burst write operation is unfinished, the input data must be masked
by means of DQMB for assurance of the clock defined by tDPL.
WRITE to PRECHARGE Command Interval (same bank):
Burst Length = 4 (To stop write operation)
CK
Command
PRE/PALL
WRIT
DQMB
Din
tDPL
CK
Command
PRE/PALL
WRIT
DQMB
Din
in A0
in A1
tDPL
Burst Length = 4 (To write all data)
CK
Command
PRE/PALL
WRIT
DQMB
Din
in A0
in A1
in A2
in A3
tDPL
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HB52R1289E2-A6A/B6A
Bank active command interval:
1. Same bank: The interval between the two bank-active commands must be no less than tRC.
Bank Active to Bank Active for Same Bank
CK
Command
ACTV
ACTV
Address
ROW
ROW
BA
t RC
Bank 0
Active
Bank 0
Active
2. In the case of different bank-active commands: The interval between the two bank-active commands
must be no less than tRRD.
Bank Active to Bank Active for Different Bank
CK
Command
Address
ACTV
ACTV
ROW:0
ROW:1
BA
t RRD
Bank 0
Active
Bank 3
Active
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HB52R1289E2-A6A/B6A
Mode register set to Bank-active command interval: The interval between setting the mode register and
executing a bank-active command must be no less than lRSA .
CK
Command
Address
MRS
ACTV
CODE
BS & ROW
I RSA
Mode
Register Set
50
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Bank
Active
HB52R1289E2-A6A/B6A
DQMB Control
The DQMB mask the DQ data. The timing of DQMB is different during reading and writing.
Reading: When data is read, the output buffer can be controlled by DQMB. By setting DQMB to Low,
the output buffer becomes Low-Z, enabling data output. By setting DQMB to High, the output buffer
becomes High-Z, and the corresponding data is not output. However, internal reading operations continue.
The latency of DQMB during reading is 3 clocks.
Writing: Input data can be masked by DQMB. By setting DQMB to Low, data can be written. In
addition, when DQMB is set to High, the corresponding data is not written, and the previous data is held.
The latency of DQMB during writing is 1 clock.
Reading
CK
DQMB
Dout
High-Z
out 0
out 1
out 3
lDOD = 3 Latency
Writing
CK
DQMB
Din
in 0
in 1
in 3
l DID = 1 Latency
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HB52R1289E2-A6A/B6A
Refresh
Auto-refresh: All the banks must be precharged before executing an auto-refresh command. Since the
auto-refresh command updates the internal counter every time it is executed and determines the banks and
the ROW addresses to be refreshed, external address specification is not required. The refresh cycle is
8192 cycles/64 ms. (8192 cycles are required to refresh all the ROW addresses.) The output buffer
becomes High-Z after auto-refresh start. In addition, since a precharge has been completed by an internal
operation after the auto-refresh, an additional precharge operation by the precharge command is not
required.
Self-refresh: After executing a self-refresh command, the self-refresh operation continues while CKE is
held Low. During self-refresh operation, all ROW addresses are refreshed by the internal refresh timer. A
self-refresh is terminated by a self-refresh exit command. Before and after self-refresh mode, execute autorefresh to all refresh addresses in or within 64 ms period on the condition (1) and (2) below.
(1) Enter self-refresh mode within 7.8 µs after either burst refresh or distributed refresh at equal interval to
all refresh addresses are completed.
(2) Start burst refresh or distributed refresh at equal interval to all refresh addresses within 7.8 µs after
exiting from self-refresh mode.
Others
Power-down mode: The SDRAM module enters power-down mode when CKE goes Low in the IDLE
state. In power down mode, power consumption is suppressed by deactivating the input initial circuit.
Power down mode continues while CKE is held Low. In addition, by setting CKE to High, the SDRAM
module exits from the power down mode, and command input is enabled from the next clock. In this
mode, internal refresh is not performed.
Clock suspend mode: By driving CKE to Low during a bank-active or read/write operation, the SDRAM
module enters clock suspend mode. During clock suspend mode, external input signals are ignored and the
internal state is maintained. When CKE is driven High, the SDRAM module terminates clock suspend
mode, and command input is enabled from the next clock. For details, refer to the "CKE Truth Table".
Power-up sequence: The SDRAM module should be gone on the following sequence with power up.
The CK, CKE, S, DQMB and DQ pins keep low till power stabilizes.
The CK pin is stabilized within 100 µs after power stabilizes before the following initialization sequence.
The CKE and DQMB is driven to high between power stabilizes and the initialization sequence.
This SDRAM module has VCC clamp diodes for CK, CKE, S, DQMB and DQ pins. If these pins go high
before power up, the large current flows from these pins to VCC through the diodes.
Initialization sequence: When 200 µs or more has past after the above power-up sequence, all banks must
be precharged using the precharge command (PALL). After t RP delay, set 8 or more auto refresh commands
(REF). Set the mode register set command (MRS) to initialize the mode register. We recommend that by
keeping DQMB to High, the output buffer becomes High-Z during Initialization sequence, to avoid DQ bus
contention on memory system formed with a number of device.
52
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HB52R1289E2-A6A/B6A
Stabilization time: The PLL requires a stabilization time to achieve phase lock of the feedback signal to
the reference signal. This stabilization time is required following power-up. So this SDRAM module
needs dummy cycle for 50 µs after power-up.
Initialization sequence
Power up sequence
100 µs
VCC
200 µs
0V
CKE, DQMB
Low
CK
Low
S, DQ
Low
Power stabilize
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HB52R1289E2-A6A/B6A
Timing Waveforms
Read Cycle
t CK
t CKH t CKL
CK
t RC
VIH
CKE
t RAS
t
t RCD
t CS t CH
t CS t CH
RP
t CS t CH
t CS t CH
t CS t CH
t CS t CH
t CS t CH
t CS t CH
S
t CS t CH
t CS t CH
RE
t CS t CH
t CS t CH
CE
t CS t CH
t CS t CH
t AS t AH
t AS t AH
t AS t AH
t AS t AH
t AS t AH
t CS t CH
t CS t CH
W
t AS t AH
BA
t AS t AH
A10
t AS t AH
t AS t AH
t AS t AH
t AS t AH
Address
t CH
t CS
DQMB
Din
t AC
Dout
t AC
t AC
t HZ
t AC
Bank 0
Active
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Bank 0
Read
t LZ
t OH
t OH
t OH
Bank 0
Precharge
t OH
CE latency = 3
Burst length = 4
Bank 0 access
= VIH or VIL
HB52R1289E2-A6A/B6A
Write Cycle
t CK
t CKH t CKL
CK
t RC
VIH
CKE
t RAS
t RCD
t CS t CH
t RP
t CS t CH
t CS t CH
t CS t CH
t CS t CH
t CS t CH
t CS t CH
t CS t CH
S
t CS t CH
t CS t CH
RE
t CS t CH
t CS t CH
CE
t CS t CH
t CS t CH
t CS t CH
t AS t AH
t AS t AH
t AS t AH
t AS t AH
t CS t CH
W
t AS t AH
t AS t AH
BA
t AS t AH
t AS t AH
A10
t AS t AH
t AS t AH
t AS t AH
Address
t CS
t CH
DQMB
t DS t DH tDS
t DH t DS t DH t DS
t DH
Din
t DPL
Dout
Bank 0
Active
Bank 0
Write
Bank 0
Precharge
CE latency = 3
Burst length = 4
Bank 0 access
= VIH or VIL
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HB52R1289E2-A6A/B6A
Mode Register Set Cycle
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
b+3
b’
b’+1
b’+2
b’+3
19
CK
VIH
CKE
S
RE
CE
W
BA
Address
code R: b
valid
C: b’
C: b
DQMB
Dout
b
High-Z
Din
l RSA
l RP
Precharge
If needed
l RCD
Mode
Bank 3
register Active
Set
Output mask
l RCD = 3
CE latency = 4
Burst length = 4
= VIH or VIL
Bank 3
Read
Read Cycle/Write Cycle
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
CK
CKE
VIH
Read cycle
RE-CE delay = 3
CE latency = 4
Burst length = 4
= VIH or VIL
S
RE
CE
W
BA
Address
R:a
C:a
R:b
C:b
C:b'
C:b"
DQMB
Dout
Din
CKE
a
a+1 a+2 a+3
b
b+1 b+2 b+3 b'
b'+1 b"
b"+1 b"+2 b"+3
High-Z
Bank 0
Active
Bank 0
Read
Bank 3
Active
Bank 3 Bank 0
Read
Precharge
Bank 3
Read
Bank 3
Read
Bank 3
Precharge
VIH
Write cycle
RE-CE delay = 3
CE latency = 4
Burst length = 4
= VIH or VIL
S
RE
CE
W
BA
Address
R:a
C:a
R:b
C:b
C:b'
C:b"
DQMB
High-Z
Dout
Din
a
Bank 0
Active
Bank 0
Write
56
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a+1 a+2 a+3
Bank 3
Active
b
Bank 3
Write
b+1 b+2 b+3 b'
Bank 0
Precharge
Bank 3
Write
b'+1 b"
Bank 3
Write
b"+1 b"+2 b"+3
Bank 3
Precharge
HB52R1289E2-A6A/B6A
Read/Single Write Cycle
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
CK
CKE
VIH
S
RE
CE
W
BA
R:a
Address
C:a
R:b
C:a' C:a
DQMB
a
Din
Dout
a
Bank 0
Active
CKE
Bank 0
Read
Bank 3
Active
C:a
R:b
a+1 a+2 a+3
a
Bank 0 Bank 0
Write
Read
a+1 a+2 a+3
Bank 0
Precharge
Bank 3
Precharge
VIH
S
RE
CE
W
BA
Address
R:a
C:a
C:b C:c
DQMB
a
Din
Dout
a
Bank 0
Active
Bank 0
Read
Bank 3
Active
a+1
b
c
a+3
Bank 0
Write
Bank 0 Bank 0
Write
Write
Bank 0
Precharge
Read/Single write
RE-CE delay = 3
CE latency = 4
Burst length = 4
= VIH or VIL
57
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HB52R1289E2-A6A/B6A
Read/Burst Write Cycle
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
0
CK
CKE
S
RE
CE
W
BA
R:a
Address
C:a
R:b
C:a'
DQMB
a
Din
Dout
a
Bank 0
Active
CKE
Bank 0
Read
Bank 3
Active
C:a
R:b
a+1 a+2 a+3
a+1 a+2 a+3
Clock
suspend
Bank 0
Precharge
Bank 0
Write
Bank 3
Precharge
VIH
S
RE
CE
W
BA
Address
R:a
C:a
DQMB
a
Din
Dout
a
Bank 0
Active
Bank 0
Read
Bank 3
Active
a+1
a+1 a+2 a+3
a+3
Bank 0
Write
Bank 0
Precharge
Read/Burst write
RE-CE delay = 3
CE latency = 4
Burst length = 4
= VIH or VIL
58
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HB52R1289E2-A6A/B6A
Full Page Read/Write Cycle
CK
CKE
VIH
Read cycle
RE-CE delay = 3
CE latency = 4
Burst length = full page
= VIH or VIL
S
RE
CE
W
BA
Address
R:a
C:a
R:b
DQMB
Dout
Din
CKE
a
a+1
a+2
High-Z
Bank 0
Active
Bank 0
Read
Bank 3
Active
Burst stop
VIH
Write cycle
RE-CE delay = 3
CE latency = 4
Burst length = full page
= VIH or VIL
S
RE
CE
W
BA
Address
Bank 3
Precharge
R:a
C:a
R:b
DQMB
High-Z
Dout
Din
a
Bank 0
Active
Bank 0
Write
a+1
Bank 3
Active
a+2
a+3
a+4
a+5
Burst stop
Bank 3
Precharge
59
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HB52R1289E2-A6A/B6A
Auto Refresh Cycle
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
a
a+1
CK
CKE
VIH
S
RE
CE
W
BA
Address
C:a
R:a
A10=1
DQMB
Din
High-Z
Dout
t RC
t RP
Auto Refresh
Precharge
If needed
tRC
Active
Bank 0
Auto Refresh
Read
Bank 0
Refresh cycle and
Read cycle
RE-CE delay = 2
CE latency = 4
Burst length = 4
= VIH or VIL
Self Refresh Cycle
CK
l SREX
CKE Low
CKE
S
RE
CE
W
BA
Address
A10=1
DQMB
Din
High-Z
Dout
tRP
Precharge command
If needed
tRC
tRC
Self refresh entry
command
60
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Self refresh exit
ignore command
or No operation
Next
clock
enable
Self refresh entry
command
Auto
Next
clock refresh
enable
Self refresh cycle
RE-CE delay = 3
CE latency = 4
Burst length = 4
= VIH or VIL
HB52R1289E2-A6A/B6A
Clock Suspend Mode
t CES
0
1
2
3
4
5
t CES
t CEH
6
7
8
9
10
11
12
13
14
15
16
CK
CKE
RE
CE
W
BA
R:a
C:a
R:b
C:b
DQMB
a
Dout
a+1 a+2
a+3
High-Z
Din
Bank0 Active clock
Active suspend start
Active clock Bank0
suspend end Read
Bank3
Active
Read suspend
start
Read suspend
end
Bank3
Read
Bank0
Precharge
CKE
19
20
b+1 b+2 b+3
b
Earliest Bank3
Precharge
Write cycle
RE-CE delay = 2
CE latency = 3
Burst length = 4
= VIH or VIL
S
RE
CE
W
BA
Address
18
Read cycle
RE-CE delay = 2
CE latency = 3
Burst length = 4
= VIH or VIL
S
Address
17
C:a R:b
R:a
C:b
DQMB
High-Z
Dout
a
Din
Bank0
Active
Active clock
suspend start
Active clock Bank0 Bank3
supend end Write Active
a+1 a+2
Write suspend
start
a+3 b
Write suspend
end
b+1 b+2 b+3
Bank3 Bank0
Write Precharge
Earliest Bank3
Precharge
61
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HB52R1289E2-A6A/B6A
Power Down Mode
CK
CKE Low
CKE
S
RE
CE
W
BA
Address
R: a
A10=1
DQMB
Din
High-Z
Dout
tRP
Power down entry
Precharge command
If needed
Power down cycle
RE-CE delay = 3
CE latency = 3
Burst length = 4
= VIH or VIL
Power down
mode exit
Active Bank 0
Initialization Sequence
0
1
2
3
4
5
6
7
8
9
10
48
49
50
51
52
53
54
CK
CKE
VIH
S
RE
CE
W
DQMB
code
valid
Address
Valid
VIH
High-Z
DQ
t RP
All banks
Precharge
62
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t RC
Auto Refresh
t RSA
tRC
Auto Refresh
Mode register
Set
Bank active
If needed
55
HB52R1289E2-A6A/B6A
Physical Outline
Unit: mm
inch
Front side
133.37
5.251
3.00
0.118
4.80
0.189
4.00 min
0.157 min
127.35
5.014
3.00
0.118
Component area
(Front)
1
84
B
C
11.43
8.89
0.350
A
36.83
1.450
0.450
1.27 ± 0.10
0.050 ± 0.004
54.61
2.150
Back side
85
Detail B
FULL R
4.175
0.164
3.175
0.125
6.35
0.250
2.00 ± 0.10
0.079 ± 0.004
3.125 ± 0.125
0.123 ± 0.005
1.00 ± 0.05
0.039 ± 0.002
Detail C
FULL R
3.125 ± 0.125
0.123 ± 0.005
1.27
0.050
0.20 ± 0.15
0.008 ± 0.006
2.50 ± 0.20
0.098 ± 0.008
Detail A
38.10
1.500
168
Component area
(Back)
17.80
0.700
4.00
0.157
2 – φ 3.00
2 – φ 0.118
6.35
0.250
2.00 ± 0.10
0.079 ± 0.004
Note: Tolerance on all dimensions ± 0.15/0.006 unless otherwise specified.
63
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HB52R1289E2-A6A/B6A
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent,
copyright, trademark, or other intellectual property rights for information contained in this document.
Hitachi bears no responsibility for problems that may arise with third party’s rights, including
intellectual property rights, in connection with use of the information contained in this document.
2. Products and product specifications may be subject to change without notice. Confirm that you have
received the latest product standards or specifications before final design, purchase or use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,
contact Hitachi’s sales office before using the product in an application that demands especially high
quality and reliability or where its failure or malfunction may directly threaten human life or cause risk
of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation,
traffic, safety equipment or medical equipment for life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly
for maximum rating, operating supply voltage range, heat radiation characteristics, installation
conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used
beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable
failure rates or failure modes in semiconductor devices and employ systemic measures such as failsafes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other
consequential damage due to operation of the Hitachi product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without
written approval from Hitachi.
7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor
products.
Hitachi, Ltd.
Semiconductor & IC Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109
URL
NorthAmerica
: http:semiconductor.hitachi.com/
Europe
: http://www.hitachi-eu.com/hel/ecg
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Asia (Taiwan)
: http://www.hitachi.com.tw/E/Product/SICD_Frame.htm
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Japan
: http://www.hitachi.co.jp/Sicd/indx.htm
For further information write to:
Hitachi Semiconductor
(America) Inc.
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Brisbane, CA 94005-1897
Tel: <1> (800) 285-1601
Fax: <1> (303) 297-0447
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Electronic components Group
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D-85622 Feldkirchen, Munich
Germany
Tel: <49> (89) 9 9180-0
Fax: <49> (89) 9 29 30 00
Hitachi Europe Ltd.
Electronic Components Group.
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Lower Cookham Road
Maidenhead
Berkshire SL6 8YA, United Kingdom
Tel: <44> (1628) 585000
Fax: <44> (1628) 778322
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Tel: 535-2100
Fax: 535-1533
Hitachi Asia Ltd.
Taipei Branch Office
3F, Hung Kuo Building. No.167,
Tun-Hwa North Road, Taipei (105)
Tel: <886> (2) 2718-3666
Fax: <886> (2) 2718-8180
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Group III (Electronic Components)
7/F., North Tower, World Finance Centre,
Harbour City, Canton Road, Tsim Sha Tsui,
Kowloon, Hong Kong
Tel: <852> (2) 735 9218
Fax: <852> (2) 730 0281
Telex: 40815 HITEC HX
Copyright © Hitachi, Ltd., 1998. All rights reserved. Printed in Japan.
64
This Material Copyrighted by Its Respective Manufacturer
HB52R1289E2-A6A/B6A
Revision Record
Rev. Date
0.0
Contents of Modification
Drawn by
Approved by
Sep. 22, 1998 Initial issue
(referred to HM5225165A/HM5225805A/HM5225405AA6/B6 rev 0.1)
65
This Material Copyrighted by Its Respective Manufacturer