ETC HB52A89DB-10

HB52A89DB Series
64 MB Unbuffered SDRAM S.O.DIMM
8-Mword × 72-bit, 66 MHz Memory Bus, 1-Bank Module
(7 pcs of 8 M × 8 and 1 pc of 8 M × 16 components)
ADE-203-913A (Z)
Rev. 1.0
Oct. 15, 1998
Description
The HB52A89DB is a 8M × 72 × 1 bank Synchronous Dynamic RAM Small Outline Dual In-line Memory
Module (S.O.DIMM), mounted 7 piece of 64-Mbit SDRAM (HM5264805TT/LTT) sealed in TSOP
package, 1 piece of 128-Mbit SDRAM (HM5212165TD/LTD) sealed in TSOP package, and 1 piece of
serial EEPROM (2-kbit EEPROM) for Presence Detect (PD). An outline of the product is 144-pin Zig Zag
Dual tabs socket type compact and thin package. Therefore, it makes high density mounting possible
without surface mount technology. It provides common data inputs and outputs. Decoupling capacitors
are mounted beside TSOP on the module board.
Features
• Fully compatible with JEDEC standard outline unbuffered 8-byte S.O.DIMM
• 144-pin Zig Zag Dual tabs socket type
 Outline: 67.60 mm (Length) × 26.67 mm (Height) × 3.80 mm (Thickness)
 Lead pitch: 0.80 mm
• 3.3 V power supply
• Clock frequency: 66 MHz
• LVTTL interface
• Data bus width: × 72 ECC
• Single pulsed RAS
• 4 Banks can operates simultaneously and independently
• Burst read/write operation and burst read/single write operation capability
• Programmable burst length : 1/2/4/8/full page
• 2 Variations of burst sequence
 Sequential
 Interleave
• Programmable CE latency: 2/3
• Byte control by DQMB
• Refresh cycles: 4096 refresh cycles/64 ms
• 2 variations of refresh
This Material Copyrighted by Its Respective Manufacturer
HB52A89DB Series
 Auto refresh
 Self refresh
• Low self refresh current: HB52A89DB-10L (L-version)
• Full page burst length capability
 Sequential burst
 Burst stop capability
Ordering Information
Type No.
Frequency
Package
Contact pad
HB52A89DB-10
HB52A89DB-10L
66 MHz
66 MHz
Small outline DIMM (144-pin)
Gold
Pin Arrangement
Front Side
1pin
59pin
61pin
143pin
2pin
60pin
62pin
144pin
Back Side
2
This Material Copyrighted by Its Respective Manufacturer
HB52A89DB Series
Pin Arrangement (cont.)
Front side
Back side
Pin No.
Signal name Pin No.
Signal name Pin No.
Signal name Pin No.
Signal name
1
VSS
73
NC
2
VSS
74
CK1
3
DQ0
75
VSS
4
DQ32
76
VSS
5
DQ1
77
CB2
6
DQ33
78
CB6
7
DQ2
79
CB3
8
DQ34
80
CB7
9
DQ3
81
VCC
10
DQ35
82
VCC
11
VCC
83
DQ16
12
VCC
84
DQ48
13
DQ4
85
DQ17
14
DQ36
86
DQ49
15
DQ5
87
DQ18
16
DQ37
88
DQ50
17
DQ6
89
DQ19
18
DQ38
90
DQ51
19
DQ7
91
VSS
20
DQ39
92
VSS
21
VSS
93
DQ20
22
VSS
94
DQ52
23
DQMB0
95
DQ21
24
DQMB4
96
DQ53
25
DQMB1
97
DQ22
26
DQMB5
98
DQ54
27
VCC
99
DQ23
28
VCC
100
DQ55
29
A0
101
VCC
30
A3
102
VCC
31
A1
103
A6
32
A4
104
A7
33
A2
105
A8
34
A5
106
A13 (BA0)
35
VSS
107
VSS
36
VSS
108
VSS
37
DQ8
109
A9
38
DQ40
110
A12 (BA1)
39
DQ9
111
A10 (AP)
40
DQ41
112
A11
41
DQ10
113
VCC
42
DQ42
114
VCC
43
DQ11
115
DQMB2
44
DQ43
116
DQMB6
45
VCC
117
DQMB3
46
VCC
118
DQMB7
47
DQ12
119
VSS
48
DQ44
120
VSS
49
DQ13
121
DQ24
50
DQ45
122
DQ56
51
DQ14
123
DQ25
52
DQ46
124
DQ57
53
DQ15
125
DQ26
54
DQ47
126
DQ58
55
VSS
127
DQ27
56
VSS
128
DQ59
57
CB0
129
VCC
58
CB4
130
VCC
59
CB1
131
DQ28
60
CB5
132
DQ60
61
CK0
133
DQ29
62
CKE0
134
DQ61
63
VCC
135
DQ30
64
VCC
136
DQ62
65
RE
137
DQ31
66
CE
138
DQ63
3
This Material Copyrighted by Its Respective Manufacturer
HB52A89DB Series
Front side
Back side
Pin No.
Signal name Pin No.
Signal name Pin No.
Signal name Pin No.
Signal name
67
W
139
VSS
68
NC
140
VSS
69
S0
141
SDA
70
NC
142
SCL
71
NC
143
VCC
72
NC
144
VCC
Pin Description
Pin name
Function
A0 to A11
Address input
Row address
A0 to A11
Column address A0 to A8
A12/A13
Bank select address
DQ0 to DQ63
Data-input/output
CB0 to CB7
Check bit (Data-input/output )
S0
Chip select
RE
Row address asserted bank enable
CE
Column address asserted
W
Write enable
DQMB0 to DQMB7
Byte input/output mask
CK0/CK1
Clock input
CKE0
Clock enable
SDA
Data-input/output for serial PD
SCL
Clock input for serial PD
VCC
Power supply
VSS
Ground
NC
No connection
4
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BA1, BA0
HB52A89DB Series
Serial PD Matrix*1
Byte No. Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments
0
Number of bytes used by
module manufacturer
1
0
0
0
0
0
0
0
80
128
1
Total SPD memory size
0
0
0
0
1
0
0
0
08
256 byte
2
Memory type
0
0
0
0
0
1
0
0
04
SDRAM
3
Number of row addresses bits 0
0
0
0
1
1
0
0
0C
12
4
Number of column addresses
bits
0
0
0
0
1
0
0
1
09
9
5
Number of banks
0
0
0
0
0
0
0
1
01
1
6
Module data width
0
1
0
0
1
0
0
0
48
72
7
Module data width (continued) 0
0
0
0
0
0
0
0
00
0 (+)
8
Module interface signal levels 0
0
0
0
0
0
0
1
01
LVTTL
9
SDRAM cycle time
(highest CE latency)
15 ns
1
1
1
1
0
0
0
0
F0
CL = 3
10
SDRAM access from Clock
(highest CE latency)
9 ns
1
0
0
1
0
0
0
0
90
11
Module configuration type
0
0
0
0
0
0
1
0
02
ECC
12
Refresh rate/type
1
0
0
0
0
0
0
0
80
Normal
(15.625 µs)
Self refresh
13
SDRAM width
0
0
0
0
1
0
0
0
08
8M × 8
14
Error checking SDRAM width
0
0
0
0
1
0
0
0
08
×8
15
0
SDRAM device attributes:
minimum clock delay for backto-back random column
addresses
0
0
0
0
0
0
1
01
1 CLK
16
SDRAM device attributes:
Burst lengths supported
1
0
0
0
1
1
1
1
8F
1, 2, 4, 8, full
page
17
SDRAM device attributes:
number of banks on SDRAM
device
0
0
0
0
0
1
0
0
04
4
18
SDRAM device attributes:
CE latency
0
0
0
0
0
1
1
0
06
2, 3
19
SDRAM device attributes:
S0 latency
0
0
0
0
0
0
0
1
01
0
20
SDRAM device attributes:
W latency
0
0
0
0
0
0
0
1
01
0
21
SDRAM module attributes
0
0
0
0
0
0
0
0
00
Non buffer
5
This Material Copyrighted by Its Respective Manufacturer
HB52A89DB Series
Byte No. Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments
22
SDRAM device attributes:
General
0
0
0
0
1
1
1
0
0E
VCC ± 10%
23
SDRAM cycle time
(2nd highest CE latency)
15 ns
1
1
1
1
0
0
0
0
F0
CL = 2
24
SDRAM access from Clock
(2nd highest CE latency)
9 ns
1
0
0
1
0
0
0
0
90
25
SDRAM cycle time
(3rd highest CE latency)
Undefined
0
0
0
0
0
0
0
0
00
26
SDRAM access from Clock
(3rd highest CE latency)
Undefined
0
0
0
0
0
0
0
0
00
27
Minimum row precharge time
0
0
0
1
1
1
1
0
1E
30 ns
28
Row active to row active min
0
0
0
1
0
1
0
0
14
20 ns
29
RE to CE delay min
0
0
0
1
1
1
1
0
1E
30 ns
30
Minimum RE pulse width
0
0
1
1
1
1
0
0
3C
60 ns
31
Density of each bank on
module
0
0
0
1
0
0
0
0
10
64M byte
32
Address and command signal 0
input setup time
0
1
1
0
0
0
0
30
3 ns
33
Address and command signal 0
input hold time
0
0
1
0
1
0
1
15
1.5 ns
34
Data signal input setup time
0
0
1
1
0
0
0
0
30
3 ns
35
Data signal input hold time
0
0
0
1
0
1
0
1
15
1.5 ns
36 to 61 Superset information
0
0
0
0
0
0
0
0
00
Future use
62
SPD data revision code
0
0
0
1
0
0
1
0
12
Rev. 1.2A
63
Checksum for bytes 0 to 62
0
1
0
1
1
1
1
1
5F
95
64
Manuf act urer’s JEDEC ID c ode
0
0
0
0
0
1
1
1
07
HITACHI
65 to 71 Manuf act urer’s JEDEC ID c ode
0
0
0
0
0
0
0
0
00
72
Manufacturing location
×
×
×
×
×
×
×
×
××
* 3 (ASCII8bit code)
73
Manufacturer’s part number
0
1
0
0
1
0
0
0
48
H
74
Manufacturer’s part number
0
1
0
0
0
0
1
0
42
B
75
Manufacturer’s part number
0
0
1
1
0
1
0
1
35
5
76
Manufacturer’s part number
0
0
1
1
0
0
1
0
32
2
77
Manufacturer’s part number
0
1
0
0
0
0
0
1
41
A
6
This Material Copyrighted by Its Respective Manufacturer
HB52A89DB Series
Byte No. Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments
78
Manufacturer’s part number
0
0
1
1
1
0
0
0
38
8
79
Manufacturer’s part number
0
0
1
1
1
0
0
1
39
9
80
Manufacturer’s part number
0
1
0
0
0
1
0
0
44
D
81
Manufacturer’s part number
0
1
0
0
0
0
1
0
42
B
82
Manufacturer’s part number
0
0
1
0
1
1
0
1
2D
—
83
Manufacturer’s part number
0
0
1
1
0
0
0
1
31
1
84
Manufacturer’s part number
0
0
1
1
0
0
0
0
30
0
85
Manufacturer’s part number
(L-version)
0
1
0
0
1
1
0
0
4C
L
Manufacturer’s part number
0
0
1
0
0
0
0
0
20
(Space)
86
Manufacturer’s part number
0
0
1
0
0
0
0
0
20
(Space)
87
Manufacturer’s part number
0
0
1
0
0
0
0
0
20
(Space)
88
Manufacturer’s part number
0
0
1
0
0
0
0
0
20
(Space)
89
Manufacturer’s part number
0
0
1
0
0
0
0
0
20
(Space)
90
Manufacturer’s part number
0
0
1
0
0
0
0
0
20
(Space)
91
Revision code
0
0
1
1
0
0
0
0
30
Initial
92
Revision code
0
0
1
0
0
0
0
0
20
(Space)
93
Manufacturing date
×
×
×
×
×
×
×
×
××
Year code
(BCD)*4
94
Manufacturing date
×
×
×
×
×
×
×
×
××
Week code
(BCD)*4
95 to 98 Assembly serial number
*6
99 to 125 Manufacturer specific data
—
—
—
—
—
—
—
—
—
*5
126
Intel specification frequency
0
1
1
0
0
1
1
0
66
66 MHz
127
Intel specification CE# latency 0
support
0
0
0
0
1
1
0
06
CL = 2, 3
Notes: 1. All serial PD data are not protected. 0: Serial data, “driven Low”, 1: Serial data, “driven High”
These SPD are based on Intel specification (Rev.1.2A).
2. Regarding byte32 to 35, based on JEDEC Committee Ballot JC42.5-97-119.
3. Byte72 is manufacturing location code. (ex: In case of Japan, byte72 is 4AH. 4AH shows “J” on
ASCII code.)
4. Regarding byte93 and 94, based on JEDEC Committee Ballot JC42.5-97-135. BCD is “Binary
Coded Decimal”.
5. All bits of 99 through 125 are not defined (“1” or “0”).
6. Bytes 95 through 98 are assembly serial number.
7
This Material Copyrighted by Its Respective Manufacturer
HB52A89DB Series
Block Diagram
RE, CE, W
S0
DQMB0
DQMB4
DQM
8
DQ
DQ0 to DQ7
CS
D0
8
DQ32 to DQ39
DQMB1
DQ8 to DQ15
DQM
CS
DQ
D3
DQMB5
DQMU/L CS
DQ
M0
8
8
CB0 to CB7
DQ
DQM
CS
DQ
D4
8
DQ40 to DQ47
DQMB2
DQMB6
8
DQ16 to DQ23
DQM
CS
DQ
D1
DQM
CS
CS
DQM
8
DQ48 to DQ55
DQMB3
D5
DQ
DQMB7
8
DQ
DQ24 to DQ31
D2
8
DQ56 to DQ63
BA0
A13(D0 to D6, M0)
BA1
A12 (D0 to D6, M0)
CKE0
CKE (D0 to D6, M0)
R0
CK0
R1
R2
CK1
R3
VCC
C0-C15
CLK (D0)
CLK (D3)
CLK (M0)
CLK (D4)
CLK (D1)
CLK (D5)
CLK (D2)
CLK (D6)
VCC (D0 to D6, M0, U0)
C100-C107
VSS
8
This Material Copyrighted by Its Respective Manufacturer
VSS (D0 to D6, M0, U0)
CS
DQ
D6
Serial PD
A0 to A11(D0 to D6, M0)
A0 to A11
DQM
SCL
SDA
SCL
A0
SDA
U0
A1
A2
VSS
Notes :
1. The SDA pull-up resistor is required due to
the open-drain/open-collector output.
2. The SCL pull-up resistor is recommended
because of the normal SCL line inacitve
"high" state.
* D0 to D6 : HM5264805TT/LTT
M0 : HM5212165TD/LTD
U0 : 2-kbit EEPROM
C0 to C15 : 0.33 µF
C100 to C107 : 0.1 µF
R0 to R3 : Resistors (10 Ω)
HB52A89DB Series
Absolute Maximum Ratings
Parameter
Symbol
Value
Unit
Note
Voltage on any pin relative to V SS
VT
–0.5 to VCC + 0.5 (≤ 4.6 (max))
V
1
Supply voltage relative to VSS
VCC
–0.5 to +4.6
V
1
Short circuit output current
Iout
50
mA
Power dissipation
PT
8.0
W
Operating temperature
Topr
0 to +65
°C
Storage temperature
Tstg
–55 to +125
°C
Note:
1. Respect to V SS .
DC Operating Conditions (Ta = 0 to +65°C)
Parameter
Symbol
Min
Typ
Max
Unit
Notes
Supply voltage
VCC
3.0
3.3
3.6
V
1, 2
VSS
0
0
0
V
3
Input high voltage
VIH
2.0
—
VCC + 0.3
V
1, 4, 5
Input low voltage
VIL
–0.3
—
0.8
V
1, 6
Notes: 1.
2.
3.
4.
5.
6.
All voltage referred to VSS
The supply voltage with all VCC pins must be on the same level.
The supply voltage with all VSS pins must be on the same level.
CK, CKE, S, DQMB, DQ pins: VIH (max) = VCC + 0.5 V for pulse width ≤ 5 ns at VCC.
Others: V IH (max) = 4.6 V for pulse width ≤ 5 ns at VCC.
VIL (min) = –1.0 V for pulse width ≤ 5 ns at VSS.
9
This Material Copyrighted by Its Respective Manufacturer
HB52A89DB Series
DC Characteristics (Ta = 0 to 65°C, VCC = 3.3 V ± 0.3 V, VSS = 0 V)
HB52A89DB
Parameter
Symbol Min
Max
Unit
Test conditions
Notes
Operating current
(CE latency = 2)
—
585
mA
Burst length = 1
t RC = min
1, 2, 3
I CC1
(CE latency = 3)
I CC1
—
630
mA
Standby current in power down I CC2P
—
27
mA
CKE0 = VIL, t CK = 15 ns 6
Standby current in power down I CC2PS
(input signal stable)
—
18
mA
CKE0 = VIL, t CK = ∞
7
Standby current in non power
down
I CC2N
—
180
mA
CKE0, S = VIH,
t CK = 15 ns
4
Active standby current in power I CC3P
down
—
54
mA
CKE0, S = VIH,
t CK = 15 ns
1, 2, 6
Active standby current in non
power down
I CC3N
—
270
mA
CKE0, S = VIH,
t CK = 15 ns
1, 2, 4
I CC4
—
810
mA
t CK = min, BL = 4
1, 2, 5
I CC4
—
1080
mA
Refresh current
I CC5
—
990
mA
t RC = min
3
Self refresh current
I CC6
—
18
mA
VIH ≥ VCC – 0.2 V
VIL ≤ 0.2 V
8
Self refresh current
(L-version)
I CC6
—
4.4
mA
Input leakage current
I LI
–10
10
µA
0 ≤ Vin ≤ VCC
Output leakage current
I LO
–10
10
µA
0 ≤ Vout ≤ VCC
DQ = disable
Output high voltage
VOH
2.4
—
V
I OH = –2 mA
Output low voltage
VOL
—
0.4
V
I OL = 2 mA
Burst operating current
(CE latency = 2)
(CE latency = 3)
Notes: 1. I CC depends on output load condition when the device is selected. ICC (max) is specified at the
output open condition.
2. One bank operation.
3. Input signals are changed once per one clock.
4. Input signals are changed once per two clocks.
5. Input signals are changed once per four clocks.
6. After power down mode, CK0/CK1 operating current.
7. After power down mode, no CK0/CK1 operating current.
8. After self refresh mode set, self refresh current.
10
This Material Copyrighted by Its Respective Manufacturer
HB52A89DB Series
Capacitance (Ta = 25°C, VCC = 3.3 V ± 0.3 V)
Parameter
Symbol
Max
Unit
Notes
Input capacitance (Address)
CIN
55
pF
1, 2, 4
Input capacitance (RE, CE, W, S0, CKE0)
CIN
55
pF
1, 2, 4
Input capacitance (CK0/CK1)
CIN
55
pF
1, 2, 4
Input capacitance (DQMB0 to DQMB7)
CIN
20
pF
1, 2, 4
Input/Output capacitance (DQ0 to DQ63, CB0 to CB7) CI/O
20
pF
1, 2, 3, 4
Notes: 1.
2.
3.
4.
Capacitance measured with Boonton Meter or effective capacitance measuring method.
Measurement condition: f = 1 MHz, 1.4 V bias, 200 mV swing.
DQMB = VIH to disable Data-out.
This parameter is sampled and not 100% tested.
AC Characteristics (Ta = 0 to 65°C, VCC = 3.3 V ± 0.3 V, VSS = 0 V)
HB52A89DB
Parameter
Symbol
Min
Max
Unit
Notes
System clock cycle time
(CE latency = 2)
t CK
Tclk
15
—
ns
1
t CK
Tclk
15
—
CK0/CK1 high pulse width
t CKH
Tch
5
—
ns
1
CK0/CK1 low pulse width
t CKL
Tcl
5
—
ns
1
Access time from CK0/CK1
(CE latency = 2)
t AC
—
9
ns
1, 2
t AC
—
9
Data-out hold time
t OH
2.5
—
ns
1, 2
CK0/CK1 to Data-out low impedance
t LZ
2
—
ns
1, 2, 3
CK0/CK1 to Data-out high impedance
t HZ
—
7
ns
1, 4
Data-in setup time
t DS
Tsi
3
—
ns
1
Data in hold time
t DH
Thi
1.5
—
ns
1
Address setup time
t AS
Tsi
3
—
ns
1
Address hold time
t AH
Thi
1.5
—
ns
1
CKE0 setup time
t CES
Tsi
3
—
ns
1, 5
CKE0 setup time for power down exit
t CESP
Tpde
3
—
ns
1
CKE0 hold time
t CEH
Thi
1.5
—
ns
1
Command (S0, RE, CE, W, DQMB)
setup time
t CS
Tsi
3
—
ns
1
Command (S0, RE, CE, W, DQMB)
hold time
t CH
Thi
1.5
—
ns
1
(CE latency = 3)
(CE latency = 3)
11
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HB52A89DB Series
HB52A89DB
Parameter
Symbol
Min
Max
Unit
Notes
Ref/Active to Ref/Active command
period
t RC
105
—
ns
1
Active to precharge command period
t RAS
60
120000
ns
1
Active command to column command
(same bank)
t RCD
30
—
ns
1
Precharge to active command period
t RP
30
—
ns
1
Write recovery or data in to precharge t DPL
lead time
30
—
ns
1
Active (a) to Active (b) command
period
t RRD
20
—
ns
1
Transition time (rise to fall)
tT
1
5
ns
Refresh period
t REF
—
64
ms
Notes: 1.
2.
3.
4.
5.
AC measurement assumes t T = 1 ns. Reference level for timing of input signals is 1.4 V.
Access time is measured at 1.4 V. Load condition is C L = 50 pF with current source.
t LZ (max) defines the time at which the outputs achieves the low impedance state.
t HZ (max) defines the time at which the outputs achieves the high impedance state.
t CES defines CKE0 setup time to CKE0 rising edge except power down exit command.
Test Conditions
• Input and output timing reference levels: 1.4 V
• Input waveform and output load: See following figures
2.8 V
80%
input
DQ
50 Ω
20%
V SS
+1.4 V
CL
t
T
12
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tT
HB52A89DB Series
Relationship Between Frequency and Minimum Latency
Parameter
HB52A89DB
Frequency (MHz)
66
tCK (ns)
Symbol
15
Notes
Active command to column command
(same bank)
I RCD
2
1
7
= [IRAS + IRP]
1
Active command to active command (same bank)
(CE latency = 2)
I RC
(CE latency = 3)
Active command to precharge command
(same bank)
(CE latency = 2)
I RC
8
1
I RAS
4
I RAS
5
Precharge command to active command
(same bank)
I RP
2
1
Write recovery or data input to precharge
command (same bank)
I DPL
2
1
Active command to active command
(different bank)
I RRD
2
1
Self refresh exit time
I SREX
Tsrx
2
2
Last data in to active command
(Auto precharge, same bank)
I APW
Tdal
5
= [IDPL + IRP]
Self refresh exit to command input
I SEC
7
= [IRC]
3
Precharge command to high impedance
(CE latency = 2)
I HZP
Troh
2
I HZP
Troh
3
(CE latency = 3)
(CE latency = 3)
Last data out to active command (auto precharge) I APR
(same bank)
Last data out to precharge (early precharge)
(CE latency = 2)
(CE latency = 3)
1
I EP
–1
I EP
–2
Column command to column command
I CCD
Tccd
1
Write command to data in latency
I WCD
Tdwd
0
DQMB to data in
I DID
Tdgm
0
DQMB to data out
(CE latency = 2)
I DOD
Tdgz
2
(CE latency = 3)
I DOD
Tdgz
3
I CLE
Tcke
1
CKE0 to CK0/CK1 disable
13
This Material Copyrighted by Its Respective Manufacturer
HB52A89DB Series
Relationship Between Frequency and Minimum Latency (cont)
Parameter
HB52A89DB
Frequency (MHz)
66
tCK (ns)
Symbol
Register set to active command
t RSA
S0 to command disable
I CDD
0
Power down exit to command input
I PEC
1
Burst stop to output valid data hold
(CE latency = 2)
I BSR
1
I BSR
2
I BSH
2
(CE latency = 3)
I BSH
3
Burst stop to write data ignore
I BSW
0
(CE latency = 3)
Burst stop to output high impedance
(CE latency = 2)
15
Tmrd
3
Notes: 1. lRCD to l RRD are recommended value.
2. Be valid [DSEL] or [NOP] at next command of self refresh exit.
3. Except [DSEL] and [NOP]
14
This Material Copyrighted by Its Respective Manufacturer
Notes
HB52A89DB Series
Pin Functions
CK0/CK1 (input pin): CK is the master clock input to this pin. The other input signals are referred at CK
rising edge.
S0 (input pin): When S is Low, the command input cycle becomes valid. When S is High, all inputs are
ignored. However, internal operations (bank active, burst operations, etc.) are held.
RE, CE and W (input pins): Although these pin names are the same as those of conventional DRAM
modules, they function in a different way. These pins define operation commands (read, write, etc.)
depending on the combination of their voltage levels. For details, refer to the command operation section.
A0 to A11 (input pins): Row address (AX0 to AX11) is determined by A0 to A11 level at the bank active
command cycle CK rising edge. Column address (AY0 to AY8) is determined by A0 to A8 level at the
read or write command cycle CK rising edge. And this column address becomes burst access start address.
A10 defines the precharge mode. When A10 = High at the precharge command cycle, both banks are
precharged. But when A10 = Low at the precharge command cycle, only the bank that is selected by
A12/A13 (BS) is precharged.
A12/A13 (input pin): A12/A13 is a bank select signal (BS). The memory array is divided into bank0,
bank1, bank2 and bank3. If A12 is Low and A13 is Low, bank0 is selected. If A12 is High and A13 is
Low, bank1 is selected. If A12 is Low and A13 is High, bank2 is selected. If A12 is High and A13 is
HIgh, bank3 is selected.
CKE0 (input pin): This pin determines whether or not the next CK is valid. If CKE is High, the next CK
rising edge is valid. If CKE is Low, the next CK rising edge is invalid. This pin is used for power-down
mode, clock suspend mode and self refresh mode.
DQMB0 to DQMB7 (input pins): Read operation: If DQMB is High, the output buffer becomes High-Z.
If the DQMB is Low, the output buffer becomes Low- Z (The latency of DQMB during reading is 2
clocks).
Write operation: If DQMB is High, the previous data is held (the new data is not written). If DQMB is
Low, the data is written (The latency of DQMB during writing is 0 clock).
DQ0 to DQ63 (DQ pins): Data is input to and output from these pins.
VCC (power supply pins): 3.3 V is applied.
VSS (power supply pins): Ground is connected.
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HB52A89DB Series
Command Operation
Command Truth Table
The SDRAM module recognizes the following commands specified by the S, RE, CE, W and address pins.
CKE0
Command
Symbol
n-1
n
S0
RE
CE
W
A12/
A0
A13 A10 to A11
Ignore command
DESL
H
×
H
×
×
×
×
×
×
No operation
NOP
H
×
L
H
H
H
×
×
×
Burst stop in full page
BST
H
×
L
H
H
L
×
×
×
Column address and read command
READ
H
×
L
H
L
H
V
L
V
Read with auto-precharge
READ A
H
×
L
H
L
H
V
H
V
Column address and write command WRIT
H
×
L
H
L
L
V
L
V
Write with auto-precharge
WRIT A
H
×
L
H
L
L
V
H
V
Row address strobe and bank act.
ACTV
H
×
L
L
H
H
V
V
V
Precharge select bank
PRE
H
×
L
L
H
L
V
L
×
Precharge all bank
PALL
H
×
L
L
H
L
×
H
×
Refresh
REF/SELF H
V
L
L
L
H
×
×
×
Mode register set
MRS
×
L
L
L
L
V
V
V
H
Note: H: VIH. L: VIL. ×: V IH or VIL. V: Valid address input
Ignore command [DESL]: When this command is set (S0 is High), the SDRAM module ignore command
input at the clock. However, the internal status is held.
No operation [NOP]: This command is not an execution command. However, the internal operations
continue.
Burst stop in full-page [BST]: This command stops a full-page burst operation (burst length = full-page),
and is illegal otherwise. When data input/output is completed for a full page of data, it automatically
returns to the start address, and input/output is performed repeatedly.
Column address strobe and read command [READ]: This command starts a read operation. In
addition, the start address of burst read is determined by the column address and the bank select address
(BA). After the read operation, the output buffer becomes High-Z.
Read with auto-precharge [READ A]: This command automatically performs a precharge operation
after a burst read with a burst length of 1, 2, 4, or 8. When the burst length is full-page, this command is
illegal.
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HB52A89DB Series
Column address strobe and write command [WRIT]: This command starts a write operation. When the
burst write mode is selected, the column address and the bank select address (BA) become the burst write
start address. When the single write mode is selected, data is only written to the location specified by the
column address and the bank select address (BA).
Write with auto-precharge [WRIT A]: This command automatically performs a precharge operation
after a burst write with a length of 1, 2, 4, or 8, or after a single write operation. When the burst length is
full-page, this command is illegal.
Row address strobe and bank activate [ACTV]: This command activates the bank that is selected by
bank select address (BA) and determines the row address (AX0 to AX11). When A12 and A13 are Low,
bank0 is activated. When A12 is High and A13 is Low, bank1 is activated. When A12 is Low and A13 is
High, bank2 is activated. When A12 and A13 are High, bank3 is activated.
Precharge selected bank [PRE]: This command starts precharge operation for the bank selected by
A12/A13. If A12 and A13 are Low, bank0 is selected. If A12 is High and A13 is Low, bank1 is selected.
If A12 is Low and A13 is High, bank2 is selected. If A12 and A13 are High, bank3 is selected.
Precharge all banks [PALL]: This command starts a precharge operation for all banks.
Refresh [REF/SELF]: This command starts the refresh operation. There are two types of refresh
operation, the one is auto-refresh, and the other is self-refresh. For details, refer to the CKE0 truth table
section.
Mode register set [MRS]: The SDRAM module has a mode register that defines how it operates. The
mode register is specified by the address pins (A0 to A13) at the mode register set cycle. For details, refer
to the mode register configuration. After power on, the contents of the mode register are undefined,
execute the mode register set command to set up the mode register.
DQMB Truth Table
CKE0
Command
Symbol
n-1
n
DQMB
Write enable/output enable
ENB
H
×
L
Write inhibit/output disable
MASK
H
×
H
Note: H: VIH. L: VIL. ×: V IH or VIL.
I DOD is needed.
The SDRAM module can mask input/output data by means of DQMB During reading, the output buffer is
set to Low-Z by setting DQMB to Low, enabling data output. On the other hand, when DQMB is set to
High, the output buffer becomes High-Z, disabling data output. During writing, data is written by setting
DQMB to Low. When DQMB is set to High, the previous data is held (the new data is not written).
Desired data can be masked during burst read or burst write by setting DQMB. For details, refer to the
DQMB control section of the SDRAM module operating instructions.
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HB52A89DB Series
CKE Truth Table
CKE0
Current state
Command
n-1
n
S0
RE
CE
W
Address
Active
Clock suspend mode entry
H
L
H
×
×
×
×
Any
Clock suspend
L
L
×
×
×
×
×
Clock suspend
Clock suspend mode exit
L
H
×
×
×
×
×
Idle
Auto refresh command
H
H
L
L
L
H
×
Idle
Self refresh entry
H
L
L
L
L
H
×
Idle
Power down entry
H
L
L
H
H
H
×
H
L
H
×
×
×
×
L
H
L
H
H
H
×
L
H
H
×
×
×
×
L
H
L
H
H
H
×
L
H
H
×
×
×
×
Self-refresh
Power down
Self refresh exit
Power down exit
REF
SELF
SELFX
Note: H: VIH. L: VIL. ×: V IH or VIL.
Clock suspend mode entry: The SDRAM module enters clock suspend mode from active mode by
setting CKE to Low. The clock suspend mode changes depending on the current status (1 clock before) as
shown below.
ACTIVE clock suspend: This suspend mode ignores inputs after the next clock by internally maintaining
the bank active status.
READ suspend and READ with Auto-precharge suspend: The data being output is held (and continues
to be output).
WRITE suspend and WRIT with Auto-precharge suspend: In this mode, external signals are not
accepted. However, the internal state is held.
Clock suspend: During clock suspend mode, keep the CKE to Low.
Clock suspend mode exit: The SDRAM module exits from clock suspend mode by setting CKE to High
during the clock suspend state.
IDLE: In this state, all banks are not selected, and completed precharge operation.
Auto refresh command [REF]: When this command is input from the IDLE state, the SDRAM module
starts auto refresh operation. (The auto refresh is the same as the CBR refresh of conventional DRAM
module.) During the auto refresh operation, refresh address and bank select address are generated inside
the SDRAM module. For every auto refresh cycle, the internal address counter is updated. Accordingly,
4096 times are required to refresh the entire memory. Before executing the auto refresh command, all the
banks must be in the IDLE state. In addition, since the precharge for all banks is automatically performed
after auto refresh, no precharge command is required after auto refresh.
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HB52A89DB Series
Self refresh entry [SELF]: When this command is input during the IDLE state, the SDRAM module
starts self refresh operation. After the execution of this command, self refresh continues while CKE0 is
Low. Since self refresh is performed internally and automatically, external refresh operations are
unnecessary.
Power down mode entry: When this command is executed during the IDLE state, the SDRAM module
enters power down mode. In power down mode, power consumption is suppressed by cutting off the initial
input circuit.
Self refresh exit: When this command is executed during self refresh mode, the SDRAM module can exit
from self refresh mode. After exiting from self refresh mode, the SDRAM module enters the IDLE state.
Power down exit: When this command is executed at the power down mode, the SDRAM module can
exit from power down mode. After exiting from power down mode, the SDRAM module enters the IDLE
state.
Function Truth Table
The following table shows the operations that are performed when each command is issued in each mode of
the SDRAM module. The following table assumes that CKE is high.
Current state S
RE
CE
W
Address
Command
Operation
Precharge
H
×
×
×
×
DESL
Enter IDLE after t RP
L
H
H
H
×
NOP
Enter IDLE after t RP
L
H
H
L
×
BST
NOP
L
H
L
H
BA, CA, A10
READ/READ A
ILLEGAL
L
H
L
L
BA, CA, A10
WRIT/WRIT A
ILLEGAL
L
L
H
H
BA, RA
ACTV
ILLEGAL
L
L
H
L
BA, A10
PRE, PALL
NOP
L
L
L
H
×
REF, SELF
ILLEGAL
L
L
L
L
MODE
MRS
ILLEGAL
H
×
×
×
×
DESL
NOP
L
H
H
H
×
NOP
NOP
L
H
H
L
×
BST
NOP
L
H
L
H
BA, CA, A10
READ/READ A
ILLEGAL
L
H
L
L
BA, CA, A10
WRIT/WRIT A
ILLEGAL
L
L
H
H
BA, RA
ACTV
Bank and row active
L
L
H
L
BA, A10
PRE, PALL
NOP
L
L
L
H
×
REF, SELF
Refresh
L
L
L
L
MODE
MRS
Mode register set
Idle
19
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HB52A89DB Series
Current state S
RE
CE
W
Address
Command
Operation
Row active
H
×
×
×
×
DESL
NOP
L
H
H
H
×
NOP
NOP
L
H
H
L
×
BST
NOP
L
H
L
H
BA, CA, A10
READ/READ A
Begin read
L
H
L
L
BA, CA, A10
WRIT/WRIT A
Begin write
L
L
H
H
BA, RA
ACTV
Other bank active
ILLEGAL on same bank*3
L
L
H
L
BA, A10
PRE, PALL
Precharge
L
L
L
H
×
REF, SELF
ILLEGAL
L
L
L
L
MODE
MRS
ILLEGAL
H
×
×
×
×
DESL
Continue burst to end
L
H
H
H
×
NOP
Continue burst to end
L
H
H
L
×
BST
Burst stop to full page
L
H
L
H
BA, CA, A10
READ/READ A
Continue burst read to CE latency
and new read
L
H
L
L
BA, CA, A10
WRIT/WRIT A
Term burst read/start write
L
L
H
H
BA, RA
ACTV
Other bank active
ILLEGAL on same bank*3
L
L
H
L
BA, A10
PRE, PALL
Term burst read and Precharge
L
L
L
H
×
REF, SELF
ILLEGAL
L
L
L
L
MODE
MRS
ILLEGAL
Read with
H
auto-precharge
×
×
×
×
DESL
Continue burst to end and
precharge
L
H
H
H
×
NOP
Continue burst to end and
precharge
L
H
H
L
×
BST
ILLEGAL
L
H
L
H
BA, CA, A10
READ/READ A
ILLEGAL
L
H
L
L
BA, CA, A10
WRIT/WRIT A
ILLEGAL
L
L
H
H
BA, RA
ACTV
Other bank active
ILLEGAL on same bank*3
L
L
H
L
BA, A10
PRE, PALL
ILLEGAL
L
L
L
H
×
REF, SELF
ILLEGAL
L
L
L
L
MODE
MRS
ILLEGAL
Read
20
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HB52A89DB Series
Current state S
RE
CE
W
Address
Command
Operation
Write
H
×
×
×
×
DESL
Continue burst to end
L
H
H
H
×
NOP
Continue burst to end
L
H
H
L
×
BST
Burst stop on full page
L
H
L
H
BA, CA, A10
READ/READ A
Term burst and new read
L
H
L
L
BA, CA, A10
WRIT/WRIT A
Term burst and new write
L
L
H
H
BA, RA
ACTV
Other bank active
ILLEGAL on same bank*3
L
L
H
L
BA, A10
PRE, PALL
Term burst write and precharge*2
L
L
L
H
×
REF, SELF
ILLEGAL
L
L
L
L
MODE
MRS
ILLEGAL
Write with
H
auto-precharge
×
×
×
×
DESL
Continue burst to end and
precharge
L
H
H
H
×
NOP
Continue burst to end and
precharge
L
H
H
L
×
BST
ILLEGAL
L
H
L
H
BA, CA, A10
READ/READ A
ILLEGAL
L
H
L
L
BA, CA, A10
WRIT/WRIT A
ILLEGAL
L
L
H
H
BA, RA
ACTV
Other bank active
ILLEGAL on same bank*3
L
L
H
L
BA, A10
PRE, PALL
ILLEGAL
L
L
L
H
×
REF, SELF
ILLEGAL
L
L
L
L
MODE
MRS
ILLEGAL
H
×
×
×
×
DESL
Enter IDLE after t RC
L
H
H
H
×
NOP
Enter IDLE after t RC
L
H
H
L
×
BST
Enter IDLE after t RC
L
H
L
H
BA, CA, A10
READ/READ A
ILLEGAL
L
H
L
L
BA, CA, A10
WRIT/WRIT A
ILLEGAL
L
L
H
H
BA, RA
ACTV
ILLEGAL
L
L
H
L
BA, A10
PRE, PALL
ILLEGAL
L
L
L
H
×
REF, SELF
ILLEGAL
L
L
L
L
MODE
MRS
ILLEGAL
Refresh
(auto refresh)
Notes: 1. H: VIH. L: VIL. ×: V IH or VIL.
The other combinations are inhibit.
2. An interval of t DPL is required between the final valid data input and the precharge command.
3. If tRRD is not satisfied, this operation is illegal.
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HB52A89DB Series
From PRECHARGE state, command operation
To [DESL], [NOR] or [BST]: When these commands are executed, the SDRAM module enters the IDLE
state after tRP has elapsed from the completion of precharge.
From IDLE state, command operation
To [DESL], [NOP], [BST], [PRE] or [PALL]: These commands result in no operation.
To [ACTV]: The bank specified by the address pins and the ROW address is activated.
To [REF], [SELF]: The SDRAM module enters refresh mode (auto refresh or self refresh).
To [MRS]: The SDRAM module enters the mode register set cycle.
From ROW ACTIVE state, command operation
To [DESL], [NOP] or [BST]: These commands result in no operation.
To [READ], [READ A]: A read operation starts. (However, an interval of tRCD is required.)
To [WRIT], [WRIT A]: A write operation starts. (However, an interval of tRCD is required.)
To [ACTV]: This command makes the other bank active. (However, an interval of tRRD is required.)
Attempting to make the currently active bank active results in an illegal command.
To [PRE], [PALL]: These commands set the SDRAM module to precharge mode. (However, an interval
of t RAS is required.)
From READ state, command operation
To [DESL], [NOP]: These commands continue read operations until the burst operation is completed.
To [BST]: This command stops a full-page burst.
To [READ], [READ A]: Data output by the previous read command continues to be output. A f t e r CE
latency, the data output resulting from the next command will start.
To [WRIT], [WRIT A]: These commands stop a burst read, and start a write cycle.
To [ACTV]: This command makes other banks bank active. (However, an interval of tRRD is required.)
Attempting to make the currently active bank active results in an illegal command.
To [PRE], [PALL]: These commands stop a burst read, and the SDRAM module enters precharge mode.
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HB52A89DB Series
From READ with AUTO PRECHARGE state, command operation
To [DESL], [NOP]: These commands continue read operations until the burst operation is completed, and
the SDRAM module then enters precharge mode.
To [ACTV]: This command makes other banks bank active. (However, an interval of tRRD is required.)
Attempting to make the currently active bank active results in an illegal command.
From WRITE state, command operation
To [DESL], [NOP]: These commands continue write operations until the burst operation is completed.
To [BST]: This command stops a full-page burst.
To [READ], [READ A]: These commands stop a burst and start a read cycle.
To [WRIT], [WRIT A]: These commands stop a burst and start the next write cycle.
To [ACTV]: This command makes the other bank active. (However, an interval of tRRD is required.)
Attempting to make the currently active bank active results in an illegal command.
To [PRE], [PALL]: These commands stop burst write and the SDRAM module then enters precharge
mode.
From WRITE with AUTO-PRECHARGE state, command operation
To [DESL], [NOP]: These commands continue write operations until the burst is completed, and the
SDRAM module enters precharge mode.
To [ACTV]: This command makes the other bank active. (However, an interval of tRRD is required.)
Attempting to make the currently active bank active results in an illegal command.
From REFRESH state, command operation
To [DESL], [NOP], [BST]: After an auto-refresh cycle (after tRC), the SDRAM module automatically
enters the IDLE state.
23
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HB52A89DB Series
Simplified State Diagram
SELF
REFRESH
SR ENTRY
SR EXIT
MRS
MODE
REGISTER
SET
REFRESH
IDLE
*1
AUTO
REFRESH
CKE
CKE_
IDLE
POWER
DOWN
ACTIVE
ACTIVE
CLOCK
SUSPEND
CKE_
CKE
ROW
ACTIVE
BST
(on full page)
BST
(on full page)
WRITE
Write
WRITE
SUSPEND
CKE_
WRITE
READ
WRITE
WITH
AP
READ
WRITE
CKE
READ
WITH AP
WRITE
WITH AP
WRITEA
READ
CKE
CKE
POWER
ON
READ
SUSPEND
READ
WITH AP
CKE_
READA
CKE
PRECHARGE
POWER
APPLIED
WRITE
WITH AP
Read
CKE_
PRECHARGE
CKE_
WRITEA
SUSPEND
READ
WITH
AP
READA
SUSPEND
PRECHARGE
PRECHARGE
PRECHARGE
Automatic transition after completion of command.
Transition resulting from command input.
Note: 1. After the auto-refresh operation, precharge operation is performed automatically and
enter the IDLE state.
24
This Material Copyrighted by Its Respective Manufacturer
HB52A89DB Series
Mode Register Configuration
The mode register is set by the input to the address pins (A0 to A13) during mode register set cycles. The
mode register consists of five sections, each of which is assigned to address pins.
A13, A12, A11, A10, A9, A8: (OPCODE): The SDRAM module has two types of write modes. One is
the burst write mode, and the other is the single write mode. These bits specify write mode.
Burst read and burst write: Burst write is performed for the specified burst length starting from the
column address specified in the write cycle.
Burst read and single write: Data is only written to the column address specified during the write cycle,
regardless of the burst length.
A7: Keep this bit Low at the mode register set cycle. If this pin is high, the vender test mode is set.
A6, A5, A4: (LMODE): These pins specify the CE latency.
A3: (BT): A burst type is specified. When full-page burst is performed, only “sequential” can be
selected.
A2, A1, A0: (BL): These pins specify the burst length.
A13
A12
A11
A10
A9
A8
OPCODE
A7
A6
0
A4
LMODE
A6 A5 A4 CAS Latency
A13 A12 A11 A10
A5
A3
BT
0
0
R
0 Sequential
0
0
1
R
1
0
1
0
0
1
1
1
X
X
A8
0
0
0
0
0
0
X
X
X
X
0
1
X
X
X
X
1
0
X
X
X
X
1
1
A0
BL
A2 A1 A0
Burst Length
BT=0
BT=1
0
0
0
1
2
0
0
1
2
2
3
0
1
0
4
4
R
0
1
1
8
8
1
0
0
R
R
1
0
1
R
R
1
1
0
R
R
1
1
1
F.P.
R
Write mode
Burst read and burst write
R
Burst read and single write
R
A1
A3 Burst Type
0
A9
A2
Interleave
1
F.P. = Full Page
R is Reserved (inhibit)
X: 0 or 1
25
This Material Copyrighted by Its Respective Manufacturer
HB52A89DB Series
Burst Sequence
Burst length = 2
Burst length = 4
Starting Ad. Addressing(decimal)
A0
Sequential Interleave
Starting Ad. Addressing(decimal)
A1
A0
Sequential
Interleave
0
0, 1,
0, 1,
0
0, 1, 2, 3,
0
1
1, 0,
1, 0,
0
0, 1, 2, 3,
1
1, 2, 3, 0,
1, 0, 3, 2,
1
0
2, 3, 0, 1,
2, 3, 0, 1,
1
1
3, 0, 1, 2,
3, 2, 1, 0,
Burst length = 8
Addressing(decimal)
Starting Ad.
A2
A1
0
0
A0 Sequential
0
0, 1, 2, 3, 4, 5, 6, 7,
0, 1, 2, 3, 4, 5, 6, 7,
0
0
1
1, 2, 3, 4, 5, 6, 7, 0,
1, 0, 3, 2, 5, 4, 7, 6,
0
1
0
2, 3, 4, 5, 6, 7, 0, 1,
2, 3, 0, 1, 6, 7, 4, 5,
0
1
1
3, 4, 5, 6, 7, 0, 1, 2,
3, 2, 1, 0, 7, 6, 5, 4,
1
0
0
4, 5, 6, 7, 0, 1, 2, 3,
4, 5, 6, 7, 0, 1, 2, 3,
1
0
1
5, 6, 7, 0, 1, 2, 3, 4,
5, 4, 7, 6, 1, 0, 3, 2,
1
1
0
6, 7, 0, 1, 2, 3, 4, 5,
6, 7, 4, 5, 2, 3, 0, 1,
1
1
1
7, 0, 1, 2, 3, 4, 5, 6,
7, 6, 5, 4, 3, 2, 1, 0,
26
This Material Copyrighted by Its Respective Manufacturer
Interleave
HB52A89DB Series
Operation of the SDRAM module
Read/Write Operations
Bank active: Before executing a read or write operation, the corresponding bank and the row address must
be activated by the bank active (ACTV) command. Bank0, bank1, bank2 or bank3 is activated according
to the status of the bank select address pin, and the row address (AX0 to AX11) is activated by the A0 to
A11 pins at the bank active command cycle. An interval of tRCD is required between the bank active
command input and the following read/write command input.
Read operation: A read operation starts when a read command is input. Output buffer becomes Low-Z in
the (C E Latency-1) cycle after read command set. The SDRAM module can perform a burst read
operation. The burst length can be set to 1, 2, 4, 8 or full-page. The start address for a burst read is
specified by the column address and the bank select address (BA) at the read command set cycle. In a read
operation, data output starts after the number of clocks specified by the CE Latency. The CE Latency can
be set to 2 or 3. When the burst length is 1, 2, 4, or 8, full-page, the Dout buffer automatically becomes
High-Z at the next clock after the successive burst-length data has been output. The CE latency and burst
length must be specified at the mode register.
CE Latency
CK
t RCD
Command
Address
Dout
ACTV
Row
CL = 2
CL = 3
READ
Column
out 0
out 1
out 2
out 3
out 0
out 1
out 2
out 3
CL = CE latency
Burst Length = 4
27
This Material Copyrighted by Its Respective Manufacturer
HB52A89DB Series
Burst Length
CK
t RCD
Command
ACTV
READ
Address
Row
Column
out 0
BL = 1
out 0 out 1
BL = 2
out 0 out 1 out 2 out 3
Dout
BL = 4
out 0 out 1 out 2 out 3 out 4 out 5 out 6 out 7
BL = 8
out 0 out 1 out 2 out 3 out 4 out 5 out 6 out 7 out 8
out 0-1
BL = full page
out 0
out 1
BL : Burst Length
CE Latency = 3
Write operation: Burst write or single write mode is selected by the OPCODE (A13, A12, A11, A10, A9,
A8) of the mode register.
Burst write
A burst write operation is enabled by setting OPCODE (A9, A8) to (0, 0). A burst write starts in the same
clock as a write command set. (The latency of data input is 0 clock.) The burst length can be set to 1, 2, 4,
8, and full-page, like burst read operations. The write start address is specified by the column address and
the bank select address (BA) at the write command set cycle.
CK
t RCD
Command
ACTV
WRIT
Address
Row
Column
BL = 1
in 0
in 0
in 1
in 0
in 1
in 2
in 3
in 0
in 1
in 2
in 3
in 4
in 5
in 6
in 7
in 0
in 1
in 2
in 3
in 4
in 5
in 6
in 7
BL = 2
Din
BL = 4
BL = 8
BL = full page
28
This Material Copyrighted by Its Respective Manufacturer
in 8
in 0-1
in 0
in 1
CE Latency = 2, 3
HB52A89DB Series
Single write
A single write operation is enabled by setting OPCODE (A9, A8) to (1, 0). In a single write operation, data
is only written to the column address and the bank select address (BA) specified by the write command set
cycle without regard to the burst length setting. (The latency of data input is 0 clock).
CK
t RCD
Command
Address
WRIT
ACTV
Row
Column
Din
in 0
CE Latency = 2, 3
Burst Length = 1, 2, 4, 8, full page
Auto Precharge
Read with auto precharge: In this operation, since precharge is automatically performed after completing
a read operation, a precharge command need not be executed after each read operation. The command
executed for the same bank after the execution of this command must be the bank active (ACTV)
command. In addition, an interval defined by IAPR is required before execution of the next command.
CE latency
Precharge start cycle
3
2 cycle before the final data is output
2
1 cycle before the final data is output
Burst Read (Burst Length = 4)
CK
CL=2 Command
ACTV
READ A
ACTV
lRAS
Dout
out0
out1
out2
out3
lAPR
CL=3 Command
ACTV
READ A
ACTV
lRAS
Dout
out0
out1
out2
out3
lAPR
Note: Internal auto-precharge starts at the timing indicated by " ".
And an interval of tRAS (lRAS) is required between previous active (ACTV) command and internal precharge "
".
29
This Material Copyrighted by Its Respective Manufacturer
HB52A89DB Series
Write with auto-precharge: In this operation, since precharge is automatically performed after
completing a burst write or single write operation, a precharge command need not be executed after each
write operation. The command executed for the same bank after the execution of this command must be the
bank active (ACTV) command. In addition, an interval of lAPW is required between the final valid data
input and input of next command.
Burst Write (Burst Length = 4)
CK
Command
ACTV
ACTV
WRIT A
IRAS
Din
in0
in1
in2
in3
lAPW
Note: Internal auto-precharge starts at the timing indicated by " ".
and an interval of tRAS (lRAS) is required between previous active (ACTV) command
and internal precharge " ".
Single Write
CK
Command
ACTV
ACTV
WRIT A
IRAS
Din
in
lAPW
Note: Internal auto-precharge starts at the timing indicated by " ".
and an interval of tRAS (lRAS) is required between previous active (ACTV) command
and internal precharge " ".
30
This Material Copyrighted by Its Respective Manufacturer
HB52A89DB Series
Full-page Burst Stop
Burst stop command during burst read: The burst stop (BST) command is used to stop data output
during a full-page burst. The BST command sets the output buffer to High-Z and stops the full-page burst
read. The timing from command input to the last data changes depending on the CE latency setting. In
addition, the BST command is valid only during full-page burst mode, and is invalid with burst lengths 1,
2, 4 and 8.
CE latency
BST to valid data
BST to high impedance
2
1
2
3
2
3
CE Latency = 2, Burst Length = full page
CK
BST
Command
Dout
out
out
out
out
out
out
l BSH = 2 clocks
l BSR = 1 clock
CE Latency = 3, Burst Length = full page
CK
BST
Command
Dout
out
out
out
out
out
out
l BSR = 2 clocks
out
l BSH = 3 clocks
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This Material Copyrighted by Its Respective Manufacturer
HB52A89DB Series
Burst stop command at burst write: The burst stop command (BST command) is used to stop data input
during a full-page burst write. No data is written in the same clock as the BST command and in subsequent
clocks. In addition, the BST command is only valid during full-page burst mode, and is invalid with burst
lengths of 1, 2, 4 and 8. And an interval of tDPL is required between last data-in and the next precharge
command.
Burst Length = full page
CK
BST
Command
Din
in
in
t DPL
I BSW = 0 clock
32
This Material Copyrighted by Its Respective Manufacturer
PRE/PALL
HB52A89DB Series
Command Intervals
Read command to Read command interval:
1. Same bank, same ROW address: When another read command is executed at the same ROW address
of the same bank as the preceding read command execution, the second read can be performed after an
interval of no less than 1 clock. Even when the first command is a burst read that is not yet finished, the
data read by the second command will be valid.
READ to READ Command Interval (same ROW address in same bank)
CK
Command
Address
ACTV
Row
READ
READ
Column A Column B
BA
Dout
out A0 out B0 out B1 out B2 out B3
Bank0
Active
Column =A Column =B Column =A Column =B
Dout
Read
Read
Dout
CE Latency = 3
Burst Length = 4
Bank 0
2. Same bank, different ROW address: When the ROW address changes on same bank, consecutive
read commands cannot be executed; it is necessary to separate the two read commands with a precharge
command and a bank-active command.
3. Different bank: When the bank changes, the second read can be performed after an interval of no less
than 1 clock, provided that the other bank is in the bank-active state. Even when the first command is a
burst read that is not yet finished, the data read by the second command will be valid.
READ to READ Command Interval (different bank)
CK
Command
ACTV
ACTV
READ READ
Address
Row 0
Row 1
Column A Column B
BA
Dout
out A0 out B0 out B1 out B2 out B3
Bank0
Active
Bank3 Bank0 Bank3
Active Read Read
Bank0 Bank3
Dout
Dout
CE Latency = 3
Burst Length = 4
33
This Material Copyrighted by Its Respective Manufacturer
HB52A89DB Series
Write command to Write command interval:
1. Same bank, same ROW address: When another write command is executed at the same ROW
address of the same bank as the preceding write command, the second write can be performed after an
interval of no less than 1 clock. In the case of burst writes, the second write command has priority.
WRITE to WRITE Command Interval (same ROW address in same bank)
CK
Command
Address
ACTV
Row
WRIT
WRIT
Column A Column B
BA
Din
in A0
Bank0
Active
in B0
in B1
in B2
in B3
Burst Write Mode
Burst Length = 4
Bank 0
Column =A Column =B
Write
Write
2. Same bank, different ROW address: When the ROW address changes, consecutive write commands
cannot be executed; it is necessary to separate the two write commands with a precharge command and a
bank-active command.
3. Different bank: When the bank changes, the second write can be performed after an interval of no less
than 1 clock, provided that the other bank is in the bank-active state. In the case of burst write, the second
write command has priority.
WRITE to WRITE Command Interval (different bank)
CK
Command
ACTV
Address
Row 0
ACTV WRIT
Row 1
WRIT
Column A Column B
BA
Din
in A0
Bank0
Active
in B0
Bank3 Bank0 Bank3
Active Write Write
34
This Material Copyrighted by Its Respective Manufacturer
in B1
in B2
in B3
Burst Write Mode
Burst Length = 4
HB52A89DB Series
Read command to Write command interval:
1. Same bank, same ROW address: When the write command is executed at the same ROW address of
the same bank as the preceding read command, the write command can be performed after an interval of no
less than 1 clock. However, DQMB must be set High so that the output buffer becomes High-Z before data
input.
READ to WRITE Command Interval (1)
CK
Command
READ WRIT
CL=2
DQMB
CL=3
in B0
Din
in B1
in B2
in B3
Burst Length = 4
Burst write
High-Z
Dout
READ to WRITE Command Interval (2)
CK
Command
DQMB
CL=2
Dout
CL=3
READ
WRIT
2 clock
High-Z
High-Z
Din
2. Same bank, different ROW address: When the ROW address changes, consecutive write commands
cannot be executed; it is necessary to separate the two commands with a precharge command and a bankactive command.
3. Different bank: When the bank changes, the write command can be performed after an interval of no
less than 1 clock, provided that the other bank is in the bank-active state. However, DQMB must be set
High so that the output buffer becomes High-Z before data input.
35
This Material Copyrighted by Its Respective Manufacturer
HB52A89DB Series
Write command to Read command interval:
1. Same bank, same ROW address: When the read command is executed at the same ROW address of
the same bank as the preceding write command, the read command can be performed after an interval of no
less than 1 clock. However, in the case of a burst write, data will continue to be written until one cycle
before the read command is executed.
WRITE to READ Command Interval (1)
CK
Command
WRIT
READ
DQMB
Din
in A0
Dout
out B0
Column = A
Write
Column = B
Read
out B1
out B2
out B3
Burst Write Mode
CE Latency = 2
Burst Length = 4
Bank 0
CE Latency
Column = B
Dout
WRITE to READ Command Interval (2)
CK
Command
WRIT
READ
DQMB
Din
in A0
in A1
Dout
out B0
Column = A
Write
out B1
CE Latency
Column = B
Read
Column = B
Dout
out B2
out B3
Burst Write Mode
CE Latency = 2
Burst Length = 4
Bank 0
2. Same bank, different ROW address: When the ROW address changes, consecutive read commands
cannot be executed; it is necessary to separate the two commands with a precharge command and a bankactive command.
3. Different bank: When the bank changes, the read command can be performed after an interval of no
less than 1 clock, provided that the other bank is in the bank-active state. However, in the case of a burst
write, data will continue to be written until one clock before the read command is executed (as in the case
of the same bank and the same address).
Read command to Precharge command interval (same bank): When the precharge command is
executed for the same bank as the read command that preceded it, the minimum interval between the two
36
This Material Copyrighted by Its Respective Manufacturer
HB52A89DB Series
commands is one clock. However, since the output buffer then becomes High-Z after the clocks defined by
IHZP, there is a case of interruption to burst read data output will be interrupted, if the precharge command is
input during burst read. To read all data by burst read, the clocks defined by I EP must be assured as an
interval from the final data output to precharge command execution.
READ to PRECHARGE Command Interval (same bank): To output all data
CE Latency = 2, Burst Length = 4
CK
Command
PRE/PALL
READ
Dout
out A0
out A1
CL=2
out A2
out A3
l EP = -1 cycle
CE Latency = 3, Burst Length = 4
CK
Command
READ
PRE/PALL
Dout
out A0
CL=3
out A1
out A2
out A3
l EP = -2 cycle
37
This Material Copyrighted by Its Respective Manufacturer
HB52A89DB Series
READ to PRECHARGE Command Interval (same bank): To stop output data
CE Latency = 2, Burst Length = 1, 2, 4, 8, full pqge burst
CK
Command
READ
PRE/PALL
Dout
out A0
High-Z
lHZP = 2
CE Latency = 3, Burst Length = 1, 2, 4, 8, full pqge burst
CK
Command
READ
PRE/PALL
Dout
out A0
lHZP = 3
38
This Material Copyrighted by Its Respective Manufacturer
High-Z
HB52A89DB Series
Write command to Precharge command interval (same bank): When the precharge command is
executed for the same bank as the write command that preceded it, the minimum interval between the two
commands is 1 clock. However, if the burst write operation is unfinished, the input data must be masked
by means of DQMB for assurance of the clock defined by tDPL.
WRITE to PRECHARGE Command Interval (same bank)
Burst Length = 4 (To stop write operation)
CK
Command
WRIT
PRE/PALL
DQMB
Din
tDPL
CK
Command
PRE/PALL
WRIT
DQMB
Din
in A0
in A1
tDPL
Burst Length = 4 (To write all data)
CK
Command
PRE/PALL
WRIT
DQMB
Din
in A0
in A1
in A2
in A3
tDPL
39
This Material Copyrighted by Its Respective Manufacturer
HB52A89DB Series
Bank active command interval:
1. Same bank: The interval between the two bank-active commands must be no less than tRC.
Bank active to bank active for same bank
CK
Command
ACTV
ACTV
Address
ROW
ROW
BA
t RC
Bank 0
Active
Bank 0
Active
2. In the case of different bank-active commands: The interval between the two bank-active commands
must be no less than tRRD.
Bank active to bank active for different bank
CK
Command
Address
ACTV
ACTV
ROW:0
ROW:1
BA
t RRD
Bank 0
Active
40
This Material Copyrighted by Its Respective Manufacturer
Bank 3
Active
HB52A89DB Series
Mode register set to Bank-active command interval: The interval between setting the mode register and
executing a bank-active command must be no less than lRSA .
CK
Command
Address
MRS
ACTV
CODE
BS & ROW
I RSA
Mode
Register Set
Bank
Active
41
This Material Copyrighted by Its Respective Manufacturer
HB52A89DB Series
DQMB Control
The DQMB mask the lower and upper bytes of the DQ data, respectively. The timing of DQMB is
different during reading and writing.
Reading: When data is read, the output buffer can be controlled by DQMB. By setting DQMB to Low,
the output buffer becomes Low-Z, enabling data output. By setting DQMB to High, the output buffer
becomes High-Z, and the corresponding data is not output. However, internal reading operations continue.
The latency of DQMB during reading is 2 clocks.
CK
DQMB
Dout
High-Z
out 0
out 1
out 3
lDOD = 2 Latency
Writing: Input data can be masked by DQMB. By setting DQMB to Low, data can be written. In
addition, when DQMB is set to High, the corresponding data is not written, and the previous data is held.
The latency of DQMB during writing is 0 clock.
CK
DQMB
Din
in 0
in 3
in 1
l DID = 0 Latency
42
This Material Copyrighted by Its Respective Manufacturer
HB52A89DB Series
Refresh
Auto-refresh: All the banks must be precharged before executing an auto-refresh command. Since the
auto-refresh command updates the internal counter every time it is executed and determines the banks and
the ROW addresses to be refreshed, external address specification is not required. The refresh cycle is
4096 cycles/64 ms. (4096 cycles are required to refresh all the ROW addresses.) The output buffer
becomes High-Z after auto-refresh start. In addition, since a precharge has been completed by an internal
operation after the auto-refresh, an additional precharge operation by the precharge command is not
required.
Self-refresh: After executing a self-refresh command, the self-refresh operation continues while CKE is
held Low. During self-refresh operation, all ROW addresses are refreshed by the internal refresh timer. A
self-refresh is terminated by a self-refresh exit command. Before and after self-refresh mode, execute autorefresh to all refresh addresses in or within 64 ms period on the condition (1) and (2) below.
(1) Enter self-refresh mode within 15.6 µs after either burst refresh or distributed refresh at equal interval
to all refresh addresses are completed.
(2) Start burst refresh or distributed refresh at equal interval to all refresh addresses within 15.6 µs after
exiting from self-refresh mode.
Others
Power-down mode: The SDRAM module enters power-down mode when CKE goes Low in the IDLE
state. In power down mode, power consumption is suppressed by deactivating the input initial circuit.
Power down mode continues while CKE is held Low. In addition, by setting CKE to High, the SDRAM
module exits from the power down mode, and command input is enabled from the next clock. In this
mode, internal refresh is not performed.
Clock suspend mode: By driving CKE to Low during a bank-active or read/write operation, the SDRAM
module enters clock suspend mode. During clock suspend mode, external input signals are ignored and the
internal state is maintained. When CKE is driven High, the SDRAM module terminates clock suspend
mode, and command input is enabled from the next clock. For details, refer to the “CKE Truth Table”.
Power-up sequence: The SDRAM module should be initialized by the following sequence with power up.
The CK, CKE, S, DQMB and DQ pins keep low till power stabilizes.
The CK pin is stabilized within 100 µs after power stabilizes before the following initialization sequence.
The CKE and DQMB is driven to high between power stabilizes and the initialization sequence.
This SDRAM module has VCC clamp diodes for CK, CKE, S DQMB and DQ pins. If these pins go high
before power up, the large current flows from these pins to VCC through the diodes.
Initialization sequence: When 200 µs or more has past after the above power on, all banks must be
precharged using the precharge command (PALL). After tRP delay, set 8 or more auto refresh commands
(REF). Set the mode register set command (MRS) to initialize the mode register. We recommend that by
keeping DQM, DQMU/DQML to High, the output buffer becomes High-Z during Initialization sequence,
to avoid DQ bus contention on memory system formed with a number of device.
43
This Material Copyrighted by Its Respective Manufacturer
HB52A89DB Series
Initialization sequence
Power up sequence
100 µs
VCC
0V
CKE, DQMB
Low
CK
Low
S, DQ
Low
Power stabilize
44
This Material Copyrighted by Its Respective Manufacturer
200 µs
HB52A89DB Series
Timing Waveforms
Read Cycle
t CK
t CKH t CKL
CK
t RC
VIH
CKE
t RAS
t
t RCD
t CS t CH
t CS t CH
RP
t CS t CH
t CS t CH
t CS t CH
t CS t CH
t CS t CH
t CS t CH
S
t CS t CH
t CS t CH
RE
t CS t CH
t CS t CH
CE
t CS t CH
t CS t CH
t AS t AH
t AS t AH
t AS t AH
t AS t AH
t AS t AH
t CS t CH
t CS t CH
W
t AS t AH
BA
t AS t AH
t AS t AH
A10
t AS t AH
t AS t AH
t AS t AH
Address
t CH
t CS
DQMB
Din
t AC
Dout
t AC
t AC
t HZ
t AC
Bank 0
Active
Bank 0
Read
t LZ
t OH
t OH
t OH
Bank 0
Precharge
t OH
CE latency = 2
Burst length = 4
Bank 0 access
= VIH or VIL
45
This Material Copyrighted by Its Respective Manufacturer
HB52A89DB Series
Write Cycle
t CK
t CKH t CKL
CK
t RC
VIH
CKE
t RAS
t RCD
t CS t CH
t RP
t CS t CH
t CS t CH
t CS t CH
t CS t CH
t CS t CH
t CS t CH
t CS t CH
S
t CS t CH
t CS t CH
RE
t CS t CH
t CS t CH
CE
t CS t CH
t CS t CH
t CS t CH
t AS t AH
t AS t AH
t AS t AH
t AS t AH
t CS t CH
W
t AS t AH
t AS t AH
BA
t AS t AH
t AS t AH
A10
t AS t AH
t AS t AH
t AS t AH
Address
t CS
t CH
DQMB
t DS t DH tDS
t DH t DS t DH t DS
t DH
Din
t DPL
Dout
Bank 0
Active
46
This Material Copyrighted by Its Respective Manufacturer
Bank 0
Write
Bank 0
Precharge
CE latency = 2
Burst length = 4
Bank 0 access
= VIH or VIL
HB52A89DB Series
Mode Register Set Cycle
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
b+3
b’
b’+1
b’+2
b’+3
18
CK
CKE
VIH
S
RE
CE
W
BA
Address
code R: b
valid
C: b’
C: b
DQMB
Dout
b
High-Z
Din
l RSA
l RP
Precharge
If needed
Mode
Bank 3
register Active
Set
l RCD
Output mask
Bank 3
Read
l RCD = 3
CE latency = 3
Burst length = 4
= VIH or VIL
47
This Material Copyrighted by Its Respective Manufacturer
HB52A89DB Series
Read Cycle/Write Cycle
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
CK
CKE
VIH
Read cycle
RE-CE delay = 3
CE latency = 3
Burst length = 4
= VIH or VIL
S
RE
CE
W
BA
Address
R:a
C:a
R:b
C:b
C:b'
C:b"
DQMB
Dout
Din
CKE
a
a+1 a+2 a+3
b
b+1 b+2 b+3 b'
b'+1 b"
b"+1 b"+2 b"+3
High-Z
Bank 0
Active
Bank 0
Read
Bank 3
Active
Bank 3 Bank 0
Read
Precharge
Bank 3
Read
Bank 3
Read
Bank 3
Precharge
VIH
Write cycle
RE-CE delay = 3
CE latency = 3
Burst length = 4
= VIH or VIL
S
RE
CE
W
BA
Address
R:a
C:a
R:b
C:b
C:b'
C:b"
DQMB
High-Z
Dout
Din
a
Bank 0
Active
a+1 a+2 a+3
Bank 0
Write
48
This Material Copyrighted by Its Respective Manufacturer
Bank 3
Active
b
Bank 3
Write
b+1 b+2 b+3 b'
Bank 0
Precharge
Bank 3
Write
b'+1 b"
Bank 3
Write
b"+1 b"+2 b"+3
Bank 3
Precharge
HB52A89DB Series
Read/Single Write Cycle
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
CK
CKE
VIH
S
RE
CE
W
BA
R:a
Address
C:a
R:b
C:a' C:a
DQMB
a
Din
Dout
a
Bank 0
Active
CKE
Bank 0
Read
Bank 3
Active
C:a
R:b
a+1 a+2 a+3
a
Bank 0 Bank 0
Write
Read
a+1 a+2 a+3
Bank 0
Precharge
Bank 3
Precharge
VIH
S
RE
CE
W
BA
Address
R:a
C:a
C:b C:c
a
b
DQMB
Din
Dout
a
Bank 0
Active
Bank 0
Read
Bank 3
Active
a+1
c
a+3
Bank 0
Write
Bank 0 Bank 0
Write
Write
Bank 0
Precharge
Read/Single write
RE, CE delay = 3
CE latency = 3
Burst length = 4
= VIH or VIL
49
This Material Copyrighted by Its Respective Manufacturer
HB52A89DB Series
Read/Burst Write Cycle
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
0
CK
CKE
S
RE
CE
W
BA
R:a
Address
C:a
R:b
C:a'
DQMB
a
Din
Dout
a
Bank 0
Active
CKE
Bank 0
Read
Bank 3
Active
C:a
R:b
a+1 a+2 a+3
a+1 a+2 a+3
Clock
suspend
Bank 0
Write
Bank 0
Precharge
Bank 3
Precharge
VIH
S
RE
CE
W
BA
Address
R:a
C:a
DQMB
a
Din
Dout
a
Bank 0
Active
Bank 0
Read
Bank 3
Active
a+1
a+1 a+2 a+3
a+3
Bank 0
Write
Bank 0
Precharge
Read/Burst write
RE, CE delay = 3
CE latency = 3
Burst length = 4
= VIH or VIL
50
This Material Copyrighted by Its Respective Manufacturer
HB52A89DB Series
Full Page Read/Write Cycle
CK
CKE
VIH
Read cycle
RE, CE delay = 3
CE latency = 3
Burst length = full page
= VIH or VIL
S
RE
CE
W
BA
Address
R:a
C:a
R:b
DQMB
Dout
Din
CKE
a
a+1
a+2
a+3
High-Z
Bank 0
Active
Bank 0
Read
Bank 3
Active
Burst stop
VIH
Write cycle
RE, CE delay = 3
CE latency = 3
Burst length = full page
= VIH or VIL
S
RE
CE
W
BA
Address
Bank 3
Precharge
R:a
C:a
R:b
DQMB
High-Z
Dout
Din
a
Bank 0
Active
a+1
Bank 0
Write
a+2
Bank 3
Active
a+3
a+4
a+5
a+6
Burst stop
Bank 3
Precharge
51
This Material Copyrighted by Its Respective Manufacturer
HB52A89DB Series
Auto Refresh Cycle
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
CK
CKE
VIH
S
RE
CE
W
BA
Address
C:a
R:a
A10=1
DQMB
Din
a
High-Z
Dout
t RC
t RP
Auto Refresh
Precharge
If needed
a+1
tRC
Read
Bank 0
Active
Bank 0
Auto Refresh
Refresh cycle and
Read cycle
RE, CE delay = 2
CE latency = 2
Burst length = 4
= VIH or VIL
Self Refresh Cycle
CK
l SREX
CKE Low
CKE
S
RE
CE
W
BA
Address
A10=1
DQMB
Din
High-Z
Dout
tRP
Precharge command
If needed
tRC
tRC
Self refresh entry
command
52
This Material Copyrighted by Its Respective Manufacturer
Self refresh exit
ignore command
or No operation
Next
clock
enable
Self refresh entry
command
Auto
Next
clock refresh
enable
Self refresh cycle
RE, CE delay = 3
CE latency = 3
Burst length = 4
= VIH or VIL
HB52A89DB Series
Clock Suspend Mode
t CES
0
1
2
3
4
5
t CES
t CEH
6
7
8
9
10
11
12
13
14
15
16
17
CK
CKE
RE
CE
W
BA
R:a
C:a
R:b
C:b
DQMB
Dout
a
a+1 a+2
a+3
b
High-Z
Din
Bank0 Active clock
Active suspend start
Active clock Bank0
suspend end Read
Bank3
Active
Read suspend
start
Read suspend
end
Bank3
Read
Bank0
Precharge
CKE
20
21
b+1 b+2 b+3
Earliest Bank3
Precharge
Write cycle
RE, CE delay = 2
CE latency = 2
Burst length = 4
= VIH or VIL
S
RE
CE
W
BA
Address
19
Read cycle
RE, CE delay = 2
CE latency = 2
Burst length = 4
= VIH or VIL
S
Address
18
C:a R:b
R:a
C:b
DQMB
High-Z
Dout
Din
a
Bank0
Active
Active clock
suspend start
a+1 a+2
Active clock Bank0 Bank3
supend end Write Active
Write suspend
start
a+3 b
Write suspend
end
b+1 b+2 b+3
Bank3 Bank0
Write Precharge
Earliest Bank3
Precharge
53
This Material Copyrighted by Its Respective Manufacturer
HB52A89DB Series
Power Down Mode
CK
CKE Low
CKE
S
RE
CE
W
BA
Address
R: a
A10=1
DQMB
Din
High-Z
Dout
tRP
Power down entry
Precharge command
If needed
Power down cycle
RE, CE delay = 3
CE latency = 3
Burst length = 4
= VIH or VIL
Power down
mode exit
Active Bank 0
Initialization Sequence
0
1
2
3
4
5
6
7
8
9
10
48
49
50
51
52
53
54
CK
CKE
VIH
S
RE
CE
W
DQMB
code
valid
Address
Valid
VIH
High-Z
DQ
t RP
All banks
Precharge
54
This Material Copyrighted by Its Respective Manufacturer
t RC
Auto Refresh
t RSA
tRC
Auto Refresh
Mode register
Set
Bank active
If needed
55
HB52A89DB Series
Physical Outline
Unit: mm
inch
67.60
2.661
3.80Max.
0.150Max.
(Datum -A-)
A
1.00 ± 0.10
0.039 ± 0.004
4.60
0.181 32.80
1.291
Component area
(back)
2-R2.00
2-R0.079
4.00 ± 0.10
0.157 ± 0.004
4.60
0.181
32.80
1.291
2
3.70
0.146
B
144
23.20
0.913
2.50
0.098
2.10
0.083
23.20
0.913
3.30
0.130
4.00Min.
0.157Min.
20.00
0.787
1
143
26.67
1.050
Component area
(front)
3.20Min.
0.126Min.
2R3.00Min
2R0.118Min.
2.00Min.
0.079Min.
(Datum -A-)
Detail B
Detail A
(DATUM -A-)
2.5
0.098
0.80
0.031
R0.75
R0.030
4.00 ± 0.10
0.157 ± 0.004
2.55
0.100
0.25 Max.
0.010 Max.
0.60 ± 0.05
0.024 ± 0.002
1.50 ± 0.10
0.059 ± 0.004
55
This Material Copyrighted by Its Respective Manufacturer
HB52A89DB Series
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent,
copyright, trademark, or other intellectual property rights for information contained in this document.
Hitachi bears no responsibility for problems that may arise with third party’s rights, including
intellectual property rights, in connection with use of the information contained in this document.
2. Products and product specifications may be subject to change without notice. Confirm that you have
received the latest product standards or specifications before final design, purchase or use.
3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However,
contact Hitachi’s sales office before using the product in an application that demands especially high
quality and reliability or where its failure or malfunction may directly threaten human life or cause risk
of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation,
traffic, safety equipment or medical equipment for life support.
4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly
for maximum rating, operating supply voltage range, heat radiation characteristics, installation
conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used
beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable
failure rates or failure modes in semiconductor devices and employ systemic measures such as failsafes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other
consequential damage due to operation of the Hitachi product.
5. This product is not designed to be radiation resistant.
6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without
written approval from Hitachi.
7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi semiconductor
products.
Hitachi, Ltd.
Semiconductor & IC Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109
URL
NorthAmerica
: http:semiconductor.hitachi.com/
Europe
: http://www.hitachi-eu.com/hel/ecg
Asia (Singapore) : http://www.has.hitachi.com.sg/grp3/sicd/index.htm
Asia (Taiwan)
: http://www.hitachi.com.tw/E/Product/SICD_Frame.htm
Asia (HongKong) : http://www.hitachi.com.hk/eng/bo/grp3/index.htm
Japan
: http://www.hitachi.co.jp/Sicd/indx.htm
For further information write to:
Hitachi Semiconductor
(America) Inc.
2000 Sierra Point Parkway
Brisbane, CA 94005-1897
Tel: <1> (800) 285-1601
Fax: <1> (303) 297-0447
Hitachi Europe GmbH
Electronic components Group
Dornacher Straße 3
D-85622 Feldkirchen, Munich
Germany
Tel: <49> (89) 9 9180-0
Fax: <49> (89) 9 29 30 00
Hitachi Europe Ltd.
Electronic Components Group.
Whitebrook Park
Lower Cookham Road
Maidenhead
Berkshire SL6 8YA, United Kingdom
Tel: <44> (1628) 585000
Fax: <44> (1628) 778322
Hitachi Asia Pte. Ltd.
16 Collyer Quay #20-00
Hitachi Tower
Singapore 049318
Tel: 535-2100
Fax: 535-1533
Hitachi Asia Ltd.
Taipei Branch Office
3F, Hung Kuo Building. No.167,
Tun-Hwa North Road, Taipei (105)
Tel: <886> (2) 2718-3666
Fax: <886> (2) 2718-8180
Hitachi Asia (Hong Kong) Ltd.
Group III (Electronic Components)
7/F., North Tower, World Finance Centre,
Harbour City, Canton Road, Tsim Sha Tsui,
Kowloon, Hong Kong
Tel: <852> (2) 735 9218
Fax: <852> (2) 730 0281
Telex: 40815 HITEC HX
Copyright © Hitachi, Ltd., 1998. All rights reserved. Printed in Japan.
56
This Material Copyrighted by Its Respective Manufacturer
HB52A89DB Series
Revision Record
Rev. Date
Contents of Modification
Drawn by
0.0
Jul. 16, 1998
Initial issue
T.Sato
(referred to HM5264165/HM5264805/HM5264405 Series
rev 1.0 and HM5212165/HM5212805 Series rev 0.1)
1.0
Oct. 15, 1998 AC Characteristics
Relationship Between Frequency and Minimum Latency
IRP: 3 to 2
Approved by
K.Tsuneda
DC Characteristics
I CC1(CL = 3): TBD to 630
I CC4(CL = 3): TBD to 1080
(referred to HM5264165/805/405 Series rev 1.0
and HM5212165/805 Series rev 1.0)
57
This Material Copyrighted by Its Respective Manufacturer