ETC HB52RD328DC-B6F

HB52RD328DC-F
256 MB Unbuffered SDRAM S.O.DIMM
32-Mword × 64-bit, 100 MHz Memory Bus, 2-Bank Module
(32 pcs of 16 M × 4 components)
PC100 SDRAM
ADE-203-1044B (Z)
Rev. 1.0
Jan. 18, 2000
Description
The HB52RD328DC is a 16M × 64 × 2 banks Synchronous Dynamic RAM Small Outline Dual In-line
Memory Module (S.O.DIMM), mounted 32 pieces of 64-Mbit SDRAM (HM5264405FTB) sealed in TCP
package and 1 piece of serial EEPROM (2-kbit EEPROM) for Presence Detect (PD). An outline of the
product is 144-pin Zig Zag Dual tabs socket type compact and thin package. Therefore, it makes high density
mounting possible without surface mount technology. It provides common data inputs and outputs.
Decoupling capacitors are mounted beside TCP on the module board.
Note: Do not push the cover or drop the modules in order to protect from mechanical defects, which would
be electrical defects.
Features
• Fully compatible with : JEDEC standard outline 8-byte S.O.DIMM
• 144-pin Zig Zag Dual tabs socket type (dual lead out)
 Outline: 67.60 mm (Length) × 31.75 mm (Height) × 3.80 mm (Thickness)
 Lead pitch: 0.80 mm
• 3.3 V power supply
• Clock frequency: 100 MHz (max)
• LVTTL interface
• Data bus width: × 64 Non parity
• Single pulsed RAS
• 4 Banks can operates simultaneously and independently
• Burst read/write operation and burst read/single write operation capability
• Programmable burst length : 1/2/4/8/full page
This Material Copyrighted by Its Respective Manufacturer
HB52RD328DC-F
• 2 variations of burst sequence
 Sequential (BL = 1/2/4/8/full page)
 interleave (BL = 1/2/4/8)
• Programmable CE latency : 2/3 (HB52RD328DC-A6F/A6FL)
: 3 (HB52RD328DC-B6F/B6FL)
• Byte control by DQMB
• Refresh cycles: 4096 refresh cycles/64 ms
• 2 variations of refresh
 Auto refresh
 Self refresh
• Low self refresh current: HB52RD328DC-A6FL/B6FL (L-version)
• Full page burst length capability
 Sequential burst
 Burst stop capability
Ordering Information
Type No.
Frequency
CE latency
Package
Contact pad
HB52RD328DC-A6F
HB52RD328DC-B6F
HB52RD328DC-A6FL
HB52RD328DC-B6FL
100 MHz
100 MHz
100 MHz
100 MHz
2/3
3
2/3
3
Small outline DIMM (144-pin)
Gold
2 Material Copyrighted by Its Respective Manufacturer
This
HB52RD328DC-F
Pin Arrangement
Front Side
1pin
59pin
61pin
143pin
2pin
60pin
62pin
144pin
Back Side
Front side
Back side
Pin No.
Signal name Pin No.
Signal name Pin No.
Signal name Pin No.
Signal name
1
VSS
73
NC
2
VSS
74
CK1
3
DQ0
75
VSS
4
DQ32
76
VSS
5
DQ1
77
NC
6
DQ33
78
NC
7
DQ2
79
NC
8
DQ34
80
NC
9
DQ3
81
VCC
10
DQ35
82
VCC
11
VCC
83
DQ16
12
VCC
84
DQ48
13
DQ4
85
DQ17
14
DQ36
86
DQ49
15
DQ5
87
DQ18
16
DQ37
88
DQ50
17
DQ6
89
DQ19
18
DQ38
90
DQ51
19
DQ7
91
VSS
20
DQ39
92
VSS
21
VSS
93
DQ20
22
VSS
94
DQ52
23
DQMB0
95
DQ21
24
DQMB4
96
DQ53
25
DQMB1
97
DQ22
26
DQMB5
98
DQ54
27
VCC
99
DQ23
28
VCC
100
DQ55
29
A0
101
VCC
30
A3
102
VCC
31
A1
103
A6
32
A4
104
A7
33
A2
105
A8
34
A5
106
A13 (BA0)
35
VSS
107
VSS
36
VSS
108
VSS
37
DQ8
109
A9
38
DQ40
110
A12 (BA1)
39
DQ9
111
A10 (AP)
40
DQ41
112
A11
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3
HB52RD328DC-F
Front side
Back side
Pin No.
Signal name Pin No.
Signal name Pin No.
Signal name Pin No.
Signal name
41
DQ10
113
VCC
42
DQ42
114
VCC
43
DQ11
115
DQMB2
44
DQ43
116
DQMB6
45
VCC
117
DQMB3
46
VCC
118
DQMB7
47
DQ12
119
VSS
48
DQ44
120
VSS
49
DQ13
121
DQ24
50
DQ45
122
DQ56
51
DQ14
123
DQ25
52
DQ46
124
DQ57
53
DQ15
125
DQ26
54
DQ47
126
DQ58
55
VSS
127
DQ27
56
VSS
128
DQ59
57
NC
129
VCC
58
NC
130
VCC
59
NC
131
DQ28
60
NC
132
DQ60
61
CK0
133
DQ29
62
CKE0
134
DQ61
63
VCC
135
DQ30
64
VCC
136
DQ62
65
RE
137
DQ31
66
CE
138
DQ63
67
W
139
VSS
68
CKE1
140
VSS
69
S0
141
SDA
70
NC
142
SCL
71
S1
143
VCC
72
NC
144
VCC
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This
HB52RD328DC-F
Pin Description
Pin name
Function
A0 to A11
Address input
 Row address
A0 to A11
 Column address
A0 to A9
A12/A13
Bank select address
DQ0 to DQ63
Data-input/output
S0/S1
Chip select
RE
Row address asserted bank enable
CE
Column address asserted
W
Write enable
DQMB0 to DQMB7
Byte input/output mask
CK0/CK1
Clock input
CKE0/CKE1
Clock enable
SDA
Data-input/output for serial PD
SCL
Clock input for serial PD
VCC
Power supply
VSS
Ground
NC
No connection
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BA1, BA0
5
HB52RD328DC-F
Serial PD Matrix*1
Byte No. Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments
0
Number of bytes used by
module manufacturer
1
0
0
0
0
0
0
0
80
128
1
Total SPD memory size
0
0
0
0
1
0
0
0
08
256 byte
2
Memory type
0
0
0
0
0
1
0
0
04
SDRAM
3
Number of row addresses bits 0
0
0
0
1
1
0
0
0C
12
4
Number of column addresses
bits
0
0
0
0
1
0
1
0
0A
10
5
Number of banks
0
0
0
0
0
0
1
0
02
2
6
Module data width
0
1
0
0
0
0
0
0
40
64
7
Module data width (continued) 0
0
0
0
0
0
0
0
00
0 (+)
8
Module interface signal levels 0
0
0
0
0
0
0
1
01
LVTTL
9
SDRAM cycle time
(highest CE latency)
10 ns
1
0
1
0
0
0
0
0
A0
CL = 3
*7
10
SDRAM access from Clock
(highest CE latency)
6 ns
0
1
1
0
0
0
0
0
60
CL = 3
*7
11
Module configuration type
0
0
0
0
0
0
0
0
00
Non parity
12
Refresh rate/type
1
0
0
0
0
0
0
0
80
Normal
(15.625 µs)
Self refresh
13
SDRAM width
0
0
0
0
0
1
0
0
04
16M × 4
14
Error checking SDRAM width
0
0
0
0
0
0
0
0
00
—
15
0
SDRAM device attributes:
minimum clock delay for backto-back random column
addresses
0
0
0
0
0
0
1
01
1 CLK
16
SDRAM device attributes:
Burst lengths supported
1
0
0
0
1
1
1
1
8F
1, 2, 4, 8, full
page
17
SDRAM device attributes:
number of banks on SDRAM
device
0
0
0
0
0
1
0
0
04
4
18
SDRAM device attributes:
CE latency
0
0
0
0
0
1
1
0
06
2, 3
19
SDRAM device attributes:
S latency
0
0
0
0
0
0
0
1
01
0
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This
HB52RD328DC-F
Byte No. Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments
20
SDRAM device attributes:
W latency
0
0
0
0
0
0
0
1
01
0
21
SDRAM module attributes
0
0
0
0
0
0
0
0
00
Non buffer
22
SDRAM device attributes:
General
0
0
0
0
1
1
1
0
0E
VCC ± 10%
23
SDRAM cycle time
(2nd highest CE latency)
(-A6F/A6FL) 10 ns
1
0
1
0
0
0
0
0
A0
CL = 2
*7
1
1
1
1
0
0
0
0
F0
0
1
1
0
0
0
0
0
60
1
0
0
0
0
0
0
0
80
(-B6F/B6FL) 15 ns
24
SDRAM access from Clock
(2nd highest CE latency)
(-A6F/A6FL) 6 ns
(-B6F/B6FL) 8 ns
CL = 2
*7
25
SDRAM cycle time
(3rd highest CE latency)
Undefined
0
0
0
0
0
0
0
0
00
26
SDRAM access from Clock
(3rd highest CE latency)
Undefined
0
0
0
0
0
0
0
0
00
27
Minimum row precharge time
0
0
0
1
0
1
0
0
14
20 ns
28
Row active to row active min
0
0
0
1
0
1
0
0
14
20 ns
29
RE to CE delay min
0
0
0
1
0
1
0
0
14
20 ns
30
Minimum RE pulse width
0
0
1
1
0
0
1
0
32
50 ns
31
Density of each bank on
module
0
0
1
0
0
0
0
0
20
2 bank
128M byte
32
Address and command signal 0
input setup time
0
1
0
0
0
0
0
20
2 ns* 7
33
Address and command signal 0
input hold time
0
0
1
0
0
0
0
10
1 ns* 7
34
Data signal input setup time
0
0
1
0
0
0
0
0
20
2 ns* 7
35
Data signal input hold time
0
0
0
1
0
0
0
0
10
1 ns* 7
36 to 61 Superset information
0
0
0
0
0
0
0
0
00
Future use
62
SPD data revision code
0
0
0
1
0
0
1
0
12
Rev. 1.2A
63
Checksum for bytes 0 to 62
(-A6F/A6FL)
0
0
0
1
0
0
1
1
13
19
1
0
0
0
0
0
1
1
83
131
Manuf act urer’s JEDEC ID c ode
0
0
0
0
0
1
1
1
07
HITACHI
65 to 71 Manuf act urer’s JEDEC ID c ode
0
0
0
0
0
0
0
0
00
(-B6F/B6FL)
64
This Material Copyrighted by Its Respective Manufacturer
7
HB52RD328DC-F
Byte No. Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments
72
Manufacturing location
×
×
×
×
×
×
×
×
××
* 3 (ASCII8bit code)
73
Manufacturer’s part number
0
1
0
0
1
0
0
0
48
H
74
Manufacturer’s part number
0
1
0
0
0
0
1
0
42
B
75
Manufacturer’s part number
0
0
1
1
0
1
0
1
35
5
76
Manufacturer’s part number
0
0
1
1
0
0
1
0
32
2
77
Manufacturer’s part number
0
1
0
1
0
0
1
0
52
R
78
Manufacturer’s part number
0
1
0
0
0
1
0
0
44
D
79
Manufacturer’s part number
0
0
1
1
0
0
1
1
33
3
80
Manufacturer’s part number
0
0
1
1
0
0
1
0
32
2
81
Manufacturer’s part number
0
0
1
1
1
0
0
0
38
8
82
Manufacturer’s part number
0
1
0
0
0
1
0
0
44
D
83
Manufacturer’s part number
0
1
0
0
0
0
1
1
43
C
84
Manufacturer’s part number
0
0
1
0
1
1
0
1
2D
—
85
Manufacturer’s part number
(-A6D/A6DL)
0
1
0
0
0
0
0
1
41
A
0
1
0
0
0
0
1
0
42
B
(-B6D/B6DL)
86
Manufacturer’s part number
0
0
1
1
0
1
1
0
36
6
87
Manufacturer’s part number
0
1
0
0
0
1
1
0
46
F
88
Manufacturer’s part number
(L-version)
0
1
0
0
1
1
0
0
4C
L
Manufacturer’s part number
0
0
1
0
0
0
0
0
20
(Space)
89
Manufacturer’s part number
0
0
1
0
0
0
0
0
20
(Space)
90
Manufacturer’s part number
0
0
1
0
0
0
0
0
20
(Space)
91
Revision code
0
0
1
1
0
0
0
0
30
Initial
92
Revision code
0
0
1
0
0
0
0
0
20
(Space)
93
Manufacturing date
×
×
×
×
×
×
×
×
××
Year code
(BCD)*4
94
Manufacturing date
×
×
×
×
×
×
×
×
××
Week code
(BCD)*4
95 to 98 Assembly serial number
*6
99 to 125 Manufacturer specific data
—
—
—
—
—
—
—
—
—
*5
126
Intel specification frequency
0
1
1
0
0
1
0
0
64
100 MHz
127
Intel specification CE# latency 1
support
(-A6FD/A6FDL)
1
0
0
0
1
1
1
C7
CL = 2, 3
1
0
0
0
1
0
1
C5
CL = 3
(-B6FD/B6FDL)
1
8 Material Copyrighted by Its Respective Manufacturer
This
HB52RD328DC-F
Notes: 1. All serial PD data are not protected. 0: Serial data, “driven Low”, 1: Serial data, “driven High”
These SPD are based on Intel specification (Rev.1.2A)
2. Regarding byte32 to 35, based on JEDEC Committee Ballot JC42.5-97-119.
3. Byte72 is manufacturing location code. (ex: In case of Japan, byte72 is 4AH. 4AH shows “J” on
ASCII code.)
4. Regarding byte93 and 94, based on JEDEC Committee Ballot JC42.5-97-135. BCD is “Binary
Coded Decimal”.
5. All bits of 99 through 125 are not defined (“1” or “0”).
6. Bytes 95 through 98 are assembly serial number.
7. These specifications are defined based on component specification, not module.
This Material Copyrighted by Its Respective Manufacturer
9
HB52RD328DC-F
Block Diagram
S0
S1
DQMB0
N0, N1
DQ0 to DQ7
DQMB1
CS
DQMB
CS D16
DQMB
DQMB4
I/O0 to I/O3
I/O0 to I/O3
DQ32 to DQ39
CS
DQMB
D0
DQMB2
DQMB3
N6, N7
DQ24 to DQ31
CS D17
DQMB
CS
DQMB
CS D25
DQMB
I/O0 to I/O3
I/O0 to I/O3
I/O0 to I/O3
I/O0 to I/O3
CS
DQMB
CS D18
DQMB
DQMB5
CS
DQMB
CS D26
DQMB
I/O0 to I/O3
I/O0 to I/O3
DQ40 to DQ47
CS
DQMB
D1
D2
N10, N11
CS D19
DQMB
CS
DQMB
CS D27
DQMB
I/O0 to I/O3
I/O0 to I/O3
I/O0 to I/O3
I/O0 to I/O3
CS
DQMB
CS D20
DQMB
DQMB6
CS
DQMB
CS D28
DQMB
I/O0 to I/O3
I/O0 to I/O3
DQ48 to DQ55
CS
DQMB
D3
D4
N12, N13
VCC
D12
I/O0 to I/O3
CS D21
DQMB
CS
DQMB
CS D29
DQMB
I/O0 to I/O3
I/O0 to I/O3
I/O0 to I/O3
I/O0 to I/O3
CS
DQMB
CS D22
DQMB
CS
DQMB
CS D30
DQMB
D5
D6
I/O0 to I/O3
I/O0 to I/O3
CS
DQMB
D7
DQMB7
N14, N15
D13
D14
I/O0 to I/O3
I/O0 to I/O3
CS D23
DQMB
CS
DQMB
CS D31
DQMB
I/O0 to I/O3
I/O0 to I/O3
VCC (D0 to D31)
C0 to C15
VSS
D11
I/O0 to I/O3
DQ56 to DQ63
CLK (D0 to D3, D16 to D19)
CLK (D4 to D7, D20 to D23)
CLK (D8 to D11, D24 to D27)
CLK (D12 to D15, D28 to D31)
CK1
D10
I/O0 to I/O3
RAS (D0 to D31)
CAS (D0 to D31)
A0 to A11 (D0 to D31)
BA0 (D0 to D31)
BA1 (D0 to D31)
CKE (D0 to D15)
CKE (D16 to D31)
WE (D0 to 31)
CK0
D9
I/O0 to I/O3
I/O0 to I/O3
RE
CE
A0 to A11
BA0
BA1
CKE0
CKE1
WE
CS D24
DQMB
I/O0 to I/O3
N4, N5
DQ16 to DQ23
D8
I/O0 to I/O3
N2, N3
DQ8 to DQ15
CS
DQMB
N8, N9
VSS (D0 to D31)
10 Material Copyrighted by Its Respective Manufacturer
This
D15
I/O0 to I/O3
Serial PD
SCL
SCL
A0
A1
A2
SDA
SDA
U0
Notes:
1.SDA pull-up resister is required due to
the open-drain/open-collector output.
2.SCL pull-up resistore is recommended
because of the normal SCL line inactive
"High" state.
D0 to D3: HM5264405F
U0: 2-kbit EEPROM
C0 to C15: 0.1 µF
N0 to N15: Network resistors(10 Ω)
HB52RD328DC-F
Absolute Maximum Ratings
Parameter
Symbol
Value
Unit
Note
Voltage on any pin relative to V SS
VT
–0.5 to VCC + 0.5
(≤ 4.6 (max))
V
1
Supply voltage relative to VSS
VCC
–0.5 to +4.6
V
1
Short circuit output current
Iout
50
mA
Power dissipation
PT
4.0
W
Operating temperature
Topr
0 to +65
°C
Storage temperature
Tstg
–55 to +125
°C
Note:
1. Respect to V SS .
DC Operating Conditions (Ta = 0 to +65°C)
Parameter
Symbol
Min
Max
Unit
Notes
Supply voltage
VCC
3.0
3.6
V
1, 2
VSS
0
0
V
3
Input high voltage
VIH
2.0
VCC + 0.3
V
1, 4, 5
Input low voltage
VIL
–0.3
0.8
V
1, 6
Notes: 1.
2.
3.
4.
5.
6.
All voltage referred to VSS
The supply voltage with all VCC pins must be on the same level.
The supply voltage with all VSS pins must be on the same level.
CK, CKE, S, DQMB, DQ pins: VIH (max) = VCC + 0.5 V for pulse width ≤ 5 ns at VCC.
Others: V IH (max) = 4.6 V for pulse width ≤ 5 ns at VCC.
VIL (min) = –1.0 V for pulse width ≤ 5 ns at VSS.
This Material Copyrighted by Its Respective Manufacturer
11
HB52RD328DC-F
VIL/VIH Clamp (Component characteristic)
This SDRAM component has VIL and V IH clamp for CK, CKE, S, DQMB and DQ pins.
Minimum VIL Clamp Current
VIL (V)
I (mA)
–2
–32
–1.8
–25
–1.6
–19
–1.4
–13
–1.2
–8
–1
–4
–0.9
–2
–0.8
–0.6
–0.6
0
–0.4
0
–0.2
0
0
0
0
–5
–2
–1.5
–1
I (mA)
–10
–15
–20
–25
–30
–35
VIL (V)
12 Material Copyrighted by Its Respective Manufacturer
This
–0.5
0
HB52RD328DC-F
Minimum VIH Clamp Current
VIH (V)
I (mA)
VCC + 2
10
VCC + 1.8
8
VCC + 1.6
5.5
VCC + 1.4
3.5
VCC + 1.2
1.5
VCC + 1
0.3
VCC + 0.8
0
VCC + 0.6
0
VCC + 0.4
0
VCC + 0.2
0
VCC + 0
0
10
I (mA)
8
6
4
2
0
VCC + 0
VCC + 0.5
VCC + 1
VCC + 1.5
VCC + 2
VIH (V)
This Material Copyrighted by Its Respective Manufacturer
13
HB52RD328DC-F
IOL/IOH Characteristics (Component characteristic)
Output Low Current (IOL)
I OL
I OL
Vout (V)
Min (mA)
Max (mA)
0
0
0
0.4
27
71
0.65
41
108
0.85
51
134
1
58
151
1.4
70
188
1.5
72
194
1.65
75
203
1.8
77
209
1.95
77
212
3
80
220
3.45
81
223
250
IOL (mA)
200
150
min
max
100
50
0
0
0.5
1
1.5
2
Vout (V)
14 Material Copyrighted by Its Respective Manufacturer
This
2.5
3
3.5
HB52RD328DC-F
Output High Current (I OH ) (Ta = 0 to 65˚C, V CC = 3.0 V to 3.45 V, VSS = 0 V)
I OH
I OH
Vout (V)
Min (mA)
Max (mA)
3.45
—
–3
3.3
—
–28
3
0
–75
2.6
–21
–130
2.4
–34
–154
2
–59
–197
1.8
–67
–227
1.65
–73
–248
1.5
–78
–270
1.4
–81
–285
1
–89
–345
0
–93
–503
0
0
0.5
1
1.5
2
2.5
3
3.5
IOH (mA)
–100
–200
min
max
–300
–400
–500
–600
Vout (V)
This Material Copyrighted by Its Respective Manufacturer
15
HB52RD328DC-F
DC Characteristics (Ta = 0 to 65˚C, VCC = 3.3 V ± 0.3 V, VSS = 0 V)
HB52RD328DC
-A6F/A6FL
-B6F/B6FL
Parameter
Symbol Min
Max
Test conditions
Notes
Operating current
(CE latency = 2)
I CC1
—
1248 —
1248 mA
Burst length = 1
t RC = min
1, 2, 3
(CE latency = 3)
I CC1
—
1248 —
1248 mA
Standby current in power down
I CC2P
—
48
—
48
mA
CKE = VIL,
tCK = 12 ns
6
Standby current in power down
(input signal stable)
I CC2PS
—
32
—
32
mA
CKE = VIL, t CK = ∞
7
Standby current in non power
down
I CC2N
—
320
—
320
mA
CKE, S = VIH,
t CK = 12 ns
4
Active standby current in power
down
I CC3P
—
128
—
128
mA
CKE = VIL,
tCK = 12 ns
1, 2, 6
Active standby current in non
power down
I CC3N
—
576
—
576
mA
CKE, S = VIH,
t CK = 12 ns
1, 2, 4
I CC4
—
1168 —
1168 mA
t CK = min, BL = 4
1, 2, 5
I CC4
—
1168 —
1168 mA
Refresh current
I CC5
—
2048 —
2048 mA
t RC = min
2, 3
Self refresh current
I CC6
—
32
—
32
mA
VIH ≥ VCC – 0.2 V
VIL ≤ 0.2 V
8
Self refresh current (L-version)
I CC6
—
12.8
—
12.8
mA
Input leakage current
I LI
–1
1
–1
1
µA
0 ≤ Vin ≤ VCC
Output leakage current
I LO
–1.5
1.5
–1.5
1.5
µA
0 ≤ Vout ≤ VCC
DQ = disable
Output high voltage
VOH
2.4
—
2.4
—
V
I OH = –4 mA
Output low voltage
VOL
—
0.4
—
0.4
V
I OL = 4 mA
Burst operating current
(CE latency = 2)
(CE latency = 3)
16 Material Copyrighted by Its Respective Manufacturer
This
Min
Max
Unit
HB52RD328DC-F
Notes: 1. I CC depends on output load condition when the device is selected. ICC (max) is specified at the
output open condition.
2. One bank operation.
3. Input signals are changed once per one clock.
4. Input signals are changed once per two clocks.
5. Input signals are changed once per four clocks.
6. After power down mode, CLK operating current.
7. After power down mode, no CLK operating current.
8. After self refresh mode set, self refresh current.
Capacitance (Ta = 25°C, VCC = 3.3 V ± 0.3 V)
Parameter
Symbol
Max
Unit
Notes
Input capacitance (Address)
CIN
150
pF
1, 2, 4
Input capacitance (RE, CE, W, S, CKE)
CIN
150
pF
1, 2, 4
Input capacitance (CK)
CIN
90
pF
1, 2, 4
Input capacitance (DQMB)
CIN
30
pF
1, 2, 4
Input/Output capacitance (DQ)
CI/O
30
pF
1, 2, 3, 4
Notes: 1.
2.
3.
4.
Capacitance measured with Boonton Meter or effective capacitance measuring method.
Measurement condition: f = 1 MHz, 1.4 V bias, 200 mV swing.
DQMB = VIH to disable Dout.
This parameter is sampled and not 100% tested.
This Material Copyrighted by Its Respective Manufacturer
17
HB52RD328DC-F
AC Characteristics (Ta = 0 to 65˚C, VCC = 3.3 V ± 0.3 V, VSS = 0 V)
HB52RD328DC
-A6F/A6FL
-B6F/B6FL
Parameter
HITACHI PC100
Symbol Symbol Min
Max
Min
Max
Unit
Notes
System clock cycle time
(CE latency = 2)
t CK
Tclk
10
—
15
—
ns
1
(CE latency = 3)
t CK
Tclk
10
—
10
—
ns
CK high pulse width
t CKH
Tch
4
—
4
—
ns
1
CK low pulse width
t CKL
Tcl
4
—
4
—
ns
1
Access time from CK
(CE latency = 2)
t AC
Tac
—
6
—
8
ns
1, 2
(CE latency = 3)
t AC
Tac
—
6
—
6
ns
Data-out hold time
t OH
Toh
3
—
3
—
ns
1, 2
CK to Data-out low impedance t LZ
2
—
2
—
ns
1, 2, 3
CK to Data-out high impedance t HZ
—
6
—
6
ns
1, 4
Tsi
3
—
3
—
ns
1, 5, 6
CKE setup time for power down t CESP
exit
Tpde
3
—
3
—
ns
1
Data-in hold time
t AH, t CH ,
t DH, t CEH
Thi
1
—
1
—
ns
1, 5
Ref/Active to Ref/Active
command period
t RC
Trc
70
—
70
—
ns
1
Active to Precharge command
period
t RAS
Tras
50
120000
50
120000
ns
1
Active command to column
command (same bank)
t RCD
Trcd
20
—
20
—
ns
1
Precharge to active command
period
t RP
Trp
20
—
20
—
ns
1
Write recovery or data-in to
precharge lead time
t DPL
Tdpl
10
—
10
—
ns
1
Active (a) to Active (b)
command period
t RRD
Trrd
20
—
20
—
ns
1
Transition time (rise to fall)
tT
1
5
1
5
ns
Refresh period
t REF
—
64
—
64
ms
Data-in setup time
t AS , t CS,
t DS, t CES
18 Material Copyrighted by Its Respective Manufacturer
This
HB52RD328DC-F
Notes: 1.
2.
3.
4.
5.
6.
AC measurement assumes t T = 1 ns. Reference level for timing of input signals is 1.5 V.
Access time is measured at 1.5 V. Load condition is CL = 50 pF.
t LZ (max) defines the time at which the outputs achieves the low impedance state.
t HZ (max) defines the time at which the outputs achieves the high impedance state.
t CES define CKE setup time to CK rising edge except power down exit command.
t AS /tAH: Address, tCS/tCH: S, RE, CE, W, DQMB
t DS/tDH: Data-in, tCES/tCEH: CKE
Test Conditions
• Input and output timing reference levels: 1.5 V
• Input waveform and output load: See following figures
2.4 V
input
0.4 V
I/O
2.0 V
0.8 V
CL
t
T
This Material Copyrighted by Its Respective Manufacturer
tT
19
HB52RD328DC-F
Relationship Between Frequency and Minimum Latency
HB52RD328DC
Parameter
-A6F/A6FL/B6F/B6FL
Frequency (MHz)
100
tCK (ns)
HITACHI
Symbol
PC100
Symbol
10
Notes
Active command to column command
(same bank)
lRCD
2
1
Active command to active command
(same bank)
lRC
7
= [lRAS+ lRP]
1
Active command to precharge command
(same bank)
lRAS
5
1
Precharge command to active command
(same bank)
lRP
2
1
Write recovery or data-in to precharge
command (same bank)
lDPL
1
1
Active command to active command
(different bank)
lRRD
2
1
Self refresh exit time
lSREX
Tsrx
1
2
Last data in to active command
(Auto precharge, same bank)
lAPW
Tdal
3
= [lDPL + lRP]
Self refresh exit to command input
lSEC
7
= [lRC]
3
Precharge command to high impedance
(CE latency = 2)
lHZP
Troh
2
lHZP
Troh
3
(CE latency = 3)
Last data out to active command
(auto precharge) (same bank)
Last data out to precharge (early precharge)
(CE latency = 2)
(CE latency = 3)
Tdpl
lAPR
1
lEP
–1
lEP
–2
Column command to column command
lCCD
Tccd
1
Write command to data in latency
lWCD
Tdwd
0
DQMB to data in
lDID
Tdqm
0
DQMB to data out
lDOD
Tdqz
2
CKE to CK disable
lCLE
Tcke
1
Register set to active command
lRSA
Tmrd
1
20 Material Copyrighted by Its Respective Manufacturer
This
HB52RD328DC-F
HB52RD328DC
Parameter
-A6F/A6FL/B6F/B6FL
Frequency (MHz)
100
tCK (ns)
HITACHI
Symbol
S to command disable
lCDD
0
Power down exit to command input
lPEC
1
Burst stop to output valid data hold
(CE latency = 2)
lBSR
1
lBSR
2
lBSH
2
lBSH
3
lBSW
0
(CE latency = 3)
Burst stop to output high impedance
(CE latency = 2)
(CE latency = 3)
Burst stop to write data ignore
PC100
Symbol
10
Notes
Notes: 1. lRCD to l RRD are recommended value.
2. Be valid [DSEL] or [NOP] at next command of self refresh exit.
3. Except [DSEL] and [NOP].
This Material Copyrighted by Its Respective Manufacturer
21
HB52RD328DC-F
Pin Functions
CK0/CK1 (input pin): CK is the master clock input to this pin. The other input signals are referred at CK
rising edge.
S0/S1 (input pin): When S is Low, the command input cycle becomes valid. When S is High, all inputs are
ignored. However, internal operations (bank active, burst operations, etc.) are held.
RE, CE and W (input pins): Although these pin names are the same as those of conventional DRAM
modules, they function in a different way. These pins define operation commands (read, write, etc.)
depending on the combination of their voltage levels. For details, refer to the command operation section.
A0 to A11 (input pins): Row address (AX0 to AX11) is determined by A0 to A11 level at the bank active
command cycle CK rising edge. Column address (AY0 to AY7) is determined by A0 to A7 level at the read
or write command cycle CK rising edge. And this column address becomes burst access start address. A10
defines the precharge mode. When A10 = High at the precharge command cycle, both banks are precharged.
But when A10 = Low at the precharge command cycle, only the bank that is selected by A12/A13 (BA) is
precharged.
A12/A13 (input pin): A12/A13 is a bank select signal (BA). The memory array is divided into bank0,
bank1, bank2 and bank3. If A12 is Low and A13 is Low, bank0 is selected. If A12 is High and A13 is Low,
bank1 is selected. If A12 is Low and A13 is High, bank2 is selected. If A12 is High and A13 is HIgh, bank3
is selected.
CKE0, CKE1 (input pin): This pin determines whether or not the next CK is valid. If CKE is High, the
next CK rising edge is valid. If CKE is Low, the next CK rising edge is invalid. This pin is used for powerdown mode, clock suspend mode and self refresh mode.
DQMB0 to DQMB7 (input pins): Read operation: If DQMB is High, the output buffer becomes High-Z. If
the DQMB is Low, the output buffer becomes Low-Z (The latency of DQMB during reading is 2 clocks).
Write operation: If DQMB is High, the previous data is held (the new data is not written). If DQMB is Low,
the data is written (The latency of DQMB during writing is 0 clock).
DQ0 to DQ63 (DQ pins): Data is input to and output from these pins.
VCC (power supply pins): 3.3 V is applied.
VSS (power supply pins): Ground is connected.
22 Material Copyrighted by Its Respective Manufacturer
This
HB52RD328DC-F
Command Operation
Command Truth Table
The SDRAM module recognizes the following commands specified by the S, RE, CE, W and address pins.
CKE
Command
Symbol
n-1 n
S
RE
CE
W
A0
A12/A13 A10 to A11
Ignore command
DESL
H
×
H
×
×
×
×
×
×
No operation
NOP
H
×
L
H
H
H
×
×
×
Burst stop in full page
BST
H
×
L
H
H
L
×
×
×
Column address and read command READ
H
×
L
H
L
H
V
L
V
Read with auto-precharge
H
×
L
H
L
H
V
H
V
Column address and write command WRIT
H
×
L
H
L
L
V
L
V
Write with auto-precharge
H
×
L
H
L
L
V
H
V
Row address strobe and bank active ACTV
H
×
L
L
H
H
V
V
V
Precharge select bank
PRE
H
×
L
L
H
L
V
L
×
Precharge all bank
PALL
H
×
L
L
H
L
×
H
×
Refresh
REF/SELF H
V
L
L
L
H
×
×
×
Mode register set
MRS
×
L
L
L
L
V
V
V
READ A
WRIT A
H
Note: H: VIH. L: V IL. ×: VIH or VIL. V: Valid address input
Ignore command [DESL]: When this command is set (S is High), the SDRAM module ignore command
input at the clock. However, the internal status is held.
No operation [NOP]: This command is not an execution command. However, the internal operations
continue.
Burst stop in full-page [BST]: This command stops a full-page burst operation (burst length = full-page)
and is illegal otherwise. When data input/output is completed for a full page of data, it automatically returns
to the start address, and input/output is performed repeatedly.
Column address strobe and read command [READ]: This command starts a read operation. In addition,
the start address of burst read is determined by the column address and the bank select address (BA). After
the read operation, the output buffer becomes High-Z.
Read with auto-precharge [READ A]: This command automatically performs a precharge operation after a
burst read with a burst length of 1, 2, 4 or 8. When the burst length is full-page, this command is illegal.
This Material Copyrighted by Its Respective Manufacturer
23
HB52RD328DC-F
Column address strobe and write command [WRIT]: This command starts a write operation. When the
burst write mode is selected, the column address and the bank select address (BA) become the burst write start
address. When the single write mode is selected, data is only written to the location specified by the column
address and the bank select address (BA).
Write with auto-precharge [WRIT A]: This command automatically performs a precharge operation after a
burst write with a length of 1, 2, 4 or 8, or after a single write operation. When the burst length is full-page,
this command is illegal.
Row address strobe and bank activate [ACTV]: This command activates the bank that is selected by bank
select address (BA) and determines the row address (AX0 to AX11). When A12 and A13 are Low, bank 0 is
activated. When A12 is High and A13 is Low, bank 1 is activated. When A12 is Low and A13 is High, bank
2 is activated. When A12 and A13 are High, bank 3 is activated.
Precharge selected bank [PRE]: This command starts precharge operation for the bank selected by
A12/A13. If A12 and A13 are Low, bank 0 is selected. If A12 is High and A13 is Low, bank 1 is selected. If
A12 is Low and A13 is High, bank 2 is selected. If A12 and A13 are High, bank 3 is selected.
Precharge all banks [PALL]: This command starts a precharge operation for all banks.
Refresh [REF/SELF]: This command starts the refresh operation. There are two types of refresh operation,
the one is auto-refresh, and the other is self-refresh. For details, refer to the CKE truth table section.
Mode register set [MRS]: The SDRAM module has a mode register that defines how it operates. The mode
register is specified by the address pins (A0 to A13) at the mode register set cycle. For details, refer to the
mode register configuration. After power on, the contents of the mode register are undefined, execute the
mode register set command to set up the mode register.
24 Material Copyrighted by Its Respective Manufacturer
This
HB52RD328DC-F
DQMB Truth Table
CKE
Command
Symbol
n-1
n
DQMB
Write enable/output enable
ENB
H
×
L
Write inhibit/output disable
MASK
H
×
H
Note: H: VIH. L: V IL. ×: VIH or VIL.
Write: IDID is needed.
Read: I DOD is needed.
The SDRAM module can mask input/output data by means of DQMB.
During reading, the output buffer is set to Low-Z by setting DQMB to Low, enabling data output. On the
other hand, when DQMB is set to High, the output buffer becomes High-Z, disabling data output.
During writing, data is written by setting DQMB to Low. When DQMB is set to High, the previous data is
held (the new data is not written). Desired data can be masked during burst read or burst write by setting
DQMB. For details, refer to the DQMB control section of the SDRAM module operating instructions.
CKE Truth Table
CKE
Current state
Command
n-1
n
S
RE
CE
W
Address
Active
Clock suspend mode entry
H
L
×
×
×
×
×
Any
Clock suspend
L
L
×
×
×
×
×
Clock suspend
Clock suspend mode exit
L
H
×
×
×
×
×
Idle
Auto-refresh command (REF)
H
H
L
L
L
H
×
Idle
Self-refresh entry (SELF)
H
L
L
L
L
H
×
Idle
Power down entry
H
L
L
H
H
H
×
H
L
H
×
×
×
×
L
H
L
H
H
H
×
L
H
H
×
×
×
×
L
H
L
H
H
H
×
L
H
H
×
×
×
×
Self refresh
Power down
Self refresh exit (SELFX)
Power down exit
Note: H: VIH. L: V IL. ×: VIH or VIL.
This Material Copyrighted by Its Respective Manufacturer
25
HB52RD328DC-F
Clock suspend mode entry: The SDRAM module enters clock suspend mode from active mode by setting
CKE to Low. If command is input in the clock suspend mode entry cycle, the command is valid. The clock
suspend mode changes depending on the current status (1 clock before) as shown below.
ACTIVE clock suspend: This suspend mode ignores inputs after the next clock by internally maintaining
the bank active status.
READ suspend and READ with Auto-precharge suspend: The data being output is held (and continues to
be output).
WRITE suspend and WRIT with Auto-precharge suspend: In this mode, external signals are not
accepted. However, the internal state is held.
Clock suspend: During clock suspend mode, keep the CKE to Low.
Clock suspend mode exit: The SDRAM module exits from clock suspend mode by setting CKE to High
during the clock suspend state.
IDLE: In this state, all banks are not selected, and completed precharge operation.
Auto-refresh command [REF]: When this command is input from the IDLE state, the SDRAM module
starts auto-refresh operation. (The auto-refresh is the same as the CBR refresh of conventional DRAMs.)
During the auto-refresh operation, refresh address and bank select address are generated inside the SDRAM
module. For every auto-refresh cycle, the internal address counter is updated. Accordingly, 4096 times are
required to refresh the entire memory. Before executing the auto-refresh command, all the banks must be in
the IDLE state. In addition, since the precharge for all banks is automatically performed after auto-refresh, no
precharge command is required after auto-refresh.
Self-refresh entry [SELF]: When this command is input during the IDLE state, the SDRAM module starts
self-refresh operation. After the execution of this command, self-refresh continues while CKE is Low. Since
self-refresh is performed internally and automatically, external refresh operations are unnecessary.
Power down mode entry: When this command is executed during the IDLE state, the SDRAM module
enters power down mode. In power down mode, power consumption is suppressed by cutting off the initial
input circuit.
Self-refresh exit: When this command is executed during self-refresh mode, the SDRAM module can exit
from self-refresh mode. After exiting from self-refresh mode, the SDRAM module enters the IDLE state.
Power down exit: When this command is executed at the power down mode, the SDRAM module can exit
from power down mode. After exiting from power down mode, the SDRAM module enters the IDLE state.
26 Material Copyrighted by Its Respective Manufacturer
This
HB52RD328DC-F
Function Truth Table
The following table shows the operations that are performed when each command is issued in each mode of
the SDRAM module. The following table assumes that CKE is high.
Current state
S
RE
CE
W
Address
Command
Operation
Precharge
H
×
×
×
×
DESL
Enter IDLE after t RP
L
H
H
H
×
NOP
Enter IDLE after t RP
L
H
H
L
×
BST
NOP
L
H
L
H
BA, CA, A10 READ/READ A
ILLEGAL*4
L
H
L
L
BA, CA, A10 WRIT/WRIT A
ILLEGAL*4
L
L
H
H
BA, RA
ACTV
ILLEGAL*4
L
L
H
L
BA, A10
PRE, PALL
NOP*6
L
L
L
H
×
REF, SELF
ILLEGAL
L
L
L
L
MODE
MRS
ILLEGAL
H
×
×
×
×
DESL
NOP
L
H
H
H
×
NOP
NOP
L
H
H
L
×
BST
NOP
L
H
L
H
BA, CA, A10 READ/READ A
ILLEGAL*5
L
H
L
L
BA, CA, A10 WRIT/WRIT A
ILLEGAL*5
L
L
H
H
BA, RA
ACTV
Bank and row active
L
L
H
L
BA, A10
PRE, PALL
NOP
L
L
L
H
×
REF, SELF
Refresh
L
L
L
L
MODE
MRS
Mode register set
H
×
×
×
×
DESL
NOP
L
H
H
H
×
NOP
NOP
L
H
H
L
×
BST
NOP
L
H
L
H
BA, CA, A10 READ/READ A
Begin read
L
H
L
L
BA, CA, A10 WRIT/WRIT A
Begin write
L
L
H
H
BA, RA
ACTV
Other bank active
ILLEGAL on same bank*3
L
L
H
L
BA, A10
PRE, PALL
Precharge
L
L
L
H
×
REF, SELF
ILLEGAL
L
L
L
L
MODE
MRS
ILLEGAL
Idle
Row active
This Material Copyrighted by Its Respective Manufacturer
27
HB52RD328DC-F
Current state
S
RE
CE
W
Address
Command
Operation
Read
H
×
×
×
×
DESL
Continue burst to end
L
H
H
H
×
NOP
Continue burst to end
L
H
H
L
×
BST
Burst stop to full page
L
H
L
H
BA, CA, A10 READ/READ A
Continue burst read to CE
latency and New read
L
H
L
L
BA, CA, A10 WRIT/WRIT A
Term burst read/start write
L
L
H
H
BA, RA
ACTV
Other bank active
ILLEGAL on same bank*3
L
L
H
L
BA, A10
PRE, PALL
Term burst read and
Precharge
L
L
L
H
×
REF, SELF
ILLEGAL
L
L
L
L
MODE
MRS
ILLEGAL
H
×
×
×
×
DESL
Continue burst to end and
precharge
L
H
H
H
×
NOP
Continue burst to end and
precharge
L
H
H
L
×
BST
ILLEGAL
L
H
L
H
BA, CA, A10 READ/READ A
ILLEGAL*4
L
H
L
L
BA, CA, A10 WRIT/WRIT A
ILLEGAL*4
L
L
H
H
BA, RA
ACTV
Other bank active
ILLEGAL on same bank*3
L
L
H
L
BA, A10
PRE, PALL
ILLEGAL*4
L
L
L
H
×
REF, SELF
ILLEGAL
L
L
L
L
MODE
MRS
ILLEGAL
H
×
×
×
×
DESL
Continue burst to end
L
H
H
H
×
NOP
Continue burst to end
L
H
H
L
×
BST
Burst stop on full page
L
H
L
H
BA, CA, A10 READ/READ A
Term burst and New read
L
H
L
L
BA, CA, A10 WRIT/WRIT A
Term burst and New write
L
L
H
H
BA, RA
ACTV
Other bank active
ILLEGAL on same bank*3
L
L
H
L
BA, A10
PRE, PALL
Term burst write and
Precharge*2
L
L
L
H
×
REF, SELF
ILLEGAL
L
L
L
L
MODE
MRS
ILLEGAL
Read with autoprecharge
Write
28 Material Copyrighted by Its Respective Manufacturer
This
HB52RD328DC-F
Current state
S
RE
CE
W
Address
Command
Operation
Write with autoprecharge
H
×
×
×
×
DESL
Continue burst to end and
precharge
L
H
H
H
×
NOP
Continue burst to end and
precharge
L
H
H
L
×
BST
ILLEGAL
L
H
L
H
BA, CA, A10 READ/READ A
ILLEGAL*4
L
H
L
L
BA, CA, A10 WRIT/WRIT A
ILLEGAL*4
L
L
H
H
BA, RA
ACTV
Other bank active
ILLEGAL on same bank*3
L
L
H
L
BA, A10
PRE, PALL
ILLEGAL*4
L
L
L
H
×
REF, SELF
ILLEGAL
L
L
L
L
MODE
MRS
ILLEGAL
H
×
×
×
×
DESL
Enter IDLE after t RC
L
H
H
H
×
NOP
Enter IDLE after t RC
L
H
H
L
×
BST
Enter IDLE after t RC
L
H
L
H
BA, CA, A10 READ/READ A
ILLEGAL*5
L
H
L
L
BA, CA, A10 WRIT/WRIT A
ILLEGAL*5
L
L
H
H
BA, RA
ACTV
ILLEGAL*5
L
L
H
L
BA, A10
PRE, PALL
ILLEGAL*5
L
L
L
H
×
REF, SELF
ILLEGAL
L
L
L
L
MODE
MRS
ILLEGAL
Refresh (autorefresh)
Notes: 1. H: VIH. L: V IL. ×: VIH or VIL.
The other combinations are inhibit.
2. An interval of t DPL is required between the final valid data input and the precharge command.
3. If tRRD is not satisfied, this operation is illegal.
4. Illegal for same bank, except for another bank.
5. Illegal for all banks.
6. NOP for same bank, except for another bank.
This Material Copyrighted by Its Respective Manufacturer
29
HB52RD328DC-F
From PRECHARGE state, command operation
To [DESL], [NOP] or [BST]: When these commands are executed, the SDRAM module enters the IDLE
state after tRP has elapsed from the completion of precharge.
From IDLE state, command operation
To [DESL], [NOP], [BST], [PRE] or [PALL]: These commands result in no operation.
To [ACTV]: The bank specified by the address pins and the ROW address is activated.
To [REF], [SELF]: The SDRAM module enters refresh mode (auto-refresh or self-refresh).
To [MRS]: The SDRAM module enters the mode register set cycle.
From ROW ACTIVE state, command operation
To [DESL], [NOP] or [BST]: These commands result in no operation.
To [READ], [READ A]: A read operation starts. (However, an interval of tRCD is required.)
To [WRIT], [WRIT A]: A write operation starts. (However, an interval of tRCD is required.)
To [ACTV]: This command makes the other bank active. (However, an interval of tRRD is required.)
Attempting to make the currently active bank active results in an illegal command.
To [PRE], [PALL]: These commands set the SDRAM module to precharge mode. (However, an interval of
tRAS is required.)
From READ state, command operation
To [DESL], [NOP]: These commands continue read operations until the burst operation is completed.
To [BST]: This command stops a full-page burst.
To [READ], [READ A]: Data output by the previous read command continues to be output. After CE
latency, the data output resulting from the next command will start.
To [WRIT], [WRIT A]: These commands stop a burst read, and start a write cycle.
To [ACTV]: This command makes other banks bank active. (However, an interval of t RRD is required.)
Attempting to make the currently active bank active results in an illegal command.
To [PRE], [PALL]: These commands stop a burst read, and the SDRAM module enters precharge mode.
30 Material Copyrighted by Its Respective Manufacturer
This
HB52RD328DC-F
From READ with AUTO-PRECHARGE state, command operation
To [DESL], [NOP]: These commands continue read operations until the burst operation is completed, and
the SDRAM module then enters precharge mode.
To [ACTV]: This command makes other banks bank active. (However, an interval of t RRD is required.)
Attempting to make the currently active bank active results in an illegal command.
From WRITE state, command operation
To [DESL], [NOP]: These commands continue write operations until the burst operation is completed.
To [BST]: This command stops a full-page burst.
To [READ], [READ A]: These commands stop a burst and start a read cycle.
To [WRIT], [WRIT A]: These commands stop a burst and start the next write cycle.
To [ACTV]: This command makes the other bank active. (However, an interval of tRRD is required.)
Attempting to make the currently active bank active results in an illegal command.
To [PRE], [PALL]: These commands stop burst write and the SDRAM module then enters precharge mode.
From WRITE with AUTO-PRECHARGE state, command operation
To [DESL], [NOP]: These commands continue write operations until the burst is completed, and the
SDRAM module enters precharge mode.
To [ACTV]: This command makes the other bank active. (However, an interval of tRRD is required.)
Attempting to make the currently active bank active results in an illegal command.
From REFRESH state, command operation
To [DESL], [NOP], [BST]: After an auto-refresh cycle (after tRC), the SDRAM module automatically enters
the IDLE state.
This Material Copyrighted by Its Respective Manufacturer
31
HB52RD328DC-F
Simplified State Diagram
SELF
REFRESH
SR ENTRY
SR EXIT
MRS
MODE
REGISTER
SET
REFRESH
IDLE
*1
AUTO
REFRESH
CKE
CKE_
IDLE
POWER
DOWN
ACTIVE
ACTIVE
CLOCK
SUSPEND
CKE_
CKE
ROW
ACTIVE
BST
(on full page)
BST
(on full page)
WRITE
Write
WRITE
SUSPEND
READ
WRITE
WITH
AP
READ
CKE_
WRITE
WRITE
CKE
READ
WITH AP
WRITE
WITH AP
WRITEA
READ
CKE
CKE
POWER
ON
READ
SUSPEND
READ
WITH AP
CKE_
READA
CKE
PRECHARGE
POWER
APPLIED
WRITE
WITH AP
Read
CKE_
PRECHARGE
CKE_
WRITEA
SUSPEND
READ
WITH
AP
READA
SUSPEND
PRECHARGE
PRECHARGE
PRECHARGE
Automatic transition after completion of command.
Transition resulting from command input.
Note: 1. After the auto-refresh operation, precharge operation is performed automatically and
enter the IDLE state.
32 Material Copyrighted by Its Respective Manufacturer
This
HB52RD328DC-F
Mode Register Configuration
The mode register is set by the input to the address pins (A0 to A13) during mode register set cycles. The
mode register consists of five sections, each of which is assigned to address pins.
A13, A12, A11, A10, A9 A8: (OPCODE): The SDRAM module has two types of write modes. One is the
burst write mode, and the other is the single write mode. These bits specify write mode.
Burst read and burst write: Burst write is performed for the specified burst length starting from the column
address specified in the write cycle.
Burst read and single write: Data is only written to the column address specified during the write cycle,
regardless of the burst length.
A7: Keep this bit Low at the mode register set cycle. If this pin is high, the vender test mode is set.
A6, A5, A4: (LMODE): These pins specify the CE latency.
A3: (BT): A burst type is specified. When full-page burst is performed, only "sequential" can be selected.
A2, A1, A0: (BL): These pins specify the burst length.
A13
A12
A11
A10
A9
A8
OPCODE
A7
A6
0
LMODE
A6 A5 A4 CAS Latency
A13 A12 A11 A10
A5
0
0
0
R
0
0
1
R
A4
A3
A2
BT
A1
A0
BL
A3 Burst Type
0 Sequential
1
Interleave
A2 A1 A0
Burst Length
BT=0
BT=1
0
0
0
1
1
0
1
0
2*
0
0
1
2
2
0
1
1
3
0
1
0
4
4
1
X
X
R
0
1
1
8
8
1
0
0
R
R
A9
A8
0
0
0
0
0
0
X
X
X
X
0
1
X
X
X
X
1
0
X
X
X
X
1
1
Write mode
Burst read and burst write
R
Burst read and single write
R
1
0
1
R
R
1
1
0
R
R
1
1
1
F.P.
R
F.P. = Full Page
R is Reserved (inhibit)
X: 0 or 1
Note: only -A6.
This Material Copyrighted by Its Respective Manufacturer
33
HB52RD328DC-F
Burst Sequence
Burst length = 2
Burst length = 4
Starting Ad. Addressing(decimal)
A0
Sequential Interleave
Starting Ad. Addressing(decimal)
A1
A0
Sequential
Interleave
0
0, 1,
0, 1,
0
0
0, 1, 2, 3,
0, 1, 2, 3,
1
1, 0,
1, 0,
0
1
1, 2, 3, 0,
1, 0, 3, 2,
1
0
2, 3, 0, 1,
2, 3, 0, 1,
1
1
3, 0, 1, 2,
3, 2, 1, 0,
Burst length = 8
Addressing(decimal)
Starting Ad.
A2
A1
A0 Sequential
Interleave
0
0
0
0, 1, 2, 3, 4, 5, 6, 7,
0, 1, 2, 3, 4, 5, 6, 7,
0
0
1
1, 2, 3, 4, 5, 6, 7, 0,
1, 0, 3, 2, 5, 4, 7, 6,
0
1
0
2, 3, 4, 5, 6, 7, 0, 1,
2, 3, 0, 1, 6, 7, 4, 5,
0
1
1
3, 4, 5, 6, 7, 0, 1, 2,
3, 2, 1, 0, 7, 6, 5, 4,
1
0
0
4, 5, 6, 7, 0, 1, 2, 3,
4, 5, 6, 7, 0, 1, 2, 3,
1
0
1
5, 6, 7, 0, 1, 2, 3, 4,
5, 4, 7, 6, 1, 0, 3, 2,
1
1
0
6, 7, 0, 1, 2, 3, 4, 5,
6, 7, 4, 5, 2, 3, 0, 1,
1
1
1
7, 0, 1, 2, 3, 4, 5, 6,
7, 6, 5, 4, 3, 2, 1, 0,
34 Material Copyrighted by Its Respective Manufacturer
This
HB52RD328DC-F
Operation of the SDRAM module
Read/Write Operations
Bank active: Before executing a read or write operation, the corresponding bank and the row address must be
activated by the bank active (ACTV) command. Bank 0, bank 1, bank 2 or bank 3 is activated according to
the status of the bank select address (BA) pin, and the row address (AX0 to AX11) is activated by the A0 to
A11 pins at the bank active command cycle. An interval of t RCD is required between the bank active command
input and the following read/write command input.
Read operation: A read operation starts when a read command is input. Output buffer becomes Low-Z in
the (CE Latency - 1) cycle after read command set. The SDRAM module can perform a burst read operation.
The burst length can be set to 1, 2, 4, 8 or full-page. The start address for a burst read is specified by the
column address and the bank select address (BA) at the read command set cycle. In a read operation, data
output starts after the number of clocks specified by the CE Latency. The CE Latency can be set to 2 or 3.
When the burst length is 1, 2, 4 or 8, the Dout buffer automatically becomes High-Z at the next clock after the
successive burst-length data has been output.
The CE latency and burst length must be specified at the mode register.
CE Latency
CK
t RCD
Command
Address
Dout
ACTV
Row
CL = 2
READ
Column
out 0
CL = 3
out 1
out 2
out 3
out 0
out 1
out 2
out 3
CL = CE latency
Burst Length = 4
This Material Copyrighted by Its Respective Manufacturer
35
HB52RD328DC-F
Burst Length
CK
t RCD
Command
ACTV
READ
Address
Row
Column
out 0
BL = 1
out 0 out 1
BL = 2
out 0 out 1 out 2 out 3
Dout
BL = 4
out 0 out 1 out 2 out 3 out 4 out 5 out 6 out 7
BL = 8
out 0 out 1 out 2 out 3 out 4 out 5 out 6 out 7 out 8
out 0-1
BL = full page
out 0
out 1
BL : Burst Length
CE Latency = 2
Write operation: Burst write or single write mode is selected by the OPCODE (A13, A12, A11, A10, A9,
A8) of the mode register.
1. Burst write: A burst write operation is enabled by setting OPCODE (A9, A8) to (0, 0). A burst write
starts in the same clock as a write command set. (The latency of data input is 0 clock.) The burst length can
be set to 1, 2, 4, 8, and full-page, like burst read operations. The write start address is specified by the column
address and the bank select address (BA) at the write command set cycle.
CK
t RCD
Command
ACTV
WRIT
Address
Row
Column
BL = 1
in 0
in 0
in 1
in 0
in 1
in 2
in 3
in 0
in 1
in 2
in 3
in 4
in 5
in 6
in 7
in 0
in 1
in 2
in 3
in 4
in 5
in 6
in 7
BL = 2
Din
BL = 4
BL = 8
BL = full page
36 Material Copyrighted by Its Respective Manufacturer
This
in 8
in 0-1
in 0
in 1
CE Latency = 2, 3
HB52RD328DC-F
2. Single write: A single write operation is enabled by setting OPCODE (A9, A8) to (1, 0). In a single write
operation, data is only written to the column address and the bank select address (BA) specified by the write
command set cycle without regard to the burst length setting. (The latency of data input is 0 clock).
CK
t RCD
Command
WRIT
ACTV
Row
Address
Column
Din
in 0
Auto Precharge
Read with auto-precharge: In this operation, since precharge is automatically performed after completing a
read operation, a precharge command need not be executed after each read operation. The command executed
for the same bank after the execution of this command must be the bank active (ACTV) command. In
addition, an interval defined by l APR is required before execution of the next command.
CE latency
Precharge start cycle
3
2 cycle before the final data is output
2
1 cycle before the final data is output
Burst Read (Burst Length = 4)
CK
CL=2 Command
ACTV
READ A
ACTV
lRAS
Dout
out0
out1
out2
out3
lAPR
CL=3 Command
ACTV
READ A
ACTV
lRAS
Dout
out0
out1
out2
out3
lAPR
Note: Internal auto-precharge starts at the timing indicated by " ".
And an interval of tRAS (lRAS) is required between previous active (ACTV) command and internal precharge "
This Material Copyrighted by Its Respective Manufacturer
".
37
HB52RD328DC-F
Write with auto-precharge: In this operation, since precharge is automatically performed after completing
a burst write or single write operation, a precharge command need not be executed after each write operation.
The command executed for the same bank after the execution of this command must be the bank active
(ACTV) command. In addition, an interval of lAPW is required between the final valid data input and input of
next command.
Burst Write (Burst Length = 4)
CK
Command
ACTV
ACTV
WRIT A
IRAS
Din
in0
in1
in2
in3
lAPW
Note: Internal auto-precharge starts at the timing indicated by " ".
and an interval of tRAS (lRAS) is required between previous active (ACTV) command
and internal precharge " ".
Single Write
CK
Command
ACTV
ACTV
WRIT A
IRAS
Din
in
lAPW
Note: Internal auto-precharge starts at the timing indicated by " ".
and an interval of tRAS (lRAS) is required between previous active (ACTV) command
and internal precharge " ".
38
This Material Copyrighted by Its Respective Manufacturer
HB52RD328DC-F
Full-page Burst Stop
Burst stop command during burst read: The burst stop (BST) command is used to stop data output during
a full-page burst. The BST command sets the output buffer to High-Z and stops the full-page burst read. The
timing from command input to the last data changes depending on the CE latency setting. In addition, the
BST command is valid only during full-page burst mode, and is illegal with burst lengths 1, 2, 4 and 8.
CE latency
BST to valid data
BST to high impedance
2
1
2
3
2
3
CE Latency = 2, Burst Length = full page
CK
BST
Command
Dout
out
out
out
out
out
out
l BSH = 2 cycle
l BSR = 1 cycle
CE Latency = 3, Burst Length = full page
CK
BST
Command
Dout
out
out
out
out
out
out
l BSR = 2 cycle
This Material Copyrighted by Its Respective Manufacturer
out
l BSH = 3 cycle
39
HB52RD328DC-F
Burst stop command at burst write: The burst stop command (BST command) is used to stop data input
during a full-page burst write. No data is written in the same clock as the BST command, and in subsequent
clocks. In addition, the BST command is only valid during full-page burst mode, and is illegal with burst
lengths of 1, 2, 4 and 8. And an interval of tDPL is required between last data-in and the next precharge
command.
Burst Length = full page
CK
BST
Command
Din
in
in
t DPL
I BSW = 0 cycle
40 Material Copyrighted by Its Respective Manufacturer
This
PRE/PALL
HB52RD328DC-F
Command Intervals
Read command to Read command interval:
1. Same bank, same ROW address: When another read command is executed at the same ROW address
of the same bank as the preceding read command execution, the second read can be performed after an
interval of no less than 1 clock. Even when the first command is a burst read that is not yet finished, the data
read by the second command will be valid.
READ to READ Command Interval (same ROW address in same bank)
CK
Command
Address
ACTV
Row
READ
READ
Column A Column B
BA
Dout
out A0 out B0 out B1 out B2 out B3
Bank0
Active
Column =A Column =B Column =A Column =B
Dout
Read
Read
Dout
CE Latency = 3
Burst Length = 4
Bank 0
2. Same bank, different ROW address: When the ROW address changes on same bank, consecutive read
commands cannot be executed; it is necessary to separate the two read commands with a precharge command
and a bank-active command.
3. Different bank: When the bank changes, the second read can be performed after an interval of no less
than 1 clock, provided that the other bank is in the bank-active state. Even when the first command is a burst
read that is not yet finished, the data read by the second command will be valid.
READ to READ Command Interval (different bank)
CK
Command
ACTV
ACTV
READ READ
Address
Row 0
Row 1
Column A Column B
BA
Dout
out A0 out B0 out B1 out B2 out B3
Bank0
Active
Bank3 Bank0 Bank3
Active Read Read
This Material Copyrighted by Its Respective Manufacturer
Bank0 Bank3
Dout
Dout
CE Latency = 3
Burst Length = 4
41
HB52RD328DC-F
Write command to Write command interval:
1. Same bank, same ROW address: When another write command is executed at the same ROW address
of the same bank as the preceding write command, the second write can be performed after an interval of no
less than 1 clock. In the case of burst writes, the second write command has priority.
WRITE to WRITE Command Interval (same ROW address in same bank)
CK
Command
Address
ACTV
Row
WRIT
WRIT
Column A Column B
BA
Din
in A0
Bank0
Active
in B0
in B1
in B2
in B3
Burst Write Mode
Burst Length = 4
Bank 0
Column =A Column =B
Write
Write
2. Same bank, different ROW address: When the ROW address changes, consecutive write commands
cannot be executed; it is necessary to separate the two write commands with a precharge command and a
bank-active command.
3. Different bank: When the bank changes, the second write can be performed after an interval of no less
than 1 clock, provided that the other bank is in the bank-active state. In the case of burst write, the second
write command has priority.
WRITE to WRITE Command Interval (different bank)
CK
Command
ACTV
Address
Row 0
ACTV WRIT
Row 1
WRIT
Column A Column B
BA
Din
in A0
Bank0
Active
in B0
in B1
Bank3 Bank0 Bank3
Active Write Write
42 Material Copyrighted by Its Respective Manufacturer
This
in B2
in B3
Burst Write Mode
Burst Length = 4
HB52RD328DC-F
Read command to Write command interval:
1. Same bank, same ROW address: When the write command is executed at the same ROW address of the
same bank as the preceding read command, the write command can be performed after an interval of no less
than 1 clock. However, DQMB must be set High so that the output buffer becomes High-Z before data input.
READ to WRITE Command Interval (1)
CK
Command
READ WRIT
CL=2
DQMB
CL=3
in B0
Din
in B1
in B2
in B3
Burst Length = 4
Burst write
High-Z
Dout
READ to WRITE Command Interval (2)
CK
Command
READ
WRIT
DQMB
2 clock
CL=2
Dout
CL=3
High-Z
High-Z
Din
2. Same bank, different ROW address: When the ROW address changes, consecutive write commands
cannot be executed; it is necessary to separate the two commands with a precharge command and a bankactive command.
3. Different bank: When the bank changes, the write command can be performed after an interval of no less
than 1 clock, provided that the other bank is in the bank-active state. However, DQMB must be set High so
that the output buffer becomes High-Z before data input.
This Material Copyrighted by Its Respective Manufacturer
43
HB52RD328DC-F
Write command to Read command interval:
1. Same bank, same ROW address: When the read command is executed at the same ROW address of the
same bank as the preceding write command, the read command can be performed after an interval of no less
than 1 clock. However, in the case of a burst write, data will continue to be written until one cycle before the
read command is executed.
WRITE to READ Command Interval (1)
CK
Command
WRIT
READ
DQMB
Din
in A0
Dout
out B0
Column = A
Write
Column = B
Read
out B1
out B2
out B3
Burst Write Mode
CE Latency = 2
Burst Length = 4
Bank 0
CE Latency
Column = B
Dout
WRITE to READ Command Interval (2)
CK
Command
WRIT
READ
DQMB
Din
in A0
in A1
Dout
out B0
Column = A
Write
out B1
CE Latency
Column = B
Read
Column = B
Dout
out B2
out B3
Burst Write Mode
CE Latency = 2
Burst Length = 4
Bank 0
2. Same bank, different ROW address: When the ROW address changes, consecutive read commands
cannot be executed; it is necessary to separate the two commands with a precharge command and a bankactive command.
3. Different bank: When the bank changes, the read command can be performed after an interval of no less
than 1 clock, provided that the other bank is in the bank-active state. However, in the case of a burst write,
data will continue to be written until one clock before the read command is executed (as in the case of the
same bank and the same address).
44 Material Copyrighted by Its Respective Manufacturer
This
HB52RD328DC-F
Read with auto precharge to Read command interval
1. Different bank: When some banks are in the active state, the second read command (another bank) is
executed. Even when the first read with auto-precharge is a burst read that is not yet finished, the data read by
the second command is valid. The internal auto-precharge of one bank starts at the next clock of the second
command.
Read with Auto Precharge to Read Command Interval (Different bank)
CK
Command
READ A
READ
BA
Dout
out A0
bank0
Read A
out A1
out B0
bank3
Read
out B1
CE Latency = 3
Burst Length = 4
Note: Internal auto-precharge starts at the timing indicated by "
".
2. Same bank: The consecutive read command (the same bank) is illegal.
Write with auto precharge to Write command interval
1. Different bank: When some banks are in the active state, the second write command (another bank) is
executed. In the case of burst writes, the second write command has priority. The internal auto-precharge of
one bank starts at the next clock of the second command .
Write with Auto Precharge to Write Command Interval (Different bank)
CK
Command
WRIT A
WRIT
BA
Din
in A0
bank0
Write A
in A1
in B0
in B1
in B2
bank3
Write
Note: Internal auto-precharge starts at the timing indicated by "
in B3
Burst Length = 4
".
2. Same bank: The consecutive write command (the same bank) is illegal.
This Material Copyrighted by Its Respective Manufacturer
45
HB52RD328DC-F
Read with auto precharge to Write command interval
Different bank: When some banks are in the active state, the second write command (another bank) is
executed. However, DQMB must be set High so that the output buffer becomes High-Z before data input.
The internal auto-precharge of one bank starts at the next clock of the second command.
Read with Auto Precharge to Write Command Interval (Different bank)
CK
Command
READ A
WRIT
BA
DQMB
CL = 2
CL = 3
Din
in B0
Dout
in B1
in B2
in B3
High-Z
bank0
Read A
Burst Length = 4
bank3
Write
Note: Internal auto-precharge starts at the timing indicated by "
".
2. Same bank: The consecutive write command from read with auto precharge (the same bank) is illegal. It
is necessary to separate the two commands with a bank active command.
46 Material Copyrighted by Its Respective Manufacturer
This
HB52RD328DC-F
Write with auto precharge to Read command interval
1. Different bank: When some banks are in the active state, the second read command (another bank) is
executed. However, in case of a burst write, data will continue to be written until one clock before the read
command is executed. The internal auto-precharge of one bank starts at the next clock of the second
command.
Write with Auto Precharge to Read Command Interval (Different bank)
CK
Command
WRIT A
READ
BA
DQMB
Din
in A0
Dout
out B0
bank0
Write A
out B1
out B3
CE Latency = 3
Burst Length = 4
bank3
Read
Note: Internal auto-precharge starts at the timing indicated by "
out B2
".
2. Same bank: The consecutive read command from write with auto precharge (the same bank) is illegal. It
is necessary to separate the two commands with a bank active command.
This Material Copyrighted by Its Respective Manufacturer
47
HB52RD328DC-F
Read command to Precharge command interval (same bank):
When the precharge command is executed for the same bank as the read command that preceded it, the
minimum interval between the two commands is one clock. However, since the output buffer then becomes
High-Z after the clocks defined by lHZP , there is a case of interruption to burst read data output will be
interrupted, if the precharge command is input during burst read. To read all data by burst read, the clocks
defined by lEP must be assured as an interval from the final data output to precharge command execution.
READ to PRECHARGE Command Interval (same bank): To output all data
CE Latency = 2, Burst Length = 4
CK
Command
PRE/PALL
READ
Dout
out A0
out A1
CL=2
out A2
out A3
l EP = -1 cycle
CE Latency = 3, Burst Length = 4
CK
Command
READ
PRE/PALL
Dout
out A0
CL=3
48 Material Copyrighted by Its Respective Manufacturer
This
out A1
out A2
l EP = -2 cycle
out A3
HB52RD328DC-F
READ to PRECHARGE Command Interval (same bank): To stop output data
CE Latency = 2, Burst Length = 1, 2, 4, 8, full page burst
CK
Command
READ
PRE/PALL
Dout
out A0
High-Z
lHZP = 2
CE Latency = 3, Burst Length = 1, 2, 4, 8, full page burst
CK
Command
READ
PRE/PALL
Dout
out A0
High-Z
lHZP = 3
This Material Copyrighted by Its Respective Manufacturer
49
HB52RD328DC-F
Write command to Precharge command interval (same bank): When the precharge command is executed
for the same bank as the write command that preceded it, the minimum interval between the two commands is
1 clock. However, if the burst write operation is unfinished, the input data must be masked by means of
DQMB for assurance of the clock defined by tDPL.
WRITE to PRECHARGE Command Interval (same bank):
Burst Length = 4 (To stop write operation)
CK
Command
WRIT
PRE/PALL
DQMB
Din
tDPL
CK
Command
PRE/PALL
WRIT
DQMB
Din
in A0
in A1
tDPL
Burst Length = 4 (To write all data)
CK
Command
PRE/PALL
WRIT
DQMB
Din
in A0
in A1
in A2
in A3
tDPL
50 Material Copyrighted by Its Respective Manufacturer
This
HB52RD328DC-F
Bank active command interval:
1. Same bank: The interval between the two bank-active commands must be no less than tRC.
Bank Active to Bank Active for Same Bank
CK
Command
ACTV
ACTV
Address
ROW
ROW
BA
t RC
Bank 0
Active
Bank 0
Active
2. In the case of different bank-active commands: The interval between the two bank-active commands
must be no less than tRRD.
Bank Active to Bank Active for Different Bank
CK
Command
Address
ACTV
ACTV
ROW:0
ROW:1
BA
t RRD
Bank 0
Active
This Material Copyrighted by Its Respective Manufacturer
Bank 3
Active
51
HB52RD328DC-F
Mode register set to Bank-active command interval: The interval between setting the mode register and
executing a bank-active command must be no less than lRSA .
CK
Command
Address
MRS
ACTV
CODE
BS & ROW
I RSA
Mode
Register Set
Bank
Active
DQMB Control
The DQMB mask the DQ data. The timing of DQMB is different during reading and writing.
Reading: When data is read, the output buffer can be controlled by DQMB. By setting DQMB to Low, the
output buffer becomes Low-Z, enabling data output. By setting DQMB to High, the output buffer becomes
High-Z, and the corresponding data is not output. However, internal reading operations continue. The
latency of DQMB during reading is 2 clocks.
Writing: Input data can be masked by DQMB. By setting DQMB to Low, data can be written. In addition,
when DQMB is set to High, the corresponding data is not written, and the previous data is held. The latency
of DQMB during writing is 0 clock.
52 Material Copyrighted by Its Respective Manufacturer
This
HB52RD328DC-F
Reading
CK
DQMB
Dout
High-Z
out 0
out 1
out 3
lDOD = 2 Latency
Writing
,
CK
DQMB
Din
in 0
in 3
in 1
l DID = 0 Latency
This Material Copyrighted by Its Respective Manufacturer
53
HB52RD328DC-F
Refresh
Auto-refresh: All the banks must be precharged before executing an auto-refresh command. Since the autorefresh command updates the internal counter every time it is executed and determines the banks and the
ROW addresses to be refreshed, external address specification is not required. The refresh cycle is 4096
cycles/64 ms. (4096 cycles are required to refresh all the ROW addresses.) The output buffer becomes HighZ after auto-refresh start. In addition, since a precharge has been completed by an internal operation after the
auto-refresh, an additional precharge operation by the precharge command is not required.
Self-refresh: After executing a self-refresh command, the self-refresh operation continues while CKE is held
Low. During self-refresh operation, all ROW addresses are refreshed by the internal refresh timer. A selfrefresh is terminated by a self-refresh exit command. Before and after self-refresh mode, execute auto-refresh
to all refresh addresses in or within 64 ms period on the condition (1) and (2) below.
(1) Enter self-refresh mode within 15.6 µs after either burst refresh or distributed refresh at equal interval to
all refresh addresses are completed.
(2) Start burst refresh or distributed refresh at equal interval to all refresh addresses within 15.6 µs after
exiting from self-refresh mode.
Others
Power-down mode: The SDRAM module enters power-down mode when CKE goes Low in the IDLE state.
In power down mode, power consumption is suppressed by deactivating the input initial circuit. Power down
mode continues while CKE is held Low. In addition, by setting CKE to High, the SDRAM module exits from
the power down mode, and command input is enabled from the next clock. In this mode, internal refresh is
not performed.
Clock suspend mode: By driving CKE to Low during a bank-active or read/write operation, the SDRAM
module enters clock suspend mode. During clock suspend mode, external input signals are ignored and the
internal state is maintained. When CKE is driven High, the SDRAM module terminates clock suspend mode,
and command input is enabled from the next clock. For details, refer to the "CKE Truth Table".
Power-up sequence: The SDRAM module should be gone on the following sequence with power up.
The CK, CKE, S, DQMB and DQ pins keep low till power stabilizes.
The CK pin is stabilized within 100 µs after power stabilizes before the following initialization sequence.
The CKE and DQMB is driven to high between power stabilizes and the initialization sequence.
This SDRAM module has VCC clamp diodes for CK, CKE, S, DQMB and DQ pins. If these pins go high
before power up, the large current flows from these pins to VCC through the diodes.
Initialization sequence: When 200 µs or more has past after the above power-up sequence, all banks must
be precharged using the precharge command (PALL). After tRP delay, set 8 or more auto refresh commands
(REF). Set the mode register set command (MRS) to initialize the mode register. We recommend that by
keeping DQMB to High, the output buffer becomes High-Z during Initialization sequence, to avoid DQ bus
contention on memory system formed with a number of device.
54 Material Copyrighted by Its Respective Manufacturer
This
HB52RD328DC-F
Initialization sequence
Power up sequence
100 µs
VCC
200 µs
0V
CKE, DQMB
Low
CK
Low
S, DQ
Low
Power stabilize
This Material Copyrighted by Its Respective Manufacturer
55
HB52RD328DC-F
#
#$*+2:
")1893&!(0%,-4<;.5=/67>'
9+,34;'./67>?=$%-BCKL:,,
Timing Waveforms
Read Cycle
t CK
t CKH t CKL
CK
,
,,,
,
,
,,,,
,
t RC
VIH
CKE
t CS t CH
t RP
t RAS
t RCD
t CS t CH
t CS t CH
t CS t CH
t CS t CH
t CS t CH
t CS t CH
t CS t CH
S
t CS t CH
t CS t CH
RE
t CS t CH
t CS t CH
CE
t CS t CH
t CS t CH
t AS t AH
t AS t AH
t AS t AH
t AS t AH
t AS t AH
t CS t CH
t CS t CH
W
t AS t AH
A12/A13
t AS t AH
t AS t AH
A10
t AS t AH
t AS t AH
t AS t AH
Address
t CH
t CS
DQMB
Din
t AC
Dout
t AC
t AC
t HZ
t AC
Bank 0
Active
Bank 0
Read
t LZ
56 Material Copyrighted by Its Respective Manufacturer
This
t OH
t OH
t OH
Bank 0
Precharge
t OH
CE latency = 2
Burst length = 4
Bank 0 access
= VIH or VIL
!
4
3
+
#
"
,
%
$
9
2
*
:
>
=
7
6
/
.
?
3
+
$
<
;
5
4
,
&
%
'
/7>?!'(-./8,0!(")1
HB52RD328DC-F
Write Cycle
t CK
t CKH t CKL
CK
t RC
VIH
CKE
t RAS
t RP
, ,
,
,
t RCD
t CS t CH
t CS t CH
t CS t CH
t CS t CH
t CS t CH
t CS t CH
t CS t CH
t CS t CH
S
t CS t CH
t CS t CH
RE
t CS t CH
t CS t CH
CE
t CS t CH
t CS t CH
t CS t CH
t AS t AH
t AS t AH
t AS t AH
t AS t AH
t CS t CH
W
t AS t AH
t AS t AH
A12/A13
t AS t AH
t AS t AH
A10
t AS t AH
t AS t AH
t AS t AH
Address
t CS
t CH
DQMB
t DS t DH tDS
t DH t DS t DH t DS
t DH
Din
t DPL
Dout
Bank 0
Active
Bank 0
Write
This Material Copyrighted by Its Respective Manufacturer
Bank 0
Precharge
CE latency = 2
Burst length = 4
Bank 0 access
= VIH or VIL
57
HB52RD328DC-F
GOP>F45<=FH@I&%-.76?'(/08A$
N;DLMCK
,
,,,,
,,
,
,
,,
Mode Register Set Cycle
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
b+3
b’
b’+1
b’+2
b’+3
18
CK
CKE
VIH
S
RE
CE
W
BA
Address
code R: b
valid
C: b’
C: b
DQMB
Dout
b
High-Z
Din
l RP
Precharge
If needed
l RSA
l RCD
Mode
Bank 3
register Active
Set
58 Material Copyrighted by Its Respective Manufacturer
This
Output mask
Bank 3
Read
l RCD = 3
CE latency = 3
Burst length = 4
= VIH or VIL
,#5>+FG4=O<E19:BC45=EF/78?@I%!IJH%
(!)12$-@9:B0'8/AK7$
AJKL
,,,,
HB52RD328DC-F
Read Cycle/Write Cycle
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
CK
CKE
VIH
Read cycle
RE-CE delay = 3
CE latency = 3
Burst length = 4
= VIH or VIL
S
RE
CE
W
BA
Address
R:a
C:a
R:b
C:b
C:b'
C:b"
DQMB
Dout
Din
CKE
a
a+1 a+2 a+3
b
b+1 b+2 b+3 b'
b'+1 b"
b"+1 b"+2 b"+3
High-Z
Bank 0
Active
Bank 0
Read
Bank 3
Active
Bank 3 Bank 0
Read
Precharge
Bank 3
Read
Bank 3
Read
Bank 3
Precharge
VIH
Write cycle
RE-CE delay = 3
CE latency = 3
Burst length = 4
= VIH or VIL
S
RE
CE
W
BA
Address
R:a
C:a
R:b
C:b
C:b'
C:b"
DQMB
High-Z
Dout
Din
a
Bank 0
Active
Bank 0
Write
a+1 a+2 a+3
Bank 3
Active
b
Bank 3
Write
This Material Copyrighted by Its Respective Manufacturer
b+1 b+2 b+3 b'
Bank 0
Precharge
Bank 3
Write
b'+1 b"
Bank 3
Write
b"+1 b"+2 b"+3
Bank 3
Precharge
59
,
#
#5>FGOPENM+,34<=!*3)12:>FGOP&!"*+23!*)BKL9JAI8
%'(01):2;C$-6
$,
,
9ABJKL
HB52RD328DC-F
,
,
Read/Single Write Cycle
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
CK
CKE
VIH
S
RE
CE
W
BA
R:a
Address
C:a
R:b
C:a' C:a
DQMB
a
Din
Dout
a
Bank 0
Active
CKE
Bank 0
Read
Bank 3
Active
C:a
R:b
a+1 a+2 a+3
a
Bank 0 Bank 0
Write
Read
a+1 a+2 a+3
Bank 0
Precharge
Bank 3
Precharge
VIH
S
RE
CE
W
BA
Address
R:a
C:a
C:b C:c
a
b
DQMB
Din
Dout
a
Bank 0
Active
Bank 0
Read
a+1
Bank 3
Active
c
a+3
Bank 0
Write
Bank 0 Bank 0
Write
Write
Bank 0
Precharge
Read/Single write
RE-CE delay = 3
CE latency = 3
Burst length = 4
= VIH or VIL
60 Material Copyrighted by Its Respective Manufacturer
This
20
HB52RD328DC-F
, ,,
,
Read/Burst Write Cycle
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
#
""P#+,5*23<4=DEN;F'(01,&'
@
?
7
/
.
)
1
(
$
J
B
A
9
8
0
H
I
*AIJ8H9BK&'./67@23:;CD
0
CK
CKE
S
RE
CE
W
BA
R:a
Address
C:a
R:b
C:a'
DQMB
a
Din
Dout
a
Bank 0
Active
CKE
Bank 0
Read
Bank 3
Active
C:a
R:b
a+1 a+2 a+3
a+1 a+2 a+3
Clock
suspend
Bank 0
Write
Bank 0
Precharge
Bank 3
Precharge
VIH
S
RE
CE
W
BA
Address
R:a
C:a
DQMB
a
Din
Dout
a
Bank 0
Active
Bank 0
Read
a+1
Bank 3
Active
a+1 a+2 a+3
a+3
Bank 0
Write
Bank 0
Precharge
Read/Burst write
RE-CE delay = 3
CE latency = 3
Burst length = 4
= VIH or VIL
This Material Copyrighted by Its Respective Manufacturer
61
HB52RD328DC-F
Full Page Read/Write Cycle
DMVWaEO1;YN;DENOX"#,56?*)23($.%@IJS]RH>-7A<\QFZ[
ST]^\>HQR
CK
CKE
VIH
Read cycle
RE-CE delay = 3
CE latency = 3
Burst length = full page
= VIH or VIL
S
RE
CE
W
BA
Address
R:a
C:a
R:b
DQMB
Dout
Din
CKE
a
a+1
a+3
High-Z
Bank 0
Active
Bank 0
Read
Bank 3
Active
Burst stop
VIH
Bank 3
Precharge
Write cycle
RE-CE delay = 3
CE latency = 3
Burst length = full page
= VIH or VIL
S
RE
CE
W
BA
Address
a+2
R:a
C:a
R:b
DQMB
High-Z
Dout
Din
a
Bank 0
Active
Bank 0
Write
a+1
a+2
Bank 3
Active
a+3
a+4
a+5
a+6
62 Material Copyrighted by Its Respective Manufacturer
This
Burst stop
Bank 3
Precharge
)2:;BCLK!"*'(01$F<=#,45
DM,!)*12;:C9'%&
H
?
6
7
6
H
?
"
5
,
N
F
E
=
<
4
+
I
@
8
7
/
'
P
G
:BCJK.78?@HI$
%-.6JKAB9,I'/AJH&0?6@H
HB52RD328DC-F
,
,
,
,,,,,,,,
,,,, ,,,,
Auto Refresh Cycle
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
a
a+1
CK
CKE
VIH
S
RE
CE
W
BA
Address
C:a
R:a
A10=1
DQMB
Din
High-Z
Dout
t RC
t RP
tRC
Auto Refresh
Precharge
If needed
Read
Bank 0
Active
Bank 0
Auto Refresh
Refresh cycle and
Read cycle
RE-CE delay = 2
CE latency = 2
Burst length = 4
= VIH or VIL
Self Refresh Cycle
CK
l SREX
CKE Low
CKE
S
RE
CE
W
BA
Address
A10=1
DQMB
Din
High-Z
Dout
tRP
Precharge command
If needed
tRC
tRC
Self refresh entry
command
Self refresh exit
ignore command
or No operation
This Material Copyrighted by Its Respective Manufacturer
Next
clock
enable
Self refresh entry
command
Auto
Next
clock refresh
enable
Self refresh cycle
RE-CE delay = 3
CE latency = 3
Burst length = 4
= VIH or VIL
63
!
,
+
#
"
GP()129:ABK45=>KLCHB%.67?8@I'/0&;<DM2:)-+34*"#!,=E(9N,&
ML&./67@
HB52RD328DC-F
,,,
,
,
,
Clock Suspend Mode
t CES
0
1
2
3
4
5
t CES
t CEH
6
7
8
9
10
11
12
13
14
15
16
CK
CKE
RE
CE
W
BA
R:a
C:a
R:b
C:b
DQMB
Dout
a
a+1 a+2
a+3
b
High-Z
Din
Bank0 Active clock
Active suspend start
Active clock Bank0
suspend end Read
Bank3
Active
Read suspend
start
Read suspend
end
Bank3
Read
Bank0
Precharge
CKE
19
20
b+1 b+2 b+3
Earliest Bank3
Precharge
Write cycle
RE-CE delay = 2
CE latency = 2
Burst length = 4
= VIH or VIL
S
RE
CE
W
BA
Address
18
Read cycle
RE-CE delay = 2
CE latency = 2
Burst length = 4
= VIH or VIL
S
Address
17
C:a R:b
R:a
C:b
DQMB
High-Z
Dout
Din
a
Bank0
Active
Active clock
suspend start
a+1 a+2
Active clock Bank0 Bank3
supend end Write Active
Write suspend
start
64 Material Copyrighted by Its Respective Manufacturer
This
a+3 b
Write suspend
end
b+1 b+2 b+3
Bank3 Bank0
Write Precharge
Earliest Bank3
Precharge
HB52RD328DC-F
Power Down Mode
,
,
,
,
,
,,,,,,
,
,
,,,
#
!
+
"
P'(0@AIJ)/789.?HB,45=>EFNOG/78?@HI9AJ'(0%&.6$
6?
CK
CKE Low
CKE
S
RE
CE
W
BA
Address
R: a
A10=1
DQMB
Din
High-Z
Dout
tRP
Precharge command
If needed
Power down entry
Power down
mode exit
Active Bank 0
Power down cycle
RE-CE delay = 3
CE latency = 3
Burst length = 4
= VIH or VIL
,
,,
,,,,
Initialization Sequence
0
1
2
3
4
5
6
7
8
9
10
48
49
50
51
52
53
54
55
CK
CKE
VIH
S
RE
CE
W
DQMB
code
valid
Address
Valid
VIH
High-Z
DQ
t RP
All banks
Precharge
t RC
Auto Refresh
This Material Copyrighted by Its Respective Manufacturer
t RSA
tRC
Auto Refresh
Mode register
Set
Bank active
If needed
65
HB52RD328DC-F
Physical Outline
Unit: mm
inch
67.60
2.661
3.80 Max
0.150 Max
(Datum -A-)
B
4.60
0.181
1.00 ± 0.10
0.039 ± 0.004
4.60
0.181 32.80
1.291
2
3.70
0.146
A
144
2.10
0.083
23.20
0.913
32.80
1.291
Component area
(back)
2-R2.00
2-R0.079
4.00 ± 0.10
0.157 ± 0.004
23.20
0.913
2.50
0.098
3.30
0.130
4.00 Min
0.157 Min
20.00
0.787
1
143
31.75
1.250
Component area
(front)
3.20 Min
0.126 Min
2R3.00 Min
2R0.118 Min
2.00 Min
0.079 Min
(Datum -A-)
Detail B
Detail A
(DATUM -A-)
2.5
0.098
0.80
0.031
66 Material Copyrighted by Its Respective Manufacturer
This
R0.75
R0.030
4.00 ± 0.10
0.157 ± 0.004
0.25 Max
0.010 Max
0.100 Min
2.55 Min
0.60 ± 0.05
0.024 ± 0.002
1.50 ± 0.10
0.059 ± 0.004
HB52RD328DC-F
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent,
copyright, trademark, or other intellectual property rights for information contained in this document.
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Hitachi, Ltd.
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For further information write to:
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(America) Inc.
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Germany
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Telex: 40815 HITEC HX
Copyright © Hitachi, Ltd., 1998. All rights reserved. Printed in Japan.
This Material Copyrighted by Its Respective Manufacturer
67
HB52RD328DC-F
Revision Record
Rev. Date
Contents of Modification
Drawn by
Approved by
0.0
May. 10, 1999 Initial issue
(referred to HM5264165F/HM5264805F/HM5264405F75/A60/B60 rev 0.1)
S. Tsukui
K. Tsuneda
0.1
Aug. 26, 1999 (referred to HM5264165F/HM5264805F/HM5264405F75/A60/B60 rev 0.1)
Serial PD Matrix
Byte 10 : 70 to 60
Byte 24 : 70 to 60 (-A6F/A6FL)
: 90 to 80 (-B6F/B6FL)
Byte 32 : 30 to 20
Byte 34 : 30 to 20
Byte 63 : 53 to13 (-A6F/A6FL)
: C3 to 83 (-B6F/B6FL)
AC Characteristics
t AC (CE latency = 2) max: 7/9 ns to 6/8 ns
t AC (CE latency = 3) max: 7/7 ns to 6/6 ns
t HZ (max): 7/7 ns to 6/6 ns
S. Tsukui
T. Tsuneda
1.0
Jan. 18, 2000 (referred to HM5264165F/HM5264805F/HM5264405F75/A60/B60 rev 1.0)
CKE Truth Table
Clock suspend mode entry (S): H to ×
DC Characteristics
I CC1 max (CL = 2): 1440/1360 mA to 1248/1248 mA
I CC1 max (CL = 3): 1440/1440 mA to 1248/1248 mA
I CC2P max: 96/96 mA to 48/48 mA
I CC2PS max: 64/64 mA to 32/32 mA
I CC2N max: 512/512 mA to 320/320 mA
I CC3N max: 640/640 mA to 576/576 mA
I CC4 max (CL = 2): 1440/1280 mA to 1168/1168 mA
I CC4 max (CL = 3): 1440/1440 mA to 1168/1168 mA
I CC5 max: 2160/2160 mA to 2048/2048 mA
Relation Between Frequency and Minimum Latency
I APW max: 4 to 3
Physical outline: Correct error
68 Material Copyrighted by Its Respective Manufacturer
This